935318468096 [NXP]
RISC Microcontroller;
| 型号： | 935318468096 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总72页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
K22P80M120SF7
Rev. 7, 08/2016
Kinetis K22F 512KB Flash 80-Pin
MK22FN512CAP12R
MK22FN256CAP12R
MK22FN512CBP12R
WLCSP
120 MHz ARM® Cortex®-M4 Based Microcontroller with FPU
The Kinetis K22 product family members are optimized for
space-constrained, cost-sensitive applications requiring
lowpower, USB connectivity, and processing efficiency with a
floating point unit. These devices share the comprehensive
enablement and scalability of the Kinetis family.
This product offers:
• Run power consumption down to 156 μA/MHz and static
power consumption down to 3.8 μA, full state retention and
6 μS wakeup. Lowest static mode down to 140 nA.
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator. USB FS device crystal-less functionality.
80 WLCSP (AP)
4.13 x 3.56 x 0.564 mm 4.13 x 3.56 x 0.321 mm
Pitch 0.4 mm Pitch 0.4 mm
80 WLCSP (BP)
Performance
• 120 MHz ARM® Cortex®-M4 core with DSP
Analog modules
• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)
• Up to two 12-bit DACs
instructions delivering 1.25 Dhrystone MIPS per MHz
• Two analog comparators (CMP) with 6-bit DAC
• Accurate internal voltage reference
Memories and memory interfaces
• 512 or 256 KB of embedded flash, and 128 KB of RAM
• FlexBus external bus interface
Communication interfaces
• Serial programming interface (EzPort)
• Preprogrammed Kinetis flashloader for one-time, in-
system factory programming
• USB LS/FS OTG 2.0 with on-chip transceiver and
USB LDO voltage regulator
• USB full-speed device crystal-less operation
• Two SPI modules
System peripherals
• Three UART modules and one low-power UART
• Two I2C: Support for up to 1 Mbps operation
• I2S module
• Flexible low-power modes, multiple wake up sources
• 16-channel DMA controller
• Independent external and software watchdog monitor
Timers
Clocks
• Two 8-ch general-purpose/PWM timers
• Two 2-ch general-purpose timers with quadrature
decoder functionality
• Periodic interrupt timers
• 16-bit low-power timer
• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or
3-32 MHz
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Multi-purpose clock generator with PLL and FLL
• Real-time clock with independent power domain
• Programmable delay block
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
• Hardware random-number generator
• Flash access control to protect proprietary software
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
• Temperature range (ambient): -40 to 85°C
Human-machine interface
• 52 general-purpose I/O (GPIO)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Memory
Part Number
Maximum number of I/Os
Flash (KB)
SRAM (KB)
128
MK22FN512CAP12R
MK22FN256CAP12R
MK22FN512CBP12R
512
256
512
52
52
52
128
128
Device Revision Number
Device Mask Set Number
0N50M
SIM_SDID[REVID]
JTAG ID Register[PRN]
0001
0001
Related Resources
Description
Type
Document
Selector Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector
KINETISKMCUSELGD
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M120SF7RM
K22P80M120SF7
Data Sheet
The Data Sheet is this document. It includes electrical characteristics and
signal connections.
Chip Errata
The chip mask set Errata provides additional or corrective information for a KINETIS_K_xN50M1
particular device mask set.
Package drawing Package dimensions are provided by part number:
• MK22FN512CAP12R
Package drawing:
• 98ASA00710D
• 98ASA00710D
• 98ASA00820D
• MK22FN256CAP12R
• MK22FN512CBP12R
1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision
of the device you are using.
Figure 1 shows the functional modules in the chip.
2
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
®
ARM Cortex™-M4
System
Memories and Memory Interfaces
Clocks
Core
Program
flash
(512 KB)
RAM
(128 KB)
Phase-
locked loop
DMA (16ch)
Low-leakage
wakeup
Frequency-
locked loop
Debug
FlexBus
DSP
FPU
interfaces
Internal
and external
watchdogs
Low/high
frequency
oscillators
Serial
programming
interface
Interrupt
contoller
(EzPort)
Internal
reference
clocks
Communication Interfaces
2
Security
Human-Machine
Interface (HMI)
Analog
Timers
and Integrity
Timers
x2 (8ch)
x2 (2ch)
Up to
52 GPIOs
I C
x2
16-bit
ADC x2
2
CRC
I S
Comparator
with 6-bit DAC
x2
Random
number
Programmable
delay block
UART
x3
USB OTG
LS/FS
generator
Flash access
control
Periodic
interrupt
timers
12-bit DAC
x2
LPUART
x1
USB LS/FS
transceiver
High
performance
voltage ref
16-bit
low-power
timer
SPI
x2
USB voltage
regulator
Independent
real-time
clock
Figure 1. Functional block diagram
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
3.6 Analog............................................................................. 36
3.6.1 ADC electrical specifications............................... 37
3.6.2 CMP and 6-bit DAC electrical specifications....... 41
3.6.3 12-bit DAC electrical characteristics....................43
3.6.4 Voltage reference electrical specifications.......... 46
3.7 Timers..............................................................................47
3.8 Communication interfaces............................................... 47
3.8.1 USB electrical specifications............................... 48
3.8.2 USB VREG electrical specifications.................... 48
3.8.3 DSPI switching specifications (limited voltage
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....17
2.2.7 Designing with radiated emissions in mind..........18
2.2.8 Capacitance attributes.........................................18
2.3 Switching specifications...................................................18
2.3.1 Device clock specifications..................................18
2.3.2 General switching specifications......................... 19
2.4 Thermal specifications.....................................................20
2.4.1 Thermal operating requirements......................... 20
2.4.2 Thermal attributes................................................20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 SWD electricals .................................................. 21
3.1.2 JTAG electricals.................................................. 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications..............................................25
3.3.2 IRC48M specifications.........................................27
3.3.3 Oscillator electrical specifications........................28
3.3.4 32 kHz oscillator electrical characteristics...........30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications..............................31
3.4.2 EzPort switching specifications........................... 33
3.4.3 Flexbus switching specifications..........................33
3.5 Security and integrity modules........................................ 36
range).................................................................. 49
3.8.4 DSPI switching specifications (full voltage
range).................................................................. 51
3.8.5 Inter-Integrated Circuit Interface (I2C) timing...... 52
3.8.6 UART switching specifications............................ 54
3.8.7 I2S/SAI switching specifications..........................54
4 Dimensions............................................................................. 60
4.1 Obtaining package dimensions....................................... 60
5 Pinout......................................................................................61
5.1 K22F Signal Multiplexing and Pin Assignments.............. 61
5.2 Recommended connection for unused analog and
digital pins........................................................................64
5.3 K22 Pinouts..................................................................... 65
6 Part identification.....................................................................66
6.1 Description.......................................................................66
6.2 Format............................................................................. 66
6.3 Fields............................................................................... 66
6.4 Example...........................................................................67
6.5 80-pin WLCSP part marking............................................67
7 Terminology and guidelines.................................................... 68
7.1 Definitions........................................................................68
7.2 Examples.........................................................................68
7.3 Typical-value conditions.................................................. 69
7.4 Relationship between ratings and operating
requirements....................................................................69
7.5 Guidelines for ratings and operating requirements..........70
8 Revision History...................................................................... 70
4
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
1
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
5
NXP Semiconductors
General
Symbol
Description
Min.
–0.3
Max.
3.8
Unit
V
VDD
IDD
Digital supply voltage
Digital supply current
—
169
mA
V
VDIO
Digital input voltage
Analog1
–0.3
VDD + 0.3
VDD + 0.3
25
VAIO
–0.3
V
ID
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
USB0_DP input voltage
USB0_DM input voltage
USB regulator input
–25
mA
V
VDDA
VDD – 0.3
–0.3
VDD + 0.3
3.63
VUSB0_DP
VUSB0_DM
VREGIN
VBAT
V
–0.3
3.63
V
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
General
Notes
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
Max.
3.6
3.6
0.1
0.1
3.6
—
Unit
V
Supply voltage
VDDA
Analog supply voltage
1.71
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
V
–0.1
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
1.71
V
0.7 × VDD
0.75 × VDD
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
V
VIL
Input low voltage
—
—
0.35 × VDD
0.3 × VDD
V
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
V
2
VDD voltage required to retain RAM
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
—
1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
2.62
2.70
2.78
V
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
7
NXP Semiconductors
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW2H
VLVW3H
VLVW4H
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.72
2.80
2.88
V
2.82
2.92
2.90
3.00
2.98
3.08
V
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VOH
VOH
IOHT
Output high voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
1
Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
Output high current total for all ports
VDD – 0.5
VDD – 0.5
—
—
—
—
—
—
V
V
1
100
mA
Table continues on the next page...
8
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VOL
VOL
VOL
Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
—
—
0.5
0.5
V
V
1
Output low voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
Output low voltage — RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
Output low current total for all ports
—
—
—
—
0.5
0.5
V
V
1
—
—
—
—
—
—
0.5
0.5
100
V
V
IOLT
IIN
mA
Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins
High drive port pins
—
—
—
0.002
0.004
—
0.5
0.5
1.0
μA
μA
μA
1, 2
2
IIN
Input leakage current (total all pins) for full
temperature range
RPU
RPD
Internal pullup resistors
20
20
—
—
50
50
kΩ
kΩ
3
4
Internal pulldown resistors
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 80 MHz
• Bus clock = 40 MHz
• FlexBus clock = 20 MHz
• Flash clock = 20 MHz
• MCG mode: FEI
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
9
NXP Semiconductors
General
Table 5. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
—
—
300
μs
1
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS2 → RUN
• LLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
140
140
80
μs
μs
μs
μs
μs
μs
μs
μs
80
6
6
5.7
5.7
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
10
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
@ 1.8V
Min.
—
Typ.
28.0
28.0
Max.
29.33
29.33
Unit
mA
mA
Notes
2, 3, 4
@ 3.0V
—
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
25.6
25.7
26.93
27.03
mA
mA
2
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
35.5
35.6
36.83
36.93
mA
mA
5
IDD_RUN Run mode current in Compute operation —
CoreMark benchmark code executing from flash
@ 1.8V
@ 3.0V
—
—
17.5
17.5
18.83
18.83
mA
mA
3, 4, 6
IDD_RUN Run mode current in Compute operation —
code executing from flash
@ 1.8V
@ 3.0V
—
—
15.10
15.10
17.10
17.33
mA
mA
6
7
8
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
16.6
16.8
17.93
18.13
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
—
22.8
24.13
mA
@ 3.0V
• @ 25°C
—
—
—
22.9
23.1
23.5
24.23
24.43
24.83
mA
mA
mA
• @ 70°C
• @ 85°C
IDD_RUN Run mode current — Compute operation, code
executing from flash
@ 1.8V
—
15.1
16.43
mA
9
@ 3.0V
• @ 25°C
—
—
—
—
15.1
15.4
15.6
9.3
16.43
16.73
16.93
10.63
mA
mA
mA
mA
• @ 70°C
• @ 85°C
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
7
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Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
11
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
5.4
6.73
mA
10
IDD_VLPR Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V
@ 3.0V
—
—
0.88
0.89
1.02
1.03
mA
mA
3, 4, 11
IDD_VLPR Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V
@ 3.0V
—
—
—
0.62
0.63
0.76
0.77
0.77
0.90
mA
mA
mA
11
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
12
13
14
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
—
1.2
1.34
0.59
mA
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
0.45
IDD_STOP Stop mode current at 3.0 V
@ -40°C to 25°C
—
—
—
0.28
0.34
0.38
0.37
0.51
0.55
mA
mA
mA
@ 70°C
@ 85°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ -40°C to 25°C
—
—
—
8.7
18.10
79.55
µA
µA
µA
@ 70°C
31.1
50.3
@ 85°C
110.15
IDD_LLS3 Low leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C
—
—
—
3.8
5.65
28.75
47.60
µA
µA
µA
@ 70°C
12.5
20.2
@ 85°C
IDD_LLS2 Low leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C
—
—
—
3.0
7.8
4.10
16.40
30.15
µA
µA
µA
@ 70°C
@ 85°C
12.3
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C
—
—
—
2.8
9.5
3.95
21.25
34.65
µA
µA
µA
@ 70°C
@ 85°C
15.3
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C
@ 70°C
—
—
—
1.9
4.5
6.8
2.45
8.50
µA
µA
µA
@ 85°C
12.15
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
12
NXP Semiconductors
General
Notes
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ -40°C to 25°C
@ 70°C
—
—
—
0.73
1.8
1.42
3.90
5.25
µA
µA
µA
@ 85°C
3.0
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ -40°C to 25°C
@ 70°C
—
—
—
0.43
1.4
0.55
2.45
4.00
µA
µA
µA
@ 85°C
2.6
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ -40°C to 25°C
@ 70°C
—
—
—
0.14
1.1
0.24
2.15
3.85
µA
µA
µA
@ 85°C
2.3
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
@ -40°C to 25°C
@ 70°C
—
—
—
0.18
0.66
1.52
0.21
0.86
2.24
µA
µA
µA
@ 85°C
IDD_VBAT Average current when CPU is not accessing
RTC registers
@ 1.8V
• @ -40°C to 25°C
—
—
—
0.59
1.00
1.76
0.70
1.3
µA
µA
µA
15
• @ 70°C
• @ 85°C
2.59
@ 3.0V
• @ -40°C to 25°C
—
—
—
0.71
1.22
2.08
0.84
1.59
3.06
µA
µA
µA
• @ 70°C
• @ 85°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120MHz core and system clock, 60MHz bus clock, 24MHz FlexBus clock, and 24MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. Cache on and prefetch on, low compiler optimization.
4. Coremark benchmark compiled using IAR 7.2 with optimization level low.
5. 120MHz core and system clock, 60MHz bus clock, 24MHz FlexBus clock, and 24MHz flash clock. MCG configured for
PEE mode. All peripheral clocks enabled.
6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode.
Compute operation.
7. 80MHz core and system clock, 40MHz bus clock, 20MHz FlexBus clock, and 26.67MHz flash clock. MCG configured
for FEI mode. All peripheral clocks disabled.
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
13
NXP Semiconductors
General
8. 80MHz core and system clock, 40MHz bus clock, 20MHz FlexBus clock, and 26.67MHz flash clock. MCG configured for
FEI mode. All peripheral clocks enabled.
9. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute
operation.
10. 25MHz core and system clock, 25MHz bus clock, and 25MHz FlexBus and flash clock. MCG configured for FEI mode.
11. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute
operation. Code executing from flash.
12. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
13. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
14. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
15. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
IEREFSTEN4MHz
IEREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
uA
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
440
440
490
510
510
350
22
490
490
490
560
560
350
22
540
540
540
560
560
350
22
560
560
560
560
560
350
22
570
570
570
610
610
350
22
580
580
680
680
680
350
22
nA
VLLS3
LLS
VLPS
STOP
I48MIRC
ICMP
48 Mhz internal reference clock
µA
µA
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
Table continues on the next page...
14
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
General
Unit
Table 7. Low power mode peripheral adders—typical value (continued)
Symbol
Description
Temperature (°C)
-40
25
50
70
85
105
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
66
214
45
66
237
45
66
246
45
66
254
45
66
260
45
66
268
45
µA
>OSCERCLK (4 MHz external crystal)
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz. MCG in PEE mode at frequencies
greater than 100 MHz.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
15
NXP Semiconductors
General
Run Mode Current vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
All Peripheral Clk Gates
ALLOFF
ALLON
Clk Ratio
Core-Bus-FlexBus-Flash
Core Freq (Mhz)
Figure 3. Run mode supply current vs. core frequency
16
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
General
Very Low Power Run (VLPR) Current vs Core Frequency
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
All Peripheral Clk Gates
ALLOFF
ALLON
Clk Ratio
Core-Bus-FlexBus-Flash
Core Freq (Mhz)
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
Parame Conditions
ter
Clocks
Frequency range
Level
(Typ.)
Unit
Notes
VEME
Device configuration,
FSYS = 120 MHz
150 kHz–50 MHz
50 MHz–150 MHz
150 MHz–500 MHz
500 MHz–1000 MHz
IEC level
14
23
23
9
dBuV
1, 2, 3
test conditions and EM
testing per standard IEC
61967-2.
FBUS = 60 MHz
External crystal = 8 MHz
Supply voltages:
• VREGIN (USB) =
5.0 V
L
4
• VDD = 3.3 V
Temp = 25°C
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on the 64LQFP device, MK22FN512VLH12 .
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
17
NXP Semiconductors
General
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed run mode
fSYS
fBUS
System and core clock
Bus clock
—
—
120
60
MHz
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
80
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
FB_CLK
fFLASH
Bus clock
—
—
—
—
50
30
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
LPTMR clock
26.67
25
fLPTMR
VLPR mode1
Table continues on the next page...
18
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
General
Notes
Table 10. Device clock specifications (continued)
Symbol
fSYS
Description
Min.
—
Max.
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
System and core clock
Bus clock
fBUS
—
4
FB_CLK
fFLASH
FlexBus clock
—
4
Flash clock
—
1
fERCLK
fLPTMR_pin
External reference clock
LPTMR clock
—
16
25
16
12.5
4
—
fLPTMR_ERCLK LPTMR external reference clock
—
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
—
—
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
50
—
—
ns
3
4
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
ns
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time
• Slew disabled
5
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
10
5
ns
ns
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
30
16
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
19
NXP Semiconductors
General
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
95
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
85
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board type
Symbol
Description
80 WLCSP
(AP)
80
WLCSP
(BP)
Unit
Notes
Single-layer
(1s)
RθJA
Thermal resistance, junction to
ambient (natural convection)
49.0
36.6
39.3
32.1
36.8
0.2
102.4
°C/W
1
2
3
3
4
5
6
Four-layer
(2s2p)
RθJA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
Thermal resistance, junction to
ambient (natural convection)
47.3
86.4
42.7
25.7
4.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Single-layer
(1s)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Four-layer
(2s2p)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
—
—
Thermal resistance, junction to
board
Thermal resistance, junction to
case
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
0.1
0.2
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
20
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
SWD_CLK frequency of operation
• Serial wire debug
0
33
—
MHz
ns
S2
S3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/S1
15
—
ns
S4
S9
SWD_CLK rise and fall times
—
8
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
25
—
S10
S11
S12
1.4
—
5
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 5. Serial wire clock input timing
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NXP Semiconductors
Peripheral operating requirements and behaviors
SWD_CLK
SWD_DIO
S9
S10
Input data valid
S11
Output data valid
SWD_DIO
S12
SWD_DIO
S11
Output data valid
SWD_DIO
Figure 6. Serial wire data timing
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
10
20
• JTAG and CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
ns
ns
• JTAG and CJTAG
J4
J5
J6
J7
J8
J9
TCLK rise and fall times
—
20
1
3
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
—
—
25
25
—
—
—
8
Table continues on the next page...
22
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 14. JTAG limited voltage range electricals (continued)
Symbol
J10
Description
Min.
1
Max.
—
Unit
ns
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
J11
—
19
ns
J12
—
19
ns
J13
TRST assert time
100
8
—
ns
J14
TRST setup time (negation) to TCLK high
—
ns
Table 15. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
10
15
• JTAG and CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
33
—
—
ns
ns
• JTAG and CJTAG
J4
J5
TCLK rise and fall times
—
20
1.4
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
27
27
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
26.2
26.2
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 7. Test clock input timing
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23
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 9. Test Access Port timing
24
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Δfints_t
fints_t
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
31.25
—
+0.5/-0.7
—
2
39.0625
0.6
%
Internal reference frequency (slow clock) —
user trimmed
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.3
2
%fdco
%fdco
1, 2
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
—
4
—
5
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
5
MHz
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
floc_low Loss of external clock minimum frequency —
RANGE = 00
Min.
Typ.
Max.
Unit
Notes
(3/5) x
fints_t
—
—
kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
20.97
MHz
3, 4
frequency range
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
180
150
—
—
—
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
120
—
MHz
µA
PLL operating current
8
8
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
9
—
—
120
75
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
9
Table continues on the next page...
26
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
• fvco = 48 MHz
Min.
Typ.
Max.
Unit
Notes
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
400
48
500
—
μA
Internal reference frequency
—
MHz
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
—
high voltage (VDD=1.89V-3.6V) over 0°C to 70°C
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
—
0.2
0.4
0.5
1.0
%firc48m
1
1
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
Regulator enable
—
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. IRC48M specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
%firc48m
%fhost
Notes
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
1
Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
—
—
—
0.4
0.5
—
1.0
1.5
0.1
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
2
3
over voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean 3 sigma).
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high-gain mode (HGO=1)
• 32 kHz
1
—
—
25
—
—
μA
μA
400
Table continues on the next page...
28
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• 4 MHz
—
500
—
μA
• 8 MHz (RANGE=01)
—
—
—
2.5
3
—
—
—
mA
mA
mA
• 16 MHz
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
29
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1 32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
30
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.4.2 32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT
.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk256k Erase Block high-voltage time for 256 KB
—
1
—
13
113
904
ms
ms
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
1
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
31
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
• 256 KB program flash
—
—
1.7
ms
trd1sec2k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
trdrsrc
tpgm4
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 256 KB program flash
30
1
145
—
2
tersblk256k
—
250
1500
ms
tersscr
trd1all
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
14
—
114
1.8
30
ms
ms
μs
2
1
trdonce
—
1
tpgmonce Program Once execution time
100
500
—
—
μs
—
2
tersall
Erase All Blocks execution time
3000
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
32
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.2 EzPort switching specifications
Table 26. EzPort switching specifications
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
—
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
25
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 11. EzPort Timing Diagram
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
33
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given
in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency
may be the same as the internal system bus frequency or an integer divider of that
frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can
be derived from these values.
Table 27. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
MHz
ns
FB1
FB2
FB3
FB4
FB5
33.3
—
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
15
ns
0.5
14.5
0.5
—
ns
1
2
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 28. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
MHz
ns
FB1
FB2
FB3
FB4
FB5
33.3
—
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
21.5
—
ns
–1.0
20.0
0.5
ns
1
2
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
34
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB5
FB3
Address
FB4
FB2
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
S1
S0
S2
S3
S0
Figure 12. FlexBus read timing diagram
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
35
NXP Semiconductors
Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
FB_RW
Address
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 13. FlexBus write timing diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
36
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on
the differential pins ADCx_DPx, ADCx_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1 16-bit ADC operating conditions
Table 29. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20
37
—
—
1200
461
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
37
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 29. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 14. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
Table continues on the next page...
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NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
1.2
2.4
3.0
4.4
Typ.2
Max.
3.9
Unit
MHz
MHz
MHz
MHz
Notes
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
tADACK = 1/
fADACK
4.0
6.1
fADACK
5.2
7.3
6.2
9.5
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
• <12-bit modes
—
—
1.0
0.5
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
Table continues on the next page...
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39
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor voltage 25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 15. Typical ENOB vs. ADC_CLK for 16-bit differential mode
40
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 16. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
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NXP Semiconductors
Peripheral operating requirements and behaviors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 17. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 32. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
330
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
1200
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
44
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 19. Typical INL error vs. digital code
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
45
NXP Semiconductors
Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 20. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 34. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
Notes
1.71
3.6
V
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
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Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
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Peripheral operating requirements and behaviors
Table 35. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1920
1.1950
1.1980
V
1
nominal VDDA and temperature=25°C
Vout
Voltage reference output with user trim at
nominal VDDA and temperature=25°C
1.1945
1.1950
1.1955
V
1
Vstep
Vtdrift
Voltage reference trim step
—
—
0.5
—
—
mV
mV
1
1
Temperature drift (Vmax -Vmin across the full
temperature range)
15
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
Low-power buffer current
High-power buffer current
1
1
Ihp
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full
voltage range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 36. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
70
°C
Table 37. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vtdrift
Temperature drift (Vmax -Vmin across the limited
temperature range)
—
10
mV
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
47
NXP Semiconductors
Peripheral operating requirements and behaviors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter or signaling
rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the USB
clock recovery mode is enabled. It does not meet the USB
signaling rate specifications for certification in Host mode
operation.
3.8.2 USB VREG electrical specifications
Table 38. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
V
Notes
VREGIN Input supply voltage
—
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
3.6
3.6
V
V
• Standby mode
2.1
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 38. USB VREG electrical specifications
(continued)
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
3.8.3 DSPI switching specifications (limited voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provide DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 39. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-2
8.5
—
—
—
ns
ns
ns
ns
16.2
0
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
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NXP Semiconductors
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 21. DSPI classic SPI timing — master mode
Table 40. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
15
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
1
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
21.4
—
ns
ns
2.6
7
—
ns
—
ns
—
—
17
17
ns
ns
1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with
continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock
is 60 MHz, the SPI clock must not be greater than 10 MHz.
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 22. DSPI classic SPI timing — slave mode
50
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
3.8.4 DSPI switching specifications (full voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provides DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 41. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
24.6
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 23. DSPI classic SPI timing — master mode
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 42. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
29.5
—
ns
ns
3.2
7
—
ns
—
ns
—
—
25
25
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 24. DSPI classic SPI timing — slave mode
3.8.5 Inter-Integrated Circuit Interface (I2C) timing
Table 43. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
4001
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
52
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 43. I 2C timing (continued)
Characteristic
Symbol
Standard Mode
Minimum Maximum
02 3.453
Fast Mode
Unit
Minimum
Maximum
Data hold time for I2C bus devices
Data set-up time
tHD; DAT
tSU; DAT
tr
04
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
0.92
µs
ns
ns
ns
µs
µs
2505
—
1000
300
—
—
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 44. I 2C 1 Mbps timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tLOW
tHIGH
0.5
0.26
0.26
0
—
—
µs
µs
µs
µs
ns
ns
ns
µs
µs
tSU; STA
tHD; DAT
tSU; DAT
tr
—
—
50
—
, 2
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
20 +0.1Cb
20 +0.1Cb
0.26
120
120
—
2
tf
tSU; STO
tBUF
Bus free time between STOP and START
condition
0.5
—
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
53
NXP Semiconductors
Peripheral operating requirements and behaviors
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 25. Timing definition for devices on the I2C bus
3.8.6 UART switching specifications
See General switching specifications.
3.8.7 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.7.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 45. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
40
3.6
—
V
S1
S2
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
55%
MCLK period
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
54
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 45. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S3
S4
S5
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
80
—
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
18
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 26. I2S/SAI timing — master modes
Table 46. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
2.7
80
3.6
—
V
S11
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
55
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 46. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num.
S14
Characteristic
Min.
Max.
Unit
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
20
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
4.5
2
—
—
25
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 27. I2S/SAI timing — slave modes
3.8.7.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 47. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
45%
55%
MCLK period
Table continues on the next page...
56
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 47. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S3
S4
S5
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
80
—
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
27
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 28. I2S/SAI timing — master modes
Table 48. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
80
3.6
—
V
S11
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
57
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 48. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
S14
Characteristic
Min.
Max.
Unit
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
28.5
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
5.8
2
—
ns
ns
ns
—
—
26.3
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 29. I2S/SAI timing — slave modes
3.8.7.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 49. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
3.6
—
V
S1
S2
S3
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
55%
—
MCLK period
ns
Table continues on the next page...
58
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 49. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
55%
Unit
BCLK period
S4
S5
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
—
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 30. I2S/SAI timing — master modes
Table 50. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
250
3.6
—
V
S11
ns
S12
S13
S14
S15
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
7
—
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
63
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
59
NXP Semiconductors
Dimensions
Table 50. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
S16
Characteristic
Min.
Max.
Unit
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
30
4
—
—
72
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 31. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
80-pin WLCSP (AP)
Then use this document number
98ASA00710D
80-pin WLCSP (BP)
98ASA00820D
60
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Pinout
5 Pinout
5.1 K22F Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
The MK22FN512VFX12 (88QFN) does not support the
FlexBus function.
80
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
E7
PTE0/
CLKOUT32K
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
DISABLED
DISABLED
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
PTE0/
CLKOUT32K
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
SPI1_SIN
UART1_TX
UART1_RX
I2C1_SDA
I2C1_SCL
RTC_
CLKOUT
A8
PTE1/
LLWU_P0
PTE1/
LLWU_P0
SPI1_SIN
A9
PTE2/
LLWU_P1
PTE2/
LLWU_P1
UART1_
CTS_b
A10
B8
PTE3
PTE3
UART1_
RTS_b
SPI1_SOUT
PTE4/
LLWU_P2
PTE4/
LLWU_P2
SPI1_PCS0
SPI1_PCS2
LPUART0_TX
C8
PTE5
PTE5
LPUART0_
RX
FTM3_CH0
B9
B10
D8
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
C10
D10
C9
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
D9
E10
ADC1_DP1/
ADC0_DP2
ADC1_DP1/
ADC0_DP2
ADC1_DP1/
ADC0_DP2
F10
E9
ADC1_DM1/
ADC0_DM2
ADC1_DM1/
ADC0_DM2
ADC1_DM1/
ADC0_DM2
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
F9
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
G9
VDDA
VDDA
VDDA
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
61
NXP Semiconductors
Pinout
80
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
G10
H10
H9
VREFH
VREFL
VREFH
VREFH
VREFL
VSSA
VREFL
VSSA
VSSA
E8
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
F8
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
G7
RTC_
RTC_
RTC_
WAKEUP_B
WAKEUP_B
WAKEUP_B
G8
H8
H7
F7
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_
CTS_b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
F6
F5
PTA1
PTA2
JTAG_TDI/
EZP_DI
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
JTAG_TDO/
TRACE_
SWO/
JTAG_TDO/
TRACE_SWO
EZP_DO
EZP_DO
F4
G6
H5
H6
H4
G5
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
JTAG_TMS/
SWD_DIO
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
NMI_b
EZP_CS_b
PTA5
DISABLED
DISABLED
DISABLED
DISABLED
PTA5
USB_CLKIN
I2S0_TX_
BCLK
JTAG_TRST_
b
PTA12
PTA12
I2S0_TXD0
FTM1_QD_
PHA
PTA13/
LLWU_P4
PTA13/
LLWU_P4
I2S0_TX_FS
FTM1_QD_
PHB
PTA14
PTA14
SPI0_PCS0
I2S0_RX_
BCLK
G4
H3
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
I2S0_RXD0
SPI0_SOUT
UART0_
CTS_b
I2S0_RX_FS
G3
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_MCLK
E6
G2
H2
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
62
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Pinout
80
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
H1
PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
LPTMR0_
ALT1
G1
F3
RESET_b
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
SPI1_PCS0
SPI1_SCK
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
E3
F2
F1
E2
PTB1
PTB2
PTB3
PTB10
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
PTB2
PTB3
PTB10
PTB11
FTM1_QD_
PHB
ADC0_SE12
ADC0_SE13
ADC1_SE14
ADC0_SE12
ADC0_SE13
ADC1_SE14
UART0_
RTS_b
FTM0_FLT3
FTM0_FLT0
FTM0_FLT1
FTM0_FLT2
UART0_
CTS_b
LPUART0_
RX
FB_AD19
FB_AD18
E1
E4
D5
D1
D2
D3
PTB11
VSS
ADC1_SE15
VSS
ADC1_SE15
VSS
LPUART0_TX
VDD
VDD
VDD
PTB16
PTB17
PTB18
DISABLED
DISABLED
DISABLED
PTB16
PTB17
PTB18
SPI1_SOUT
SPI1_SIN
UART0_RX
UART0_TX
FTM2_CH0
FTM_CLKIN0 FB_AD17
FTM_CLKIN1 FB_AD16
EWM_IN
EWM_OUT_b
I2S0_TX_
BCLK
FB_AD15
FB_OE_b
FB_AD14
FB_AD13
FB_AD12
CLKOUT
FTM2_QD_
PHA
D4
C1
B1
C2
C3
PTB19
PTC0
DISABLED
ADC0_SE14
ADC0_SE15
PTB19
PTC0
FTM2_CH1
I2S0_TX_FS
FTM2_QD_
PHB
ADC0_SE14
ADC0_SE15
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
PDB0_
EXTRG
USB_SOF_
OUT
PTC1/
LLWU_P6
PTC1/
LLWU_P6
UART1_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
I2S0_TXD0
LPUART0_
RTS_b
PTC2
ADC0_SE4b/
CMP1_IN0
ADC0_SE4b/
CMP1_IN0
PTC2
UART1_
CTS_b
I2S0_TX_FS
LPUART0_
CTS_b
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
UART1_RX
I2S0_TX_
BCLK
LPUART0_
RX
E5
D6
A1
VSS
VDD
VSS
VSS
VDD
VDD
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
I2S0_RXD0
FB_AD11
FB_AD10
FB_AD9
FB_AD8
FB_AD7
FB_AD6
CMP1_OUT
CMP0_OUT
I2S0_MCLK
LPUART0_TX
FTM0_CH2
B2
A2
B3
A3
C4
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
CMP0_IN1
PTC5/
LLWU_P9
LPTMR0_
ALT2
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_
EXTRG
I2S0_RX_
BCLK
PTC7
PTC8
PTC9
PTC7
PTC8
PTC9
USB_SOF_
OUT
I2S0_RX_FS
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
FTM3_CH4
I2S0_MCLK
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
FTM3_CH5
I2S0_RX_
BCLK
FTM2_FLT0
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
63
NXP Semiconductors
Pinout
80
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EZPORT
B4
A4
PTC10
PTC11/
ADC1_SE6b
ADC1_SE7b
ADC1_SE6b
ADC1_SE7b
PTC10
I2C1_SCL
I2C1_SDA
FTM3_CH6
FTM3_CH7
I2S0_RX_FS
FB_AD5
PTC11/
FB_RW_b
LLWU_P11
LLWU_P11
B5
PTC16
DISABLED
PTC16
LPUART0_
RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_8_
b
A5
C5
PTC17
DISABLED
DISABLED
PTC17
LPUART0_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_0_b
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
UART2_
RTS_b
FTM3_CH0
FB_ALE/
FB_CS1_b/
FB_TS_b
LPUART0_
RTS_b
B6
A6
PTD1
ADC0_SE5b
DISABLED
ADC0_SE5b
PTD1
SPI0_SCK
UART2_
CTS_b
FTM3_CH1
FTM3_CH2
FB_CS0_b
LPUART0_
CTS_b
PTD2/
LLWU_P13
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FB_AD4
LPUART0_
RX
I2C0_SCL
C6
B7
PTD3
DISABLED
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FTM0_CH4
FB_AD3
FB_AD2
LPUART0_TX I2C0_SDA
EWM_IN SPI1_PCS0
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
A7
C7
D7
PTD5
ADC0_SE6b
ADC0_SE7b
DISABLED
ADC0_SE6b
ADC0_SE7b
PTD5
SPI0_PCS2
SPI0_PCS3
UART0_
CTS_b
FTM0_CH5
FTM0_CH6
FTM0_CH7
FB_AD1
FB_AD0
EWM_OUT_b SPI1_SCK
PTD6/
LLWU_P15
PTD6/
LLWU_P15
UART0_RX
FTM0_FLT0
FTM0_FLT1
SPI1_SOUT
SPI1_SIN
PTD7
PTD7
UART0_TX
5.2 Recommended connection for unused analog and digital
pins
The following table shows the recommended connections for analog interface pins if
those analog interfaces are not used in the customer's application.
Table 51. Recommended connection for unused analog interfaces
Pin Type
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Short recommendation
Float
Detailed recommendation
Analog input - Float
PGAx/ADCx
ADCx/CMPx
VREF_OUT
DACx_OUT
RTC_WAKEUP_B
XTAL32
Float
Float
Float
Float
Float
Analog input - Float
Analog output - Float
Analog output - Float
Analog output - Float
Analog output - Float
Table continues on the next page...
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
64
NXP Semiconductors
Pinout
Table 51. Recommended connection for unused analog interfaces (continued)
Pin Type
Analog/non GPIO
GPIO/Analog
Short recommendation
Float
Detailed recommendation
Analog input - Float
EXTAL32
PTA18/EXTAL0
PTA19/XTAL0
PTx/ADCx
Float
Float
Float
Float
Float
Analog input - Float
GPIO/Analog
Analog output - Float
GPIO/Analog
Float (default is analog input)
Float (default is analog input)
GPIO/Analog
PTx/CMPx
GPIO/Digital
PTA0/JTAG_TCLK
Float (default is JTAG with
pulldown)
GPIO/Digital
GPIO/Digital
GPIO/Digital
GPIO/Digital
PTA1/JTAG_TDI
PTA2/JTAG_TDO
PTA3/JTAG_TMS
PTA4/NMI_b
Float
Float
Float
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
USB
PTx
Float
Float
Float
Float (default is disabled)
USB0_DP
USB0_DM
VOUT33
Float
Float
USB
USB
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
VREGIN
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
VBAT
VDDA
VBAT
VDDA
Float
Float
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
Always connect to VDD
potential
Always connect to VDD
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
5.3 K22 Pinouts
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
65
NXP Semiconductors
Part identification
1
2
3
4
5
6
7
8
9
10
PTC4/
LLWU_P8 LLWU_P10
PTC6/
PTC11/
LLWU_P11
PTD2/
LLWU_P13
PTE1/
LLWU_P0 LLWU_P1
PTE2/
A
B
C
D
E
F
PTC8
PTC17
PTD5
PTE3
A
B
C
D
E
F
PTC1/
LLWU_P6 LLWU_P9
PTC5/
PTD4/
PTE4/
VDD
PTC7
PTC10
PTC9
PTB19
VSS
PTC16
PTD1
PTD3
VDD
VSS
LLWU_P14 LLWU_P2
PTC3/
LLWU_P7
PTD0/
LLWU_P12
PTD6/
LLWU_P15
PTC0
PTB16
PTB11
PTB3
PTC2
PTB17
PTB10
PTB2
VSS
PTE5
VOUT33
USB0_DP
PTB18
PTB1
VDD
VSS
PTD7
VSS
VREGIN USB0_DM
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PTE0/
CLKOUT32K
ADC0_DP0/ ADC1_DP1/
ADC1_DP3
VDD
ADC0_DP2
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
PTB0/
LLWU_P5
ADC0_DM0/ADC1_DM1/
ADC1_DM3
PTA3
PTA2
PTA14
PTA5
PTA1
PTA0
ADC0_DM2
PTA4/
LLWU_P3
RTC_
WAKEUP_B
G
H
RESET_b
PTA19
PTA17
PTA16
PTA15
XTAL32
VDDA
VREFH
G
H
PTA13/
LLWU_P4
PTA18
PTA12
VBAT
EXTAL32
VSSA
VREFL
Figure 32. K22F 80 WLCSP pinout diagram (transparent top view)
6 Part identification
6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
6.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
66
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Part identification
6.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow, full
reel
• P = Prequalification
• K = Fully qualified, general market flow, 100
piece reel
K##
A
Kinetis family
Key attribute
• K22
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
Silicon revision
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
R
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• C = –40 to 85
PP
• AP = 80 WLCSP (4.13 mm x 3.56 mm x
0.564 mm)
• BP = 80 WLCSP (4.13 mm x 3.56 mm x
0.321 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 12 = 120 MHz
• R = Tape and reel
6.4 Example
This is an example part number:
MK22FN512CAP12R
6.5 80-pin WLCSP part marking
The 80-pin WLCSP package parts follow the part-marking scheme in the following
table.
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
67
NXP Semiconductors
Terminology and guidelines
Table 52. 80-pin WLCSP part marking
MK Part number
MK Part Marking
MK22FN512CAP12
MK22FN256CAP12
MK22FN512CBP12
MK22FN512CAP12R
MK22FN256CAP12R
MK22FN512CBP12R
7 Terminology and guidelines
7.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
68
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
NXP Semiconductors
Terminology and guidelines
7.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
7.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
69
NXP Semiconductors
Revision History
7.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
7.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8 Revision History
The following table provides a revision history for this document.
Table 53. Revision History
Rev. No.
Date
Substantial Changes
7
08/2016
• Updated the Front Matter
• Added Terminology and Guidelines section
• Added Device Revision Number Table
• Updated Chip Errata naming convention in Related Resource table
6
10/2015
• Throughout: Removed notes related to limited availability of the 80-pin WLCSP (BP)
Table continues on the next page...
70
NXP Semiconductors
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
Revision History
Table 53. Revision History (continued)
Rev. No.
Date
Substantial Changes
• In "Power consumption operating behaviors" section, added "Low power mode
peripheral adders—typical value" table
• In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + ΘJA" to
"TJ = TA + RΘJA
"
• Updated "IRC48M specifications" table
• Updated "NVM program/erase timing specifications" table; removed row for thversall
and added row for thversblk256k
• Updated "Flash command timing specifications" table; added rows for trd1blk256k and
tersblk256k
• In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding
maximum frequency of operation
• Added new section, "Recommended connections for unused analog and digital pins"
5
4/2015
Initial public release
Kinetis K22F 512KB Flash 80-Pin WLCSP, Rev. 7, 08/2016
71
NXP Semiconductors
How to Reach Us:
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address:nxp.com/SalesTermsandConditions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER
WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V.
All other product or service names are the property of their respective owners.
ARM, the ARM Powered logo, and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. The USB-IF Logo is a
registered trademark of USB Implementers Forum, Inc. All rights reserved.
© 2014–2016 NXP B.V.
Document Number K22P80M120SF7
Revision 7, 08/2016
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