935318485557 [NXP]
RISC Microcontroller;
| 型号： | 935318485557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总60页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
KV11P64M75
Data Sheet: Technical Data
Rev. 4, 05/2017
Kinetis V Series KV10 and KV11,
MKV11Z128VXX7
MKV11Z64VXX7
MKV10Z64VXX7
MKV10Z128VXX7
MKV11Z128VLX7P
MKV10Z64VLX7P
128/64 KB Flash
75 MHz Cortex-M0+ Based Microcontroller
The Kinetis V Series KV11x MCU family is built on ARM Cortex-
M0+ core and enabled by innovative 90nm thin film storage
(TFS) flash process technology. The KV11x is an extension of
the existing KV10x family providing increased memory, higher
pin count, additional FTMs and a FlexCAN serial interface.
• Dual 16-bit ADCs sampling at up to 1.2 MS/s in 12-bit
mode
32 QFN
64 LQFP
• Highly accurate and flexible motor control timers
• Ideal for industrial motor control applications, inverters, and
low-end power conversion applications
5 x 5 x 1.23 mm Pitch 10 x 10 x 1.4 mm Pitch
0.5 mm
0.5 mm
• Enabled to support Kinetis Motor Suite (KMS), a bundled
hardware and software solution that enables rapid
configuration of BLDC and PMSM motor drive systems
32 LQFP
7 x 7 x 1.4 mm Pitch
0.8 mm
48 LQFP
7 x 7 x 1.4 mm Pitch
0.5 mm
Performance
• Up to 75 MHz ARM Cortex-M0+ based core
Communication interfaces
• One 16-bit SPI module
• One I2C module
Memories and memory interfaces
• Up to 128 KB of program flash memory
• Up to 16 KB of RAM
• Two UART modules
• One FlexCAN module1
Timers
• Programmable delay block
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• 8-channel DMA controller
• SWD interface and Micro Trace buffer
• Bit Manipulation Engine (BME)
• External watchdog timer
• Two 6-channel FlexTimers (FTM) for motor control/
general purpose applications
• Four 2-channel FlexTimers (FTM) with quadrature
decoder functionality
• 16-bit low-power timer (LPTMR)
• Advanced independent clocked watchdog
• Memory Mapped Divide and Square Root (MMDVSQ)
module
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Clocks
• 32-40 kHz or 4-32 MHz external crystal oscillator
• Multipurpose clock generator (MCG) with frequency-
locked loop referencing either internal or external
reference clock
Analog modules
• Two 16-bit SAR ADCs
• 12-bit DAC
• Two analog comparators (ACMP) containing a 6-bit
DAC and programmable reference input
Security and integrity modules
• 80-bit unique identification (ID) number per chip
• Hardware CRC module
Human-machine interface
• General-purpose I/O
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Kinetis Motor Suite
• Supports Velocity and Position control of BLDC &
PMSM motors
• Implements Field Orient Control (FOC) using Back
EMF to improve motor efficiency
• Utilizes SpinTAC control theory that improves
overall system performance and reliability
1. Available only on KV11 parts
Ordering Information
Part Number 1
Memory
FlexCAN
Maximum number of
I\O's
Flash (KB)
SRAM (KB)
16
MKV11Z128VLH7
MKV11Z128VLF7
MKV11Z128VLC7 2
MKV11Z128VFM7
MKV11Z64VLH7
MKV11Z64VLF7
MKV11Z64VLC7 2
MKV11Z64VFM7
MKV11Z128VLH7P
MKV11Z128VLF7P
MKV11Z128VLC7P 2
MKV11Z128VFM7P
MKV10Z64VLH7P
MKV10Z64VLF7P
MKV10Z64VLC7P 2
MKV10Z64VFM7P
MKV10Z64VLH7
MKV10Z64VLF7
128
128
128
128
64
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
46
35
26
26
46
35
26
26
46
35
26
26
46
35
26
26
46
35
26
26
46
35
26
26
16
16
16
16
64
16
64
16
64
16
120
120
120
120
56
16
16
16
16
16
56
16
56
16
56
16
64
16
No
64
16
No
MKV10Z64VLC7 2
MKV10Z64VFM7
MKV10Z128VLH7
MKV10Z128VLF7
MKV10Z128VLC7 2
MKV10Z128VFM7
64
16
No
128
128
128
128
128
16
No
16
No
16
No
16
No
16
No
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
2. The 32-pin LQFP package supporting this part number is not yet available, however it is included in a Package Your
Way program for Kinetis MCUs. Please visit http://www.nxp.com/KPYW for more details.
2
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Related Resources
Description
Type
Selector
Guide
Resource
Selector Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KV10PB 1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV10P48M75RM 1
This document
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KMS User
Guide
The KMS User Guide provides a comprehensive description of the
features and functions of the Kinetis Motor Suite solution.
Kinetis Motor Suite User’s
Guide (KMS100UG) 1
KMS API
Reference
Manual
The KMS API reference manual provides a comprehensive description Kinetis Motor Suite API
of the API of the Kinetis Motor Suite function blocks.
Reference Manual
(KMS100RM)1
Chip Errata
The chip mask set Errata provides additional or corrective information
for a particular device mask set.
• KV10Z_1N81H1
• KINETIS_V_0N63P1
Package
drawing
Package dimensions are provided in package drawings.
• QFN 32-pin:
98ASA00473D1
• LQFP 32-pin:
98ASH70029A1
• LQFP 48-pin:
98ASH00962A1
• LQFP 64-pin:
98ASS23234W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
3
NXP Semiconductors
LEGEND
Not available on all parts. See ordering information table.
Figure 1. KV11 block diagram
4
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
Table of Contents
1
2
Ratings................................................................................ 6
3.6.2 CMP and 6-bit DAC electrical specifications....32
3.6.3 12-bit DAC electrical characteristics................ 34
3.7 Timers..........................................................................37
3.8 Communication interfaces........................................... 37
3.8.1 DSPI switching specifications (limited voltage
1.1 Thermal handling ratings............................................. 6
1.2 Moisture handling ratings.............................................6
1.3 ESD handling ratings................................................... 6
1.4 Voltage and current operating ratings..........................6
General............................................................................... 7
2.1 AC electrical characteristics.........................................7
2.2 Nonswitching electrical specifications..........................8
2.2.1 Voltage and current operating requirements....8
2.2.2 LVD and POR operating requirements............ 9
2.2.3 Voltage and current operating behaviors......... 10
2.2.4 Power mode transition operating behaviors.....10
2.2.5 KV11x Power consumption operating
range)...............................................................37
3.8.2 DSPI switching specifications (full voltage
range)...............................................................40
3.8.3 I2C................................................................... 44
3.8.4 UART............................................................... 44
Kinetis Motor Suite.............................................................. 44
Dimensions..........................................................................44
5.1 Obtaining package dimensions....................................44
Pinout.................................................................................. 45
6.1 KV11 Signal Multiplexing and Pin Assignments.......... 45
6.2 KV11 Pinouts............................................................... 48
Ordering parts..................................................................... 52
7.1 Determining valid orderable parts................................52
Part identification.................................................................52
8.1 Description...................................................................53
8.2 Format..........................................................................53
8.3 Fields........................................................................... 53
8.4 Example.......................................................................53
Terminology and guidelines................................................ 54
9.1 Definition: Operating requirement................................54
9.2 Definition: Operating behavior..................................... 54
9.3 Definition: Attribute.......................................................54
9.4 Definition: Rating..........................................................55
9.5 Result of exceeding a rating........................................ 55
9.6 Relationship between ratings and operating
4
5
behaviors......................................................... 11
6
2.2.6 EMC radiated emissions operating behaviors..17
2.2.7 Designing with radiated emissions in mind...... 18
2.2.8 Capacitance attributes..................................... 18
2.3 Switching specifications...............................................18
2.3.1 Device clock specifications.............................. 18
2.3.2 General switching specifications......................19
2.4 Thermal specifications................................................. 20
2.4.1 Thermal operating requirements......................20
2.4.2 Thermal attributes............................................ 20
Peripheral operating requirements and behaviors.............. 21
3.1 Core modules...............................................................21
3.1.1 SWD Electricals .............................................. 21
3.2 System modules.......................................................... 22
3.3 Clock modules............................................................. 22
3.3.1 MCG specifications.......................................... 22
3.3.2 Oscillator electrical specifications.................... 24
3.4 Memories and memory interfaces................................26
3.4.1 Flash electrical specifications...........................26
3.5 Security and integrity modules.....................................28
3.6 Analog..........................................................................28
3.6.1 ADC electrical specifications............................28
7
8
3
9
requirements................................................................56
9.7 Guidelines for ratings and operating requirements......56
9.8 Definition: Typical value...............................................57
9.9 Typical Value Conditions............................................. 58
10 Revision history...................................................................58
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
5
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human-body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
1.4 Voltage and current operating ratings
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NXP Semiconductors
General
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
Digital supply voltage
V
mA
V
IDD
Digital supply current
120
VDD + 0.31
VIO
Digital pin input voltage (except open drain pins)
Open drain pins (PTC6 and PTC7)
–0.3
–0.3
–25
5.5
V
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. Maximum value of VIO (except open drain pins) must be 3.8 V.
2 General
Electromagnetic compatibility (EMC) performance depends on the environment in
which the MCU resides. Board design and layout, circuit topology choices, location,
characteristics of external components, and MCU software operation play a significant
role in EMC performance.
See the following applications notes available on nxp.com for guidelines on
optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
7
NXP Semiconductors
General
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-5
—
—
V
Pin negative DC injection current—single pin
• VIN < VSS–0.3V
1
mA
Table continues on the next page...
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Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
General
Notes
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
IICcont
Contiguous pin DC injection current—regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
–25
1.2
—
—
mA
V
• Negative current injection
VRAM
VDD voltage required to retain RAM
1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed, then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/IICIO
.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
40
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
9
NXP Semiconductors
General
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad
All port pins, except PTC6 and PTC7
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH
Output high voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
All port pins
—
100
mA
—
—
0.5
0.5
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
VOL
Output low voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
—
—
0.5
0.5
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) for full temperature
range
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
41
μA
μA
1
1
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
RPU
20
50
2
1. Measured at VDD = 3.6 V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
10
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
General
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 75 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the
—
—
300
μs
1
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
123
123
67
4
132
132
72
5
μs
μs
μs
μs
μs
4
5
1. Normal boot FTFA_FOPT[LPBOOT]=11
2.2.5 KV11x Power consumption operating behaviors
Table 5. KV11x power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
1
IDDA
Analog supply current
—
—
5
mA
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
Target IDD
• at 1.8 V 50 MHz (25 MHz Bus)
• at 3.0 V 50 MHz (25 MHz Bus)
—
—
—
—
5.3
5.4
7.2
7.3
6.2
6.3
8.3
8.3
mA
mA
mA
mA
• at 1.8 V 75 MHz (25 MHz Bus)
• at 3.0 V 75 MHz (25 MHz Bus)
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
Target IDD
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
11
NXP Semiconductors
General
Table 5. KV11x power consumption operating behaviors (continued)
Symbol Description
• at 1.8 V 50 MHz
Min.
Typ.
Max.
Unit
Notes
—
8.5
9.7
mA
• at 3.0 V 50 MHz
• at 1.8 V 75 MHz
• at 3.0 V 75 MHz
—
—
—
—
8.5
11.6
11.7
4
9.8
13.0
13.2
—
mA
mA
mA
mA
IDD_WAIT Wait mode high frequency 75 MHz current at
3.0 V — all peripheral clocks disabled
—
—
IDD_WAIT Wait mode reduced frequency 50 MHz current
at 3.0 V — all peripheral clocks disabled
—
—
3.4
—
—
mA
μA
IDD_VLPR Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks disabled
268
4 MHz CPU
speed, 1
MHz bus
speed.
IDD_VLPR Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks enabled
—
—
—
437
—
—
—
μA
μA
μA
4 MHz CPU
speed, 1
MHz bus
speed.
IDD_VLPW Very-Low-Power Wait mode current at 3.0 V
— all peripheral clocks enabled
348.9
173.4
4 MHz CPU
speed, 1
MHz bus
speed.
IDD_VLPW Very-Low-Power Wait mode current at 3.0 V
— all peripheral clocks disabled
4 MHz CPU
speed, 1
MHz bus
speed.
IDD_STOP Stop mode current at 3.0 V
• -40 °C to 25 °C
—
—
—
—
—
—
—
—
247.2
260.7
286
286
300
312
353
494
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
μA
324
422.7
IDD_VLPS Very-Low-Power Stop mode current at 3.0 V
• -40 °C to 25 °C
—
—
—
—
—
2.9
6.8
3
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
5.9
13
39
86
15.4
29.1
66.4
μA
μA
IDD_VLLS3 Very-Low-Leakage Stop mode 3 current at 3.0
V
—
—
—
—
1.3
2
1.6
2.3
4.3
7.5
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
3.7
6.7
Table continues on the next page...
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Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
General
Table 5. KV11x power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• at 85 °C
—
15.1
16
• at 105 °C
IDD_VLLS1 Very-Low-Leakage Stop mode 1 current at 3.0
μA
—
V
—
—
—
—
—
0.8
1.2
2.2
4.0
9.4
1.2
1.4
• -40°C to 25°C
• at 50°C
• at 70°C
• at 85°C
• at 105°C
2.7
5.1
11.8
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• -40 °C to 25 °C
μA
—
—
—
—
—
—
0.279
0.638
1.63
3.4
0.386
0.854
2.2
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
4.5
8.9
11.2
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
• -40 °C to 25 °C
μA
2
—
—
—
—
—
0.098
0.448
1.4
0.452
0.674
1.9
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
3.19
8.47
4.3
10.6
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. No brownout
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
Table continues on the next page...
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NXP Semiconductors
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
440
440
510
510
490
490
560
560
540
540
560
560
560
560
560
560
570
570
610
610
580
580
680
680
VLLS1
VLLS3
VLPS
nA
µA
STOP
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
22
22
22
22
22
22
consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
µA
µA
µA
MCGIRCLK (4 MHz internal reference
clock)
214
237
246
254
260
268
OSCERCLK (4 MHz external crystal)
ISPI
SPI peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
MCGIRCLK (4 MHz internal reference
clock)
214
237
246
254
260
268
OSCERCLK (4 MHz external crystal)
II2C
I2C peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
MCGIRCLK (4 MHz internal reference
clock)
214
237
246
254
260
268
OSCERCLK (4 MHz external crystal)
Table continues on the next page...
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14
NXP Semiconductors
General
Unit
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
-40
25
50
70
85
105
IFTM
FTM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
µA
MCGIRCLK (4 MHz internal reference
clock)
150
150
150
150
150
150
OSCERCLK (4 MHz external crystal)
300
45
300
45
300
45
320
45
340
45
350
45
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366
366
366
366
366
366
IWDOG
WDOG peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
66
66
66
66
66
66
µA
MCGIRCLK (4 MHz internal reference
clock)
214
237
246
254
260
268
OSCERCLK (4 MHz external crystal)
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode (except for 75 MHz which is in FEE mode), and
BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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NXP Semiconductors
General
Figure 3. Run mode supply current vs. core frequency
16
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NXP Semiconductors
General
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
15
17
12
4
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
M
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
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NXP Semiconductors
General
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 75 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
High Speed run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
75
25
25
25
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
Table continues on the next page...
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Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
General
Notes
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fFTM
FTM clock
—
75
MHz
VLPR mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
1
LPTMR clock
25
16
25
16
External reference clock
fLPTMR_pin LPTMR clock
fLPTMR_ERCL LPTMR external reference clock
K
fosc_hi_2
Oscillator crystal or resonator frequency — high
—
16
MHz
frequency mode (high range) (MCG_C2[RANGE]=1x)
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
16
—
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
Fast slew rate
ns
2
3
—
—
8
7
ns
ns
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
Port rise and fall time
Slow slew rate
—
—
15
25
ns
ns
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (low drive) is 25pF.
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NXP Semiconductors
General
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Die junction temperature
Ambient temperature 1
TA
105
°C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type
Symb
ol
Description
64 LQFP
48
32
32
QFN
Unit
Notes
LQFP LQFP
Single-layer
(1S)
RθJA Thermal resistance,
junction to ambient
64
81
57
68
51
85
57
72
50
98
34
82
28
°C/W
1
(natural convection)
Four-layer
(2s2p)
RθJA Thermal resistance,
junction to ambient
46
52
39
°C/W
°C/W
°C/W
(natural convection)
Single-layer
(1S)
RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
Four-layer
(2s2p)
RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
—
—
—
RθJB Thermal resistance,
junction to board
28
15
2
35
25
7
33
25
7
14
2.5
8
°C/W
°C/W
°C/W
2
3
4
RθJC Thermal resistance,
junction to case
ΨJT Thermal characterization
parameter, junction to
package top outside
center (natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
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Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
Peripheral operating requirements and behaviors
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD Electricals
Table 13. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 5. Serial wire clock input timing
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NXP Semiconductors
Peripheral operating requirements and behaviors
SWD_CLK
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
SWD_DIO
J12
SWD_DIO
J11
Output data valid
SWD_DIO
Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 14. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
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Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0 - 70 °C
—
0.4
1.5
%fdco
1, 2
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
3
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS = 00,
20.97
MHz
3, 4
frequency range
DMX32 = 0)
640 × ffll_ref
Mid range (DRS = 01,
DMX32 = 0)
40
60
—
—
–
41.94
62.915
23.99
48
75
—
—
–
MHz
MHz
MHz
MHz
MHz
1280 × ffll_ref
Mid range (DRS = 10,
DMX32 = 0)
1920 x ffll_ref
5
fdco_t_DMX3 DCO output
Low range (DRS = 00,
DMX32 = 1)
frequency
2
6
732 × ffll_ref
Mid range (DRS = 01,
DMX32 = 1)
47.97
1464 × ffll_ref
Mid range (DRS = 10,
DMX32 = 1)
71.991
2197 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 75 MHz
—
—
180
—
—
1
ps
7
8
tfll_acquire FLL target frequency acquisition time
ms
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
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Peripheral operating requirements and behaviors
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or there is a change from FLL disabled (BLPE, BLPI) to FLL enabled
(FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
500
600
2.5
3
—
—
—
—
—
μA
μA
mA
mA
mA
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
10
—
1
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RS Series resistor — low-frequency, low-power
—
—
—
kΩ
mode (HGO=0)
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
—
200
—
—
—
kΩ
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
32
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
—
50
60
MHz
%
1, 2
40
50
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Table 16. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tcst Crystal startup time — 32 kHz low-frequency,
—
1000
—
ms
3, 4
low-power mode (HGO=0)
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 17. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
13
113
904
ms
ms
thversall
Erase All high-voltage time
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1.2 Flash timing specifications — commands
Table 18. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec2k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
1
1
—
45
μs
trdrsrc
tpgm4
tersscr
trd1all
trdonce
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
30
μs
1
65
145
114
0.9
30
μs
—
2
14
ms
ms
μs
—
1
—
1
tpgmonce Program Once execution time
100
140
—
—
μs
—
2
tersall
Erase All Blocks execution time
1150
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 19. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
12.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
8.0
mA
3.4.1.4 Reliability specifications
Table 20. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
27
NXP Semiconductors
ADC electrical specifications
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
3.6.1.1 16-bit ADC operating conditions
Table 21. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
Ground voltage Delta to VSS (VSS – VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
—
1200
Ksps
Continuous conversions
enabled, subsequent
conversion time
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NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
Table 21. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 7. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
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29
NXP Semiconductors
ADC electrical specifications
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
1.2
2.4
3.0
4.4
Typ.2
Max.
3.9
Unit
Notes
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC =
0
2.4
tADACK =
1/fADACK
4.0
6.1
MHz
MHz
MHz
MHz
• ADLPC = 1, ADHSC =
1
5.2
7.3
fADACK
6.2
9.5
• ADLPC = 0, ADHSC =
0
• ADLPC = 0, ADHSC =
1
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
—
0.7
–1.1 to
+1.9
–0.3 to 0.5
• <12-bit modes
• 12-bit modes
—
—
0.2
1.0
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
• <12-bit modes
—
0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN
VDDA
=
5
Quantization
error
0.5
ENOB
Effective number 16-bit differential mode
6, 7
of bits
• Avg = 32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.7
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise See ENOB
plus distortion
7
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic 16-bit differential mode
7, 8
distortion
• Avg = 32
—
—
–97
–91
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
16-bit differential mode
7, 8
dynamic range
82
100
—
dB
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NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
Typ.2
Max.
Unit
Notes
• Avg = 32
78
92
—
dB
16-bit single-ended mode
• Avg = 32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
9
VTEMP25 Temp sensor
voltage
25 °C
9
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. This data was collected with an external clock.
8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
9. ADC conversion clock < 3 MHz
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
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NXP Semiconductors
ADC electrical specifications
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 23. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
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NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
Table 23. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDDHS
Supply current, high-speed mode (EN = 1, PMODE =
1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN = 1, PMODE =
0)
—
—
20
μA
VAIN
VAIO
VH
Analog input voltage
VSS
—
—
—
VDD
20
V
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
mV
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
35
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20
ns
tDLS
Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80
100
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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NXP Semiconductors
ADC electrical specifications
CMP Hysteresis vs Vinn
90.00E-03
80.00E-03
70.00E-03
60.00E-03
50.00E-03
40.00E-03
30.00E-03
20.00E-03
10.00E-03
000.00E+00
HYSTCTR
Setting
0
1
2
3
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
CMP Hysteresis vs Vinn
180.00E-03
160.00E-03
140.00E-03
120.00E-03
HYSTCTR
Setting
100.00E-03
0
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00
-20.00E-03
1
2
3
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
34
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
ADC electrical specifications
3.6.3.1 12-bit DAC operating requirements
Table 24. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2 12-bit DAC operating behaviors
Table 25. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
150
μA
μA
μs
μs
μs
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
1
700
200
30
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08)—high-speed mode
—
—low-power mode
—
—
—
—
5
μs
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
100
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
—
—
—
VDACR
mV
LSB
LSB
LSB
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
35
NXP Semiconductors
ADC electrical specifications
Table 25. 12-bit DAC operating behaviors (continued)
Symbol Description
• High power (SPHP
• Low power (SPLP
Min.
Typ.
Max.
Unit
Notes
)
1.2
1.7
—
)
0.05
0.12
—
BW
3dB bandwidth
• High power (SPHP
• Low power (SPLP
kHz
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 12. Typical INL error vs. digital code
36
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
37
NXP Semiconductors
ADC electrical specifications
3.8.1 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 26. Master mode DSPI timing (limited voltage range)
Symbol Description
Operating voltage
Min.
Max.
Unit
V
Notes
2.7
3.6
Frequency of operation
25
MHz
ns
1
2
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
2 x tBUS
–
(tSCK/2) – 2
(tSCK/2) – 2
(tSCK/2) + 2
–
ns
DSPI_PCSn valid to DSPI_SCK
delay
ns
3
4
DS4
DSPI_SCK to DSPI_PCSn invalid
(tSCK/2) – 2
–
ns
delay
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Frequency of operation
–
8.7
ns
ns
–2
−
17
0
–
ns
–
ns
–
25
MHz
ns
5
2
DS1
DS2
DS3
DSPI_SCK output cycle time
2 x tBUS
(tSCK/2) – 2
(tSCK/2) – 2
–
DSPI_SCK output high/low time
(tSCK/2) + 2
–
ns
DSPI_PCSn valid to DSPI_SCK
ns
3
4
delay
DS4
DSPI_SCK to DSPI_PCSn invalid
(tSCK/2) – 2
–
ns
delay
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Frequency of operation
–
14.7
ns
ns
–2
−
17
0
–
ns
–
ns
–
37.5
MHz
ns
6
2
DS1
DS2
DS3
DSPI_SCK output cycle time
2 x tBUS
(tSCK/2) – 2
(tSCK/2) – 2
–
DSPI_SCK output high/low time
(tSCK/2) + 2
–
ns
DSPI_PCSn valid to DSPI_SCK
ns
3
4
delay
DS4
DSPI_SCK to DSPI_PCSn invalid
(tSCK/2) – 2
–
ns
delay
DS5
DS6
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
–
8.7
−
ns
ns
–2
Table continues on the next page...
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Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
Table 26. Master mode DSPI timing (limited voltage range) (continued)
Symbol Description
Min.
13
0
Max.
Unit
ns
Notes
DS7
DS8
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
–
–
ns
1. Normal pads
2. The SPI module is clocked by the system clock
3. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
4. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
5. Open Drain pads: SIN: PTC7, SOUT:PTC6
6. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 14. DSPI classic SPI timing — master mode
Table 27. Slave mode DSPI timing (limited voltage range)
Symbol
Description
Min.
Max.
Unit
V
Notes
Operating voltage
2.7
3.6
Frequency of operation
–
12.5
MHz
ns
1
2
DS9
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
4 x tBUS
–
DS10
DS11
DS12
DS13
DS14
DS15
DS16
(tSCK/2) – 2
(tSCK/2) + 2
ns
–
0
21
–
ns
ns
2.2
7
–
ns
–
ns
–
15
15
ns
DSPI_SS inactive to DSPI_SOUT not
driven
–
ns
Frequency of operation
–
12.5
MHz
ns
3
2
DS9
DS10
DS11
DS12
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
4 x tBUS
—
(tSCK/2) – 2
(tSCK/2) + 2
ns
–
0
27
–
ns
ns
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
39
NXP Semiconductors
ADC electrical specifications
Table 27. Slave mode DSPI timing (limited voltage range) (continued)
Symbol
DS13
DS14
DS15
DS16
Description
Min.
2.2
7
Max.
–
Unit
ns
Notes
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
–
ns
–
15
21
ns
DSPI_SS inactive to DSPI_SOUT not
driven
–
ns
Frequency of operation
–
18.75
MHz
ns
4
2
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
(tSCK/2) – 2
(tSCK/2) + 2
ns
–
0
17
–
ns
ns
2.2
7
–
ns
–
ns
–
15
11
ns
DSPI_SS inactive to DSPI_SOUT not
driven
–
ns
1. Normal pads
2. The SPI module is clocked by the system clock
3. Open Drain pads: SIN: PTC7, SOUT:PTC6
4. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
DS12
DS16
DS11
(CPOL=0)
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 15. DSPI classic SPI timing — slave mode
40
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
3.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 28. Master mode DSPI timing (full voltage range)
Symbol Description
Operating voltage
Min.
1.7
Max.
3.6
Unit
V
Notes
1
2
3
Frequency of operation
–
18.75
–
MHz
ns
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle
time
2 x tBUS
DSPI_SCK output
high/low time
(tSCK/2) – 4
(tSCK/2) + 4
ns
ns
ns
DSPI_PCSn valid to
DSPI_SCK delay
(tSCK/2) – 4
–
–
4
5
DSPI_SCK to
DSPI_PCSn invalid delay
(tSCK/2) – 4
DSPI_SCK to
DSPI_SOUT valid
–
–7.8
24
0
10
–
DSPI_SCK to
DSPI_SOUT invalid
ns
ns
ns
DSPI_SIN to DSPI_SCK
input setup
–
DSPI_SCK to DSPI_SIN
input hold
–
Frequency of operation
–
18.75
MHz
6
3
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle
time
2 x tBUS
–
ns
DSPI_SCK output
high/low time
(tSCK/2) – 4
(tSCK/2) + 4
ns
ns
ns
DSPI_PCSn valid to
DSPI_SCK delay
(tSCK/2) – 4
–
–
4
5
DSPI_SCK to
DSPI_PCSn invalid delay
(tSCK/2) – 4
DSPI_SCK to
DSPI_SOUT valid
–
–7.8
24
0
26
–
DSPI_SCK to
DSPI_SOUT invalid
ns
ns
ns
DSPI_SIN to DSPI_SCK
input setup
–
DSPI_SCK to DSPI_SIN
input hold
–
Table continues on the next page...
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
41
NXP Semiconductors
ADC electrical specifications
Table 28. Master mode DSPI timing (full voltage range) (continued)
Symbol Description
Frequency of operation
Min.
–
Max.
25
Unit
MHz
ns
Notes
7
3
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle
time
2 x tBUS
–
DSPI_SCK output
high/low time
(tSCK/2) – 4
(tSCK/2) + 4
ns
ns
ns
DSPI_PCSn valid to
DSPI_SCK delay
(tSCK/2) – 4
–
–
4
5
DSPI_SCK to
DSPI_PCSn invalid delay
(tSCK/2) – 4
DSPI_SCK to
DSPI_SOUT valid
–
–7.8
17
0
10
–
DSPI_SCK to
DSPI_SOUT invalid
ns
ns
ns
DSPI_SIN to DSPI_SCK
input setup
–
DSPI_SCK to DSPI_SIN
input hold
–
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. Normal pads
3. The SPI module is clocked by the system clock
4. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
5. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]
6. Open Drain pads: SIN: PTC7, SOUT:PTC6
7. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 16. DSPI classic SPI timing — master mode
Table 29. Slave mode DSPI timing (full voltage range)
Symbol
Description
Min.
1.7
–
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
9.375
MHz
1
Table continues on the next page...
42
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
ADC electrical specifications
Table 29. Slave mode DSPI timing (full voltage range) (continued)
Symbol
DS9
Description
Min.
Max.
Unit
ns
Notes
DSPI_SCK input cycle time
4 x tBUS
—
2
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Frequency of operation
(tSCK/2) – 4
(tSCK/2) + 4
ns
–
27.8
ns
0
–
ns
2.7
–
ns
7
–
ns
–
22
ns
–
22
ns
–
9.375
MHz
ns
3
2
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Frequency of operation
(tSCK/2) – 4
(tSCK/2) + 4
ns
–
0
43.8
ns
–
ns
2.7
7
–
ns
–
ns
–
22
ns
–
38
ns
12.5
MHz
ns
4
2
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
(tSCK/2) – 4
(tSCK/2) + 4
ns
–
0
20.8
–
ns
ns
2.7
7
–
ns
–
ns
–
22
15
ns
–
ns
1. Normal pads
2. The SPI module is clocked by the system clock
3. Open Drain pads: SIN: PTC7, SOUT:PTC6
4. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
43
NXP Semiconductors
Kinetis Motor Suite
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 17. DSPI classic SPI timing — slave mode
3.8.3 I2C
See General switching specifications.
3.8.4 UART
See General switching specifications.
4 Kinetis Motor Suite
Kinetis Motor Suite is a bundled software solution that enables the rapid configuration
of motor drive systems, and accelerates development of the final motor drive
application. Several members of the KV1x family are enabled with Kinetis motor suite.
The enabled devices can be identified within the orderable part numbers in this table.
For more information refer to Kinetis Motor Suite User's Guide (KMS100UG ) and
Kinetis Motor Suite API Reference Manual (KMS100RM, 1).
5 Dimensions
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
44
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Pinout
5.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ASA00473D
32-pin LQFP 1
48-pin LQFP
64-pin LQFP
98ASH70029A
98ASH00962A
98ASS23234W
1. The 32-pin LQFP package for this product is not yet available, however it is included in a Package Your Way program
for Kinetis MCUs. Please visit http://www.nxp.com/KPYW for more details.
6 Pinout
6.1 KV11 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, PTD7
are high current pins.
• PTC6 and PTC7 have open drain outputs
64
48
32
32
Pin Name
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP QFP
QFN LQFP
—
—
—
—
7
8
7
8
VDDA/
VREFH
VDDA/
VREFH
VDDA/
VREFH
VREFL/
VSSA
VREFL/
VSSA
VREFL/
VSSA
1
2
—
—
—
—
—
—
PTE0
ADC1_SE12 ADC1_SE12 PTE0
ADC1_SE13 ADC1_SE13 PTE1/
UART1_TX
UART1_RX
PTE1/
LLWU_P0
LLWU_P0
3
4
5
1
2
3
1
2
3
1
2
3
VDD
VDD
VSS
VDD
VSS
VSS
PTE16
ADC0_SE1/
ADC0_DP1/
ADC1_SE0
ADC0_SE1/
ADC0_DP1/
ADC1_SE0
PTE16
SPI0_PCS0
UART1_TX
FTM_
CLKIN0
FTM0_FLT3
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
45
NXP Semiconductors
Pinout
64
48
32
32
Pin Name
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP QFP
QFN LQFP
6
7
8
4
5
6
4
5
6
4
5
6
PTE17/
LLWU_P19
ADC0_DM1/ ADC0_DM1/ PTE17/
SPI0_SCK
UART1_RX
FTM_
CLKIN1
LPTMR0_
ALT3
ADC0_SE5/
ADC1_SE5
ADC0_SE5/
ADC1_SE5
LLWU_P19
PTE18/
LLWU_P20
ADC0_SE6/
ADC1_SE1/
ADC1_DP1
ADC0_SE6/
ADC1_SE1/
ADC1_DP1
PTE18/
LLWU_P20
SPI0_SOUT
SPI0_SIN
UART1_
CTS_b
I2C0_SDA
SPI0_SIN
PTE19
ADC0_SE7/
ADC1_SE7/
ADC1_DM1
ADC0_SE7/
ADC1_SE7/
ADC1_DM1
PTE19
UART1_
RTS_b
I2C0_SCL
SPI0_SOUT
9
7
8
—
—
—
—
PTE20
PTE21
ADC0_SE0/
ADC0_DP0
ADC0_SE0/
ADC0_DP0
PTE20
PTE21
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
10
ADC0_SE4/
ADC0_DM0
ADC0_SE4/
ADC0_DM0
11
12
13
14
15
16
17
—
—
9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
ADC0_SE12 ADC0_SE12 PTE22
ADC0_SE13 ADC0_SE13 PTE23
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
10
11
12
13
PTE29
CMP1_IN5/
CMP0_IN5
CMP1_IN5/
CMP0_IN5
PTE29
PTE30
FTM0_CH2
FTM0_CH3
FTM_
CLKIN0
18
14
9
9
PTE30
ADC1_SE4/
CMP1_IN4/
DAC0_OUT
ADC1_SE4/
CMP1_IN4/
DAC0_OUT
FTM_
CLKIN1
19
20
21
22
23
24
25
26
—
15
16
17
18
19
20
21
—
10
11
12
13
14
15
16
—
10
11
12
13
14
15
16
PTE31
PTE24
ADC0_SE14/ ADC0_SE14/ PTE31
CMP0_IN4
CMP0_IN4
DISABLED
PTE24
CAN0_TX
CAN0_RX
FTM0_CH0
FTM0_CH1
FTM0_CH5
FTM2_CH0
FTM2_CH1
FTM0_CH0
FTM0_CH1
I2C0_SCL
I2C0_SDA
EWM_IN
EWM_OUT_
b
PTE25/
LLWU_P21
DISABLED
SWD_CLK
DISABLED
DISABLED
SWD_DIO
NMI_b
PTE25/
LLWU_P21
EWM_IN
PTA0
PTA1
PTA2
PTA3
SWD_CLK
PTA0
PTA1
PTA2
PTA3
UART0_
CTS_b
SWD_CLK
FTM4_CH0
FTM4_CH1
SWD_DIO
NMI_b
UART0_RX
CMP0_OUT
CMP1_OUT
FTM2_FLT0
FTM4_FLT0
FTM5_FLT0
FTM2_QD_
PHA
FTM1_CH1
FTM1_CH0
UART0_TX
FTM2_QD_
PHB
SWD_DIO
NMI_b
UART0_
RTS_b
EWM_OUT_
b
PTA4/
LLWU_P3
PTA4/
FTM0_FLT3
LLWU_P3
27
28
—
—
—
—
—
—
PTA5
DISABLED
DISABLED
PTA5
FTM0_CH2
FTM1_CH0
PTA12
PTA12
CAN0_TX
CAN0_RX
FTM1_QD_
PHA
29
30
—
—
—
—
—
PTA13/
LLWU_P4
DISABLED
VDD
PTA13/
LLWU_P4
FTM1_CH1
FTM1_QD_
PHB
22
VDD
VDD
46
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
Pinout
64
48
32
32
Pin Name
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP QFP
QFN LQFP
31
32
23
24
—
—
VSS
VSS
VSS
17
17
PTA18
PTA19
PTA20
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM1_FLT0
FTM_
CLKIN0
FTM3_CH2
33
25
18
18
XTAL0
XTAL0
PTA19
PTA20
FTM0_FLT0
FTM_
CLKIN1
LPTMR0_
ALT1
34
35
26
27
19
20
19
20
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
UART0_RX
36
37
28
29
21
—
21
—
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
FTM0_FLT2
FTM0_FLT1
EWM_IN
FTM1_QD_
PHB
UART0_TX
PTB2
ADC0_SE10/ ADC0_SE10/ PTB2
ADC1_SE10/ ADC1_SE10/
UART0_
RTS_b
FTM0_FLT3
ADC1_DM2
ADC1_DM2
38
39
40
30
31
32
—
—
—
—
—
—
PTB3
ADC1_SE2/
ADC1_DP2
ADC1_SE2/
ADC1_DP2
PTB3
I2C0_SDA
UART0_
CTS_b
FTM0_FLT0
EWM_IN
PTB16
PTB17
DISABLED
PTB16
PTB17
UART0_RX
FTM_
CLKIN2
CAN0_TX
CAN0_RX
DISABLED
UART0_TX
FTM_
CLKIN1
EWM_OUT_
b
41
42
43
—
—
33
—
—
—
—
—
—
PTB18
PTB19
PTC0
DISABLED
DISABLED
PTB18
PTB19
CAN0_TX
CAN0_RX
SPI0_PCS4
FTM3_CH2
FTM3_CH3
ADC1_SE11 ADC1_SE11 PTC0
PDB_
EXTRG0
CMP0_OUT
FTM2_CH0
FTM2_CH1
CLKOUT
FTM0_FLT0
FTM3_FLT0
SPI0_PCS0
44
45
46
34
35
36
22
23
24
22
23
24
PTC1/
LLWU_P6
ADC1_SE3
ADC1_SE3
PTC1/
LLWU_P6
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
UART1_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
PTC2
ADC0_SE11/ ADC0_SE11/ PTC2
CMP1_IN0
UART1_
CTS_b
CMP1_IN0
PTC3/
CMP1_IN1
CMP1_IN1
PTC3/
UART1_RX
LLWU_P7
LLWU_P7
47
48
49
—
—
37
—
—
25
—
—
25
VSS
VDD
VSS
VSS
VDD
VDD
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
CMP1_OUT
CMP0_OUT
50
51
38
39
26
27
26
27
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
CMP0_IN1
PTC5/
LLWU_P9
LPTMR0_
ALT2
FTM0_CH2
I2C0_SCL
I2C0_SDA
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB_
EXTRG1
UART0_RX
UART0_TX
52
53
40
—
28
—
28
—
PTC7
PTC8
PTC7
ADC1_SE14/ ADC1_SE14/ PTC8
CMP0_IN2 CMP0_IN2
FTM3_CH4
FTM3_CH5
FTM5_CH0
54
55
—
—
—
—
—
—
PTC9
ADC1_SE15/ ADC1_SE15/ PTC9
CMP0_IN3 CMP0_IN3
PTC10
ADC1_SE16 ADC1_SE16 PTC10
FTM5_QD_
PHA
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
47
NXP Semiconductors
Pinout
64
48
32
32
Pin Name
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP QFP
QFN LQFP
56
57
58
59
—
41
42
43
—
—
—
—
—
—
—
—
PTC11/
LLWU_P11
ADC1_SE17 ADC1_SE17 PTC11/
LLWU_P11
FTM5_CH1
FTM5_QD_
PHB
PTD0/
LLWU_P12
DISABLED
ADC0_SE2
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART0_
CTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
UART1_RX
UART1_TX
FTM3_CH0
FTM3_CH1
FTM3_CH2
PTD1
ADC0_SE2
PTD1
UART0_
RTS_b
PTD2/
PTD2/
UART0_RX
I2C0_SCL
LLWU_P13
LLWU_P13
60
61
44
45
—
—
PTD3
DISABLED
DISABLED
PTD3
SPI0_SIN
UART0_TX
FTM0_CH3
FTM0_CH4
FTM3_CH3
EWM_IN
I2C0_SDA
29
29
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
SPI0_PCS0
62
63
64
46
47
48
30
31
32
30
31
32
PTD5
ADC0_SE3
ADC1_SE6
DISABLED
ADC0_SE3
ADC1_SE6
PTD5
SPI0_PCS2
FTM4_CH0
FTM4_CH1
UART0_
CTS_b
FTM0_CH5
FTM0_CH0
FTM0_CH1
EWM_OUT_ SPI0_SCK
b
PTD6/
LLWU_P15
PTD6/
LLWU_P15
UART0_RX
FTM0_FLT0
SPI0_SOUT
PTD7
PTD7
UART0_TX
FTM0_FLT1
SPI0_SIN
6.2 KV11 Pinouts
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
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NXP Semiconductors
Pinout
PTE0
PTE1/LLWU_P0
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
VSS
4
PTE16
5
PTC1/LLWU_P6
PTC0
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
6
7
PTB19
8
PTB18
PTE20
9
PTB17
PTE21
10
11
12
13
14
15
16
PTB16
PTE22
PTB3
PTE23
PTB2
VDDA
PTB1
VREFH
PTB0/LLWU_P5
PTA20
VREFL
VSSA
PTA19
Figure 18. 64 LQFP Pinout Diagram
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
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NXP Semiconductors
Pinout
PTC3/LLWU_P7
PTC2
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC1/LLWU_P6
PTC0
PTE16
3
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
4
PTB17
5
PTB16
6
PTE20
PTB3
7
PTE21
PTB2
8
VDDA
PTB1
9
VREFH
PTB0/LLWU_P5
PTA20
10
11
12
VREFL
VSSA
PTA19
Figure 19. 48 QFP Pinout Diagram
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NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
Pinout
PTC3/LLWU_P7
PTC2
VDD
VSS
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC1/LLWU_P6
PTB1
PTE16
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
PTB0/LLWU_P5
PTA20
VDDA/VREFH
VREFL/VSSA
PTA19
18
17
PTA18
Figure 20. 32 LQFP Pinout Diagram
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
51
NXP Semiconductors
Ordering parts
PTC3/LLWU_P7
PTC2
VDD
VSS
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC1/LLWU_P6
PTB1
PTE16
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
PTB0/LLWU_P5
PTA20
VDDA/VREFH
VREFL/VSSA
PTA19
18
17
PTA18
Figure 21. 32 QFN Pinout Diagram
7 Ordering parts
7.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.nxp.com and perform a part number search for the
MKV11 device numbers.
8 Part identification
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Part identification
8.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
8.2 Format
Part numbers for this device have the following format:
Q KV## M FFF R T PP CC S N
8.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KV##
M
Kinetis family
Key attribute
• KV10 and KV11
• Z = M0+ core
• 128 = 128 KB
• V = –40 to 105
FFF
T
Program flash memory size
Temperature range (°C)
Package identifier
PP
• LC = 32 LQFP (7 mm x 7 mm)
• FM = 32 QFN (5 mm x 5 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
CCC
S
Maximum CPU frequency (MHz)
Software type
• 7 = 75 MHz
• P = KMS-PMSM and BLDC
• (Blank) = Not software enabled
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
8.4 Example
This is an example part number:
MKV11Z128VFM7
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NXP Semiconductors
Terminology and guidelines
9 Terminology and guidelines
9.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
9.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
9.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
9.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
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NXP Semiconductors
Terminology and guidelines
9.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
9.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
9.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
9.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
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55
NXP Semiconductors
Terminology and guidelines
9.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
9.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
9.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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NXP Semiconductors
Terminology and guidelines
9.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
9.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
9.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
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57
NXP Semiconductors
Revision history
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
9.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
10 Revision history
The following table provides a revision history for this document.
Table 30. Revision history
Rev. No.
Date
Substantial Changes
Initial Prelim release.
0
1
11/2014
02/2015
Updated the following sections:
• DSPI switching specifications (limited voltage range)
• DSPI switching specifications (full voltage range)
• KV11 Signal Multiplexing and Pin Assignments
Table continues on the next page...
58
NXP Semiconductors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
Revision history
Table 30. Revision history (continued)
Rev. No.
Date
Substantial Changes
2
04/2015
Updated the following sections:
• Power mode transition operating behaviors
• Power consumption operating behaviors
• 16-bit ADC operating conditions
• Fields
• Updated the table "16-bit ADC electrical characteristics" with a
footnote
• Added the figure "Run mode supply current vs. core frequency" to
the section "Diagram: Typical IDD_RUN operating behavior"
3
4
06/2015
05/2017
• Added a footnote to the ambient temperature entry in the table
"Thermal operating requirements"
• Added KMS related information in front matter
• Added the section "KMS Motor Suite"
• Added "S" in the sections "Format" and "Fields" to specify software
type in part number
• Updated the section "Example" to add an example for KMS part
number
• Added the KMS supported part numbers in the table "Ordering
information"
• Updated the table "Related resources," to include references to
KMS documents
• Updated the figure "KV11 block diagram"
• Added a note to the tPOR in the table "Power mode transition
operating behaviors."
• Changed freescale.com to nxp.com throughout
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59
NXP Semiconductors
How to Reach Us:
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
Freescale, NXP, the NXP logo, and Kinetis are trademarks of NXP B.V. All other
product or service names are the property of their respective owners. ARM and
Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU
and/or elsewhere. SpinTAC is a trademark of LineStream Technologies, Inc. All
rights reserved.
©2014-2017 NXP B.V.
Document Number KV11P64M75
Revision 4, 05/2017
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