935318642557 [NXP]
RISC Microcontroller;
| 型号： | 935318642557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总83页 (文件大小：1557K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5602D
Rev. 6, 01/2013
MPC5602D
100 LQFP
14 mm x 14 mm
64 LQFP
10 mm x 10 mm
MPC5602D Microcontroller
Data Sheet
•
•
Up to 79 configurable general purpose pins
supporting input and output operations (package
dependent)
•
Single issue, 32-bit CPU core complex (e200z0h)
®
— Compliant with the Power Architecture
embedded category
Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
•
Up to 4 periodic interrupt timers (PIT) with 32-bit
counter resolution
instructions, it is possible to achieve significant
code size footprint reduction.
•
•
1 System Timer Module (STM)
•
Up to 256 KB on-chip Code Flash supported with
Flash controller and ECC
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class 1 standard
•
•
•
64 KB on-chip Data Flash with ECC
Up to 16 KB on-chip SRAM with ECC
•
•
Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
Interrupt controller (INTC) with multiple interrupt
vectors, including 20 external interrupt sources and
18 external interrupt/wakeup sources
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
•
•
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, Flash, or SRAM from multiple bus
masters
•
•
Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
•
Up to 33 channel 12-bit analog-to-digital converter
(ADC)
•
•
2 serial peripheral interface (DSPI) modules
3 serial communication interface (LINFlex) modules
— LINFlex 1 and 2: Master capable
— LINFlex 0: Master capable and slave capable;
connected to eDMA
•
1 enhanced full CAN (FlexCAN) module with
configurable buffers
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2009–2013. All rights reserved.
Table of Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1
4.10 Power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.11 Flash memory electrical characteristics. . . . . . . . . . . . 42
4.11.1 Program/Erase characteristics. . . . . . . . . . . . . 42
4.11.2 Flash power supply DC characteristics . . . . . . 44
4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 45
4.12 Electromagnetic compatibility (EMC) characteristics. . 45
4.12.1 Designing hardened software to avoid
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Pad configuration during reset phases . . . . . . . . . . . . . .9
3.3 Voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .22
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field
2
3
noise problems. . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 46
4.12.3 Absolute maximum ratings (electrical sensitivity)46
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 51
4.15 Fast internal RC oscillator (16 MHz) electrical
4
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 54
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.17.2 Input impedance and ADC accuracy . . . . . . . . 55
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 60
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 62
4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 63
4.18.3 JTAG characteristics . . . . . . . . . . . . . . . . . . . . 70
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 70
5.1.1 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.2 64 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.3 NVUSRO[WATCHDOG_EN] field description . .22
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .22
4.5 Recommended operating conditions . . . . . . . . . . . . . .23
4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .26
4.6.1 Package thermal characteristics . . . . . . . . . . . .26
4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . .26
4.7 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .27
4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.7.2 I/O input DC characteristics. . . . . . . . . . . . . . . .27
4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .28
4.7.4 Output pin transition times. . . . . . . . . . . . . . . . .31
4.7.5 I/O pad current specification . . . . . . . . . . . . . . .31
4.8 RESET electrical characteristics. . . . . . . . . . . . . . . . . .35
4.9 Power management electrical characteristics. . . . . . . .37
4.9.1 Voltage regulator electrical characteristics . . . .37
4.9.2 Low voltage detector electrical characteristics .40
5
6
7
MPC5602D Microcontroller Data Sheet, Rev. 6
2
Freescale Semiconductor
Introduction
1
Introduction
1.1
Document overview
This document describes the device features and highlights the important electrical and physical characteristics.
1.2
Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the
development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control
and seat control applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power
Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing
improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access
memory (SRAM) and internal flash memory.
Table 1. MPC5602D device comparison
Device
Feature
MPC5601DxLH
MPC5601DxLL
MPC5602DxLH
MPC5602DxLL
CPU
e200z0h
Execution speed
Code flash memory
Data flash memory
SRAM
Static – up to 48 MHz
64 KB (4 × 16 KB)
16 ch
128 KB
12 KB
256 KB
16 KB
eDMA
ADC (12-bit)
CTU
16 ch
33 ch
16 ch
33 ch
16 ch
Total timer I/O1
eMIOS
14 ch, 16-bit
28 ch, 16-bit
14 ch, 16-bit
28 ch, 16-bit
• Type X2
• Type Y3
• Type G4
• Type H5
SCI (LINFlex)
SPI (DSPI)
CAN (FlexCAN)
GPIO6
2 ch
—
5 ch
9 ch
7 ch
7 ch
2 ch
—
5 ch
9 ch
7 ch
7 ch
7 ch
4 ch
7 ch
4 ch
3
2
1
45
79
45
79
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
3
Block diagram
Table 1. MPC5602D device comparison (continued)
Device
Feature
MPC5601DxLH
MPC5601DxLL
MPC5602DxLH
MPC5602DxLL
Debug
JTAG
Package
64 LQFP
100 LQFP
64 LQFP
100 LQFP
1
Refer to eMIOS chapter of device reference manual for information on the channel configuration and functions.
Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC
Type Y = OPWMT + OPWMB + SAIC + SAOC
2
3
4
5
6
Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC
Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC
I/O count based on multiplexing with peripherals
2
Block diagram
Figure 1 shows a top-level block diagram of the MPC5602D device series.
MPC5602D Microcontroller Data Sheet, Rev. 6
4
Freescale Semiconductor
Block diagram
SRAM
16 KB
Code Flash
256 KB
Data Flash
64 KB
JTAG
JTAG Port
Instructions
(Master)
SRAM
Controller
Flash
Controller
Nexus 1
e200z0h
Data
NMI
(Slave)
(Master)
SIUL
Voltage
Regulator
(Slave)
Interrupt requests
from peripheral
blocks
(Slave)
NMI
(Master)
eDMA
INTC
Clocks
CMU
FMPLL
RTC
MC_RGM MC_CGM MC_ME MC_PCU
SSCM
STM
PIT
BAM
SWT
ECSM
Peripheral Bridge
SIUL
1 x
eMIOS
3 x
LINFlex
2 x
DSPI
1 x
FlexCAN
33 ch.
ADC
WKPU
CTU
Reset Control
Interrupt
Request
External
Interrupt
Request
IMUX
Interrupt
Request
GPIO &
Pad Control
. . .
. . .
. . .
. . .
I/O
Legend:
ADC
BAM
Analog-to-Digital Converter
Boot Assist Module
MC_CGM Clock Generation Module
MC_ME Mode Entry Module
CMU
CTU
Clock Monitor Unit
Cross Triggering Unit
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
DSPI
ECSM
eDMA
eMIOS
Flash
Deserial Serial Peripheral Interface
Error Correction Status Module
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Flash memory
NMI
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
XBAR
Non-Maskable Interrupt
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Crossbar switch
FlexCAN Controller Area Network (FlexCAN)
FMPLL
IMUX
INTC
JTAG
Frequency-Modulated Phase-Locked Loop
Internal Multiplexer
Interrupt Controller
JTAG controller
LINFlex
Serial Communication Interface (LIN support)
Figure 1. MPC5602D series block diagram
Table 2 summarizes the functions of all blocks present in the MPC5602D series of microcontrollers. Please note that the
presence and number of blocks varies by device and package.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
5
Block diagram
Table 2. MPC5602D series block summary
Function
Block
Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to-digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Cross triggering unit (CTU)
Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices
(DSPI)
Enhanced direct memory access Performs complex data transfers with minimal intervention from a host processor
(eDMA)
via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
Generates high-speed system clocks and supports programmable frequency
phase-locked loop (FMPLL)
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Interrupt controller (INTC)
JTAG controller (JTAGC)
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-maskable interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Periodic interrupt timer (PIT)
Power control unit (MC_PCU)
Produces periodic interrupts and triggers
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
MPC5602D Microcontroller Data Sheet, Rev. 6
6
Freescale Semiconductor
Package pinouts and signal descriptions
Table 2. MPC5602D series block summary (continued)
Block
Function
Real-time counter (RTC)
Provides a free-running counter and interrupt generation capability that can be
used for timekeeping applications
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration Provides system configuration and status data (such as memory size and status,
module (SSCM)
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR (Automotive
Open System Architecture) and operating system tasks
Software watchdog timer (SWT) Provides protection from runaway code
Wakeup unit (WKPU) Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup events.
3
Package pinouts and signal descriptions
3.1
Package pinouts
The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please refer to Table 5.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
7
Package pinouts and signal descriptions
Figure 2 shows the MPC5602D in the 100 LQFP package.
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
9
PE[9]
PE[10]
PA[0]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
Figure 2. 100 LQFP pin configuration (top view)
MPC5602D Microcontroller Data Sheet, Rev. 6
8
Freescale Semiconductor
Package pinouts and signal descriptions
Figure 3 shows the MPC5602D in the 64 LQFP package.
PB[3]
PC[9]
PA[2]
PA[1]
PA[0]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[10]
PB[0]
PA[3]
PB[15]
PB[14]
PB[13]
PB[12]
PB[11]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC
VSS_HV_ADC
64 LQFP
9
10
11
12
13
14
15
16
PB[1]
PC[6]
Figure 3. 64 LQFP pin configuration (top view)
3.2
Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
•
•
•
•
•
•
PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
PA[8] (ABS[0]) is pull-up.
RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
JTAG pads (TCK, TMS and TDI) are pull-up while TDO remains tristate.
Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
Main oscillator pads (EXTAL, XTAL) are tristate.
3.3
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
9
Package pinouts and signal descriptions
Table 3. Voltage supply pin descriptions
Pin number
Port pin
Function
64 LQFP
100 LQFP
VDD_HV Digital supply voltage
VSS_HV Digital ground
7, 28, 34, 56
6, 8, 26, 33, 55
11, 23, 57
15, 37, 52, 70, 84
14, 16, 35, 51, 69, 83
19, 32, 85
VDD_LV 1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VSS_LV pin.1
VSS_LV 1.2V decoupling pins. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV pin.1
10, 24, 58
18, 33, 86
VDD_BV Internal regulator supply voltage
12
20
1
A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable
voltage (see the recommended operating conditions in the device datasheet for details).
3.4
Pad types
In the device the following types of pads are available for system pins and functional port pins:
1
S = Slow
1 2
M = Medium
1 2
F = Fast
1
I = Input only with analog feature
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
3.5
System pins
The system pins are listed in Table 4.
Table 4. System pin descriptions
Pin number
I/O
RESET
configuration
Port pin
Function
Pad type
direction
64 LQFP 100 LQFP
RESET Bidirectional reset with Schmitt-Trigger
characteristics and noise filter.
I/O
I/O
M
Input, weak
pull-up only
after PHASE2
9
17
EXTAL Analog output of the oscillator amplifier circuit,
when the oscillator is not in bypass mode.
Analog input for the clock generator when the
oscillator is in bypass mode.1
X
Tristate
27
36
XTAL Analog input of the oscillator amplifier circuit.
Needs to be grounded if oscillator is used in
bypass mode.1
I
X
Tristate
25
34
1
Refer to the relevant section of the device datasheet.
1. See the I/O pad electrical characteristics in the device datasheet for details.
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see the
PCR[SRC] description in the device reference manual).
MPC5602D Microcontroller Data Sheet, Rev. 6
10
Freescale Semiconductor
Package pinouts and signal descriptions
3.6
Functional ports
The functional port pins are listed in Table 5.
Table 5. Functional port pin descriptions
Pin number
Alternate
I/O
Pad
Port pin
PA[0]
PCR
Function
Peripheral
function1
direction2 type
64 LQFP 100 LQFP
Port A
PCR[0]
PCR[1]
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19]3
SIUL
eMIOS_0
CGL
eMIOS_0
WKPU
I/O
I/O
O
I/O
I
M
S
Tristate
Tristate
5
4
12
7
PA[1]
AF0
AF1
AF2
AF3
—
GPIO[1]
E0UC[1]
—
SIUL
eMIOS_0
—
—
WKPU
WKPU
I/O
I/O
—
—
I
—
NMI4
—
WKPU[2]3
I
PA[2]
PA[3]
PCR[2]
PCR[3]
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
SIUL
eMIOS_0
—
ADC
WKPU
I/O
I/O
—
O
S
S
Tristate
Tristate
3
5
MA[2]
WKPU[3]3
I
AF0
AF1
AF2
AF3
—
GPIO[3]
E0UC[3]
—
CS4_0
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
—
DSPI_0
SIUL
I/O
I/O
—
I/O
I
43
68
—
ADC
I
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
GPIO[4]
E0UC[4]
—
SIUL
eMIOS_0
—
DSPI_1
WKPU
I/O
I/O
—
I/O
I
S
Tristate
20
29
CS0_1
WKPU[9]3
PA[5]
PA[6]
PCR[5]
PCR[6]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
—
SIUL
eMIOS_0
—
I/O
I/O
—
M
S
Tristate
Tristate
51
52
79
80
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
SIUL
eMIOS_0
—
DSPI_1
SIUL
I/O
I/O
—
I/O
I
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
11
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PA[7]
PCR[7]
AF0
AF1
AF2
AF3
—
GPIO[7]
E0UC[7]
—
SIUL
eMIOS_0
—
—
SIUL
ADC
I/O
I/O
—
—
I
S
S
Tristate
44
45
71
72
—
EIRQ[2]
ADC1_S[1]
—
I
PA[8]
PA[9]
PCR[8]
PCR[9]
AF0
AF1
AF2
AF3
—
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
I/O
I/O
—
—
I
Input, weak
pull-up
N/A5
I
AF0
AF1
AF2
AF3
N/A5
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
I/O
I/O
—
I/O
I
S
S
S
Pull-down
Tristate
46
47
48
73
74
75
PA[10] PCR[10]
PA[11] PCR[11]
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
—
LIN2TX
ADC1_S[2]
SIUL
eMIOS_0
—
LINFlex_2
ADC
I/O
I/O
—
O
I
AF0
AF1
AF2
AF3
—
GPIO[11]
E0UC[11]
—
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
Tristate
—
EIRQ[16]
ADC1_S[3]
LIN2RX
—
—
ADC
LINFlex_2
I
I
PA[12] PCR[12]
AF0
AF1
AF2
AF3
—
GPIO[12]
—
SIUL
—
—
—
SIUL
DSPI_0
I/O
—
—
—
I
S
Tristate
22
31
—
—
EIRQ[17]
SIN_0
—
I
PA[13] PCR[13]
PA[14] PCR[14]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
—
SIUL
DSPI_0
—
I/O
O
—
M
M
Tristate
Tristate
21
19
30
28
CS3_1
DSPI_1
I/O
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
MPC5602D Microcontroller Data Sheet, Rev. 6
12
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PA[15] PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
I/O
I/O
I/O
I
M
Tristate
18
27
E0UC[1]
WKPU[10]3
Port B
PB[0] PCR[16]
PB[1] PCR[17]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
—
SIUL
FlexCAN_0
—
I/O
O
—
O
M
S
Tristate
Tristate
14
15
23
24
LIN2TX
LINFlex_2
AF0
AF1
AF2
AF3
—
GPIO[17]
—
SIUL
—
—
I/O
—
—
I
—
LIN0RX
LINFlex_0
WKPU
WKPU[4]3
I
—
CAN0RX FlexCAN_0
I
PB[2] PCR[18]
PB[3] PCR[19]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
—
SIUL
LINFlex_0
—
I/O
O
—
—
M
S
Tristate
Tristate
64
1
100
1
—
—
AF0
AF1
AF2
AF3
—
GPIO[19]
SIUL
—
—
I/O
—
—
—
I
—
—
—
—
WKPU[11]3
LIN0RX
WKPU
LINFlex_0
—
I
PB[4] PCR[20]
PB[5] PCR[21]
PB[6] PCR[22]
AF0
AF1
AF2
AF3
—
GPIO[20]
SIUL
—
—
—
ADC
I
I
I
I
Tristate
Tristate
Tristate
32
35
36
50
53
54
—
—
—
—
—
—
I
ADC1_P[0]
AF0
AF1
AF2
AF3
—
GPIO[21]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[1]
AF0
AF1
AF2
AF3
—
GPIO[22]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[2]
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
13
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PB[7] PCR[23]
PB[8] PCR[24]
AF0
AF1
AF2
AF3
—
GPIO[23]
SIUL
—
—
—
ADC
I
I
I
Tristate
Tristate
37
30
55
39
—
—
—
—
—
—
I
ADC1_P[3]
AF0
AF1
AF2
AF3
—
GPIO[24]
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
—
—
—
ADC1_S[4]
—
WKPU[25]3
I
PB[9] PCR[25]
PB[10] PCR[26]
AF0
AF1
AF2
AF3
—
GPIO[25]
SIUL
—
—
—
ADC
WKPU
I
—
—
—
I
I
Tristate
Tristate
29
31
38
40
—
—
—
ADC1_S[5]
—
WKPU[26]3
I
AF0
AF1
AF2
AF3
—
GPIO[26]
SIUL
—
—
—
ADC
WKPU
I/O
—
—
—
I
J
—
—
—
ADC1_S[6]
—
WKPU[8]3
I
PB[11] PCR[27]
PB[12] PCR[28]
PB[13] PCR[29]
PB[14] PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC1_S[12]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
I/O
I
J
J
J
J
Tristate
Tristate
Tristate
Tristate
38
39
40
41
59
61
63
65
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC1_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC1_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC1_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
I
MPC5602D Microcontroller Data Sheet, Rev. 6
14
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PB[15] PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC1_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC
I/O
I/O
—
O
J
Tristate
42
67
I
Port C
PC[0]6 PCR[32]
PC[1]6 PCR[33]
PC[2] PCR[34]
AF0
AF1
AF2
AF3
GPIO[32]
SIUL
—
JTAGC
—
I/O
—
I
M
F
Input, weak
pull-up
59
54
50
87
82
78
—
TDI
—
—
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
Tristate
Tristate
—
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
—
—
EIRQ[5]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
M
PC[3] PCR[35]
PC[4] PCR[36]
AF0
AF1
AF2
AF3
—
GPIO[35]
CS0_1
MA[0]
—
EIRQ[6]
SIUL
DSPI_1
ADC
—
SIUL
I/O
I/O
O
—
I
S
Tristate
Tristate
49
62
77
92
AF0
AF1
AF2
AF3
—
GPIO[36]
—
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
M
—
—
SIN_1
EIRQ[18]
—
I
PC[5] PCR[37]
PC[6] PCR[38]
AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
M
S
Tristate
Tristate
61
16
91
25
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
—
SIUL
LINFlex_1
—
I/O
O
—
—
—
—
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
15
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PC[7] PCR[39]
AF0
AF1
AF2
AF3
—
GPIO[39]
SIUL
—
—
I/O
—
—
—
I
S
Tristate
17
26
—
—
—
—
LIN1RX
LINFlex_1
WKPU
—
WKPU[12]3
I
PC[8] PCR[40]
PC[9] PCR[41]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
—
SIUL
LINFlex_2
eMIOS_0
—
I/O
O
I/O
—
S
S
Tristate
Tristate
63
2
99
2
AF0
AF1
AF2
AF3
—
GPIO[41]
—
E0UC[7]
—
SIUL
—
eMIOS_0
—
LINFlex_2
WKPU
I/O
—
I/O
—
I
LIN2RX
—
WKPU[13]3
I
PC[10] PCR[42]
PC[11] PCR[43]
AF0
AF1
AF2
AF3
GPIO[42]
—
—
MA[1]
SIUL
—
—
I/O
—
—
O
M
S
Tristate
Tristate
13
—
22
21
ADC
AF0
AF1
AF2
AF3
—
GPIO[43]
—
SIUL
—
—
ADC
WKPU
I/O
—
—
O
—
MA[2]
WKPU[5]3
I
PC[12] PCR[44]
AF0
AF1
AF2
AF3
—
GPIO[44]
E0UC[12]
—
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
—
97
—
EIRQ[19]
PC[13] PCR[45]
PC[14] PCR[46]
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
—
SIUL
eMIOS_0
—
I/O
I/O
—
S
S
Tristate
Tristate
—
—
98
3
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
—
—
EIRQ[8]
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
PC[15] PCR[47]
AF0
AF1
AF2
AF3
—
GPIO[47]
E0UC[15]
—
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
M
Tristate
—
4
—
EIRQ[20]
MPC5602D Microcontroller Data Sheet, Rev. 6
16
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
Port D
PD[0] PCR[48]
AF0
AF1
AF2
AF3
—
GPIO[48]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
I
I
Tristate
Tristate
—
—
41
42
—
—
—
WKPU[27]3
ADC1_P[4]
—
I
PD[1] PCR[49]
AF0
AF1
AF2
AF3
—
GPIO[49]
SIUL
—
—
—
WKPU
ADC
I
—
—
—
I
—
—
—
WKPU[28]3
ADC1_P[5]
—
I
PD[2] PCR[50]
PD[3] PCR[51]
PD[4] PCR[52]
PD[5] PCR[53]
PD[6] PCR[54]
PD[7] PCR[55]
AF0
AF1
AF2
AF3
—
GPIO[50]
SIUL
—
—
—
ADC
I
I
I
I
I
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
43
44
45
46
47
48
—
—
—
—
—
—
I
ADC1_P[6]
AF0
AF1
AF2
AF3
—
GPIO[51]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[7]
AF0
AF1
AF2
AF3
—
GPIO[52]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[8]
AF0
AF1
AF2
AF3
—
GPIO[53]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[9]
AF0
AF1
AF2
AF3
—
GPIO[54]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[10]
AF0
AF1
AF2
AF3
—
GPIO[55]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[11]
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
17
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PD[8] PCR[56]
PD[9] PCR[57]
PD[10] PCR[58]
PD[11] PCR[59]
PD[12] PCR[60]
PD[13] PCR[61]
PD[14] PCR[62]
PD[15] PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[56]
SIUL
—
—
—
ADC
I
I
I
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
—
—
—
—
—
—
—
—
49
56
57
58
60
62
64
66
—
—
—
—
—
—
I
ADC1_P[12]
AF0
AF1
AF2
AF3
—
GPIO[57]
SIUL
—
—
—
ADC
I
—
—
—
—
—
—
I
ADC1_P[13]
AF0
AF1
AF2
AF3
—
GPIO[58]
SIUL
—
—
—
ADC
I
I
—
—
—
—
—
—
I
ADC1_P[14]
AF0
AF1
AF2
AF3
—
GPIO[59]
SIUL
—
—
—
ADC
I
I
—
—
—
—
—
—
I
ADC1_P[15]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
I
J
J
J
J
ADC1_S[8]
ADC
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
SIUL
DSPI_1
eMIOS_0
—
I/O
I/O
I/O
—
I
ADC1_S[9]
ADC
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
SIUL
DSPI_1
eMIOS_0
—
I/O
O
I/O
—
I
ADC1_S[10]
ADC
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
SIUL
DSPI_1
eMIOS_0
—
I/O
O
I/O
—
I
ADC1_S[11]
ADC
Port E
MPC5602D Microcontroller Data Sheet, Rev. 6
18
Freescale Semiconductor
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PE[0] PCR[64]
AF0
AF1
AF2
AF3
—
GPIO[64]
E0UC[16]
—
SIUL
eMIOS_0
—
—
WKPU
I/O
I/O
—
—
I
S
Tristate
—
6
—
WKPU[6]3
PE[1] PCR[65]
PE[2] PCR[66]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
—
SIUL
eMIOS_0
—
I/O
I/O
—
M
M
Tristate
Tristate
—
—
8
—
—
—
AF0
AF1
AF2
AF3
—
GPIO[66]
E0UC[18]
—
SIUL
eMIOS_0
—
—
SIUL
I/O
I/O
—
—
I
89
—
EIRQ[21]
SIN_1
—
DSPI_1
I
PE[3] PCR[67]
PE[4] PCR[68]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
M
M
Tristate
Tristate
—
—
90
93
—
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
I/O
—
I
EIRQ[9]
SIUL
PE[5] PCR[69]
PE[6] PCR[70]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
SIUL
eMIOS_0
DSPI_1
ADC
I/O
I/O
I/O
O
M
M
Tristate
Tristate
—
—
94
95
MA[2]
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC
I/O
I/O
O
O
I
SIUL
PE[7] PCR[71]
PE[8] PCR[72]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC
I/O
I/O
O
O
I
M
M
Tristate
Tristate
—
—
96
9
SIUL
AF0
AF1
AF2
AF3
GPIO[72]
—
E0UC[22]
—
SIUL
—
eMIOS_0
—
I/O
—
I/O
—
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
19
Package pinouts and signal descriptions
Table 5. Functional port pin descriptions (continued)
Pin number
Alternate
function1
I/O
Pad
Port pin
PCR
Function
Peripheral
direction2 type
64 LQFP 100 LQFP
PE[9] PCR[73]
PE[10] PCR[74]
PE[11] PCR[75]
PE[12] PCR[76]
AF0
AF1
AF2
AF3
—
GPIO[73]
—
SIUL
—
eMIOS_0
—
I/O
—
I/O
—
I
S
S
S
S
Tristate
Tristate
Tristate
Tristate
—
—
—
—
10
11
13
76
E0UC[23]
—
WKPU[7]3
WKPU
AF0
AF1
AF2
AF3
—
GPIO[74]
—
CS3_1
—
SIUL
—
DSPI_1
—
I/O
—
O
—
I
EIRQ[10]
SIUL
AF0
AF1
AF2
AF3
—
GPIO[75]
E0UC[24]
CS4_1
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
I
—
WKPU[14]3
WKPU
AF0
AF1
AF2
AF3
—
GPIO[76]
—
SIUL
—
—
—
ADC
SIUL
I/O
—
—
—
I
—
—
ADC1_S[7]
EIRQ[11]
—
I
Port H
PH[9]6 PCR[121]
PH[10]6 PCR[122]
AF0
AF1
AF2
AF3
GPIO[121]
SIUL
—
JTAGC
—
I/O
—
I
S
S
Input, weak
pull-up
60
53
88
81
—
TCK
—
—
AF0
AF1
AF2
AF3
GPIO[122]
SIUL
—
JTAGC
—
I/O
—
I
Input, weak
pull-up
—
TMS
—
—
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00 AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF3. This is intended to select
the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the
values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
2
3
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
All WKPU pins also support external interrupt capability. See “wakeup unit” chapter of the device reference manual
for further details.
4
5
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
“Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of
the device reference manual for details.
MPC5602D Microcontroller Data Sheet, Rev. 6
20
Freescale Semiconductor
Electrical characteristics
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
6
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1 2001.
4
Electrical characteristics
4.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This can be done by the
DD
SS
internal pull-up or pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 6 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 6. Parameter classifications
Classification tag
Tag description
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.3
NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical
parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after
reset).
For a detailed description of the NVUSRO register, please refer to the device reference manual.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
21
Electrical characteristics
4.3.1
NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 7 shows how NVUSRO[PAD3V5V] controls
the device configuration.
Table 7. PAD3V5V field description
Value1
Description
0
1
High voltage supply is 5.0 V
High voltage supply is 3.3 V
1
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 8 shows how
NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Table 8. OSCILLATOR_MARGIN field description
Value1
Description
0
1
Low consumption configuration (4 MHz/8 MHz)
High margin configuration (4 MHz/16 MHz)
1
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.3.3
NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 8 shows how
NVUSRO[WATCHDOG_EN] controls the device configuration.
Table 9. WATCHDOG_EN field description
Value1
Description
0
1
Disable after reset)
Enable after reset
1
Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
4.4
Absolute maximum ratings
Table 10. Absolute maximum ratings
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VSS
VDD
SR Digital ground on VSS_HV pins
—
—
0
0
V
V
SR Voltage on VDD_HV pins with respect to
0.3
6.0
ground (VSS
)
VSS_LV SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS
—
VSS 0.1 VSS + 0.1
V
)
MPC5602D Microcontroller Data Sheet, Rev. 6
22
Freescale Semiconductor
Electrical characteristics
Table 10. Absolute maximum ratings (continued)
Value
Unit
Symbol
Parameter
Conditions
Min
Max
VDD_BV SR Voltage on VDD_BV (regulator supply) pin
with respect to ground (VSS
—
0.3
6.0
V
)
Relative to VDD
VDD 0.3 VDD + 0.3
VSS 0.1 VSS + 0.1
VSS_ADC SR Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground (VSS
—
—
V
V
)
)
VDD_ADC SR Voltage on VDD_HV_ADC (ADC
reference) pin with respect to ground (VSS
0.3
VDD 0.3 VDD + 0.3
0.3 6.0
VDD 0.3 VDD + 0.3
6.0
Relative to VDD
Relative to VDD
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS
—
V
)
IINJPAD SR Injected input current on any pin during
overload condition
—
—
10
10
mA
mA
mA
IINJSUM SR Absolute sum of all injected input currents
during overload condition
50
50
IAVGSEG SR Sum of all the static I/O current within a
supply segment1
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
—
70
64
V
DD = 3.3 V ± 10%, PAD3V5V = 1
ICORELV SR Low voltage static current sink through
VDD_BV
—
150
mA
°C
TSTORAGE SR Storage temperature
—
55
150
1
Supply segments are described in Section 4.7.5, I/O pad current specification.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (V > V or
IN
DD
V
< V ), the voltage on pins with respect to ground (V ) must not exceed the
IN
SS SS
recommended values.
4.5
Recommended operating conditions
Table 11. Recommended operating conditions (3.3 V)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
VSS
SR — Digital ground on VSS_HV pins
—
—
0
0
V
V
1
VDD
SR — Voltage on VDD_HV pins with respect to ground
3.0
3.6
(VSS
)
2
VSS_LV SR — Voltage on VSS_LV (low voltage digital supply)
—
VSS 0.1 VSS + 0.1
V
pins with respect to ground (VSS
)
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
23
Electrical characteristics
Table 11. Recommended operating conditions (3.3 V) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
3
VDD_BV SR — Voltage on VDD_BV pin (regulator supply) with
—
3.0
3.6
V
respect to ground (VSS
)
Relative to VDD VDD 0.1 VDD + 0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin
with respect to ground (VSS
—
VSS 0.1 VSS + 0.1
V
V
)
VDD_ADC SR — Voltage on VDD_HV_ADC pin (ADC reference)
with respect to ground (VSS
—
3.05
3.6
4
)
Relative to VDD VDD 0.1 VDD + 0.1
VIN
SR — Voltage on any GPIO pin with respect to ground
(VSS
—
Relative to VDD
—
VSS 0.1
—
VDD + 0.1
5
V
)
—
IINJPAD SR — Injected input current on any pin during overload
condition
5
mA
mA
IINJSUM SR — Absolute sum of all injected input currents during
overload condition
—
50
50
TVDD
SR — VDD slope to ensure correct power up6
—
—
0.25
85
V/µs
°C
TA C-Grade SR — Ambient temperature under bias
fCPU 48 MHz
40
Part
TJ C-Grade SR — Junction temperature under bias
40
40
40
40
40
110
105
130
125
150
Part
TA V-Grade SR — Ambient temperature under bias
Part
TJ V-Grade SR — Junction temperature under bias
Part
TA M-Grade SR — Ambient temperature under bias
Part
TJ M-Grade SR — Junction temperature under bias
Part
1
100 nF capacitance needs to be provided between each VDD/VSS pair.
2
3
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4
5
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL
device is reset.
,
6
Guaranteed by device validation
Table 12. Recommended operating conditions (5.0 V)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
VSS
SR — Digital ground on VSS_HV pins
—
0
0
V
MPC5602D Microcontroller Data Sheet, Rev. 6
24
Freescale Semiconductor
Electrical characteristics
Table 12. Recommended operating conditions (5.0 V) (continued)
Value
Symbol
C
Parameter
Conditions
Unit
Min
Max
1
VDD
SR — Voltage on VDD_HV pins with respect to ground
(VSS
—
Voltage drop2
—
4.5
3.0
5.5
5.5
V
)
3
VSS_LV SR — Voltage on VSS_LV (low voltage digital supply) pins
VSS 0.1 VSS + 0.1
V
V
with respect to ground (VSS
)
4
VDD_BV SR — Voltage on VDD_BV pin (regulator supply) with
—
4.5
3.0
5.5
5.5
respect to ground (VSS
)
Voltage drop(2)
Relative to VDD VDD 0.1 VDD + 0.1
VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with
respect to ground (VSS
—
VSS 0.1 VSS + 0.1
V
V
5
VDD_ADC SR — Voltage on VDD_HV_ADC pin (ADC reference) with
—
4.5
3.0
5.5
5.5
respect to ground (VSS
)
Voltage drop(2)
Relative to VDD VDD 0.1 VDD + 0.1
VIN
SR — Voltage on any GPIO pin with respect to ground
(VSS
—
Relative to VDD
—
VSS 0.1
—
VDD + 0.1
5
V
)
—
IINJPAD SR — Injected input current on any pin during overload
condition
5
mA
mA
IINJSUM SR — Absolute sum of all injected input currents during
overload condition
—
50
50
TVDD
SR — VDD slope to ensure correct power up6
—
—
0.25
85
V/µs
°C
TA C-Grade SR — Ambient temperature under bias
fCPU 48 MHz
40
Part
TJ C-Grade SR — Junction temperature under bias
40
40
40
40
40
110
105
130
125
150
Part
TA V-Grade SR — Ambient temperature under bias
Part
TJ V-Grade SR — Junction temperature under bias
Part
TA M-Grade SR — Ambient temperature under bias
Part
TJ M-Grade SR — Junction temperature under bias
Part
1
100 nF capacitance needs to be provided between each VDD/VSS pair.
2
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3
4
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5
6
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
Guaranteed by device validation
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
25
Electrical characteristics
NOTE
SRAM data retention is guaranteed with V
not below 1.08 V.
DD_LV
4.6
Thermal characteristics
4.6.1
Package thermal characteristics
1
Table 13. LQFP thermal characteristics
Conditions2
Symbol C
Parameter
Value Unit
RJA CC D Thermal resistance, junction-to-ambient natural Single-layer board —1s LQFP64
72.1 °C/W
65.2
convection3
LQFP100
Four-layer board — 2s2p LQFP64
LQFP100
57.3
51.8
RJB CC D Thermal resistance, junction-to-board4
RJC CC D Thermal resistance, junction-to-case5
Four-layer board — 2s2p LQFP64
LQFP100
44.1 °C/W
41.3
Single-layer board — 1s LQFP64
LQFP100
26.5 °C/W
23.9
Four-layer board — 2s2p LQFP64
LQFP100
26.2
23.7
JB CC D Junction-to-board thermal characterization
Single-layer board — 1s LQFP64
LQFP100
41
41.6
43
°C/W
parameter, natural convection
Four-layer board — 2s2p LQFP64
LQFP100
43.4
JC CC D Junction-to-case thermal characterization
Single-layer board — 1s LQFP64
LQFP100
11.5 °C/W
10.4
parameter, natural convection
Four-layer board — 2s2p LQFP64
LQFP100
11.1
10.2
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C
2
3
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-7. Thermal test board
meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA
.
4
5
Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB
.
Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
When Greek letters are not available, the symbols are typed as RthJC
.
4.6.2
Power considerations
The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:
J
MPC5602D Microcontroller Data Sheet, Rev. 6
26
Freescale Semiconductor
Electrical characteristics
T = T + (P x R )
JA
Eqn. 1
J
A
D
Where:
T is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
JA
P is the sum of P
and P (P = P
+ P ).
D
INT
I/O
D
INT I/O
P
P
is the product of I and V , expressed in watts. This is the chip internal power.
DD DD
INT
I/O
represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, P < P
and may be neglected. On the other hand, P may be significant, if the device
I/O
INT
I/O
is configured to continuously drive external modules and/or memories.
An approximate relationship between P and T (if P is neglected) is given by:
D
J
I/O
P = K / (T + 273 °C)
Eqn. 2
Eqn. 3
D
J
Therefore, solving equations 1 and 2:
Where:
2
K = P x (T + 273 °C) + R
x P
D
D
A
JA
K is a constant for the particular part, which may be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T Using this value of K, the values of P and T may be obtained by solving equations 1 and 2
A.
D
J
iteratively for any value of T .
A
4.7
I/O pad electrical characteristics
I/O pad types
4.7.1
The device provides four main I/O pad types depending on the associated alternate functions:
•
•
•
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low
electromagnetic emission.
Medium pads—These pads provide transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing low input leakage.
Medium pads can use slow configuration to reduce electromagnetic emission except for PC[1], that is medium only, at the cost
of reducing AC performance.
4.7.2
I/O input DC characteristics
Table 14 provides input DC electrical characteristics as described in Figure 4.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
27
Electrical characteristics
V
IN
V
DD
V
IH
V
HYS
V
IL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Figure 4. Input DC electrical characteristics definition
Table 14. I/O input DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH SR P Input high level CMOS (Schmitt
Trigger)
—
—
—
0.65VDD
—
VDD+0.4
V
V
VIL SR P Input low level CMOS (Schmitt
Trigger)
0.4
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS (Schmitt
Trigger)
0.1VDD
V
ILKG CC D Digital input leakage
No injection
on adjacent
pin
TA = 40 °C
TA = 25 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
—
—
2
2
200
200
300
500
1000
40
nA
D
D
D
—
5
—
12
70
—
—
P
—
2
WFI
SR P Digital input filtered pulse
—
—
—
ns
ns
(2)
WNFI SR P Digital input not filtered pulse
1000
—
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and
voltage.
4.7.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
•
Table 15 provides weak pull figures. Both pull-up and pull-down resistances are supported.
MPC5602D Microcontroller Data Sheet, Rev. 6
28
Freescale Semiconductor
Electrical characteristics
•
•
Table 16 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 17 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 15. I/O pull-up/pull-down DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
|IWPU| CC P Weak pull-up current
VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0
PAD3V5V = 12
10
10
10
10
—
—
—
—
—
—
150 µA
250
absolute value
C
P
VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1
VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0
150
|IWPD| CC P Weak pull-down current
150 µA
250
absolute value
C
PAD3V5V = 1(2) 10
P
VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10
150
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
2
Table 16. SLOW configuration output buffer electrical characteristics
Value
Symbol C
Parameter
Conditions1
Unit
Min
Typ Max
VOH CC P Output high level
SLOW configuration
Push Pull IOH = 2 mA,
0.8VDD
—
—
V
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
C
C
I
OH = 2 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V ± 10%, PAD3V5V = 12
IOH = 1 mA,
VDD 0.8
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VOL CC P Output low level
SLOW configuration
Push Pull IOL = 2 mA,
—
—
0.1VDD
V
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
C
C
I
OL = 2 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
2
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
29
Electrical characteristics
Table 17. MEDIUM configuration output buffer electrical characteristics
Value
Typ Max
Symbol C
Parameter
Conditions1
Unit
Min
VOH CC C Output high level
MEDIUM configuration
Push Pull IOH = 3.8 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
0.8VDD
—
—
V
P
I
OH = 2 mA,
0.8VDD
—
—
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
C
C
I
OH = 1 mA,
0.8VDD
—
—
—
—
VDD = 5.0 V ± 10%, PAD3V5V = 12
I
OH = 1 mA,
DD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
VDD 0.8
V
C
I
OH = 100 µA,
0.8VDD
—
—
—
VDD = 5.0 V ± 10%, PAD3V5V = 0
VOL CC C Output low level
Push Pull IOL = 3.8 mA,
— 0.2VDD
— 0.1VDD
V
MEDIUM configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
P
IOL = 2 mA,
—
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
C
C
IOL = 1 mA,
—
—
— 0.1VDD
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOL = 1 mA,
—
0.5
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
C
I
OL = 100 µA,
—
— 0.1VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but
RESET are configured in input or in high impedance state.
MPC5602D Microcontroller Data Sheet, Rev. 6
30
Freescale Semiconductor
Electrical characteristics
4.7.4
Output pin transition times
Table 18. Output pin transition times
Value
Unit
Symbol C
Parameter
Conditions1
Min Typ Max
ttr CC D Output transition time output pin2 CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 —
SLOW configuration
—
—
—
—
—
—
—
—
—
—
—
—
50 ns
100
125
50
T
CL = 50 pF
—
—
D
CL = 100 pF
D
CL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 —
T
CL = 50 pF
—
—
100
125
10 ns
20
D
CL = 100 pF
ttr CC D Output transition time output
CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 —
SIUL.PCRx.SRC = 1
pin(2)
T
CL = 50 pF
—
—
MEDIUM configuration
D
D
T
CL = 100 pF
40
CL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 —
SIUL.PCRx.SRC = 1
12
CL = 50 pF
—
—
25
D
CL = 100 pF
40
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
CL includes device and package capacitances (CPKG < 5 pF).
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as
DD SS
described in Table 19.
Table 20 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I
maximum value.
AVGSEG
Table 19. I/O supply segment
Supply segment
Package
1
2
3
4
100 LQFP
64 LQFP
pin 16 – pin 35
pin 8 – pin 26
pin 37 – pin 69
pin 28 – pin 55
pin 70 – pin 83
pin 56 – pin 7
pin 84 – pin 15
—
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
31
Electrical characteristics
Table 20. I/O consumption
Conditions1
Value
Symbol
C
Parameter
Unit
Min Typ Max
,2
ISWTSLW
CC D Dynamic I/O current CL = 25 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
—
—
—
—
—
—
20
16
29
17
mA
for SLOW
configuration
VDD = 3.3 V ± 10%,
PAD3V5V = 1
(2)
ISWTMED
CC D Dynamic I/O current CL = 25 pF
for MEDIUM
VDD = 5.0 V ± 10%,
PAD3V5V = 0
mA
configuration
VDD = 3.3 V ± 10%,
PAD3V5V = 1
IRMSSLW
CC D Root mean square
I/O current for SLOW
configuration
CL = 25 pF, 2 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.3 mA
3.2
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
CL = 100 pF, 2 MHz
6.6
VDD = 3.3 V ± 10%,
PAD3V5V = 1
1.6
2.3
4.7
IRMSMED CC D Root mean square
I/O current for
CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,
6.6 mA
13.4
18.3
5
PAD3V5V = 0
CL = 25 pF, 40 MHz
MEDIUM
configuration
CL = 100 pF, 13 MHz
CL = 25 pF, 13 MHz VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 25 pF, 40 MHz
8.5
CL = 100 pF, 13 MHz
11
IAVGSEG
SR D Sum of all the static VDD = 5.0 V ± 10%, PAD3V5V = 0
I/O current within a
70
65
mA
VDD = 3.3 V ± 10%, PAD3V5V = 1
supply segment
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
1
2
Table 21 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below 100%.
MPC5602D Microcontroller Data Sheet, Rev. 6
32
Freescale Semiconductor
Electrical characteristics
1
Table 21. I/O weight
100 LQFP/64 LQFP
Pad
Weight 5 V
Weight 3.3 V
SRC2 = 0
SRC = 1
SRC = 0
SRC = 1
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
9%
8%
8%
8%
8%
7%
7%
7%
6%
6%
6%
5%
5%
7%
8%
8%
8%
8%
8%
8%
7%
7%
7%
7%
1%
1%
5%
1%
1%
1%
1%
1%
9%
8%
8%
11%
8%
7%
7%
10%
9%
6%
6%
7%
5%
7%
11%
11%
8%
8%
8%
11%
11%
7%
10%
7%
1%
1%
5%
1%
1%
1%
1%
1%
10%
10%
10%
9%
9%
9%
8%
8%
8%
7%
7%
6%
6%
9%
9%
9%
10%
10%
10%
9%
9%
8%
8%
8%
1%
1%
6%
1%
1%
1%
1%
1%
10%
10%
10%
10%
9%
PE[0]
PA[1]
9%
8%
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
8%
8%
7%
7%
7%
PE[11]
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
PC[7]
PA[15]
PA[14]
PA[4]
6%
9%
10%
10%
10%
10%
10%
10%
9%
8%
PA[13]
PA[12]
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
9%
8%
1%
1%
6%
1%
1%
1%
1%
1%
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
33
Electrical characteristics
1
Table 21. I/O weight (continued)
100 LQFP/64 LQFP
Weight 5 V
Pad
Weight 3.3 V
SRC = 0 SRC = 1
SRC2 = 0
SRC = 1
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
9%
8%
8%
8%
8%
7%
7%
7%
6%
6%
4%
4%
4%
5%
5%
5%
5%
5%
5%
4%
5%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
9%
8%
8%
8%
8%
7%
7%
7%
6%
6%
4%
4%
4%
5%
5%
5%
5%
7%
6%
4%
17%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
11%
10%
10%
9%
9%
9%
8%
8%
7%
7%
5%
5%
5%
6%
6%
6%
6%
6%
5%
5%
4%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
11%
10%
10%
9%
9%
9%
8%
8%
7%
7%
5%
5%
5%
6%
6%
6%
6%
6%
6%
5%
12%
PB[5]
PB[6]
PB[7]
PD[9]
PD[10]
PD[11]
PB[11]
PD[12]
PB[12]
PD[13]
PB[13]
PD[14]
PB[14]
PD[15]
PB[15]
PA[3]
PA[7]
PA[8]
PA[9]
PA[10]
PA[11]
PE[12]
PC[3]
PC[2]
PA[5]
PA[6]
PC[1]
MPC5602D Microcontroller Data Sheet, Rev. 6
34
Freescale Semiconductor
Electrical characteristics
1
Table 21. I/O weight (continued)
100 LQFP/64 LQFP
Weight 5 V
Pad
Weight 3.3 V
SRC2 = 0
SRC = 1
SRC = 0
SRC = 1
PC[0]
PE[2]
PE[3]
PC[5]
PC[4]
PE[4]
PE[5]
PE[6]
PE[7]
PC[12]
PC[13]
PC[8]
PB[2]
6%
7%
7%
8%
8%
8%
8%
9%
9%
9%
9%
9%
9%
9%
10%
10%
11%
11%
12%
12%
12%
12%
13%
9%
7%
8%
8%
9%
9%
9%
9%
10%
10%
10%
11%
11%
11%
11%
11%
11%
12%
9%
10%
10%
10%
10%
11%
11%
11%
11%
9%
13%
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
SRC: “Slew Rate Control” bit in SIU_PCR
4.8
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
device start-up phase
Figure 5. Start-up reset requirements
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
35
Electrical characteristics
VRESET
hw_rst
‘1’
V
DD
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 6. Noise filtering on reset signal
Table 22. Reset electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
VIH
VIL
SR P Input High Level CMOS
(Schmitt Trigger)
—
—
—
0.65VDD
—
VDD + 0.4
V
V
V
V
SR P Input low Level CMOS
(Schmitt Trigger)
0.4
0.1VDD
—
—
—
—
0.35VDD
—
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
VOL CC P Output low level
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
0.1VDD
Push Pull, IOL = 1 mA,
—
—
—
—
0.1VDD
0.5
VDD = 5.0 V ± 10%, PAD3V5V = 12
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
MPC5602D Microcontroller Data Sheet, Rev. 6
36
Freescale Semiconductor
Electrical characteristics
Table 22. Reset electrical characteristics (continued)
Conditions1
Value
Symbol
C
Parameter
Unit
Min
Typ
Max
ttr
CC D Output transition time
output pin3
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
ns
MEDIUM configuration
CL = 50 pF,
—
—
—
—
—
—
—
—
—
20
40
12
25
40
40
—
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
CL = 50 pF,
—
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
WFRST SR P RESET input filtered
pulse
—
—
ns
ns
µA
WNFRST SR P RESET input not filtered
pulse
—
1000
|IWPU
|
CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1
VDD = 5.0 V ± 10%, PAD3V5V = 0
VDD = 5.0 V ± 10%, PAD3V5V = 14
10
10
10
—
—
—
150
150
250
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
3
4
CL includes device and package capacitance (CPKG < 5 pF).
The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
are configured in input or in high impedance state.
4.9
Power management electrical characteristics
Voltage regulator electrical characteristics
4.9.1
The device implements an internal voltage regulator to generate the low voltage core supply V
from the high voltage
DD_LV
ballast supply V
. The regulator itself is supplied by the common I/O supply V . The following supplies are involved:
DD_BV
DD
•
•
•
HV: High voltage external power supply for voltage regulator module. This must be provided externally through V
power pin.
DD
BV: High voltage external power supply for internal ballast module. This must be provided externally through V
DD_BV
power pin. Voltage values should be aligned with V
.
DD
LV: Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
37
Electrical characteristics
— LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
C
(LV_COR/LV_CFLA)
REG2
V
DD
V
V
DD_LV
SS_LV
V
DD_BV
DD_LVn
SS_LVn
V
REF
V
DD_BV
V
DD_LV
DEVICE
V
Voltage Regulator
I
V
SS_LV
V
V
V
V
V
DD
SS_LV
DD_LV
SS
DEVICE
C
C
DEC2
REG3
(LV_COR/LV_PLL)
(supply/IO decoupling)
Figure 7. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (C ) to be connected to the device in order to provide a stable
REGn
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three V
/V
supply pairs to ensure stable voltage (see
DD_LV SS_LV
Section 4.5, Recommended operating conditions).
Table 23. Voltage regulator electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
CREGn
RREG
SR — Internal voltage regulator external
capacitance
—
200
—
500
nF
SR — Stability capacitor equivalent serial
resistance
Range:
10 kHz to 20 MHz
—
—
0.2
MPC5602D Microcontroller Data Sheet, Rev. 6
38
Freescale Semiconductor
Electrical characteristics
Table 23. Voltage regulator electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
CDEC1
SR — Decoupling capacitance2 ballast
VDD_BV/VSS_LV pair:
1003
4704
—
nF
VDD_BV = 4.5 V to 5.5 V
V
V
DD_BV/VSS_LV pair:
DD_BV = 3 V to 3.6 V
400
10
—
—
CDEC2
SR — Decoupling capacitance regulator
supply
VDD/VSS pair
100
nF
V
VMREG CC T Main regulator output voltage
P
Before exiting from reset
—
1.16
—
1.32
1.28
—
—
—
After trimming
—
IMREG
SR — Main regulator current provided to
DD_LV domain
150
mA
mA
V
IMREGINT CC D Main regulator module current
consumption
IMREG = 200 mA
IMREG = 0 mA
—
—
—
—
2
1
VLPREG CC P Low-power regulator output voltage After trimming
1.16
—
1.28
—
—
15
V
ILPREG SR — Low power regulator current provided
mA
—
to VDD_LV domain
ILPREGINT CC D Low-power regulator module current ILPREG = 15 mA;
—
—
—
5
600
—
µA
consumption
TA = 55 °C
—
ILPREG = 0 mA;
TA = 55 °C
VULPREG CC P Ultra low power regulator output
voltage
After trimming
1.16
—
1.28
—
—
2
—
V
IULPREG SR — Ultra low power regulator current
provided to VDD_LV domain
—
5
mA
µA
IULPREGINT CC D Ultra low power regulator module
current consumption
IULPREG = 5 mA;
TA = 55 °C
—
100
—
IULPREG = 0 mA;
TA = 55 °C
—
IDD_BV CC D In-rush average current on VDD_BV
during power-up5
—
—
—
3006 mA
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
3
4
This value is acceptable to guarantee operation from 4.5 V to 5.5 V.
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
5
6
In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs,
depending on external capacitances to be loaded).
The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
39
Electrical characteristics
4.9.2
Low voltage detector electrical characteristics
The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as five low voltage
detectors (LVDs) to monitor the V and the V
voltage while device is supplied:
DD
DD_LV
•
•
•
•
•
•
POR monitors V during the power-up phase to ensure device is maintained in a safe reset state (refer to RGM
DD
Destructive Event Status (RGM_DES) Register flag F_POR in device reference manual)
LVDHV3 monitors V to ensure device reset below minimum functional supply (refer to RGM Destructive Event
DD
Status (RGM_DES) Register flag F_LVD27 in device reference manual)
LVDHV3B monitors V
to ensure device reset below minimum functional supply (refer to RGM Destructive
DD_BV
Event Status (RGM_DES) Register flag F_LVD27_VREG in device reference manual)
LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range (refer to RGM Functional Event Status
DD
(RGM_FES) Register flag F_LVD45 in device reference manual)
LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD1 in device reference manual)
LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES) Register flag
F_LVD12_PD0 in device reference manual)
V
DD
V
V
LVDHVxH
LVDHVxL
RESET
Figure 8. Low voltage detector vs reset
MPC5602D Microcontroller Data Sheet, Rev. 6
40
Freescale Semiconductor
Electrical characteristics
Table 24. Low voltage detector electrical characteristics
Value
Unit
Symbol
C
Parameter
Conditions1
Min
Typ
Max
VPORUP
VPORH
SR P Supply for functional POR module
CC P Power-on reset threshold
TA = 25 °C,
after trimming
1.0
1.5
—
—
—
—
—
—
—
—
—
—
—
5.5
2.6
V
V
V
V
V
V
V
V
V
V
VLVDHV3H CC T LVDHV3 low voltage detector high threshold
VLVDHV3L CC P LVDHV3 low voltage detector low threshold
VLVDHV3BH CC P LVDHV3B low voltage detector high threshold
VLVDHV3BL CC P LVDHV3B low voltage detector low threshold
VLVDHV5H CC T LVDHV5 low voltage detector high threshold
VLVDHV5L CC P LVDHV5 low voltage detector low threshold
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
2.95
2.9
2.6
—
2.95
2.9
2.6
—
4.5
3.8
1.08
1.08
4.4
1.16
1.16
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.10 Power consumption
Table 25 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 25. Power consumption on VDD_BV and VDD_HV
Value
Symbol
C
Parameter
Conditions1
Unit
1303 mA
Min Typ Max
2
IDDMAX
CC D RUN mode maximum
average current
—
—
90
4
IDDRUN
CC T RUN mode typical
fCPU = 8 MHz
fCPU = 16 MHz
CPU = 32 MHz
—
—
—
—
—
—
—
—
—
—
—
7
—
—
mA
average current5
T
18
29
40
8
T
f
—
P
fCPU = 48 MHz
100
15
25
IDDHALT
CC C HALT mode current6
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
mA
P
TA = 125 °C
14
IDDSTOP CC P STOP mode current7
Slow internal RC oscillator TA = 25 °C
(128 kHz) running
180 7008 µA
D
D
D
P
TA = 55 °C
500
1
—
TA = 85 °C
TA = 105 °C
TA = 125 °C
6(8) mA
9(8)
2
4.5
12(8)
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
41
Electrical characteristics
Table 25. Power consumption on VDD_BV and VDD_HV (continued) (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
IDDSTDBY CC P STANDBY mode current9 Slow internal RC oscillator TA = 25 °C
(128 kHz) running
—
—
—
—
—
30
75
100
—
µA
D
D
D
P
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
180
700
315 1000
560 1700
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Running consumption does not include I/Os toggling which is highly dependent on the application. The given value
is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify
operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used
peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions,
use low power mode when possible.
3
Higher current may be sinked by device during power-up and standby exit. Please refer to in-rush average current
on Table 23.
4
5
RUN current measured with typical application with accesses on both flash memory and SRAM.
Only for the “P” classification: Code fetched from SRAM: serial IPs CAN and LIN in loop-back mode, DSPI as Master,
PLL as system clock (3 × Multiplier) peripherals on (eMIOS/CTU/ADC) and running at maximum frequency, periodic
SW/WDG timer reset enabled.
6
Data flash power down. Code flash in low power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.
FlexCAN: 0 ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception
or transmission), instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15])
with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON.
STM ON. ADC ON but no conversion except 2 analog watchdogs.
7
8
Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPVreg off,
ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.
When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main
regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction
temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the
maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to
the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.
9
Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum
consumption, all possible modules switched off.
4.11 Flash memory electrical characteristics
The data flash operation depends strongly on the code flash operation. If code flash is switched-off, the data flash is disabled.
4.11.1 Program/Erase characteristics
Table 26 shows the program and erase characteristics.
MPC5602D Microcontroller Data Sheet, Rev. 6
42
Freescale Semiconductor
Electrical characteristics
Table 26. Program and erase specifications (code flash)
Value
Symbol
C
Parameter
Unit
Initial
Min
Typ1
Max3
max2
tdwprogram CC C Double word (64 bits) program time4
t16Kpperase CC C 16 KB block preprogram and erase time
t32Kpperase CC C 32 KB block preprogram and erase time
t128Kpperase CC C 128 KB block preprogram and erase time
—
—
—
—
—
22
300
400
800
—
50
500
600
1300
30
500
5000
5000
7500
30
µs
ms
ms
ms
µs
tesus
CC C Erase suspend latency
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
Table 27. Program and erase specifications (data flash)
Value
Symbol
C
Parameter
Unit
Initial
max2
Min
Typ1
Max3
tswprogram CC C Single word (32 bits) program time4
t16Kpperase CC C 16 KB block preprogram and erase time
—
—
—
30
70
300
1500
4800
µs
ms
ms
700
800
tBank_D
CC C 64 KB block preprogram and erase time
1900
2300
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
43
Electrical characteristics
Table 28. Flash module life
Conditions
Value
Symbol
C
Parameter
Unit
Min
Typ
Max
P/E
CC C Number of program/erase
cycles per block over the
operating temperature range
(TJ)
16 KB blocks
32 KB blocks
128 KB blocks
100,000
—
—
—
—
—
cycles
cycles
cycles
years
10,000 100,000
1,000 100,000
Retention CC C Minimum data retention at 85 °C Blocks with
average ambient temperature1 0–1,000 P/E cycles
20
10
5
—
—
—
Blocks with
1,001–10,000 P/E cycles
—
—
Blocks with
10,001–100,000 P/E cycles
1
Ambient temperature averaged over application duration. It is recommended not to exceed the product operating
temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units
will experience single bit corrections throughout the life of the product with no impact to product reliability.
Table 29. Flash memory read access timing
Symbol
C
Parameter
Conditions1 Max Unit
fCFREAD CC P Maximum working frequency for reading code flash memory at given
2 wait states 48 MHz
0 wait states 20
number of wait states in worst conditions
C
fDFREAD CC P Maximum working frequency for reading data flash memory at given
number of wait states in worst conditions
6 wait states 48 MHz
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.11.2 Flash power supply DC characteristics
Table 30 shows the power supply DC characteristics on external supply.
NOTE
Power supply for data flash is actually provided by code flash; this means that data flash
cannot work if code flash is not powered.
Table 30. Flash power supply DC electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
ICFREAD CC D Sum of the current consumption on Flash module read
Code flash
Data flash
Code flash
Data flash
—
—
—
—
—
—
—
—
33 mA
mA
33 mA
mA
VDDHV and VDDBV on read access fCPU = 48 MHz
IDFREAD CC D
4
ICFMOD CC D Sum of the current consumption on Program/Erase on-going
VDDHV and VDDBV on matrix
modification (program/erase)
while reading flash registers,
fCPU = 48 MHz
IDFMOD CC D
6
MPC5602D Microcontroller Data Sheet, Rev. 6
44
Freescale Semiconductor
Electrical characteristics
Table 30. Flash power supply DC electrical characteristics
Conditions1
Value
Unit
Symbol
C
Parameter
Min Typ Max
IFLPW CC D Sum of the current consumption on
VDDHV and VDDBV during
—
Code flash
—
—
910 µA
flash low-power mode
ICFPWD CC D Sum of the current consumption on
—
Code flash
Data flash
—
—
—
—
125 µA
25 µA
VDDHV and VDDBV during
IDFPWD CC D
flash power-down mode
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.11.3 Start-up/Switch-off timings
Table 31. Start-up time/Switch-off time
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
tFLARSTEXIT CC T Delay for flash module to exit reset mode Code flash
Data flash
—
—
—
—
—
—
125
150
0.5
µs
µs
µs
tFLALPEXIT CC T Delay for flash module to exit low-power Code flash
mode2
tFLAPDEXIT CC T Delay for flash module to exit power-down Code flash
—
—
—
—
—
—
30
303
0.5
µs
µs
µs
mode
Data flash
tFLALPENTRY CC T Delay for flash module to enter low-power Code flash
mode
tFLAPDENTRY CC T
Code flash
Data flash
—
—
—
—
1.5
µs
µs
Delay for flash module to enter
power-down mode
4(3)
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Data flash does not support low-power mode
If code flash is already switched-on.
4.12 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified
MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in
particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC
level requested for his application.
•
Software recommendations The software flowchart must include the management of runaway conditions such as:
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
45
Electrical characteristics
— Corrupted program counter
— Unexpected reset
— Critical data corruption (control registers...)
•
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the
software can be hardened to prevent unrecoverable errors occurring.
4.12.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1
standard, which specifies the general conditions for EMI measurements.
1 2
Table 32. EMI radiated emission measurement
Value
Symbol
C
Parameter
Conditions
Unit
Min Typ Max
—
SR — Scan range
—
—
—
0.150
—
—
48
1000 MHz
fCPU SR — Operating frequency
VDD_LV SR — LV operating voltages
SEMI CC T Peak level
—
—
MHz
V
—
1.28
—
VDD = 5 V, TA = 25 °C,
100 LQFP package
No PLL frequency
modulation
—
18 dBµ
V
Test conforming to IEC 61967-2,
fOSC = 8 MHz/fCPU = 48 MHz
± 2% PLL frequency
modulation
—
—
14 dBµ
V
1
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
2
For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your
local marketing representative.
4.12.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine
its performance in terms of electrical sensitivity.
4.12.3.1 Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5602D Microcontroller Data Sheet, Rev. 6
46
Freescale Semiconductor
Electrical characteristics
1 2
Table 33. ESD absolute maximum ratings
Symbol
C
Ratings
Conditions
TA = 25 °C
Class Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
H1C
2000
V
conforming to AEC-Q100-002
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
V
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
V
V
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
4.12.3.2 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 34. Latch-up results
Symbol
LU CC
C
Parameter
Conditions
Class
T Static latch-up class
TA = 125 °C
II level A
conforming to JESD 78
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
47
Electrical characteristics
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
Table 35 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.
EXTAL
C1
EXTAL
XTAL
C2
DEVICE
V
DD
I
R
EXTAL
XTAL
DEVICE
XTAL
DEVICE
Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
Figure 9. Crystal oscillator and resonator connection scheme
MPC5602D Microcontroller Data Sheet, Rev. 6
48
Freescale Semiconductor
Electrical characteristics
Table 35. Crystal description
Crystal
equivalent
series
resistance
(ESR)
Shunt
capacitance
xtalin/xtalout betweenxtalout
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Nominal
frequency
(MHz)
Load on
NDK crystal
reference
C1 = C2 (pF)1
and xtalin
C02 (pF)
4
NX8045GB
NX5032GA
300
300
150
120
120
2.68
2.46
2.93
3.11
3.90
591.0
160.7
86.6
21
17
15
15
10
2.93
3.01
2.91
2.93
3.00
8
10
12
16
56.5
25.3
1
2
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing
includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,
package, etc.).
S_MTRANS bit (ME_GS register)
‘1’
‘0’
V
XTAL
1/f
FXOSC
V
FXOSC
90%
10%
V
FXOSCOP
T
valid internal clock
FXOSCSU
Figure 10. Fast external crystal oscillator (4 to 16 MHz) timing diagram
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
49
Electrical characteristics
Table 36. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fFXOSC
SR — Fast external crystal
oscillator frequency
—
4.0
—
16.0
MHz
gmFXOSC CC C Fast external crystal
VDD = 3.3 V ± 10%,
2.2
2.0
2.7
2.5
—
—
—
—
8.2
7.4
9.7
9.2
mA/V
oscillator transconductance PAD3V5V = 1
OSCILLATOR_MARGIN = 0
CC P
CC C
CC C
VDD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
V
DD = 3.3 V ± 10%,
PAD3V5V = 1
OSCILLATOR_MARGIN = 1
V
DD = 5.0 V ± 10%,
PAD3V5V = 0
OSCILLATOR_MARGIN = 1
VFXOSC
CC T Oscillation amplitude at
EXTAL
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
1.3
1.3
—
—
—
—
V
f
OSC = 16 MHz,
OSCILLATOR_MARGIN = 1
VFXOSCOP CC P Oscillation operating point
—
—
—
—
0.95
2
V
2
IFXOSC
CC T Fast external crystal
oscillator consumption
3
6
mA
tFXOSCSU CC T Fast external crystal
oscillator start-up time
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
—
—
—
—
ms
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
1.8
VIH
VIL
SR P Input high level CMOS
(Schmitt Trigger)
Oscillator bypass mode
Oscillator bypass mode
0.65VDD
0.4
VDD+0.4
0.35VDD
V
V
SR P Input low level CMOS
(Schmitt Trigger)
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Stated values take into account only analog module consumption but not the digital contributor (clock tree and
enabled peripherals)
MPC5602D Microcontroller Data Sheet, Rev. 6
50
Freescale Semiconductor
Electrical characteristics
4.14 FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
Table 37. FMPLL electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
fPLLIN SR — FMPLL reference clock2
—
—
4
—
—
48
60
MHz
%
PLLIN SR — FMPLL reference clock duty
40
cycle(2)
fPLLOUT CC D FMPLL output clock frequency
—
—
16
—
—
48
MHz
3
fVCO
CC P VCO frequency without
frequency modulation
256
512 MHz
VCO frequency with frequency
modulation
—
245
—
533
fCPU SR — System clock frequency
fFREE CC P Free-running frequency
tLOCK CC P FMPLL lock time
—
—
20
—
—
—
—
40
—
48
MHz
—
150 MHz
Stable oscillator (fPLLIN = 16 MHz)
100
10
µs
ns
tLTJIT CC — FMPLL long term jitter
fPLLIN = 16 MHz (resonator),
fPLLCLK at 48 MHz, 4,000 cycles
IPLL
CC C FMPLL consumption
TA = 25 °C
—
—
4
mA
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN
Frequency modulation is considered ±4%.
.
3
4.15 Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz fast internal RC oscillator (FIRC). This is used as the default clock at the power-up of the device.
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics
Value
Symbol
fFIRC
2,
C
Parameter
Conditions1
Unit
Min
Typ
Max
CC P Fast internal RC oscillator high TA = 25 °C, trimmed
frequency
—
12
—
16
—
20
MHz
SR —
—
IFIRCRUN
CC T Fast internal RC oscillator high TA = 25 °C, trimmed
—
—
200
µA
µA
frequency current in running
mode
IFIRCPWD CC D Fast internal RC oscillator high TA = 25 °C
frequency current in power
—
10
down mode
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
51
Electrical characteristics
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C sysclk = off
frequency and system clock
—
—
—
—
—
—
500
600
700
900
1250
1.1
—
—
—
—
—
2.0
µA
sysclk = 2 MHz
current in stop mode
sysclk = 4 MHz
sysclk = 8 MHz
sysclk = 16 MHz
tFIRCSU CC C Fast internal RC oscillator
start-up time
VDD = 5.0 V ± 10%
µs
%
FIRCPRE CC C Fast internal RC oscillator
precision after software
TA = 25 °C
TA = 25 °C
1
—
1
trimming of fFIRC
FIRCTRIM CC C Fast internal RC oscillator
—
1.6
—
%
%
trimming step
FIRCVAR CC C Fast internal RC oscillator
variation in temperature and
supply with respect to fFIRC at
TA = 55 °C in high-frequency
configuration
—
5
5
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
4.16 Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator (SIRC). This can be used as the reference clock for the RTC module.
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
fSIRC
CC P Slow internal RC oscillator low
TA = 25 °C, trimmed
—
—
100
—
128
—
—
150
5
kHz
frequency
SR —
2,
ISIRC
CC C Slow internal RC oscillator low
frequency current
TA = 25 °C, trimmed
—
µA
µs
%
tSIRCSU
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10%
time
—
2
—
8
12
2
SIRCPRE CC C Slow internal RC oscillator precision TA = 25 °C
—
after software trimming of fSIRC
SIRCTRIM CC C Slow internal RC oscillator trimming
—
2.7
—
step
MPC5602D Microcontroller Data Sheet, Rev. 6
52
Freescale Semiconductor
Electrical characteristics
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min Typ Max
SIRCVAR CC P Slow internal RC oscillator variation High frequency configuration
in temperature and supply with
10
—
10
%
respect to fSIRC at TA = 55 °C in high
frequency configuration
1
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is
ON.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
53
Electrical characteristics
4.17 ADC electrical characteristics
4.17.1 Introduction
The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital converter.
Offset Error (E )
Gain Error (E )
G
O
1023
1022
1021
1020
1019
1 LSB ideal = V
/ 1024
DD_ADC
1018
(2)
code out
7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
4
3
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
(LSB
V
)
ideal
in(A)
Offset Error (E )
O
Figure 11. ADC characteristics and error definitions
MPC5602D Microcontroller Data Sheet, Rev. 6
54
Freescale Semiconductor
Electrical characteristics
4.17.2 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being C and C
S
p2
substantially two switched capacitances, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive
path to ground. For instance, assuming a conversion rate of 1 MHz, with C +C equal to 3 pF, a resistance of 330 k is
S
p2
obtained (R = 1 / (f × (C +C )), where f represents the conversion rate at the considered channel). To minimize the error
EQ
c
S
p2
c
induced by the voltage partitioning between this resistance (sampled voltage on C +C ) and the sum of R + R , the external
S
p2
S
F
circuit must be designed to respect the Equation 4:
Eqn. 4
R + R
S
F
1
2
--------------------
V
-- LSB
A
R
EQ
Equation 4 generates a constraint for external network design, in particular on a resistive path.
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
55
Electrical characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Current Limiter
R
R
R
R
R
AD
S
F
L
SW1
V
C
C
C
C
S
A
F
P1
P2
R : Source impedance
S
R : Filter resistance
F
C : Filter capacitance
F
R : Current limiter resistance
L
R
R
: Channel selection switch impedance
SW1
: Sampling switch impedance
AD
C : Pin capacitance (two contributions, C and C )
P2
P
P1
C : Sampling capacitance
S
Figure 12. Input equivalent circuit (precise channels)
MPC5602D Microcontroller Data Sheet, Rev. 6
56
Freescale Semiconductor
Electrical characteristics
EXTERNAL CIRCUIT
Filter
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Selection
Extended
Switch
Sampling
Source
R
Current Limiter
R
R
R
F
R
L
R
AD
SW2
S
SW1
C
S
C
V
C
F
C
C
P2
A
P1
P3
R : Source impedance
S
R : Filter resistance
F
C : Filter capacitance
F
R : Current limiter resistance
L
R
R
: Channel selection switch impedance (two contributions, R
and R
)
SW1
SW1
SW2
: Sampling switch impedance
AD
C : Pin capacitance (two contributions, C , C and C )
P3
P
P1
P2
C : Sampling capacitance
S
Figure 13. Input equivalent circuit (extended channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are
F
P1
P2
initially charged at the source voltage V (refer to the equivalent circuit in Figure 13): A charge sharing phenomenon is installed
A
when the sampling phase is started (A/D switch close).
Voltage transient on CS
V
CS
V
A
V <0.5 LSB
V
A2
1
2
1 < (RSW + RAD) CS << ts
V
A1
2 = RL (CS + CP1 + CP2)
t
t
s
Figure 14. Transient behavior during sampling phase
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
57
Electrical characteristics
In particular two different transient periods can be distinguished:
1. A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C
S
P1
P2
S
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,
P2
P1
P
P1
P2
P
S
and the time constant is
Eqn. 5
C C
P
S
--------------------
= R
+ R
1
SW
AD
C + C
P
S
Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is
S
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time t
is always much longer than the internal time constant:
s
Eqn. 6
R
+ R
C « ts
1
SW
AD
S
The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance
P1
P2
S
A1
according to Equation 7:
Eqn. 7
V
C + C + C = V C + C
A1
S
P1
P2
A
P1
P2
2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance
F
R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality
L
P2
S
P1
would be faster), the time constant is:
Eqn. 8
R C + C + C
P1 P2
2
L
S
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time t , a constraints on R sizing is obtained:
s
L
Eqn. 9
10 = 10 R C + C + C ts
P1 P2
2
L
S
Of course, R shall be sized also according to the current limitation constraints, in combination with R (source
L
S
impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V
F
F
P1 P2
S
A2
(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge
A1
balance assuming now C already charged at V ):
S
A1
Eqn. 10
V
C + C + C + C = V C + V C + C + C
P1 P2 A1 P1 P2
A2
S
F
A
F
S
The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to
F
F
provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of
S
A
F F
the filter is very high with respect to the sampling time (t ). The filter is typically designed to act as anti-aliasing.
s
MPC5602D Microcontroller Data Sheet, Rev. 6
58
Freescale Semiconductor
Electrical characteristics
Analog source bandwidth (VA)
Noise
tc < 2 RFCF (conversion rate vs. filter pole)
fF = f0 (anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
Sampled signal spectrum (fC = conversion rate)
fF
f0
fC
f
f
Figure 15. Spectral representation of input signal
Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),
0
F
according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater
C
0
than or at least equal to twice the conversion period (t ). Again the conversion period t is longer than the sampling time t ,
c
c
s
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the
F
F
sampling time t , so the charge level on C cannot be modified by the analog signal source during the time in which the sampling
s
S
switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
S
voltage on C :
S
Eqn. 11
V
C
+ C + C
P2
----------- = -------------------------------------------------------
A2
P1
F
V
C
+ C + C + C
A
P1
P2 S
F
From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of
A
half a count, a constraint is evident on C value:
F
Eqn. 12
C
2048 C
F
S
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
59
Electrical characteristics
4.17.3 ADC electrical characteristics
Table 40. ADC input leakage current
Value
Typ
Symbol C
Parameter
Conditions
Unit
Min
Max
ILKG CC C Input leakage current TA = 40 °C No current injection on adjacent pin
—
—
—
—
1
1
—
—
nA
C
C
P
TA = 25 °C
TA = 105 °C
TA = 125 °C
8
200
400
45
Table 41. ADC conversion characteristics
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
0.1
VSS_ADC SR — Voltage on
VSS_HV_ADC (ADC
—
0.1
—
V
reference) pin with
respect to ground
2
(VSS
)
VDD_ADC SR — Voltage on
VDD_HV_ADC pin
—
—
VDD 0.1
—
VDD + 0.1
V
(ADC reference) with
respect to ground
(VSS
)
VAINx SR — Analog input voltage3
VSS_ADC 0.1
—
—
—
—
VDD_ADC + 0.1
32 + 4%
20 + 4%
55
V
fADC SR — ADC analog frequency VDD = 5.0 V
VDD = 3.3 V
3.33
3.33
45
MHz
ADC_SYS SR — ADC clock duty cycle ADCLKSEL = 14
(ipg_clk)
%
tADC_PU SR — ADC power up delay
—
—
—
—
1.5
—
µs
ns
ts
CC
T
Sampling time5
VDD = 3.3 V
f
ADC = 20 MHz,
INPSAMP = 12
600
f
ADC = 3.33 MHz,
—
500
—
—
—
—
76.2
—
µs
ns
µs
INPSAMP = 255
T
Sampling time(5)
VDD = 5.0 V
fADC = 24 MHz,
INPSAMP = 13
fADC = 3.33 MHz,
INPSAMP = 255
76.2
MPC5602D Microcontroller Data Sheet, Rev. 6
60
Freescale Semiconductor
Electrical characteristics
Table 41. ADC conversion characteristics (continued)
Value
Symbol
C
Parameter
Conditions1
Unit
Min
Typ
Max
tc
CC
P
Conversion time6
VDD = 3.3 V
f
ADC = 20 MHz,
2.4
—
—
µs
INPCMP = 0
f
ADC = 13.33 MHz,
—
1.5
—
—
—
—
5
3.6
—
INPCMP = 0
P
Conversion time(6)
VDD = 5.0 V
fADC = 32 MHz,
INPCMP = 0
µs
fADC = 13.33 MHz,
INPCMP = 0
3.6
CS
CC D ADC input sampling
capacitance
—
—
—
—
—
—
—
pF
pF
pF
pF
k
k
k
mA
CP1
CP2
CP3
CC D ADC input pin
capacitance 1
3
CC D ADC input pin
capacitance 2
1
CC D ADC input pin
capacitance 3
1.5
—
—
—
—
—
RSW1 CC D Internal resistance of
analog source
—
—
—
5
5
1
2
RSW2 CC D Internal resistance of
analog source
RAD CC D Internal resistance of
analog source
0.3
5
IINJ
SR — Input current Injection Current
VDD
3.3 V ± 10%
=
injection on
one ADC input,
different from
the converted
one
VDD
5.0 V ± 10%
=
5
INLP CC
INLX CC
DNL CC
T
T
T
Absolute Integral
non-linearity-precise
channels
No overload
—
—
—
1
3
5
1
LSB
LSB
LSB
Absolute Integral
non-linearity-extended
channels
No overload
1.5
0.5
Absolute Differential No overload
non-linearity
EO
EG
CC
CC
T
T
P
T
Absolute Offset error
Absolute Gain error
—
—
—
–6
–8
2
2
—
—
6
LSB
LSB
LSB
—
TUEP7 CC
Total unadjusted error Without current injection
for precise channels,
With current injection
input only pins
8
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
61
Electrical characteristics
Table 41. ADC conversion characteristics (continued)
Value
Typ
Symbol
C
Parameter
Conditions1
Unit
Min
Max
TUEX(7) CC
T
T
Total unadjusted error Without current injection
–10
–12
10
12
LSB
for extended channel
With current injection
1
2
3
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4
5
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured
by internal divider by 2.
During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of
the sampling time tS, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tS depend on programming.
6
7
This parameter does not include the sampling time tS, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
4.18 On-chip peripherals
4.18.1 Current consumption
1
Table 42. On-chip peripherals current consumption
Parameter Conditions
CC T CAN (FlexCAN) supply 500 Kbyte/s Total (static + dynamic)
Symbol
C
Typical value2 Unit
IDD_BV(CAN)
8 × fperiph + 85 µA
8 × fperiph + 27 µA
current on VDD_BV consumption:
125 Kbyte/s
• FlexCAN in loop-back
mode
• XTAL at 8 MHz used as
CAN engine clock source
• Message sending period
is 580 µs
IDD_BV(eMIOS) CC T eMIOS supply current Static consumption:
29 × fperiph
µA
µA
on VDD_BV
• eMIOS channel OFF
• Global prescaler enabled
Dynamic consumption:
3
• It does not change varying the
frequency (0.003 mA)
IDD_BV(SCI)
CC T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynamic) consumption:
• LIN mode
5 × fperiph + 31 µA
• Baudrate: 20 Kbyte/s
MPC5602D Microcontroller Data Sheet, Rev. 6
62
Freescale Semiconductor
Electrical characteristics
Table 42. On-chip peripherals current consumption (continued)
1
Symbol
C
Parameter
Conditions
Typical value2 Unit
IDD_BV(SPI)
CC T SPI (DSPI) supply
current on VDD_BV
Ballast static consumption (only clocked)
1
µA
µA
Ballast dynamic consumption (continuous
communication):
16 × fperiph
• Baudrate: 2 Mbit/s
• Transmission every 8 µs
• Frame: 16 bits
IDD_BV(ADC)
CC T ADC supply current on VDD = 5.5 V Ballast static consumption
41 × fperiph
5 × fperiph
µA
µA
VDD_BV
(no conversion)
Ballast dynamic
consumption (continuous
conversion)3
IDD_HV_ADC(ADC) CC T ADC supply current on VDD = 5.5 V Analog static consumption
2 × fperiph
µA
VDD_HV_ADC
(no conversion)
Analog dynamic
consumption (continuous
conversion)
75 × fperiph + 32 µA
IDD_HV(FLASH) CC T CFlash + DFlash supply VDD = 5.5 V
current on VDD_HV
—
8.21
mA
µA
IDD_HV(PLL)
CC T PLL supply current on VDD = 5.5 V
VDD_HV
—
30 × fperiph
1
2
3
Operating conditions: TA = 25 °C, fperiph = 8 MHz to 48 MHz
fperiph is an absolute value.
During the conversion, the total current consumption is given from the sum of the static and dynamic consumption,
i.e., (41 + 5) × fperiph
.
4.18.2 DSPI characteristics
1
Table 43. DSPI characteristics
DSPI0/DSPI1
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tSCK
SR D SCK cycle time
Master mode
(MTFE = 0)
125
125
83
—
—
ns
D
D
D
Slave mode
(MTFE = 0)
—
—
—
—
—
—
—
Master mode
(MTFE = 1)
Slave mode
(MTFE = 1)
83
—
fDSPI
SR D DSPI digital controller frequency
—
fCPU MHz
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
63
Electrical characteristics
1
Table 43. DSPI characteristics (continued)
DSPI0/DSPI1
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
—
tCSC
CC D Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode
Master mode
Master mode
—
—
1302
ns
—
tASC
CC D Internal delay between pad
associated to SCK and pad
associated to CSn in master
mode for CSn11
—
—
130(2) ns
3
4
2
3
4
tCSCext
tASCext
tSDC
SR D CS to SCK delay
SR D After SCK delay
CC D SCK duty cycle
Slave mode
Slave mode
Master mode
Slave mode
—
32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
52
—
—
ns
ns
ns
1/fDSPI + 5
—
tSCK/2
—
SR
D
tSCK/2
5
6
7
8
9
tA
SR D Slave access time
1/fDSPI + 70
—
ns
ns
ns
ns
ns
tDI
SR D Slave SOUT disable time
SR D PCSx to PCSS time
SR D PCSS to PCSx time
SR D Data setup time for inputs
—
7
0
—
tPCSC
tPASC
tSUI
—
—
—
0
—
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
43
5
—
—
10
11
12
tHI
SR D Data hold time for inputs
CC D Data valid after SCK edge
CC D Data hold time for outputs
0
—
ns
ns
ns
25
—
—
0
—
6
tSUO
—
—
(6)
tHO
—
8
—
1
2
3
Operating conditions: COUT = 10 to 50 pF, SlewIN = 3.5 to 15 ns
Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields
in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure
positive tCSCext
.
4
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in
DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive
tASCext
.
5
6
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR.
SCK and SOUT configured as MEDIUM pad
MPC5602D Microcontroller Data Sheet, Rev. 6
64
Freescale Semiconductor
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
First Data
Data
Data
12
11
Last Data
SOUT
Note: Numbers shown reference Table 43.
Figure 16. DSPI classic SPI timing – master, CPHA = 0
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
65
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
Data
12
Data
Last Data
First Data
SIN
11
SOUT
Last Data
First Data
Note: Numbers shown reference Table 43.
Figure 17. DSPI classic SPI timing – master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Note: Numbers shown reference Table 43.
Figure 18. DSPI classic SPI timing – slave, CPHA = 0
MPC5602D Microcontroller Data Sheet, Rev. 6
66
Freescale Semiconductor
Electrical characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Note: Numbers shown reference Table 43.
Figure 19. DSPI classic SPI timing – slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Note: Numbers shown reference Table 43.
Figure 20. DSPI modified transfer format timing – master, CPHA = 0
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
67
Electrical characteristics
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Note: Numbers shown reference Table 43.
Figure 21. DSPI modified transfer format timing – master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Note: Numbers shown reference Table 43.
Figure 22. DSPI modified transfer format timing – slave, CPHA = 0
MPC5602D Microcontroller Data Sheet, Rev. 6
68
Freescale Semiconductor
Electrical characteristics
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Note: Numbers shown reference Table 43.
Figure 23. DSPI modified transfer format timing – slave, CPHA = 1
8
7
PCSS
PCSx
Note: Numbers shown reference Table 43.
Figure 24. DSPI PCS strobe (PCSS) timing
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
69
Package characteristics
4.18.3 JTAG characteristics
Table 44. JTAG characteristics
Value
Typ
No.
Symbol
C
Parameter
Unit
Min
Max
1
2
3
4
5
6
7
tJCYC
tTDIS
CC D TCK cycle time
CC D TDI setup time
CC D TDI hold time
83.33
15
5
—
—
—
—
—
—
—
—
—
—
—
—
49
—
ns
ns
ns
ns
ns
ns
ns
tTDIH
tTMSS
tTMSH
tTDOV
tTDOI
CC D TMS setup time
CC D TMS hold time
CC D TCK low to TDO valid
CC D TCK low to TDO invalid
15
5
—
6
TCK
2/4
3/5
INPUT DATA VALID
DATA INPUTS
6
DATA OUTPUTS
DATA OUTPUTS
OUTPUT DATA VALID
7
Note: Numbers shown reference Table 44.
Figure 25. Timing diagram – JTAG boundary scan
5
Package characteristics
Package mechanical data
100 LQFP
5.1
5.1.1
MPC5602D Microcontroller Data Sheet, Rev. 6
70
Freescale Semiconductor
Package characteristics
Figure 26. 100 LQFP package mechanical drawing (Part 1 of 3)
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
71
Package characteristics
Figure 27. 100 LQFP package mechanical drawing (Part 2 of 3)
MPC5602D Microcontroller Data Sheet, Rev. 6
72
Freescale Semiconductor
Package characteristics
Figure 28. 100 LQFP package mechanical drawing (Part 3 of 3)
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
73
Package characteristics
5.1.2
64 LQFP
Figure 29. 64 LQFP mechanical drawing (part 1 of 3)
MPC5602D Microcontroller Data Sheet, Rev. 6
74
Freescale Semiconductor
Package characteristics
Figure 30. 64 LQFP mechanical drawing (part 2 of 3)
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
75
Package characteristics
Figure 31. 64 LQFP mechanical drawing (part 3 of 3)
MPC5602D Microcontroller Data Sheet, Rev. 6
76
Freescale Semiconductor
Ordering information
6
Ordering information
Example code:
M
PC
56
0
2
D
F1
M
LL
4
R
Qualification Status
Power Architecture Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
Frequency
R = Tape & Reel (blank if Tray)
Qualification Status
M = MC status
S = Auto qualified
P = PC status
Flash Size (z0 core)
1= 128 KB
2 = 256 KB
Temperature spec.
C = –40 to 85 °C
V = –40 to 105 °C
M = –40 to 125 °C
Automotive Platform
56 = Power Architecture in 90 nm
Product
D = Access family
Package Code
LH = 64 LQFP
LL = 100 LQFP
Core Version
0 = e200z0h
Optional fields
F = ATMC
1 = Maskset revision
Frequency
4 = Up to 48 MHz
3 = Up to 32 MHz
Figure 32. Commercial product code structure
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
77
Document revision history
7
Document revision history
Table 45 summarizes revisions to this document.
Table 45. Revision history
Description of Changes
Revision
Date
1
2
30 Sep 2009 Initial release
18 Feb 2010 Updated the following tables:
- Absolute maximum ratings
- Low voltage power domain electrical characteristics;
- On-chip peripherals current consumption
- DSPI characteristics;
- JTAG characteristics;
- ADC conversion characteristics;
Inserted a note on “Flash power supply DC characteristics” section.
3
10 Aug 2010 “Features” section: Updated information concerning eMIOS, ADC, LINFlex, Nexus and
low power capabilities
“MPC5602D device comparison” table: updated the “Execution speed” row
“MPC5602D series block diagram” figure:
• updated max number of Crossbar Switches
• updated Legend
“MPC5602D series block summary” table: added contents concernig the eDMA block
“100 LQFP pin configuration (top view)” figure:
• removed alternate functions
• updated supply pins
“64 LQFP pin configuration (top view)” figure: removed alternate functions
Added “Pin muxing” section
“NVUSRO register” section: Deleted “NVUSRO[WATCHDOG_EN] field description“
section
“Recommended operating conditions (3.3 V)” table:
• TVDD: deleted min value
• In footnote No. 3, changed capacitance value between VDD_BV and VSS_LV
“Recommended operating conditions (5.0 V)” table: deleted TVDD min value
“LQFP thermal characteristics” table: changed RJC values
“I/O input DC electrical characteristics” table:
• WFI: updated max value
• WNFI: updated min value
“I/O consumption” table: removed IDYNSEG row
Added “I/O weight” table
“Program and erase specifications (Code Flash)” table: deleted TBank_C row
Updated the following tables:
• “Voltage regulator electrical characteristics”
• “Low voltage monitor electrical characteristics”
• “Low voltage power domain electrical characteristics”
• “Start-up time/Switch-off time”
• “Fast external crystal oscillator (4 to 16 MHz) electrical characteristics”
• “FMPLL electrical characteristics”
• “Fast internal RC oscillator (16 MHz) electrical characteristics”
• “ADC conversion characteristics”
• “On-chip peripherals current consumption”
• “DSPI characteristics”
“DSPI characteristics” section: removed “DSPI PCS strobe (PCSS) timing” figure
3
10 Aug 2010 “Ordering information” section: removed “Orderable part number summary“ table
(continued)
MPC5602D Microcontroller Data Sheet, Rev. 6
78
Freescale Semiconductor
Document revision history
Table 45. Revision history (continued)
Description of Changes
Revision
Date
3.1
23 Feb 2011 Deleted the “Freescale Confidential Proprietary” label (the document is public)
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
79
Document revision history
Table 45. Revision history (continued)
Description of Changes
Revision
Date
4
14 Jul 2011 Formatting and editorial changes throughout
Device comparison table: for the “Total timer I/O eMIOS”, changed “13 ch” to “14 ch”
Features: Replaced “e200z0“ with “e200z0h”; added an explanation of which LINFlex
modules support master mode and slave
MPC5601D/MPC5602D series block summary:
• added definition for “AUTOSAR” acronym
changed “System watchdog timer” to “Software watchdog timer”64 LQFP pin
configuration (top view): changed pin 6 from VPP_TEST to VSS_HV
Added section “Pad configuration during reset phases”
Added section “Voltage supply pins”
Added section “Pad types”
Added section “System pins”
Renamed and updated section “Functional ports” (was previously section “Pin muxing”);
update includes replacing all instances of WKUP with WKPU (WKPU is the correct
abbreviation for Wakeup Unit)
Section “NVUSRO register”: edited content to separate configuration into electrical
parameters and digital functionality
Added section “NVUSRO[WATCHDOG_EN] field description”
Absolute maximum ratings: Removed “C” column from table
Replaced “TBD” with “—” in TVDD min value cell of 3.3 V and 5 V recommended
operating conditions tables
LQFP thermal characteristics: removed RJB single layer board conditions; updated
footnote 4
I/O input DC electrical characteristics: removed footnote “All values need to be
confirmed during device validation”; updated ILKG characteristics
MEDIUM configuration output buffer electrical characteristics: changed “IOH = 100 µA”
to “IOL = 100 µA” in VOL conditions
I/O consumption: replaced instances of “Root medium square” with “Root mean square”
Updated section “Voltage regulator electrical characteristics”
Section “Low voltage detector electrical characteristics”: changed title (was “Voltage
monitor electrical characteristics”); added a fifth LVD (LVDHV3B); added event status
flag names found in RGM chapter of device reference manual to POR module and
LVD descriptions; replaced instances of “Low voltage monitor” with “Low voltage
detector”; deleted note referencing power domain No. 2 (this domain is not present
on the device); updated electrical characteristics table
Updated and renamed section “Power consumption” (was previously section “Low
voltage domain power consumption”)
Program and erase specifications (code flash): updated symbols; updated tesus values
Updated Flash memory read access timing
EMI radiated emission measurement: updated SEMI values
Updated FMPLL electrical characteristics
Crystal oscillator and resonator connection scheme: inserted footnote about possibly
requiring a series resistor
Fast internal RC oscillator (16 MHz) electrical characteristics: updated tFIRCSU values
Section “Input impedance and ADC accuracy”: changed “VA/VA2” to “VA2/VA” in
Equation 13
ADC conversion characteristics:
• updated conditions for sampling time VDD = 5.0 V
• updated conditions for conversion time VDD = 5.0 V
Commercial product code structure: added character for frequency; updated optional
fields character and description
Restored the revision history table and added an entry for Rev. 3.1
Updated Abbreviations
MPC5602D Microcontroller Data Sheet, Rev. 6
80
Freescale Semiconductor
Abbreviations
Table 45. Revision history (continued)
Description of Changes
Revision
Date
5
6
—
Rev. 5 not published.
29 Jan 2013 Removed all instances of table footnote “All values need to be confirmed during device
validation”
Section 4.1, “Introduction, removed Caution note.
In Table 42, On-chip peripherals current consumption, replaced “TBD” with “8.21 mA” in
IDD_HV(FLASH) cell.
Updated Section 4.17.2, “Input impedance and ADC accuracy
In Table 24, changed VLVDHV3L, VLVDHV3BL from 2.7 V to 2.6 V.
Revised the Table 28 (Flash module life)
Updated Table 43, DSPI characteristics, to add specifications 7 and 8, tPCSC and tPASC
Inserted Figure 24, DSPI PCS strobe (PCSS) timing.
.
Appendix A Abbreviations
Table A-1 lists abbreviations used in this document.
Table A-1. Abbreviations
Meaning
Abbreviation
APU
CMOS
CPHA
CPOL
CS
Auxilliary processing unit
Complementary metal–oxide–semiconductor
Clock phase
Clock polarity
Peripheral chip select
DAOC
ECC
Double action output compare
Error code correction
EVTO
GPIO
IPM
Event out
General purpose input/output
Input period measurement
Input pulse width measurement
Message buffer
IPWM
MB
MC
Modulus counter
MCB
Modulus counter buffered (up / down)
Message clock out
MCKO
MDO
Message data out
MSEO
MTFE
NVUSRO
OPWFMB
OPWMB
Message start/end out
Modified timing format enable
Non-volatile user options register
Output pulse width and frequency modulation buffered
Output pulse width modulation buffered
MPC5602D Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
81
Abbreviations
Table A-1. Abbreviations (continued)
Meaning
Abbreviation
OPWMCB
OPWMT
PWM
SAIC
SAOC
SCK
Center aligned output pulse width modulation buffered with dead time
Output pulse width modulation trigger
Pulse width modulation
Single action input capture
Single action output compare
Serial communications clock
Serial data out
SOUT
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
MPC5602D Microcontroller Data Sheet, Rev. 6
82
Freescale Semiconductor
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
Semiconductor was negligent regarding the design or manufacture of the part.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Beijing 100022
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org
China
+86 10 5879 8000
support.asia@freescale.com
For Literature Requests Only:
© Freescale Semiconductor, Inc. 2009–2013. All rights reserved.
Freescale Semiconductor Literature Distribution Center
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: MPC5602D
Rev. 6
01/2013
相关型号：
©2020 ICPDF网 联系我们和版权申明