935319553557 [NXP]
Microcontroller;
| 型号： | 935319553557 |
| 厂家： | 
NXP |
| 描述： | Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总47页 (文件大小：1165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Advanced Information
Document Number: MCF51JE256
Rev. 4, 08/2012
An Energy-Efficient Solution from Freescale
MCF51JE256/128
MCF51JE256/128
The MCF51JE256 series devices are members of the low-cost,
low-power, high-performance ColdFire V1 family of 32-bit
microcontrollers (MCUs).
Not all features are available in all devices or packages; see
Table 1 for a comparison of features by device.
80-LQFP
12mm x 12mm
100-LQFP
14mm x 14mm
81-BGA
10mm x 10mm
104-BGA
10mm x 10mm
Peripherals
32-Bit ColdFire V1 Central Processor Unit (CPU)
•
USB — Dual-role USB On-The-Go (OTG) device, supports USB in either
•
Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1 V
and 20 MHz CPU above 1.8 V across temperature range of -40°C to
105°C.
ColdFire Instruction Set Revision C (ISA_C).
32-bit multiply and accumulate (MAC) supports signed or unsigned integer
or signed fractional inputs.
device, host or OTG configuration. On-chip transceiver and 3.3V regulator
help save system cost, fully compliant with USB Specification 2.0. Allows
control, bulk, interrupt and isochronous transfers.
•
•
•
•
•
•
•
•
•
SCIx — Two serial communications interfaces with optional 13-bit break;
option to connect Rx input to PRACMP output on SCI1 and SCI2; High
current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge.
SPI1 — Serial peripheral interface with 32-bit FIFO buffer; 16-bit or 8-bit
data transfers; full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first shifting.
SPI2 — Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting.
IIC — Up to 100 kbps with maximum bus loading; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10-bit addressing.
CMT — Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out (IRO).
Can be used as an output compare timer.
TPMx — Two 4-channel Timer/PWM Module; Selectable input capture,
output compare, or buffered edge- or center-aligned PWM on each
channel; external clock input/pulse accumulator.
Mini-FlexBus — Multi-function external bus interface with user
programmable chip selects and the option to multiplex address and data
lines.
On-Chip Memory
•
256 K Flash comprised of two independent 128 K flash arrays;
read/program/erase over full operating voltage and temperature; allows
interrupt processing while programming.
32 KB System Random-access memory (RAM).
Security circuitry to prevent unauthorized access to RAM and Flash
contents.
•
•
Power-Saving Modes
•
•
•
Two ultra-low power stop modes. Peripheral clock enable register can
disable clocks to unused modules to reduce currents.
Time of Day (TOD) — Ultra low-power 1/4 sec counter with up to 64 sec
timeout.
Ultra-low power external oscillator that can be used in stop modes to
provide accurate clock source to the TOD. 6 µs typical wake up time from
stop3 mode.
Clock Source Options
•
•
•
Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or
ceramic resonator dedicated for TOD operation.
•
•
PRACMP — Analog comparator with selectable interrupt; compare option
to programmable internal reference voltage; operation in stop3.
ADC12 — 12-bit Successive approximation ADC with up to12
Oscillator (XOSC2) for high frequency crystal input for MCG reference to
be used for system clock and USB operations.
Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming
of internal reference allows 0.2% resolution and typical +0.5% to -1%
deviation over temperature and voltage; supports CPU frequencies up to
50 MHz.
single-ended channels; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V.
•
PDB — Programmable delay block with 16-bit counter and modulus and
prescale to set reference clock to bus divided by 1 to bus divided by 2048;
8 trigger outputs for ADC module provides periodic coordination of ADC
sampling sequence with sequence completion interrupt; Back-to-Back
mode and Timed mode.
System Protection
•
Watchdog computer operating properly (COP) reset with option to run from
dedicated 1 kHz internal clock source or bus clock.
•
Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warning with optional interrupt; selectable trip points.
Illegal opcode and illegal address detection with reset.
Flash block protection for each array to prevent accidental write/erasure.
Hardware CRC to support fast cyclic redundancy checks.
•
DAC — 12-bit resolution DAC; configurable settling time.
Input/Output
•
•
•
•
•
•
Up to 68 GPIOs and 1 output-only pin.
Voltage Reference output (VREFO).
Dedicated infrared output pin (IRO)
withhigh current sink capability.
Up to 16 KBI pins with selectable
polarity.
Development Support
•
Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
•
•
connection supports same electrical interface used by the S08 family
debug modules.
Up to 16 pins of rapid general purpose
I/O (RGPIO).
•
•
Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1
data).
On-chip trace buffer provides programmable start/stop recording
conditions.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
Contents
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents
Figure 14.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 36
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 38
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 38
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 39
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 39
Figure 19.Typical VREF Output vs Temperature . . . . . . . . . . . . 42
Figure 20.Typical VREF Output vs VDD . . . . . . . . . . . . . . . . . . . 43
1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pinouts and Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . .15
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16
3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .18
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21
3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.8 12-bit DAC Electricals . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.10 MCG and External Oscillator (XOSC) Characteristics .29
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .32
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .34
3
List of Tables
Table 1. MCF51JE Features by MCU and Package. . . . . . . . . . 4
Table 2. MCF51JE256/128 Functional Units. . . . . . . . . . . . . . . . 5
Table 2-3.Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16
Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 21
Table 11.Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 24
Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 24
Table 14.DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . . . 25
Table 15.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 26
Table 16.12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 28
3.12.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .41
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4
5
Table 17.MCG (Temperature Range = –40 to 105×C Ambient). 29
Table 18.XOSC (Temperature Range = –40 to 105×C Ambient) 31
Table 19.Mini-FlexBus AC Timing Specifications. . . . . . . . . . . . 32
Table 20.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24.Internal USB 3.3 V Voltage Regulator Characteristics 40
Table 25.VREF Electrical Specifications . . . . . . . . . . . . . . . . . . 41
Table 26.VREF Limited Range Operating Behaviors . . . . . . . . . 42
Table 27.Orderable Part Number Summary. . . . . . . . . . . . . . . . 44
Table 28.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
List of Figures
Figure 1.MCF51JE256/128 Block Diagram. . . . . . . . . . . . . . . . . 3
Figure 2.104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4.81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5.80-Pin LQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 23
Figure 7.Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 26
Figure 8.ADC Input Impedance Equivalency Diagram . . . . . . . 28
Figure 9.Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 33
Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 33
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MCF51JE256 Datasheet, Rev. 4
2
Freescale Semiconductor
COCOx
VDDA/VSSA
HWTRS[H:A]
PDB
HWTRS[H:A]
VREFH/VREFL
DADP[3:0]
DADM[3:0]
ADP[11:4]
DADP/M[3:0]
PTA7
PTA6
PTA5
Dtrig
ADC12
PTA4
ACMPO
VDDA/VSSA
PTA3/KBI1P2/FB_D6/ADP5
PTA2/KBI1P1/RX1/ADP4
PTA1/KBI1P0/TX1/FB_D1
PTA0/FB_D2/SS1
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB5/XTAL2
Dtrig
PRACMP
VREFH/VREFL
DACO
DACO
ACMPO
VDDA/VSSA
PTB4/EXTAL2
PTB3/XTAL1
PTB2/EXTAL1
PTB1/BLMS
PTB0
PTC7/KBI2P2CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
RX1
TX1
VREFH/VREFL
SCI1
SCI2
RX2
TX2
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE_b/FB_CS0
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
VREFO
SDA
SCL
VREF
IIC
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
KBI1 & KBI2 KBI1P[7:0]
KBI2P[7:0]
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
IRO
4 Ch TPM1
TPM1CH[3:0]
TPMCLK
IRO:
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW_b/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
CMT
Hardware CRC
DBG
4 Ch TPM2
TPM2CH[3:0]
TPMCLK
BDM
PTD0/BKGD/MS
INTC
PTF7/MISO1
PTF6/MOSI1
BKGD/MS
RGPIO
RGPIO[15:8]
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
MCG
RGPIO[7:0]
REF CLK
IRCLK
V1 ColdFire Core
with MAC
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTG7/FB_AD18
PTG6/FB_AD19
PTG5/FB_RW_b
PTG4/USB_SESSVLD
PTG3/USB_DP_DOWN
PTG2/USB_DM_DOWN
PTG1/USB_SESSEND
PTG0/SPSCK1
SPI1
SPI2
MOSI1 SS1
MISO1 SPSCK1
Clock Check
& Select
XOSC2
PTD1/CMPP2/RESET
MOSI2 SS2
MISO2 SPSCK2
SIM
PTE4/CMPP3/
TPMCLK/VPP/IRQ
CLKO
MINIFLEX
BUS
FB_D[7:0]
PTH7/RGPIOP7/FB_D2
FB_AD[19:0]
COP
LVD
IRQ
PTH6/RGPIOP6/FB_D3
PTH5/RGPIOP5/FB_D4
PTH4/RGPIOP4/FB_D5
PTH3/RGPIOP3/FB_D6
PTH2/RGPIOP2/FB_D7
PTH1/FB_D0
FB_AD[19:0]
XOSC1
EXTAL1
XTAL1
FLASH1
128/64 KB
Robust
USB_DM
USB_DP
USB_ALTCLK
USBOTG
CLKO
Update
PTH0/FB_OE_b
PTJ7/FB_AD13
FLASH2
Manager
USB_PULLUP(D+)
128/64 KB
PTJ6/FB_AD14
PTJ5/FB_AD15
PTJ4/RGPIOP15/FB_AD16
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
USB_DM_DOWN
USB_DP_DOWN
USB_VBUSVLD
RAM
32KB
VREG
USB_ID
TOD
USB_SESSVLD
USB_SESSEND
PTJ1/FB_AD3
PTJ0/FB_AD2
Green pins not available on the 100, 81 or 80 pin package
Blue pins not available on the 81 or 80 pin package
Red pin not available on the 80 pin package
VSS1,2,3
VDD1,2,3
USB_DP
VBUS
USB_DM
VUSB33
Figure 1. MCF51JE256/128 Block Diagram
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
3
Features
1
Features
The following table provides a cross-comparison of the features of the MCF51JE256/128 according to
package.
Table 1. MCF51JE Features by MCU and Package
Feature
MCF51JE256
MCF51JE128
FLASH size (bytes)
RAM size (bytes)
Pin quantity
262144
32K
131072
32K
104
100
81
80
81
80
Programmable Analog Comparator (PRACMP)
Debug Module (DBG)
yes
yes
yes
yes
yes
16
Multipurpose Clock Generator (MCG)
Inter-Integrated Communication (IIC)
Interrupt Request Pin (IRQ)
Keyboard Interrupt (KBI)
Digital General purpose I/O1
Power and Ground Pins
Time Of Day (TOD)
69
65
48
47
48
47
8
yes
yes
yes
yes
yes
yes
yes
yes
4
Serial Communications (SCI1)
Serial Communications (SCI2)
Serial Peripheral Interface (SPI1(FIFO))
Serial Peripheral Interface(SPI2)
Carrier Modulator Timer pin (IRO)
Programmable Delay Block (PDB)
TPM input clock pin (TPMCLK)
TPM1 channels
TPM2 channels
4
XOSC1
yes
yes
yes
XOSC2
USBOTG
MiniFlex Bus
yes
16
DATA
9
Rapid GPIO
ADC single-ended channels
DAC ouput pin (DACO)
12
yes
yes
Voltage reference output pin (VREFO)
1
Port I/O count does not include BLMS, BKGD and IRQ. BLMS BKGD are Output only, IRQ is input only.
The following table describes the functional units of the MCF51JE256/128.
MCF51JE256 Datasheet, Rev. 4
4
Freescale Semiconductor
Features
Table 2. MCF51JE256/128 Functional Units
Unit
Function
DAC (digital to analog converter)
Used to output voltage levels.
12-BIT SAR ADC (analog-to-digital
converter)
Measures analog voltages at up to 12 bits of resolution. The ADC has
up to 12 single-ended inputs.
PDB (Programmable Delay Block)
Mini-FlexBus
Precisely trigger the DAC FIFO buffer.
Provides expansion capability for off-chip memory and peripherals.
Supports the USB On-the-Go dual-role controller.
Infrared output used for the Remote Controller operation.
USB On-the-Go
CMT (Carrier Modulator Timer)
Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
MCG (Multipurpose Clock Generator)
BDM (Background Debug Module)
CF1 CORE (V1 ColdFire Core)
Provides single pin debugging interface (part of the V1 ColdFire core).
Executes programs and interrupt handlers.
Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
PRACMP
COP (Computer Operating Properly)
IRQ (Interrupt Request)
Software Watchdog.
Single-pin high-priority interrupt (part of the V1 ColdFire core).
High-speed CRC calculation.
CRC (Cyclic Redundancy Check)
Provides debugging and emulation capabilities (part of the V1 ColdFire
core).
DBG (Debug)
FLASH (Flash Memory)
IIC (Inter-integrated Circuits)
INTC (Interrupt Controller)
KBI1 & KBI2
Provides storage for program code, constants, and variables.
Supports standard IIC communications protocol and SMBus.
Controls and prioritizes all device interrupts.
Keyboard Interfaces 1 and 2.
Provides an interrupt to the ColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
LVD (Low-voltage Detect)
VREF (Voltage Reference)
The Voltage Reference output is available for both on- and off-chip use.
Provides stack and variable storage.
RAM (Random-Access Memory)
RGPIO (Rapid General-purpose
Input/output)
Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
SCI1, SCI2 (Serial Communications
Interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
5
Features
Table 2. MCF51JE256/128 Functional Units (continued)
Unit
Function
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces)
SPI1 and SPI2 provide standard master/slave capability. SPI contains a
FIFO buffer in order to increase the throughput for this peripheral.
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation.
TPM1, TPM2 (Timer/PWM Module)
VREG (Voltage Regulator)
Controls power management across the device.
These devices incorporate redundant crystal oscillators. One is
XOSC1 and XOSC2 (Crystal Oscillators) intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
MCF51JE256 Datasheet, Rev. 4
6
Freescale Semiconductor
Pinouts and Pin Assignments
2
2.1
Pinouts and Pin Assignments
104-Pin MAPBGA
The following figure shows the 104-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
PTF6
PTG0
IRO
PTF7
PTA0
PTG4
PTA4
PTA7
USB_DP
PTG3
PTA6
USB_DM
VBUS
PTG2
VUSB33
PTF5
PTF4
PTJ6
PTG5
VDD2
PTF3
PTH0
PTG7
FB_AD12
PTE5
PTJ7
PTF0
PTE4
PTA1
PTA2
PTJ2
PTD5
PTD4
PTC2
PTC4
PTD0
9
PTJ5
PTF1
PTE6
PTE3
PTJ3
PTJ0
PTD7
PTD3
PTC0
PTC5
PTB5
10
PTJ4
PTF2
PTE7
PTE2
PTE1
PTJ1
PTE0
PTD2
PTC1
PTC6
PTB4
11
A
B
C
D
E
F
PTG6
PTH1
PTA5
VSSA
VREFL
ADP2
PTB1
PTB0
VDD1
VDD3
PTG1
PTC7
G
H
J
G
H
J
PTA3
PTH7
ADP1
VSS1
PTH6
PTH5
VREFO
4
VSS2
PTH3
PTB7
VDDA
6
VSS3
PTD6
PTD1
PTB2
8
ADP0
PTH4
PTB6
VREFH
5
PTH2
PTC3
PTB3
7
K
L
K
L
ADP3
DACO
1
2
3
Figure 2. 104-Pin MAPBGA
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
7
Pinouts and Pin Assignments
2.2
100-Pin LQFP
The following figure shows the 100-pin LQFP pinout configuration.
PTA0/FB_D2/SS1
IRO
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
PTG5/FB_RW
4
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
PTH1/FB_D0
5
6
7
PTJ1/FB_AD3
8
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
9
PTD7/USB_PULLUP(D+)/RX1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTD6/USB_ALTCLK/TX1
PTA5
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTA6
100 LQFP
PTA7
PTB0
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTB1/BLMS
VSSA
VREFL
NC
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
NC
ADP2
NC
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
NC
NC
NC
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE/FB_CS0
Figure 3. 100-Pin LQFP
MCF51JE256 Datasheet, Rev. 4
8
Freescale Semiconductor
Pinouts and Pin Assignments
2.3
81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
1
2
3
4
5
6
VUSB33
PTE7
PTE6
PTA3
VDD1
VSS1
PTB6
PTC4
PTB3
6
7
8
9
A
B
C
D
E
F
IRO
PTG0
PTA0
PTA5
PTA7
PTF6
PTG1
PTA6
PTB0
USB_DP
USB_DM
PTA1
VBUS
PTF5
PTF2
PTA2
VDD3
VSS3
VREFO
PTC3
PTB2
5
PTF4
PTF1
PTE5
PTD5
PTD2
PTB7
PTC0
PTD0
PTD1
7
PTF3
PTF0
PTE2
PTD7
PTD3
PTC7
PTC1
PTC5
PTB4
8
PTE4
PTE3
PTE1
PTE0
PTD6
PTD4
PTC2
PTC6
PTB5
9
A
B
C
D
E
F
PTF7
PTA4
PTB1
VDD2
ADP2
VSS2
G
H
J
ADP0
DACO
ADP3
ADP1
VREFH
3
G
H
J
VSSA
VREFL
VDDA
1
2
4
Figure 4. 81-Pin MAPBGA
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
9
Pinouts and Pin Assignments
2.4
80-Pin LQFP
The following figure shows the 80-pin LQFP pinout configuration.
PTA0/FB_D2/SS1
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
IRO
2
PTA1/KBI1P0/TX1/FB_D1
3
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTA2/KBI1P1/RX1/ADP4
4
PTA3/KBI1P2/FB_D6/ADP5
5
PTA4
PTA5
PTA6
PTA7
PTB0
PTB1/BLMS
VSSA
VREFL
NC
6
7
8
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
9
10
11
12
13
14
15
16
17
18
19
20
80-Pin LQFP
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
NC
ADP2
NC
NC
NC
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
NC
Figure 5. 80-Pin LQFP Pinout
MCF51JE256 Datasheet, Rev. 4
10
Freescale Semiconductor
Pinouts and Pin Assignments
2.5
Pin Assignments
Table 3. Package Pin Assignments
Alternate 1 Alternate 2 Alternate 3
Package
Default
Function
104
MAPB
GA
81
MAPB
GA
Composite Pin Name
100
LQFP
80
LQFP
B2
C1
C6
C5
C7
B7
C8
D9
E9
H3
D2
D1
C3
E2
E3
D3
E1
F1
F2
G2
G1
H1
H2
F3
G3
L2
1
B2
A1
—
1
PTA0
IRO
FB_D2
SS1
—
—
—
PTA0/FB_D2/SS1
2
2
—
IRO
3
—
—
—
—
—
3
PTG5
PTG6
PTG7
PTH0
PTH1
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PTB0
PTB1
VSSA
VREFL
—
FB_RW
—
—
PTG5/FB_RW
4
—
FB_AD19
—
—
PTG6/FB_AD19
5
—
FB_AD18
—
—
PTG7/FB_AD18
6
—
FB_OE
FB_D0
KBI1P0
KBI1P1
KBI1P2
—
—
—
PTH0/FB_OE
7
—
—
—
PTH1/FB_D0
8
C4
D5
D6
C1
C2
C3
D2
D3
D4
J1
TX1
RX1
FB_D6
—
FB_D1
ADP4
ADP5
—
PTA1/KBI1P0/TX1/FB_D1
9
4
PTA2/KBI1P1/RX1/ADP4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
5
PTA3/KBI1P2/FB_D6/ADP5
6
PTA4
PTA5
PTA6
PTA7
PTB0
PTB1/BLMS
VSSA
VREFL
NC
7
—
—
—
8
—
—
—
9
—
—
—
10
11
12
13
19
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
—
—
—
BLMS
—
—
—
—
—
J2
—
—
—
D1
E2
F2
F1
E2
F3
E3
G2
G3
H4
G4
G1
H1
G5
H3
H2
—
—
—
—
—
—
—
NC
ADP2
—
—
—
—
ADP2
NC
—
—
—
NC
—
—
—
NC
—
—
—
—
NC
—
—
—
—
NC
DACO
ADP3
—
—
—
—
DACO
ADP3
NC
L1
—
—
—
K1
K2
J1
—
—
—
NC
—
—
—
NC
ADP0
—
—
—
—
ADP0
NC
J2
—
—
—
L4
VREFO
ADP1
NC
—
—
—
VREFO
ADP1
NC
K3
L3
—
—
—
—
—
—
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
11
Pinouts and Pin Assignments
Package
Table 3. Package Pin Assignments (continued)
Default
104
MAPB
GA
81
MAPB
GA
Alternate 1 Alternate 2 Alternate 3
Function
Composite Pin Name
100
LQFP
80
LQFP
L5
L6
35
36
37
38
39
40
41
42
43
J3
J4
F4
J5
J6
E4
J8
J9
G6
30
31
32
33
34
35
36
37
38
VREFH
VDDA
VSS2
PTB2
PTB3
VDD2
PTB4
PTB5
PTB6
—
—
—
—
VREFH
VDDA
—
—
H6
L8
—
—
—
VSS2
EXTAL1
XTAL1
—
—
—
PTB2/EXTAL1
PTB3/XTAL1
VDD2
L7
—
—
D6
L11
L10
K5
—
—
—
—
EXTAL2
XTAL2
KBI1P3
PTB4/EXTAL2
PTB5/XTAL2
—
—
RGPIOP0
FB_AD17
PTB6/KBI1P3/RGPIOP0/
FB_AD17
K6
44
F7
39
PTB7
KBI1P4
RGPIOP1
FB_AD0
PTB7/KBI1P4/RGPIOP1/
FB_AD0
J7
J6
45
46
47
48
49
50
51
52
53
54
55
56
57
—
—
—
—
—
—
—
—
40
41
42
43
44
45
46
PTH2
PTH3
PTH4
PTH5
PTH6
PTH7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
RGPIOP2
RGPIOP3
RGPIOP4
RGPIOP5
RGPIOP6
RGPIOP7
MOSI2
FB_D7
FB_D6
FB_D5
FB_D4
FB_D3
FB_D2
FB_OE
FB_D0
SPSCK2
SS2
—
—
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
J5
—
—
PTH4/RGPIOP4/FB_D5
K4
J4
—
—
PTH5/RGPIOP5/FB_D4
—
—
PTH6/RGPIOP6/FB_D3
J3
—
—
PTH7/RGPIOP7/FB_D2
J10
J11
J9
G7
G8
G9
H5
H6
H8
H9
FB_CS0
FB_AD1
ADP6
ADP7
ADP8
ADP9
ADP10
PTC0/MOSI2/FB_OE/ FB_CS0
PTC1/MISO2/FB_D0/FB_AD1
PTC2/KBI1P5/SPSCK2/ADP6
PTC3/KBI1P6/SS2/ADP7
PTC4/KBI1P7/CMPP0/ADP8
PTC5/KBI2P0/CMPP1/ADP9
MISO2
KBI1P5
K7
K9
K10
K11
KBI1P6
KBI1P7
CMPP0
CMPP1
PRACMPO
KBI2P0
KBI2P1
PTC6/KBI2P1/PRACMPO/
ADP10
F8
L9
58
59
60
61
F8
H7
J7
47
48
49
50
PTC7
PTD0
PTD1
PTD2
KBI2P2
BKGD
CLKOUT
MS
ADP11
—
PTC7/KBI2P2/CLKOUT/ADP11
PTD0/BKGD/MS
K8
CMPP2
RESET
—
PTD1/CMPP2/RESET
H11
E7
USB_ALTCL RGPIOP8
K
TPM1CH0 PTD2/USB_ALTCLK/RGPIOP8/
TPM1CH0
H10
H9
G9
J8
62
63
64
65
E8
F9
D7
E9
51
52
53
54
PTD3
PTD4
PTD5
PTD6
USB_PULL
UP(D+)
RGPIOP9
RGPIOP10
RGPIOP11
TX1
TPM1CH1
TPM1CH2
TPM1CH3
—
PTD3/USB_PULLUP(D+)/
RGPIOP9/TPM1CH1
SDA
PTD4/SDA/RGPIOP10/
TPM1CH2
SCL
PTD5/SCL/RGPIOP11/
TPM1CH3
USB_ALTCL
K
PTD6/USB_ALTCLK/TX1
MCF51JE256 Datasheet, Rev. 4
12
Freescale Semiconductor
Pinouts and Pin Assignments
Table 3. Package Pin Assignments (continued)
Package
Default
104
MAPB
GA
81
MAPB
GA
Alternate 1 Alternate 2 Alternate 3
Function
Composite Pin Name
100
LQFP
80
LQFP
G10
66
67
D8
55
56
PTD7
PTE0
USB_PULL
UP(D+)
RX1
—
PTD7/USB_PULLUP(D+) /RX1
G11
D9
KBI2P3
FB_ALE
FB_CS1
PTE0/KBI2P3/FB_ALE/
FB_CS1
F10
F11
F9
68
69
70
71
72
—
—
—
—
C9
—
—
—
—
57
PTJ0
PTJ1
PTJ2
PTJ3
PTE1
FB_AD2
FB_AD3
FB_AD4
RGPIOP12
KBI2P4
—
—
—
—
PTJ0/FB_AD2
PTJ1/FB_AD3
—
—
PTJ2/FB_AD4
E10
E11
FB_AD5
RGPIOP13
—
PTJ3/RGPIOP12/FB_AD5
FB_AD6
PTE1/KBI2P4/RGPIOP13/
FB_AD6
D11
73
C8
58
PTE2
KBI2P5
RGPIOP14
FB_AD7
PTE2/KBI2P5/RGPIOP14/
FB_AD7
D10
C9
74
75
B9
A9
59
60
PTE3
PTE4
KBI2P6
CMPP3
FB_AD8
TPMCLK
—
PTE3/KBI2P6/FB_AD8
IRQ
PTE4/CMPP3/TPMCLK/VPP/
IRQ
H8
D8
B8
76
77
78
F5
E5
C7
61
62
63
VSS3
VDD3
PTE5
—
—
—
—
—
—
VSS3
VDD3
FB_D7
USB_
SESSVLD
TX2
PTE5/FB_D7/USB_SESSVLD/
TX2
C10
C11
79
80
C6
B6
64
65
PTE6
PTE7
FB_RW
USB_
SESSEND
RX2
—
PTE6/FB_RW_b/
USB_SESSEND/RX2
USB_VBUS TPM2CH3
VLD
PTE7/USB_VBUSVLD/
TPM2CH3
B9
81
82
B8
B7
66
67
PTF0
PTF1
USB_ID
RX2
TPM2CH2
—
PTF0/USB_ID/TPM2CH2
B10
USB_DP_
DOWN
TPM2CH1
PTF1/RX2/USB_DP_DOWN/
TPM2CH1
B11
83
C5
68
PTF2
TX2
USB_DM_
DOWN
TPM2CH0
PTF2/TX2/USB_DM_DOWN/
TPM2CH0
A11
A10
B6
A9
A8
A7
A6
B5
A5
A4
A3
B4
84
85
86
87
88
89
90
91
92
93
94
95
—
—
—
—
—
—
—
69
70
71
72
73
74
75
PTJ4
PTJ5
RGPIOP15
FB_AD15
FB_AD14
FB_AD13
—
FB_AD16
—
PTJ4/RGPIOP15/FB_AD16
PTJ5/FB_AD15
—
—
—
—
PTJ6
—
PTJ6/FB_AD14
—
PTJ7
—
—
—
PTJ7/FB_AD13
—
FB_AD12
PTF3
—
FB_AD12
A8
A7
B5
A6
B4
A4
A5
SCL
FB_D5
FB_D4
FB_D3
—
FB_AD11
FB_AD10
FB_AD9
—
PTF3/SCL/FB_D5/FB_AD11
PTF4/SDA/FB_D4/FB_AD10
PTF5/KBI2P7/FB_D3/FB_AD9
VUSB33
PTF4
SDA
PTF5
KBI2P7
—
VUSB33
USB_DM
USB_DP
VBUS
—
—
—
USB_DM
—
—
—
USB_DP
—
—
—
VBUS
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
13
Pinouts and Pin Assignments
Package
Table 3. Package Pin Assignments (continued)
Default
104
MAPB
GA
81
MAPB
GA
Alternate 1 Alternate 2 Alternate 3
Function
Composite Pin Name
100
LQFP
80
LQFP
H4
D4
A1
A2
B1
F4
96
97
F6
E6
A3
B1
A2
B3
76
77
78
79
80
—
VSS1
VDD1
PTF6
PTF7
PTG0
PTG1
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS1
VDD1
—
98
MOSI1
MISO1
SPSCK1
PTF6/MOSI1
PTF7/MISO1
PTG0/SPSCK1
PTG1/USB_SESSEND
99
100
—
USB_SESS
END
C4
B3
C2
—
—
—
—
—
—
—
—
—
PTG2
PTG3
PTG4
USB_DM_D
OWN
—
—
—
—
—
—
PTG2/USB_DM_DOWN
PTG3/USB_DP_DOWN
PTG4/USB_SESSVLD
USB_DP_D
OWN
USB_SESS
VLD
MCF51JE256 Datasheet, Rev. 4
14
Freescale Semiconductor
Preliminary Electrical Characteristics
3
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51JE256/128 microcontroller, including detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however, be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
3.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 4. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
15
Preliminary Electrical Characteristics
Table 5. Absolute Maximum Ratings
#
Rating
Symbol
Value
Unit
1
2
3
Supply voltage
V
–0.3 to 3.8
120
V
mA
V
DD
Maximum current into V
Digital Input voltage
IDD
DD
V
–0.3 to VDD + 0.3
In
Instantaneous maximum current
4
5
ID
25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
T
–55 to 150
C
stg
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V or V ).
SS
DD
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
P
into account in power calculations, determine the difference between actual pin voltage and V or
I/O
SS
V
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
DD
loads), the difference between pin voltage and V or V will be very small.
SS
DD
MCF51JE256 Datasheet, Rev. 4
16
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 6. Thermal Characteristics
#
Symbol
Rating
Value
Unit
Operating temperature range (packaged):
1
2
TA
C
C
MCF51JE256
MCF51JE128
–40 to 105
–40 to 105
135
TJMAX
Maximum junction temperature
Thermal resistance1,2,3,4 Single-layer board — 1s
104-pin MBGA
67
53
67
53
3
4
JA
C/W
C/W
100-pin LQFP
81-pin MBGA
80-pin LQFP
Thermal resistance1, 2, 3, 4 Four-layer board — 2s2p
104-pin MBGA
100-pin LQFP
81-pin MBGA
80-pin LQFP
39
41
39
39
JA
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2
3
4
Junction to Ambient Natural Convection
1s — Single layer board, one signal layer
2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (T ) in C can be obtained from:
J
T = T + (P )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, C
A
= Package thermal resistance, junction-to-ambient, C/W
JA
P = P P
D
int
I/O
P
P
= I V , Watts — chip internal power
DD DD
= Power dissipation on input and output pins — user determined
int
I/O
For most applications, P P and can be neglected. An approximate relationship between P and T
I/O
int
D
J
(if P is neglected) is:
I/O
P = K (T + 273C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
2
K = P (T + 273C) + (P )
Eqn. 3
D
A
JA
D
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
17
Preliminary Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
3.4
ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Series Resistance
R1
C
1500
100
3
pF
—
Human Body
Storage Capacitance
Number of Pulse per pin
Series Resistance
—
R1
C
0
Machine
Latch-up
Storage Capacitance
200
3
pF
—
V
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
—
—
—
–2.5
7.5
V
Table 8. ESD and Latch-Up Protection Characteristics
#
Rating
Symbol
Minimum
Maximum
Unit
C
1
2
3
4
Human Body Model (HBM)
Machine Model (MM)
VHBM
VMM
VCDM
ILAT
2000
200
500
00
—
—
—
—
V
V
T
T
T
T
Charge Device Model (CDM)
Latch-up Current at TA = 125C
V
mA
3.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
MCF51JE256 Datasheet, Rev. 4
18
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 9. DC Characteristics
#
Symbol
Characteristic
Operating Voltage
Condition
Minimum Typical1 Maximum Unit
C
1
—
—
1.82
—
3.6
V
—
Output high
voltage
2
VOH
All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = –600 A
VDD – 0.5
—
—
V
C
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = –10 mA
VDD – 0.5
VDD – 0.5
—
—
—
—
—
—
V
V
V
P
T
VDD 2.3 V,
ILoad = –6 mA
VDD 1.8V,
Load = –3 mA
VDD – 0.5
C
I
Output high
current
3
4
IOHT
Max total IOH for all ports
—
—
—
—
—
100
0.5
mA
V
D
C
Output low
voltage
VOL
All I/O pins, low-drive strength
VDD 1.8 V,
ILoad = 600 A
All I/O pins, high-drive strength
VDD 2.7 V,
ILoad = 10 mA
—
—
—
—
—
—
0.5
0.5
0.5
V
V
V
P
T
VDD 2.3 V,
ILoad = 6 mA
VDD 1.8 V,
ILoad = 3 mA
C
Output low
current
Max total IOL for all ports
5
6
IOLT
—
—
—
100
mA
D
VIH
Input high voltage all digital inputs
Input low voltage all digital inputs
VDD 2.7 V
VDD 1.8 V
0.70 x VDD
0.85 x VDD
—
—
—
—
V
V
P
C
7
VIL
VDD 2.7 V
VDD 1.8 V
—
—
—
—
—
—
0.35 x VDD
0.30 x VDD
—
V
V
P
C
C
8
9
Vhys Input hysteresis
all digital inputs
0.06 x VDD
mV
Input leakage
current
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
VIn = VDD or VSS
—
—
—
0.5
0.5
A
A
P
P
Hi-Z (off-state)
all input/output
(per pin)
10
|IOZ
|
0.003
leakage current3
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
19
Preliminary Electrical Characteristics
Table 9. DC Characteristics (continued)
#
Symbol
Characteristic
Condition
Minimum Typical1 Maximum Unit
C
all digital inputs, when
enabled
11
RPU
Pull-up resistors
—
17.5
17.5
—
—
52.5
52.5
k
k
P
12
Internal
RPD
pull-down
—
P
D
resistors4
13
Single pin limit
VSS > VIN > VDD
–0.2
–5
—
—
0.2
5
mA
mA
DC injection
current 5, 6, 7
IIC
Total MCU limit, includes
sum of all stressed pins
V
SS > VIN > VDD
14
CIn
Input Capacitance, all pins
—
—
—
—
—
—
—
0.6
1.4
—
8
pF
V
C
C
C
D
15 VRAM RAM retention voltage
16 VPOR POR re-arm voltage8
1.0
1.79
—
0.9
10
V
17
tPOR POR re-arm time
s
18 VLVDH Low-voltage detection threshold — high range9
VDD falling
VDD rising
2.11
2.16
2.16
2.21
2.22
2.27
V
V
P
P
19 VLVDL Low-voltage detection threshold — low range9
20 VLVWH Low-voltage warning threshold — high range9
VDD falling
VDD rising
1.80
1.86
1.82
1.90
1.91
1.99
V
V
P
P
VDD falling
2.56
2.56
2.36
2.36
2.46
2.46
V
V
P
P
VDD rising
21 VLVWL Low-voltage warning threshold — low range9
VDD falling
2.11
2.16
2.16
2.21
2.22
2.27
V
V
P
P
VDD rising
Low-voltage inhibit reset/recover
22
23
Vhys
VBG
—
—
—
50
—
mV
V
C
P
hysteresis10
Bandgap Voltage Reference11
1.145
1.17
1.195
1
2
3
Typical values are measured at 25C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL
Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left floating when not used
to reduce current leakage.
.
4
5
6
Measured with VIn = VDD.
All functional non-supply pins are internally clamped to VSS and VDD,except PTD1.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values
for positive and negative clamp voltages, then use the larger of the two values.
7
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive
injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out
of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU
is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power
consumption).
MCF51JE256 Datasheet, Rev. 4
20
Freescale Semiconductor
Preliminary Electrical Characteristics
8
Maximum is highest voltage that POR is guaranteed.
Run at 1 MHz bus frequency.
9
10
11
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Factory trimmed at VDD = 3.0 V, Temp = 25C.
3.6
Supply Current Characteristics
Table 10. Supply Current Characteristics
Bus
Freq
VDD
(V)
Temperature
#
Symbol
Parameter
Typical1 Maximum Unit
C
(C)
Run supply current
1
RIDD
FEI mode, all modules ON2
25.165 MHz
25.165 MHz
20 MHz
3
3
3
3
3
44
44
48
48
—
—
—
mA
mA
mA
mA
mA
–40 to 25
105
P
P
T
T
T
32.3
16.4
2.9
–40 to 105
–40 to 105
–40 to 105
8 MHz
1 MHz
Run supply current
2
RIDD
FEI mode, all modules OFF3
25.165 MHz
20 MHz
8 MHz
3
3
3
3
29
29.6
—
mA
mA
mA
mA
–40 to 105
–40 to 105
–40 to 105
–40 to 105
C
T
T
T
25.4
12.7
2.4
—
1 MHz
—
Run supply current
3
4
RIDD
LPR=0, all modules OFF3
16 kHz FBI
16 kHz FBE
3
3
232
231
280
296
A
A
–40 to 105
–40 to 105
T
T
Run supply current
RIDD
LPR=1, all modules OFF3
16 kHz
BLPE
3
3
74
74
75
A
A
0 to 70
T
T
16 kHz
BLPE
120
–40 to 105
Wait mode supply current
5
WIDD
FEI mode, all modules OFF3
25.165 MHz
3
16.5
—
mA
–-40 to 105
C
20 MHz
8 MHz
1 MHz
3
3
3
10.3
6.6
—
—
—
mA
mA
mA
–-40 to 105
–-40 to 105
–-40 to 105
T
T
T
1.7
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
21
Preliminary Electrical Characteristics
Table 10. Supply Current Characteristics (continued)
Bus
Freq
VDD
(V)
Temperature
#
Symbol
Parameter
Typical1 Maximum Unit
C
(C)
Stop2 mode
6
S2IDD
supply current4
N/A
3
0.410
1
A
-40 to 25
P
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3
3
3
2
2
2
2
3.7
10
10
20
A
A
A
A
A
A
A
70
85
C
C
P
C
C
C
C
21
31.5
0.640
9
105
0.410
3.4
9.5
20
-40 to 25
70
18
85
30
105
Stop3 mode
7
S3IDD
supply current
No clocks active
N/A
3
0.750
1.3
A
-40 to 25
P
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3
3
3
2
2
2
2
8.5
20
18
28
A
A
A
A
A
A
A
70
85
C
C
P
C
C
C
C
53
63
105
0.400
8.2
18
0.900
16
-40 to 25
70
26
85
47
59
105
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
ON = System Clock Gating Control registers turn on system clock to the corresponding modules.
OFF = System Clock Gating Control registers turn off system clock to the corresponding modules.
All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages may have some pins that
are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in a known state.
Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. NOTE: I/O pins are configured to
output low; input-only pins are configured to pullup-enabled. IRO pin connects to ground. FB_AD12 pin is pullup-enabled. DACO, and VREFO pins
are at reset state and unconnected.
Table 11. Stop Mode Adders
Temperature (°C)
#
Parameter
Condition
Units
C
-40
25
70
85
105
1
2
3
4
LPO
—
50
600
—
75
650
73
100
750
80
150
850
93
250
1000
125
nA
nA
A
nA
D
D
T
EREFSTEN
IREFSTEN1
TOD
RANGE = HGO = 0
—
Does not include clock source current
50
75
100
150
250
D
MCF51JE256 Datasheet, Rev. 4
22
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. Stop Mode Adders (continued)
Temperature (°C)
#
Parameter
LVD1
Condition
Units
C
-40
25
70
85
105
5
6
LVDSE = 1
116
17
117
18
126
24
132
35
172
74
A
A
T
T
PRACMP1
Not using the bandgap (BGBE = 0)
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
7
8
ADC1
75
85
100
500
115
500
165
500
A
A
T
T
DAC1
High power mode; no load on DACO
500
500
1
Not available in stop2 mode.
Figure 6. Stop IDD versus Temperature
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
23
Preliminary Electrical Characteristics
3.7
PRACMP Electricals
Table 12. PRACMP Electrical Specifications
#
Characteristic
Supply voltage
Symbol
Minimum Typical Maximum
Unit
C
1
2
3
VPWR
IDDACT1
IDDACT2
1.8
—
—
—
—
3.6
80
40
V
P
D
D
Supply current (active) (PRG enabled)
Supply current (active) (PRG disabled)
A
A
—
Supply current (ACMP and PRG all
disabled)
4
IDDDIS
—
—
2
nA
D
5
6
7
8
9
Analog input voltage
VAIN
VAIO
VSS – 0.3
—
5
VDD
40
V
mV
mV
nA
s
V
D
D
D
D
D
D
Analog input offset voltage
Analog comparator hysteresis
Analog input leakage current
Analog comparator initialization delay
—
3.0
—
VH
—
—
—
—
20.0
1
IALKG
tAINIT
—
1.0
2.75
10 Programmable reference generator inputs
VIn2 (VDD25
)
1.8
Programmable reference generator setup
delay
11
tPRGST
Vstep
—
1
1
—
1.25
Vin
s
LSB
V
D
D
P
Programmable reference generator step
size
12
0.75
Programmable reference generator voltage
range
13
Vprgout
VIn/32
—
3.8
12-bit DAC Electricals
Table 13. DAC 12LV Operating Requirements
#
1
2
3
4
Characteristic
Symbol
VDDA
VDACR
TA
Minimum Maximum
Unit
C
P
C
C
C
C
Supply voltage
1.8
1.15
-40
—
3.6
3.6
105
100
1
V
V
Reference voltage
Temperature
°C
pF
mA
Output load capacitance1
Output load current
CL
IL
5
—
1
A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
MCF51JE256 Datasheet, Rev. 4
24
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
Symbol Minimum Typical Maximum Unit
#
Characteristic
C
Notes
1
Resolution
N
12
—
—
12
bit
T
IDDA_DAC
2
3
Supply current low-power mode
Supply current high-power mode
50
100
A
T
T
LP
IDDA_DAC
—
—
345
—
500
200
A
HP
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
Full-scale Settling time (1 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode
TsFSLP
4
5
s
T
T
• Temperature
= 25°C
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
Full-scale Settling time (1 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode
TsFSHP
TsC-CLP
—
—
—
30
5
s
• Temperature
= 25°C
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
Code-to-code Settling time (1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8) low-power mode
6
7
—
1
s
s
T
T
• Temperature = 25°C
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
Code-to-code Settling time (1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8) high-power mode
TsC-CHP
—
—
—
• Temperature = 25°C
DAC output voltage range low
(high-power mode, no load, DAC set
to 0, 3 V at room temperature)
100
Vdacoutl
8
9
—
—
mV
mV
T
T
DAC output voltage range high
(high-power mode, no load, DAC set
to 0x0FFF)
—
Vdacouth VDACR–100
10 Integral non-linearity error
INL
—
—
—
—
8
LSB
LSB
T
T
Differential non-linearity error
11
DNL
±1
VDACR is > 2.4 V
Calculated by a best fit
curve from VSS +
100mV to VREFH
%FSR
12 Offset error
EO
—
±0.4
±3
T
–100mV
Calculated by a best fit
curve from VSS +
100mV to VREFH
Gain error (VREF = Vext = VDD
)
%FSR
13
14
EG
—
±0.1
—
±0.5
—
T
T
–100mV
Power supply rejection ratio
VDD 2.4 V
PSRR
60
dB
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
25
Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Symbol Minimum Typical Maximum Unit
C
Notes
Temperature drift of offset voltage
(DAC set to 0x0800)1
2
See Typical Drift figure
that follows.
Tco
AC
15
—
—
—
—
mV
T
T
16 Offset aging coefficient
8
V/yr
1
See Typical Drift figure that follows.
Figure 7. Offset at Half Scale vs Temperature
3.9
ADC Characteristics
Table 15. 12-bit ADC Operating Conditions
Minimum Typical1 Maximum Unit
#
Symb
VDDAD Supply voltage Absolute
VDDAD Delta to VDD (VDD-VDDAD
Characteristic
Conditions
C
1
2
3
4
1.8
—
3.6
V
mV
mV
V
D
D
D
D
2
)
-100
-100
1.13
0
0
+100
+100
VDDAD
Supply voltage
2
VSSAD Ground voltage
Delta to VSS (VSS-VSSAD
—
)
VREFH Ref Voltage High
VDDAD
MCF51JE256 Datasheet, Rev. 4
26
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 15. 12-bit ADC Operating Conditions (continued)
#
Symb
Characteristic
Conditions
Minimum Typical1 Maximum Unit
C
5
6
VREFL Ref Voltage Low
—
—
VSSAD
VREFL
VSSAD
—
VSSAD
VREFH
V
V
D
D
VADIN
CADIN
Input Voltage
Input
Capacitance
7
—
—
—
—
4
2
5
5
pF
C
C
8
9
RADIN
RAS
Input Resistance
k
Analog Source Resistance3
12 bit mode
1
k
C
fADCK > 8 MHz
—
—
4 MHz < fADCK > 8 MHz
fADCK < 4 MHz
k
k
k
C
C
C
—
—
—
—
2
5
10-bit mode
ADCK > 8MHz
f
—
—
—
—
—
—
2
5
4 MHz < fADCK < 8 MHz
fADCK < 4 MHz
k
k
C
C
10
8-bit mode
k
k
C
C
fADCK > 8 MHz
—
—
—
—
5
fADCK < 8 MHz
10
10
fADCK
ADC Conversion Clock Freq.
High Speed (ADLPC=0,
ADHSC=1)
1.0
1.0
1.0
—
—
—
8.0
5.0
2.5
MHz
MHz
MHz
D
D
D
High Speed (ADLPC=0,
ADHSC=0)
Low Power (ADLPC=1,
ADHSC=1)
1
Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
DC potential difference.
External to MCU. Assumes ADLSMP=0.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
27
Preliminary Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 8. ADC Input Impedance Equivalency Diagram
Table 16. 12-bit SAR ADC Characteristics full operating range
(V = V , V = V
)
SSAD
REFH
DDAD REFL
#
Symbol Characteristic
Conditions1
Minimum Typical2 Maximum
Unit
C
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1
Stop, Reset, Module Off
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
—
—
—
—
—
—
215
470
610
0.01
2.4
—
—
—
—
—
—
A
A
T
T
T
C
P
P
Supply Current
IDDAD (ADLSMP=0,
ADCO=1)
1
A
A
ADC
Asynchronous
fADACK Clock Source
(tADACK
MHz
MHz
5.2
2
ADLPC=0, ADHSC=1
—
6.2
—
MHz
P
=1/fADACK
)
3
4
—
—
Sample Time — See Reference Manual for sample times.
Conversion Time — See Rreference Manual for conversion times.
Total Unadjusted 12-bit single-ended mode
—
—
1.75
0.8
3.5
LSB3
LSB3
T
T
Error
10-bit single-ended mode
±1.5
32x Hardware
5
6
TUE
Averaging(AVGE
= %1 AVGS =
%11)
8-bit single-ended mode
—
0.5
±1.0
LSB3
T
12-bit single-ended mode
—
—
—
0.7
0.5
0.2
1
LSB3
LSB3
LSB3
T
T
T
Differential
Non-Linearity
10-bit single-ended mode
±0.75
±0.5
8-bit single-ended mode
MCF51JE256 Datasheet, Rev. 4
28
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 16. 12-bit SAR ADC Characteristics full operating range
(V
= V
, V
= V
) (continued)
REFH
DDAD REFL
SSAD
#
Symbol Characteristic
Conditions1
Minimum Typical2 Maximum
Unit
C
12-bit single-ended mode
10-bit single-ended mode
8-bit single-ended mode
12-bit single-ended mode
10-bit single-ended mode
8-bit single-ended mode
12-bit single-ended mode
10-bit single-ended mode
8-bit single-ended mode
—
—
—
—
—
—
—
—
—
1.0
0.5
0.3
0.7
0.4
0.2
1.0
0.4
0.2
2.5
±1.0
±0.5
2.0
±1.0
±0.5
3.5
±1.5
±0.5
LSB3
LSB3
LSB3
LSB3
LSB3
LSB3
LSB3
LSB3
LSB3
T
T
T
T
T
T
T
T
T
Integral
INL
7
Non-Linearity
Zero-Scale Error
EZS
8
(VADIN = VSSAD
)
Full-Scale Error
(VADIN = VDDAD
9
EFS
)
Quantization
Error
10
EQ
All modes
—
—
±0.5
LSB3
D
Input Leakage
Error (IIn
=
11
EIL
leakage current All modes
(refer to DC
IIn * RAS
mV
D
Characteristics)
-40C to 25C
—
—
1.646
1.769
—
—
mV/xC
mV/xC
C
C
Temp Sensor
Slope
12
13
m
25C to 125C
25C
Temp Sensor
Voltage
VTEMP25
—
701.2
—
mV
C
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only
.
2
and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
3
3.10 MCG and External Oscillator (XOSC) Characteristics
Table 17. MCG (Temperature Range = –40 to 105C Ambient)
#
Rating
Internal reference startup time
Symbol
Min
Typical
Max
Unit
C
tirefst
1
—
55
100
s
D
factory trimmed at
VDD=3.0V and
temp=25C
—
31.25
—
kHz
C
Average internal reference
frequency
fint_ft
2
user trimmed
31.25
16
—
—
—
39.0625
20
KHz
MHz
MHz
C
C
C
Low range (DRS=00)
Mid range (DRS=01)
fdco_t
DCO output frequency range -
trimmed
32
40
3
4
High range1
(DRS=10)
40
—
60
MHz
C
Resolution of trimmed DCO output
frequency at fixed voltage and
temperature
%fdco
%fdco
with FTRIM
—
—
0.1
0.2
0.2
0.4
C
C
fdco_res_t
without FTRIM
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
29
Preliminary Electrical Characteristics
Table 17. MCG (Temperature Range = –40 to 105C Ambient) (continued)
#
Rating
Symbol
Min
Typical
Max
Unit
C
over voltage and
temperature
%fdco
—
1.0
2
P
Total deviation of trimmed DCO
output frequency over voltage and
temperature
fdco_t
5
over fixed voltage
and temp range
of 0 - 70 C
%fdco
—
0.5
1
C
FLL2
PLL3
—
—
—
—
1
1
ms
ms
C
D
tfll_acquire
tpll_acquire
Acquisition time
6
7
Long term Jitter of DCO output clock (averaged over 2mS
interval) 4
CJitter
%fdco
—
0.02
0.2
C
fvco
8
9
VCO operating frequency
7.0
1.0
—
—
55.0
2.0
MHz
MHz
D
D
fpll_ref
PLL reference frequency range
0.5664
Jitter of PLL output clock measured
Long term
fpll_jitter_625
10
—
—
%fpll
D
over 625 ns
ns
Entry5
Exit6
1.49
4.47
—
—
2.98
5.97
%
%
D
D
Dlock
Dunl
11 Lock frequency tolerance
12 Lock time
tfll_acquire+
1075(1/fint_t)
tfll_lock
FLL
—
—
—
s
D
tpll_acquire+
tpll_lock
floc_low
floc_high
PLL
—
—
—
s
D
D
1075(1/fpll_ref)
(3/5) x
fint_t
13 Loss of external clock minimum frequency - RANGE = 0
—
—
kHz
kHz
(16/5) x
fint_t
14 Loss of external clock minimum frequency - RANGE = 1
D
1
2
This should not exceed the maximum CPU frequency of 50.33 MHz.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
being used as the reference, this specification assumes it is already running.
3
4
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI)
to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are
made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via
V
DD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
5
6
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already
in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
MCF51JE256 Datasheet, Rev. 4
30
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 18. XOSC (Temperature Range = –40 to 105C Ambient)
Symbol Minimum Typical1 Maximum Unit
#
Characteristic
• Low range (RANGE = 0)
flo
32
1
—
—
38.4
5
kHz
• High range (RANGE = 1),
• FEE or FBE mode 2
fhi-fll
MHz
• High range (RANGE = 1),
• PEE or PBE mode 3
fhi-pll
1
1
—
—
16
16
MHz
MHz
Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
1
• High range (RANGE = 1),
• High gain (HGO = 1),
• FBELP mode
fhi-hgo
• High range (RANGE = 1),
• Low power (HGO = 0),
• FBELP mode
fhi-lp
1
—
8
MHz
C1
C2
2
3
Load capacitors
See Note 4
Low range
(32 kHz to 38.4 kHz)
Feedback resistor
RF
—
—
—
—
—
10
1
M
k
High range
(1 MHz to 16 MHz)
Series resistor — Low range
Series resistor — High range
Low Gain (HGO = 0)
High Gain (HGO = 1)
• Low Gain (HGO = 0)
• High Gain (HGO = 1)
8 MHz
—
—
—
0
100
0
—
—
—
4
5
RS
RS
—
—
—
0
0
0
0
k
4 MHz
10
20
1 MHz
Low range, low gain
(RANGE=0,HGO=0)
—
—
200
400
—
—
t
CSTL
Low range, high gain
(RANGE=0,HGO=1)
6
Crystal start-up time 5, 6
ms
High range, low gain
(RANGE=1,HGO=0)
—
—
5
—
—
tCSTH
High range, high gain (RANGE=1,
HGO=1)
15
1
2
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625
kHz.
3
4
5
6
When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz.
See crystal or resonator manufacturer’s recommendation.
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
o
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
31
Preliminary Electrical Characteristics
3.11 Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to
interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected
to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices, a simple
chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect
to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus
frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the
Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
Table 19. Mini-FlexBus AC Timing Specifications
#
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
C
1
2
3
—
—
39.73
—
25.1666
—
MHz
ns
—
D
T
Clock Period
Output Valid1
Output Hold1
Input Setup2
Input Hold2
MB1
MB2
20
ns
4
5
6
MB3
MB4
MB5
1.0
22
10
—
—
—
ns
ns
ns
D
T
D
1
2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
MCF51JE256 Datasheet, Rev. 4
32
Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 9. Mini-FlexBus Read Timing
Figure 10. Mini-FlexBus Write Timing
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
33
Preliminary Electrical Characteristics
3.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.12.1 Control Timing
Table 20. Control Timing
Typica
l1
#
Parameter
Symbol
Minimum
Maximum
Unit
C
1
Bus frequency (tcyc = 1/fBus)
VDD 1.8 V
fBus
fBus
fBus
dc
dc
dc
—
—
—
10
20
MHz
MHz
MHz
D
D
V
DD > 2.1 V
DD > 2.4 V
V
25.165
D
P
2
Internal low-power oscillator period
External reset pulse width2
tLPO
700
1000
1300
s
(tcyc
1/fSelf_reset
=
3
4
5
6
textrst
trstdrv
tMSSU
tMSH
100
66 x tcyc
500
—
—
—
—
—
—
—
—
ns
ns
ns
ns
D
D
D
D
)
Reset low drive
Active background debug mode
latch setup time
latch hold time
Active background debug mode
IRQ pulse width
100
7
•
•
Asynchronous path2
Synchronous path3
100
1.5 x tcyc
D
D
tILIH, IHIL
t
—
—
—
—
ns
ns
KBIPx pulse width
8
9
•
•
Asynchronous path2
Synchronous path3
100
1.5 x tcyc
tILIH, IHIL
t
Port rise and fall time (load = 50 pF)4, Low Drive
Slew rate
controldisabled
(PTxSE = 0)
tRise, tFall
tRise, tFall
tRise, tFall
tRise, tFall
—
—
—
—
11
35
40
75
—
—
—
—
ns
ns
ns
ns
D
D
D
D
Slew rate
control enabled
(PTxSE = 1)
Slew rate
controldisabled
(PTxSE = 0)
Slew rate
control enabled
(PTxSE = 1)
1
2
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset
requests from internal sources.
3
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be
recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
MCF51JE256 Datasheet, Rev. 4
34
Freescale Semiconductor
Preliminary Electrical Characteristics
textrst
RESET PIN
Figure 11. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 12. IRQ/KBIPx Timing
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
35
Preliminary Electrical Characteristics
3.12.2 TPM Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 21. TPM Input Timing
#
C
Function
Symbol
Minimum Maximum Unit
1
2
3
4
5
—
—
D
External clock frequency
External clock period
fTPMext
tTPMext
tclkh
dc
4
fBus/4
—
MHz
tcyc
tcyc
tcyc
tcyc
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
D
tclkl
—
D
tICPW
—
tTPMext
tclkh
TPMxCLK
tclkl
Figure 13. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 14. Timer Input Capture Pulse
MCF51JE256 Datasheet, Rev. 4
36
Freescale Semiconductor
Preliminary Electrical Characteristics
3.13 SPI Characteristics
The following table and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 22. SPI Timing
No.1
Characteristic2
Operating frequency
Symbol
Minimum
Maximum
Unit
C
1
Master
Slave
fop
fop
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
D
SPSCK period
2
3
4
5
6
7
Master
Slave
tSPSCK
tSPSCK
2
4
2048
—
tcyc
tcyc
D
D
D
D
D
D
Enable lead time
Master
Slave
tLead
tLead
12
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
tLag
tLag
12
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Master
Slave
tWSPSCK
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
Master
Slave
tSU
tSU
15
15
—
—
ns
ns
Master
Slave
tHI
tHI
0
25
—
—
ns
ns
8
9
Slave access time3
ta
—
—
1
1
tcyc
tcyc
D
D
Slave MISO disable time4
tdis
Data valid (after SPSCK edge)
10
11
12
13
Master
Slave
tv
tv
—
—
25
25
ns
ns
D
D
D
D
Data hold time (outputs)
Rise time
Master
Slave
tHO
tHO
0
0
—
—
ns
ns
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
1
2
Numbers in this column identify elements in Figure 15 through Figure 18.
All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins. All timing assumes slew
DD
DD
rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
3
4
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
37
Preliminary Electrical Characteristics
SS1
(OUTPUT)
2
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
4
5
SCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
11
BIT 6 . . . 1
11
LSB IN
12
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
2
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
5
4
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
12
BIT 6 . . . 1
LSB IN
11
MOSI
(OUTPUT)
MSB OUT(2)
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. SPI Master Timing (CPHA = 1)
MCF51JE256 Datasheet, Rev. 4
38
Freescale Semiconductor
Preliminary Electrical Characteristics
SS
(INPUT)
3
2
SCK
5
4
(CPOL = 0)
4
5
(INPUT)
2
SCK
(CPOL = 1)
(INPUT)
9
8
12
11
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
7
SLAVE
6
MOSI
(INPUT)
MSB IN
LSB IN
NOTE:
1. Not defined, but normally MSB of character just received
Figure 17. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
2
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
4
5
SCK
(CPOL = 1)
(INPUT)
11
SLAVE MSB OUT
12
9
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
NOTE
6
7
8
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined, but normally LSB of character just received
Figure 18. SPI Slave Timing (CPHA = 1)
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
39
Preliminary Electrical Characteristics
3.14 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
For more detailed information about program/erase operations, see the Memory chapter in the Reference
Manual for this device (MCF51JE256RM).
Table 23. Flash Characteristics
#
Characteristic
Symbol
Minimum
Typical
Maximum
Unit
C
Supply voltage for program/erase
-40C to 105C
1
—
D
Vprog/erase
VRead
fFCLK
tFcyc
1.8
1.8
150
5
3.6
3.6
V
2
3
4
5
6
7
8
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
—
—
V
D
D
D
P
P
P
P
200
6.67
kHz
s
—
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
tBurst
4
tPage
4000
20,000
Mass erase time2
tMass
Program/erase endurance3
TL to TH = –40C to + 105C
T = 25C
9
10,000
—
—
100,000
—
—
C
C
cycles
years
10 Data retention4
tD_ret
15
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating
approximate time to program and erase.
3
4
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using
the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618,
Typical Data Retention for Nonvolatile Memory.
3.15 USB Electricals
The USB electricals for the USB On-the-Go module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the
standard or require additional information, this space would be used to communicate that information.
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics
Maximu
#
Characteristic
Symbol
Minimum
Typical
Unit
C
m
1
2
Regulator operating voltage
VREG output
Vregin
3.9
3
—
5.5
V
V
C
P
Vregout
3.3
3.75
MCF51JE256 Datasheet, Rev. 4
40
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics (continued)
Maximu
m
#
Characteristic
Symbol
Minimum
Typical
Unit
C
VUSB33 input with internal VREG
disabled
3
4
Vusb33in
IVRQ
3
3.3
0.5
3.6
—
V
C
C
VREG Quiescent Current
—
mA
3.16 VREF Electrical Specifications
Table 25. VREF Electrical Specifications
#
Characteristic
Supply voltage
Symbol
Minimum
Maximum
Unit
C
1
2
3
4
5
VDDA
TA
1.80
–40
—
3.6
105
100
10
V
C
nf
C
C
Temperature
Output Load Capacitance
Maximum Load
CL
D
—
—
mA
—
Voltage Reference Output with Factory
Trim. VDD = 3 V.
Vout
1.148
1.152
V
P
6
Temperature Drift (Vmin - Vmax across
the full temperature range)
Tdrift
—
—
—
25
60
mV1
V/year
A
T
C
C
7
8
Aging Coefficient2
Ac
I
Powered down Current (Off Mode,
VREFEN = 0, VRSTEN = 0)
0.10
9
Bandgap only (MODE_LV[1:0] = 00)
Low-Power buffer (MODE_LV[1:0] = 01)
I
I
—
—
75
A
A
T
T
10
11
125
Tight-Regulation buffer (MODE_LV[1:0]
= 10)
I
—
1.1
mA
T
12
13
Load Regulation (MODE_LV = 10)
—
—
100
V/mA
C
C
Line Regulation MODE = 1:0, Tight
Regulation VDD < 2.3 V, Delta VDDA =
100 mV, VREFH = 1.2 V driven
externally with VREFO disabled.
(Power Supply Rejection
DC
70
dB
—
1
2
See typical chart below.
Linear reliability model (1008 hours stress at 125oC = 10 years operating life) used to calculate Aging V/year. Vrefo data recorded per
month.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
41
Preliminary Electrical Characteristics
Table 26. VREF Limited Range Operating Behaviors
#
Characteristic
Symbol
Minimum
Maximum
Unit
C
Voltage Reference Output with
Factory Trim
1.149
1
Vout
1.152
mV
T
Temperature Drift (Vmin – Vmax
Temperature range from 0° C to
50° C
2
Tdrift
—
3
mV1
T
1
See typical chart that follows (Figure 19).
Figure 19. Typical VREF Output vs Temperature
MCF51JE256 Datasheet, Rev. 4
42
Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 20. Typical VREF Output vs V
DD
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
43
Ordering Information
4
Ordering Information
This section contains ordering information for the device numbering system. See Table 1 for feature
summary by package information.
4.1
Part Numbers
Table 27. Orderable Part Number Summary
Freescale Part
Flash / SRAM
Description
(Kbytes)
Package
Temperature
Number
MCF51JE256VML
MCF51JE256VLL
MCF51JE256VMB
MCF51JE256VLK
MCF51JE128VMB
MCF51JE256CML
MCF51JE256CLL
MCF51JE256CMB
MCF51JE256CLK
MCF51JE128CMB
MCF51JE128CLK
MCF51JE256 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE128 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE256 ColdFire Microcontroller
MCF51JE128 ColdFire Microcontroller
MCF51JE128 ColdFire Microcontroller
256K/32K
256K/32K
256K/32K
256K/32K
128K/32K
256K/32K
256K/32K
256K/32K
256K/32K
128K/32K
128K/32K
104 MAPBGA
100 LQFP
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
81 MAPBGA
80 LQFP
81 MAPBGA
104 MAPBGA
10O LQFP
81 MAPBGA
80 LQFP
81 MAPBGA
80 LQFP
4.2
Package Information
Table 28. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
100
80
Low Quad Flat Package
Low Quad Flat Package
MAP BGA Package
LQFP
LQFP
LL
LK
983-03
1418
98ASS23308W
98ASS23174W
98ARH98267A
98ASA10670D
104
81
MAPBGA
MAPBGA
ML
MB
1285-02
1662-01
MAP BGA Package
4.3
Mechanical Drawings
Table 28 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51JE256/128 Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
•
Click on the appropriate link in Table 28, or
MCF51JE256 Datasheet, Rev. 4
44
Freescale Semiconductor
Revision History
®
•
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate
document number (from Table 28) in the “Enter Keyword” search box at the top of the page.
5
Revision History
This section lists major changes between versions of the MCF51JE256 Data Sheet.
Table 29. Revision History
Revision
Date
Description
0
March/April 09 Initial Draft
• Revised to follow standard template.
• Removed extraneous headings from the TOC.
• Corrected units for Monotoncity to be blank in for the DAC specification.
• Updated ADC characteristic tables to include 16-Bit SAR in headings.
1
2
July 2009
July 2009
• Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference
Frequency typical value from 32.768 to 31.25
• Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices.
• Revised the ESD and Latch-Up Protection Characeristic description to read: Latch-up
Current at TA = 125°C.
• Changed Table 9. DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA
conditions to 1.8 V, ILoad = 600A respectively.
• Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value
to be 1.13 instead of 1.15.
• Updated the ADC electricals.
• Inserted the Mini-FlexBus Timing Specifications.
3
April 2010
• Added a Temp Drift parameter to the VREF Electrical Specifications.
• Removed the S08 Naming Convention diagram.
• Updated the Orderable Part Number Summary to include the Freescale Part Number
suffixes.
• Completed the Package Description table values.
• Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W.
• Updated electrical characteristic data.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
45
Revision History
Revision
Table 29. Revision History
Description
Date
• In Table 1.”MCF51JE256/128 Features by MCU and Package, removed the row of
“12-bit SAR ADCDifferential Channels”.
• In Table 3, “Package Pin Assignments”, changed from: ‘A1’ — PTG1 USB_
SESSEND to:’B3’ — PTG1 USB_ SESSEND.
• In Table 10,”Supply Current Characteristics”, for S3IDD changed the max value from
‘1.2’ to ‘1.3’ and typical value from ‘0.650’ to ‘0.750’ for the first row.
• In Table 10,”Supply Current Characteristics”:
— For parameter 3 and parameter 4 changed LPS to LPR.
— For parameter 3,changed “FBILP” to “FBI”.
— For parameter 4, changed “FBELP” to “BLPE”.
• Fixed the TBD parameters and added figure"Typical Output vs VDD", following the
same setup of MM256DS
4
August 2012
— Added Figure 7,”Offset at Half Scale vs Temperature”.
— Updated Table 9,”DC Characteristics”.
— Updated Table 10,”Supply Current Characteristics”.
— Updated Table 11,”Stop Mode Adders”.
— Added Figure 20,”Typical Output vs. VDD
.
— Updated Table 14,”DAC 12-Bit Operating Behaviors”.
— Updated Table 20,”Control Timing”.
— Removed “SPI Electrical Characteristics” table.
— Updated Table 25”VREF Electrical Specifications”.
— Updated Table 26,”VREF Limited Range Operating Behaviors“.
• Updated Figure 3, Figure 4, and Figure 5.
MCF51JE256 Datasheet, Rev. 4
46
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Document Number: MCF51JE256
Rev. 4
08/2012
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