935319668557 [NXP]

RISC Microcontroller;


型号：	935319668557
厂家：	NXP
描述：	RISC Microcontroller 微控制器外围集成电路
文件：	总126页 (文件大小：1934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC5634M

Rev. 9.2, 01/2015

Freescale Semiconductor

MPC5634M Microcontroller

Datasheet

This is the MPC5634M Datasheet set consisting of the following files:

•

MPC5634M Datasheet Addendum (MPC5634M_AD), Rev. 1

MPC5634M Datasheet (MPC5634M), Rev. 9

MPC5634M_AD

Rev. 1.0, 01/2015

Freescale Semiconductor

Datasheet Addendum

MPC5634M Microcontroller

Datasheet Addendum

Table of Contents

Addendum List for Revision 9. . . . . . . . . . . . . . . . 2

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2

This addendum describes corrections to the MPC5634M

Microcontroller Datasheet, order number MPC5634M.

For convenience, the addenda items are grouped by

revision. Please check our website at

http://www.freescale.com/powerarchitecture for the

latest updates.

The current version available of the MPC5634M

Microcontroller Datasheet is Revision 9.

1 Addendum List for Revision 9

Table 1. MPC5634M Rev 9 Addendum

Location

Description

Section 4.11, “Temperature In “Temperature Sensor Electrical Characteristics” table, update the Min and Max value of

Sensor Electrical

Characteristics”,

Page 81

“Accuracy” parameter to -20^oC and +20^oC, respectively.

2 Revision History

Table 2 provides a revision history for this datasheet addendum document.

Table 2. Revision History Table

Rev. Number

Substantive Changes

Date of Release

1.0

Initial release.

12/2014

MPC5634M_AD, Rev. 1.0

Freescale Semiconductor

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

Home Page:

freescale.com

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freescale.com/support

Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for

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are the property of their respective owners.

Document Number: MPC5634M_AD

Rev. 1.0

01/2015

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5634M

Rev. 9, 05/2012

MPC5634M

144 LQFP

208 MAPBGA

20 mm x 20 mm

17 mm x 17 mm

MPC5634M Microcontroller

Data Sheet

176 LQFP

24 mm x 24 mm

•

Operating Parameters

•

High performance e200z335 core processor

— Fully static operation, 0 MHz – 80 MHz (plus

2% frequency modulation - 82 MHz)

— 32-bit Power Architecture Book E

programmer’s model

— –40 C to 150 C junction temperature

— Variable Length Encoding Enhancements

operating range

–

Allows Power Architecture instruction set to

be optionally encoded in a mixed 16 and

32-bit instructions

— Low power design

–

Less than 400 mW power dissipation

(nominal)

–

Results in smaller code size

Designed for dynamic power management

of core and peripherals

— Single issue, 32-bit Power Architecture

technology compliant CPU

Software controlled clock gating of

peripherals

— In-order execution and retirement

— Precise exception handling

— Branch processing unit

Low power stop mode, with all clocks

stopped

–

Dedicated branch address calculation adder

— Fabricated in 90 nm process

— 1.2 V internal logic

Branch acceleration using Branch

Lookahead Instruction Buffer

— Single power supply with

5.0 V   5% (4.5 V to 5.25 V) with

internal regulator to provide 3.3 V and 1.2 V for

the core

— Load/store unit

–

One-cycle load latency

Fully pipelined

— Input and output pins with

Big and Little Endian support

Misaligned access support

Zero load-to-use pipeline bubbles

5.0 V   5% (4.5 V to 5.25 V) range

–

35%/65% V

hysteresis)

CMOS switch levels (with

DDE

— Thirty-two 64-bit general purpose registers

(GPRs)

–

Selectable hysteresis

Selectable slew rate control

— Memory management unit (MMU) with

16-entry fully-associative translation look-aside

buffer (TLB)

— Nexus pins powered by 3.3 V supply

— Designed with EMI reduction techniques

–

Phase-locked loop

— Separate instruction bus and load/store bus

— Vectored interrupt support

Frequency modulation of system clock

frequency

— Interrupt latency < 120 ns @ 80 MHz

(measured from interrupt request to execution of

first instruction of interrupt exception handler)

–

On-chip bypass capacitance

Selectable slew rate and drive strength

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

Table of Contents

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58

4.3.1 General notes for specifications at maximum

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.2 MPC5634M feature details . . . . . . . . . . . . . . . . . . . . . . .9

2.2.1 e200z335 core. . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.2.2 Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2.3 eDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . .12

2.2.5 FMPLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.2.6 Calibration EBI. . . . . . . . . . . . . . . . . . . . . . . . . .13

2.2.7 SIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.2.8 ECSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.2.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.2.10 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2.11 BAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2.12 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.2.13 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.2.14 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.2.15 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.2.16 eSCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.2.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.2.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.2.19 Software Watchdog Timer (SWT) . . . . . . . . . . .24

2.2.20 Debug features . . . . . . . . . . . . . . . . . . . . . . . . .24

2.3 MPC5634M series architecture. . . . . . . . . . . . . . . . . . .26

2.3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.3.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . .27

Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .29

3.1 144 LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2 176 LQFP pinout (MPC5634M) . . . . . . . . . . . . . . . . . .30

3.3 176 LQFP pinout (MPC5633M) . . . . . . . . . . . . . . . . . .32

3.4 208 MAPBGA ballmap (MPC5634M) . . . . . . . . . . . . . .33

3.5 208 MAPBGA ballmap (MPC5633M only) . . . . . . . . . .34

3.6 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.7 Signal details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .56

junction temperature . . . . . . . . . . . . . . . . . . . . 60

4.4 Electromagnetic Interference (EMI) characteristics. . . 62

4.5 Electromagnetic static discharge (ESD) characteristics62

4.6 Power Management Control (PMC)

and Power On Reset (POR) electrical specifications . 63

4.6.1 Regulator example. . . . . . . . . . . . . . . . . . . . . . 67

4.6.2 Recommended power transistors . . . . . . . . . . 69

4.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . 69

4.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 70

4.9 I/O Pad current specifications . . . . . . . . . . . . . . . . . . . 77

4.9.1 I/O pad VRC33 current specifications . . . . . . . 78

4.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 79

4.10 Oscillator and PLLMRFM electrical characteristics . . . 80

4.11 Temperature sensor electrical characteristics . . . . . . . 82

4.12 eQADC electrical characteristics. . . . . . . . . . . . . . . . . 82

4.13 Platform flash controller electrical characteristics . . . . 85

4.14 Flash memory electrical characteristics. . . . . . . . . . . . 85

4.15 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.15.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . 87

4.16 AC timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.16.1 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 90

4.16.2 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.16.3 Calibration bus interface timing . . . . . . . . . . . . 96

4.16.4 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.16.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.16.6 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 105

Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 106

5.1.1 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.1.2 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.1.3 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 113

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 117

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

— Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g.,

power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be

recoverable)

— Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt

Controller. (Always recoverable)

— New ‘Wait for Interrupt’ instruction, to be used with new low power modes

— Reservation instructions for implementing read-modify-write accesses

— Signal processing extension (SPE) APU

–

Operating on all 32 GPRs that are all extended to 64 bits wide

Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including

integer vector MAC and MUL operations) (SIMD)

–

Provides rich array of extended 64-bit loads and stores to/from extended GPRs

Fully code compatible with e200z6 core

— Floating point (FPU)

–

IEEE 754 compatible with software wrapper

Scalar single precision in hardware, double precision with software library

Conversion instructions between single precision floating point and fixed point

Fully code compatible with e200z6 core

— Long cycle time instructions, except for guarded loads, do not increase interrupt latency

— Extensive system development support through Nexus debug port

Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)

— Three master ports, four slave ports

•

–

Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA

Slave: Flash; SRAM; Peripheral Bridge; calibration EBI

— 32-bit internal address bus, 64-bit internal data bus

Enhanced direct memory access (eDMA) controller

— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers

— Supports variable sized queues and circular queues

— Source and destination address registers are independently configured to post-increment or remain constant

— Each transfer is initiated by a peripheral, CPU, or eDMA channel request

— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

•

Interrupt controller (INTC)

— 191 peripheral interrupt request sources

— 8 software setable interrupt request sources

— 9-bit vector

–

Unique vector for each interrupt request source

Provided by hardware connection to processor or read from register

— Each interrupt source can be programmed to one of 16 priorities

— Preemption

–

Preemptive prioritized interrupt requests to processor

ISR at a higher priority preempts ISRs or tasks at lower priorities

Automatic pushing or popping of preempted priority to or from a LIFO

Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling

Protocol for accessing shared resources.

— Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

•

Frequency Modulating Phase-locked loop (FMPLL)

— Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution

— Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL

to re-lock

— System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode

— Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the

FMPLL input

— Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

— VCO free-running frequency range from 25 MHz to 125 MHz

— Four bypass modes: crystal or external reference with PLL on or off

— Two normal modes: crystal or external reference

— Programmable frequency modulation

–

Triangle wave modulation

— Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status

to report loss of lock conditions

–

User-selectable ability to generate an interrupt request upon loss of lock

User-selectable ability to generate a system reset upon loss of lock

— Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output

clocks

–

User-selectable ability to generate an interrupt request upon loss of clock

User-selectable ability to generate a system reset upon loss of clock

Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock

•

Calibration bus interface (EBI)

— Available only in the calibration package (496 CSP package)

— 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)

— Memory controller with support for various memory types

— 16-bit data bus, up to 22-bit address bus

— Selectable drive strength

— Configurable bus speed modes

— Bus monitor

— Configurable wait states

•

System integration unit (SIU)

— Centralized GPIO control of 80 I/O pins

— Centralized pad control on a per-pin basis

–

Pin function selection

Configurable weak pull-up or pull-down

Drive strength

Slew rate

Hysteresis

— System reset monitoring and generation

— External interrupt inputs, filtering and control

— Critical Interrupt control

— Non-Maskable Interrupt control

— Internal multiplexer subblock (IMUX)

–

Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

–

Allows selection of interrupt requests between external pins and DSPI

•

Error correction status module (ECSM)

— Configurable error-correcting codes (ECC) reporting

— Single-bit error correction reporting

On-chip flash memory

— Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface

— 16 KB shadow block

— Fetch Accelerator

–

Provide single cycle flash access at 80 MHz

Quadruple 128-bit wide prefetch/burst buffers

Prefetch buffers can be configured to prefetch code or data or both

— Censorship protection scheme to prevent flash content visibility

— Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other

array (used for EEPROM emulation)

— Memory block:

–

For MPC5634M: 18 blocks (4 16 KB, 2 32 KB, 2 64 KB, 10 128 KB)

For MPC5633M: 14 blocks (4 16 KB, 2 32 KB, 2 64 KB, 6 128 KB)

For MPC5632M: 12 blocks (4 16 KB, 2 32 KB, 2 64 KB, 4 128 KB)

— Hardware programming state machine

•

On-chip static RAM

— For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply

— For MPC5633M: 64 KB general purpose RAM of which 32 KB are on standby power supply

— For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply

Boot assist module (BAM)

— Enables and manages the transition of MCU from reset to user code execution in the following configurations:

–

Execution from internal flash memory

Execution from external memory on the calibration bus

Download and execution of code via FlexCAN or eSCI

•

Periodic interrupt timer (PIT)

— 32-bit wide down counter with automatic reload

— Four channels clocked by system clock

— One channel clocked by crystal clock

— Each channel can produce periodic software interrupt

— Each channel can produce periodic triggers for eQADC queue triggering

— One channel out of the five can be used as wake-up timer to wake device from low power stop mode

System timer module (STM)

•

— 32-bit up counter with 8-bit prescaler

— Clocked from system clock

— Four-channel timer compare hardware

— Each channel can generate a unique interrupt request

— Designed to address AUTOSAR task monitor function

Software watchdog timer (SWT)

— 32-bit timer

— Clock by system clock or crystal clock

— Can generate either system reset or non-maskable interrupt followed by system reset

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

— Enabled out of reset

•

Enhanced modular I/O system (eMIOS)

— 16 timer channels (up to 14 channels in 144 LQFP)

— 24-bit timer resolution

— Supports a subset of the timer modes found in eMIOS on MPC5554

— 3 selectable time bases plus shared time or angle counter bus from eTPU2

— DMA and interrupt request support

— Motor control capability

Second-generation enhanced time processor unit (eTPU2)

— Object-code compatible with eTPU—no changes are required to hardware or software if only eTPU features are

used

— Intelligent co-processor designed for timing control

— High level tools, assembler and compiler available

— 32 channels (each channel has dedicated I/O pin in all packages)

— 24-bit timer resolution

— 14 KB code memory and 3 KB data memory

— Double match and capture on all channels

— Angle clock hardware support

— Shared time or angle counter bus with eMIOS

— DMA and interrupt request support

— Nexus Class 1 debug support

— eTPU2 enhancements

–

Counters and channels can run at full system clock speed

Software watchdog

Real-time performance monitor

Instruction set enhancements for smaller more flexible code generation

Programmable channel mode for customization of channel operation

•

Enhanced queued A/D converter (eQADC)

— Two independent on-chip redundant signed digit (RSD) cyclic ADCs

–

8-, 10-, and 12-bit resolution

Differential conversions

Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and 8-bit accuracy at 1 MSample/s

(ADC_CLK = 15 MHz) for differential conversions

–

Differential channels include variable gain amplifier (VGA) for improved dynamic range (1; 2; 4)

Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics

(200 k; 100 k; low value of 5 k)

–

Single-ended signal range from 0 to 5 V

Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

Provides time stamp information when requested

Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)

Supports both right-justified unsigned and signed formats for conversion results

Temperature sensor to enable measurement of die temperature

Ability to measure all power supply pins directly

— Automatic application of ADC calibration constants

–

Provision of reference voltages (25% VREF and 75% VREF) for ADC calibration purposes

— Up to 34 input channels available to the two on-chip ADCs

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

— Four pairs of differential analog input channels

— Full duplex synchronous serial interface to an external device

–

Has a free-running clock for use by the external device

Supports a 26-bit message length

Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers,

or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are

full

— Parallel Side Interface to communicate with an on-chip companion module

— Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued

conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion is 13 system clocks + 1

ADC clock.)

— eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC

command word. Controlled by two different trigger signals; one to define the rate at which results are generated

and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific

time/angle windows, e.g., engine knock sensor sampling.

— Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform Finite

Impulse Response (FIR) or Infinite Impulse Response (IIR) filtering also in the time domain, but to down sample

the results in the angle domain. Resulting in a time domain filtered result at a given engine angle.

— Priority Based CFIFOs

–

Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When

commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served

first.

–

Supports software and several hardware trigger modes to arm a particular CFIFO

Generates interrupt when command coherency is not achieved

— External Hardware Triggers

–

Supports rising edge, falling edge, high level and low level triggers

Supports configurable digital filter

— Supports four external 8-to-1 muxes which can expand the input channel number from 34 to 59

•

Two deserial serial peripheral interface modules (DSPI)

— SPI

–

Full duplex communication ports with interrupt and DMA request support

Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family)

Support for queues in RAM

6 chip selects, expandable to 64 with external demultiplexers

Programmable frame size, baud rate, clock delay and clock phase on a per frame basis

Modified SPI mode for interfacing to peripherals with longer setup time requirements

LVDS option for output clock and data to allow higher speed communication

— Deserial serial interface (DSI)

–

Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO

32 bits per DSPI module

Triggered transfer control and change in data transfer control (for reduced EMI)

Compatible with Microsecond Channel Version 1.0 downstream

•

Two enhanced serial communication interface (eSCI) modules

— UART mode provides NRZ format and half or full duplex interface

— eSCI bit rate up to 1 Mbps

1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.

1. 176-pin and 208-ball packages.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

— Advanced error detection, and optional parity generation and detection

— Word length programmable as 8, 9, 12 or 13 bits

— Separately enabled transmitter and receiver

— LIN support

— DMA support

— Interrupt request support

— Programmable clock source: system clock or oscillator clock

— Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0

Two FlexCAN

•

— One with 32 message buffers; the second with 64 message buffers

— Full implementation of the CAN protocol specification, Version 2.0B

— Based on and including all existing features of the Freescale TouCAN module

— Programmable acceptance filters

— Short latency time for high priority transmit messages

— Arbitration scheme according to message ID or message buffer number

— Listen only mode capabilities

— Programmable clock source: system clock or oscillator clock

— Message buffers may be configured as mailboxes or as FIFO

Nexus port controller (NPC)

•

— Per IEEE-ISTO 5001-2003

— Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1

— Read and write access (Nexus class 3 feature that is supported on this device)

–

Run-time access of entire memory map

Calibration

— Support for data value breakpoints / watchpoints

–

Run-time access of entire memory map

Calibration

Table constants calibrated using MMU and internal and external RAM

Scalar constants calibrated using cache line locking

— Configured via the IEEE 1149.1 (JTAG) port

•

IEEE 1149.1 JTAG controller (JTAGC)

— IEEE 1149.1-2001 Test Access Port (TAP) interface

— 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions

— 5-bit instruction register that supports additional public instructions

— Three test data registers: a bypass register, a boundary scan register, and a device identification register

— Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled

until the next reset

— TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

•

On-chip Voltage Regulator for single 5 V supply operation

—

On-chip regulator 5 V to 3.3 V for internal supplies

On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic

Low-power modes

SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the PLL) selectively

disabled in software

—

— STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system

clock after a predetermined time

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Introduction

1.1

Document overview

This document provides an overview and describes the features of the MPC5634M series of microcontroller units (MCUs). For

functional characteristics, refer to the device reference manual. Electrical specifications and package mechanical drawings are

included in this device data sheet. Pin assignments can be found in both the reference manual and data sheet.

1.2

Description

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that contain all the features of the

MPC5500 family and many new features coupled with high performance 90 nm CMOS technology to provide substantial

reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of

this automotive controller family is built on Power Architecture technology. This family contains enhancements that improve

the architecture’s fit in embedded applications, includes additional instruction support for digital signal processing (DSP),

integrates technologies—such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller

Area Network, and an enhanced modular input-output system—that are important for today’s lower-end powertrain

applications. This device family is a completely compatible extension to Freescale’s MPC5500 family. The device has a single

level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device

also has an external bus interface (EBI) for ‘calibration’. This external bus interface has been designed to support most of the

standard memories used with the MPC5xx and MPC55xx families.

Overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5634M series of

microcontroller units (MCUs). For functional characteristics, refer to the MPC5634M Microcontroller Reference Manual.

The MPC5634M series microcontrollers are system-on-chip devices that are built on Power Architecture technology and:

•

Are 100% user-mode compatible with the Power Architecture instruction set

Contain enhancements that improve the architecture’s fit in embedded applications

Include additional instruction support for digital signal processing (DSP)

Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter,

Controller Area Network, and an enhanced modular input-output system

2.1

Device comparison

2.2

MPC5634M feature details

e200z335 core

2.2.1

The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction

Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback

(stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.

The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a

Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 3232

Hardware Multiplier array, result feed-forward hardware, and support hardware for division.

Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A

Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a

supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches.

Prefetched instructions are placed into an instruction buffer capable of holding six instructions.

Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the

instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer,

a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated

and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle

to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These

include unconditional branches and conditional branches with condition codes that can be resolved early.

Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching

which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two

clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign

extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow

effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore

operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be

optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases.

The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power

Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move,

integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching.

Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple

interrupt sources to have unique interrupt handlers invoked with no software overhead.

The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision

floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands,

thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type.

Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are

multi-cycle and are not pipelined.

The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a

full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL)

in a pipelined fashion. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide

and are used for source and destination operands, thus there is a unified storage model for 3232 MAC operations which

generate greater than 32-bit results.

The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar

and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer

of data to and from the extended 64-bit GPRs. This SPE APU is fully binary compatible with e200z6 SPE APU used in

MPC5554 and MPC5553.

The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power

Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit

instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The Power

Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are designated as

PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.

The CPU core is enhanced by the addition of two additional interrupt sources; Non-Maskable Interrupt and Critical Interrupt.

These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely

the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable

Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of

the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt

is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed

to be recoverable (code execution may be resumed from where it stopped).

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When

Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt

source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.

2.2.2

Crossbar

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The

crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access

a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher

priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher

priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave

port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following

features:

•

3 master ports:

— e200z335 core complex Instruction port

— e200z335 core complex Load/Store port

— eDMA

•

4 slave ports

— FLASH

— calibration bus

— SRAM

— Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM

and SWT)

•

32-bit internal address, 64-bit internal data paths

2.2.3

eDMA

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture

includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,

along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation

is utilized to minimize the overall block size. The eDMA module provides the following features:

•

All data movement via dual-address transfers: read from source, write to destination

Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes

Transfer control descriptor organized to support two-deep, nested transfer operations

An inner data transfer loop defined by a “minor” byte transfer count

An outer data transfer loop defined by a “major” iteration count

Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continuous transfers

— Peripheral-paced hardware requests (one per channel)

•

Support for fixed-priority and round-robin channel arbitration

Channel completion reported via optional interrupt requests

1 interrupt per channel, optionally asserted at completion of major iteration count

Error termination interrupts are optionally enabled

Support for scatter/gather DMA processing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

•

Channel transfers can be suspended by a higher priority channel

2.2.4

Interrupt controller

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically

scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request

sources, plus 165 sources reserved for compatibility with other family members).

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor

is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority

ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that

all tasks which share the resource can not preempt each other.

Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software

setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion

and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a

software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt

requests can be used instead of the peripheral ISR scheduling a task through the RTOS.

The INTC provides the following features:

•

356 peripheral interrupt request sources

8 software setable interrupt request sources

9-bit vector addresses

Unique vector for each interrupt request source

Hardware connection to processor or read from register

Each interrupt source can be programmed to one of 16 priorities

Preemptive prioritized interrupt requests to processor

ISR at a higher priority preempts executing ISRs or tasks at lower priorities

Automatic pushing or popping of preempted priority to or from a LIFO

Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources

Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

2.2.5

FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock

generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication

factor, output clock divider ratio are all software configurable. The PLL has the following major features:

•

Input clock frequency from 4 MHz to 20 MHz

Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in system clock frequencies from

16 MHz to 80 MHz with granularity of 4 MHz or better

•

Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock

3 modes of operation

— Bypass mode with PLL off

— Bypass mode with PLL running (default mode out of reset)

— PLL normal mode

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

•

Each of the three modes may be run with a crystal oscillator or an external clock reference

Programmable frequency modulation

— Modulation enabled/disabled through software

— Triangle wave modulation up to 100 kHz modulation frequency

— Programmable modulation depth (0% to 2% modulation depth)

— Programmable modulation frequency dependent on reference frequency

•

Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to

report loss of lock conditions

Clock Quality Module

— detects the quality of the crystal clock and cause interrupt request or system reset if error is detected

— detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system

clock to the crystal clock and causes an interrupt request

•

Programmable interrupt request or system reset on loss of lock

2.2.6

Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal

connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System. The

Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The

Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI

supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed

region-specific attributes. The calibration EBI supports the following features:

•

22-bit address bus (two most significant signals multiplexed with two chip selects)

16-bit data bus

Multiplexed mode with addresses and data signals present on the data lines

NOTE

The calibration EBI must be configured in multiplexed mode when the extended Nexus

trace is used on the VertiCal Calibration System. This is because Nexus signals and address

lines of the calibration bus share the same balls in the calibration package.

•

Memory controller with support for various memory types:

— Asynchronous/legacy flash and SRAM

— Most standard memories used with the MPC5xx or MPC55xx family

Bus monitor

— User selectable

— Programmable timeout period (with 8 external bus clock resolution)

Configurable wait states (via chip selects)

•

3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals)

2 write/byte enable (WE[0:1]/BE[0:1]) signals

Configurable bus speed modes

— system frequency

— 1/2 of system frequency

— 1/4 of system frequency

•

Optional automatic CLKOUT gating to save power and reduce EMI

Compatible with MPC5xx external bus (with some limitations)

Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

2.2.7

SIU

The MPC5634MSIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),

internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot

configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block

provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring

of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU

core is via the crossbar switch. The SIU provides the following features:

•

System configuration

— MCU reset configuration via external pins

— Pad configuration control for each pad

— Pad configuration control for virtual I/O via DSPI serialization

System reset monitoring and generation

— Power-on reset support

•

— Reset status register provides last reset source to software

— Glitch detection on reset input

— Software controlled reset assertion

•

External interrupt

— 11 interrupt requests

— Rising or falling edge event detection

— Programmable digital filter for glitch rejection

— Critical Interrupt request

— Non-Maskable Interrupt request

•

GPIO

— GPIO function on 80 I/O pins

— Virtual GPIO on 64 I/O pins via DSPI serialization (requires external deserialization device)

— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin

Internal multiplexing

— Allows serial and parallel chaining of DSPIs

— Allows flexible selection of eQADC trigger inputs

— Allows selection of interrupt requests between external pins and DSPI

2.2.8

ECSM

The error correction status module provides status information regarding platform memory errors reported by error-correcting

codes.

2.2.9

Flash

Devices in the MPC5634M family provide up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile

memory (NVM) can be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes

the performance of the flash array to match the CPU architecture and provides single cycle random access to the flash @

80 MHz. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA

transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface

to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential

lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are

registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be

automatically controlled, and are restricted to instruction fetch.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

The flash memory provides the following features:

•

Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword

reads are supported. Only aligned word and doubleword writes are supported.

•

Fetch Accelerator

— Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the

flash up to 80 MHz system clock speed

— Configurable read buffering and line prefetch support

— Four line read buffers (128 bits wide) and a prefetch controller

Hardware and software configurable read and write access protections on a per-master basis

•

Interface to the flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in

parallel for interleaved or pipelined flash array designs

•

Configurable access timing allowing use in a wide range of system frequencies

Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation

of other memory types

•

Software programmable block program/erase restriction control

Erase of selected block(s)

Read page size of 128 bits (four words)

ECC with single-bit correction, double-bit detection

Program page size of 64 bits (two words)

ECC single-bit error corrections are visible to software

Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC

Embedded hardware program and erase algorithm

Erase suspend

Shadow information stored in non-volatile shadow block

Independent program/erase of the shadow block

2.2.10 SRAM

The MPC5634M SRAM module provides a general-purpose up to 94 KB memory block. The SRAM controller includes these

features:

•

Supports read/write accesses mapped to the SRAM memory from any master

32 KB or 24 KB block powered by separate supply for standby operation

Byte, halfword, word and doubleword addressable

ECC performs single-bit correction, double-bit detection on 32-bit data element

2.2.11 BAM

The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by Freescale and is identical for all

MPC5634M MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM

supports different modes of booting. They are:

•

Booting from internal flash memory

Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)

Booting from external memory on calibration bus

The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5634M

hardware accordingly. The BAM provides the following features:

•

Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address

translation

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

•

Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE

code

•

Detection of user boot code

Automatic switch to serial boot mode if internal flash is blank or invalid

Supports user programmable 64-bit password protection for serial boot mode

Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol

Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing

Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code

Supports booting from calibration bus interface

Supports censorship protection for internal flash memory

Provides an option to enable the core watchdog timer

Provides an option to disable the software watchdog timer

2.2.12 eMIOS

The eMIOS (Enhanced Modular Input Output System) module provides the functionality to generate or measuretime events.

The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual

output compare as well as PWM output.

The eMIOS provides the following features:

•

16 channels (24-bit timer resolution)

For compatibility with other family members selected channels and timebases are implemented:

— Channels 0 to 6, 8 to 15, and 23

— Timebases A, B and C

•

Channels 1, 3, 5 and 6 support modes:

— General Purpose Input/Output (GPIO)

— Single Action Input Capture (SAIC)

— Single Action Output Compare (SAOC)

•

Channels 2, 4, 11 and 13 support all the modes above plus:

— Output Pulse Width Modulation Buffered (OPWMB)

Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:

— Input Period Measurement (IPM)

— Input Pulse Width Measurement (IPWM)

— Double Action Output Compare (set flag on both matches) (DAOC)

— Modulus Counter Buffered (MCB)

— Output Pulse Width and Frequency Modulation Buffered (OPWFMB)

Three 24-bit wide counter buses

•

— Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can use it as a reference

— Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference

— Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a reference

Shared time bases with the eTPU2 through the counter buses

Synchronization among internal and external time bases

•

2.2.13 eTPU2

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes

instructions and real-time input events, performs output waveform generation, and accesses shared data without host

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful

timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler

and documentation allows customers to develop their own functions on the eTPU2.

The eTPU2 includes these distinctive features:

•

The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input

[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this

enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture

characteristics of this channel mode can be programmed via microcode.

Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can

also be requested simultaneously at the same instruction.

•

Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

Channel digital filters can be bypassed.

The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input

[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

•

Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this

enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture

characteristics of this channel mode can be programmed via microcode.

Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can

also be requested simultaneously at the same instruction.

•

Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

Channel digital filters can be bypassed.

32 channels, each channel is associated with one input and one output signal

— Enhanced input digital filters on the input pins for improved noise immunity.

— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned

to more than one channel at a given time, so each signal can have any functionality.

— Each channel has an event mechanism which supports single and double action functionality in various

combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and

equal-only comparators

— Input and output signal states visible from the host

•

2 independent 24-bit time bases for channel synchronization:

— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by

output of second time base prescaler

— Second time base counter can work as a continuous angle counter, enabling angle based applications to match

angle instead of time

— Both time bases can be exported to the eMIOS timer module

— Both time bases visible from the host

Event-triggered microengine:

— Fixed-length instruction execution in two-system-clock microcycle

— 14 KB of code memory (SCM)

— 3 KB of parameter (data) RAM (SPRAM)

— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected

combinations

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,

bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign

extension and conditional execution

— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,

and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands

•

Resource sharing features support channel use of common channel registers, memory and microengine time:

— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,

host-configured priority

— Automatic channel context switch when a “task switch” occurs, i.e., one function thread ends and another begins

to service a request from other channel: channel-specific registers, flags and parameter base address are

automatically loaded for the next serviced channel

— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or

inter-channel

— Dual-parameter coherency hardware support allows atomic access to two parameters by host

Test and development support features:

•

— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware

breakpoints and watchpoints on several conditions

— Software breakpoints

— SCM continuous signature-check built-in self test (MISC — multiple input signature calculator), runs

concurrently with eTPU2 normal operation

System enhancements

— Software watchdog with programmable timeout

— Real-time performance information

Channel enhancements

•

— Channels 1 and 2 can optionally drive angle clock hardware

Programming enhancements

— Engine relative addressing mode

2.2.14 eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of

applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master

to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.

The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to

the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six

result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having

the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort

a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a

deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger

occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands

from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result

queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system

memory, which is external to the eQADC.

The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used

in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for

increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.

The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate,

passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band

noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully

process the digitized waveform.

The eQADC provides the following features:

•

Dual on-chip ADCs

— 2  12-bit ADC resolution

— Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)

–

12-bit conversion time – 1 s (1M sample/sec)

10-bit conversion time – 867 ns (1.2M sample/second)

8-bit conversion time – 733 ns (1.4M sample/second)

— Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s

— Differential conversions

— Single-ended signal range from 0 to 5 V

— Variable gain amplifiers on differential inputs (1, 2, 4)

— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

— Provides time stamp information when requested

— Parallel interface to eQADC CFIFOs and RFIFOs

— Supports both right-justified unsigned and signed formats for conversion results

•

Up to 34 input channels (accessible by both ADCs)

23 additional internal channels for measuring control and monitoring voltages inside the device

— Including Core voltage, I/O voltage, LVI voltages, etc.

•

An internal bandgap reference to allow absolute voltage measurements

4 pairs of differential analog input channels

— Programmable pull-up/pull-down resistors on each differential input for biasing and sensor diagnostic (200 k,

100 k, 5 k)

•

Silicon die temperature sensor

— provides temperature of silicon as an analog value

— read using an internal ADC analog channel

— may be read with either ADC

Decimation Filter

— Programmable decimation factor (2 to 16)

— Selectable IIR or FIR filter

— Up to 4th order IIR or 8th order FIR

— Programmable coefficients

— Saturated or non-saturated modes

— Programmable Rounding (Convergent; Two’s Complement; Truncated)

— Pre-fill mode to pre-condition the filter before the sample window opens

Full duplex synchronous serial interface to an external device

— Free-running clock for use by an external device

— Supports a 26-bit message length

•

Priority based Queues

— Supports six Queues with fixed priority. When commands of distinct Queues are bound for the same ADC, the

higher priority Queue is always served first

1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

— Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a

deterministic time after the queue trigger

— Streaming mode operation of Queue_0 to execute some commands several times

— Supports software and hardware trigger modes to arm a particular Queue

— Generates interrupt when command coherency is not achieved

External hardware triggers

•

— Supports rising edge, falling edge, high level and low level triggers

— Supports configurable digital filter

Supports four external 8-to-1 muxes which can expand the input channels to 56 channels total

2.2.15 DSPI

The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the

MPC5634M MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of

eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like

protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion,

etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI

can be configured to serialize data to an external device that supports the Microsecond Channel protocol. There are two identical

DSPI blocks on the MPC5634M MCU. The DSPI output pins support 5 V logic levels or Low Voltage Differential Signalling

(LVDS) according to the Microsecond Channel specification.

The DSPIs have three configurations:

•

Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-bit SPI with support for queues

Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32 bits with three possible sources

per bit

— eTPU, eMIOS, new virtual GPIO registers as possible bit source

— Programmable inter-frame gap in continuous mode

— Bit source selection allows microsecond channel downstream with command or data frames up to 32 bits

— Microsecond channel dual receiver mode

•

Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI configurations

interleaving DSI frames with SPI frames, giving priority to SPI frames

For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and

the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software.

The DSPI supports these SPI features:

•

Full-duplex, synchronous transfers

Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins

Master and Slave Mode

Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries

Buffered receive operation using the RX FIFO with parameterized depth of 4 entries

TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues

Visibility into the TX and RX FIFOs for ease of debugging

FIFO Bypass Mode for low-latency updates to SPI queues

Programmable transfer attributes on a per-frame basis:

— Parameterized number of transfer attribute registers (from two to eight)

— Serial clock with programmable polarity and phase

— Various programmable delays:

–

PCS to SCK delay

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

–

SCK to PCS delay

Delay between frames

— Programmable serial frame size of 4 to 16 bits, expandable with software control

— Continuously held chip select capability

•

6 Peripheral Chip Selects, expandable to 64 with external demultiplexer

Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer

DMA support for adding entries to TX FIFO and removing entries from RX FIFO:

— TX FIFO is not full (TFFF)

— RX FIFO is not empty (RFDF)

•

6 Interrupt conditions:

— End of queue reached (EOQF)

— TX FIFO is not full (TFFF)

— Transfer of current frame complete (TCF)

— Attempt to transmit with an empty Transmit FIFO (TFUF)

— RX FIFO is not empty (RFDF)

— FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty)

— FIFO Overrun (serial frame received while RX FIFO is full)

Modified transfer formats for communication with slower peripheral devices

Continuous Serial Communications Clock (SCK)

•

Power savings via support for Stop Mode

Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the Microsecond

Channel downstream frame format

The DSPIs also support these features unique to the DSI and CSI configurations:

•

2 sources of the serialized data:

— eTPU_A and eMIOS output channels

— Memory-mapped register in the DSPI

Destinations for the deserialized data:

•

— eTPU_A and eMIOS input channels

— SIU External Interrupt Request inputs

— Memory-mapped register in the DSPI

Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register

Transfer initiation conditions:

•

— Continuous

— Edge sensitive hardware trigger

— Change in data

•

Pin serialization/deserialization with interleaved SPI frames for control and diagnostics

Continuous serial communications clock

Support for parallel and serial chaining of up to four DSPI blocks

2.2.16 eSCI

The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and

other MCUs. It includes special support to interface to Local Interconnect Network (LIN) slave devices. The eSCI block

provides the following features:

•

Full-duplex operation

Standard mark/space non-return-to-zero (NRZ) format

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

•

13-bit baud rate selection

Programmable 8-bit or 9-bit, data format

Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond

Channel upstream

•

Automatic parity generation

LIN support

— Autonomous transmission of entire frames

— Configurable to support all revisions of the LIN standard

— Automatic parity bit generation

— Double stop bit after bit error

— 10- or 13-bit break support

•

Separately enabled transmitter and receiver

Programmable transmitter output parity

2 receiver wake up methods:

— Idle line wake-up

— Address mark wake-up

•

Interrupt-driven operation with flags

Receiver framing error detection

Hardware parity checking

1/16 bit-time noise detection

DMA support for both transmit and receive data

— Global error bit stored with receive data in system RAM to allow post processing of errors

2.2.17 FlexCAN

The MPC5634M MCU contains two controller area network (FlexCAN) blocks. The FlexCAN module is a communication

controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to

be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable

operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module ‘A’ contains 64

message buffers (MB); FlexCAN module ‘C’ contains 32 message buffers.

The FlexCAN module provides the following features:

•

Based on and including all existing features of the Freescale TouCAN module

Full Implementation of the CAN protocol specification, Version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— Zero to eight bytes data length

— Programmable bit rate up to 1 Mbit/s

•

Content-related addressing

64 / 32 message buffers of zero to eight bytes data length

Individual Rx Mask Register per message buffer

Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

Includes 1056 / 544 bytes of embedded memory for message buffer storage

Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers

Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)

IDs, with individual masking capability

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

•

Selectable backwards compatibility with previous FlexCAN versions

Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock

Listen only mode capability

Programmable loop-back mode supporting self-test operation

3 programmable Mask Registers

Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority

Time Stamp based on 16-bit free-running timer

Global network time, synchronized by a specific message

Maskable interrupts

Warning interrupts when the Rx and Tx Error Counters reach 96

Independent of the transmission medium (an external transceiver is assumed)

Multi master concept

High immunity to EMI

Short latency time due to an arbitration scheme for high-priority messages

Low power mode, with programmable wake-up on bus activity

2.2.18 System timers

The system timers provide two distinct types of system timer:

•

Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)

Operating system task monitors using the System Timer Module (STM)

2.2.18.1 Periodic Interrupt Timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has

no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as

periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by

the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low

power stop mode.

The following features are implemented in the PIT:

•

5 independent timer channels

Each channel includes 32-bit wide down counter with automatic reload

4 channels clocked from system clock

1 channel clocked from crystal clock (wake-up timer)

Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined

timeout period

•

Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer

reaches zero

2.2.18.2 System Timer Module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see

http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer

comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:

•

One 32-bit up counter with 8-bit prescaler

Four 32-bit compare channels

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

•

Independent interrupt source for each channel

Counter can be stopped in debug mode

2.2.19 Software Watchdog Timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog

integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can

provide a system reset or interrupt request when the correct software key is not written within the required time window.

The following features are implemented:

•

32-bit modulus counter

Clocked by system clock or crystal clock

Optional programmable watchdog window mode

Can optionally cause system reset or interrupt request on timeout

Reset by writing a software key to memory mapped register

Enabled out of reset

Configuration is protected by a software key or a write-once register

2.2.20 Debug features

2.2.20.1 Nexus port controller

The NPC (Nexus Port Controller) block provides real-time development support capabilities for the MPC5634MPower

Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for

MCUs without requiring external address and data pins for internal visibility. The NPC block is an integration of several

individual Nexus blocks that are selected to provide the development support interface for MPC5634M. The NPC block

interfaces to the host processor (e200z335), eTPU, and internal buses to provide development support as per the IEEE-ISTO

5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal

memory map and access to the Power Architecture and eTPU internal registers during halt. The Nexus interface also supports

a JTAG only mode using only the JTAG pins. MPC5634Min the production 144 LQFP supports a 3.3 V reduced (4-bit wide)

Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable I/O count of the device. When using

this Nexus port as IO, Nexus trace is still possible using VertiCal calibration. In the VertiCal calibration package, the full 12-bit

Auxiliary port is available.

NOTE

In the VertiCal package, the full Nexus Auxiliary port shares balls with the addresses of the

calibration bus. Therefore multiplexed address/data bus mode must be used for the

calibration bus when using full width Nexus trace in VertiCal assembly.

The following features are implemented:

•

5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)

— Always available in production package

— Supports both JTAG Boundary Scan and debug modes

— 3.3 V interface

— Supports Nexus class 1 features

— Supports Nexus class 3 read/write feature

9-pin Reduced Port interface in 144 LQFP production package

— Alternate function as IO

•

— 5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

— Auxiliary Output port

–

1 MCKO (message clock out) pin

4 MDO (message data out) pins

2 MSEO (message start/end out) pins

1 EVTO (event out) pin

— Auxiliary input port

1 EVTI (event in) pin

–

•

17-pin Full Port interface in calibration package used on VertiCal boards

— 3.3 V interface

— Auxiliary Output port

–

1 MCKO (message clock out) pin

4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8 extra full port pins shared with

calibration bus

–

2 MSEO (message start/end out) pins

1 EVTO (event out) pin

— Auxiliary input port

1 EVTI (event in) pin

–

•

Host processor (e200) development support features

— IEEE-ISTO 5001-2003 standard class 2 compliant

— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires

between the discontinuities. Thus, static code may be traced.

— Watchpoint trigger enable of program trace messaging

— Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a

specific value to a memory location

–

4 data value breakpoints

CPU only

Detects ‘equal’ and ‘not equal’

Byte, half word, word (naturally aligned)

NOTE

This feature is imprecise due to CPU pipelining.

— Subset of Power Architecture software debug facilities with OnCE block (Nexus class 1 features)

eTPU development support features

•

— IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU

— Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU)

Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses

for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid

prototyping for powertrain automotive development systems.

•

All features are independently configurable and controllable via the IEEE 1149.1 I/O port

Power-on-reset status indication during reset via MDO[0] in disabled and reset modes

2.2.20.2 JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant

with the IEEE 1149.1-2001 standard and supports the following features:

•

IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

A 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

•

— ACCESS_AUX_TAP_ONCE

— ACCESS_AUX_TAP_eTPU

— ACCESS_CENSOR

3 test data registers to support JTAG Boundary Scan mode

— Bypass register

— Boundary scan register

— Device identification register

•

A TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

Censorship Inhibit Register

— 64-bit Censorship password register

— If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash

shadow row, Censorship is disabled until the next system reset.

2.3

MPC5634M series architecture

Block diagram

2.3.1

Figure 1 shows a top-level block diagram of the MPC5634M series.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

JTAG

Calibration

Bus

Interface

JTAG Port

Nexus Port

e200z335

Instructions

Data

Flash

1.5 MB

Nexus

SPE

NMI

Nexus 2+

eTPU

SRAM

62 KB

NMI

MMU

SIU

critical

Interrupt

eDMA

Requests from

Peripheral

Voltage

Regulator

stby

Blocks & eDMA

Interrupt

Controller

(INTC)

(1.2V, 3.3V,

STB RAM)

DMA

Requests

from

Peripheral

Blocks

Clocks

CQM

STM

PLL

eDMA, FLASH, Bridge B,

crossbar, SRAM

PIT

SWT

Configuration

BAM

Peripheral Bridge

Nexus

eQADC

SIU

16 Ch.

eMIOS

DSPIs

eSCIs

CANs

eTPU

Reset Control

ADCI

Interrupt

Request

NEXUS 1

Serial

Analog IF

External

Interrupt

Request

32 Ch.+

Engine

IMUX

ADC ADC

RAM

14 KB/3 KB

Analog

GPIO &

AMUX

Pad Control

Decimation

Filter

Temp. Sensor

. . .

I/O

Figure 1. MPC5634M series block diagram

2.3.2

Block summary

Table 1 summarizes the functions of the blocks present on the MPC5634M series microcontrollers.

Table 1. MPC5634M series block summary

Block

Function

e200z3 core

Executes programs and interrupt handlers.

Flash memory

Provides storage for program code, constants, and variables

RAM (random-access memory)

Calibration bus

Transfers data across the crossbar switch to/from peripherals attached to the

VertiCal connector

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Overview

Table 1. MPC5634M series block summary (continued)

Function

Block

DMA (direct memory access)

DSPI (deserial serial peripheral interface)

Performs complex data movements with minimal intervention from the core

Provides a synchronous serial interface for communication with external

devices

eMIOS (enhanced modular input-output system) Provides the functionality to generate or measure events

eQADC (enhanced queued analog-to-digital

converter)

Provides accurate and fast conversions for a wide range of applications

eSCI (serial communication interface)

eTPU (enhanced time processor unit)

FlexCAN (controller area network)

Allows asynchronous serial communications with peripheral devices and

other microcontroller units

Processes real-time input events, performs output waveform generation, and

accesses shared data without host intervention

Supports the standard CAN communications protocol

FMPLL (frequency-modulated phase-locked

loop)

Generates high-speed system clocks and supports the programmable

frequency modulation of these clocks

INTC (interrupt controller)

JTAG controller

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

NPC (Nexus Port Controller)

Provides real-time development support capabilities in compliance with the

IEEE-ISTO 5001-2003 standard

PIT (peripheral interrupt timer)

Temperature sensor

Produces periodic interrupts and triggers

Provides the temperature of the device as an analog value

Provides protection from runaway code

SWT (Software Watchdog Timer)

STM (System Timer Module)

Timer providing a set of output compare events to support AutoSAR and

operating system tasks

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

This section contains the pinouts for all production packages for the MPC5634M family of devices. Please note the following:

•

Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable

device behavior or damage.

•

Pins labeled “NIC” have no internal connection.

3.1

144 LQFP pinout

Figure 2 shows the pinout for the 144-pin LQFP.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

108 TMS

107 TDI / eMIOS[5] / GPIO[232]

AN[18]

AN[17]

AN[16]

106

EVTO / eTPU_A[4] / GPIO[227]

105 TCK

104 VSS

AN[11] / ANZ

AN[9] / ANX

103

EVTI / eTPU_A[2] / GPIO[231]

VDDA

VSSA

AN[39] / AN[10] / ANY

AN[38] / AN[8] / ANW

VDDREG

102 VDDEH7

101 MSEO[1] / eTPU_A[29] / GPIO[225]

100

TDO / eMIOS[6] / GPIO[228]

99 MCKO / GPIO[219]

98 JCOMP

VRCCTL

VSTBY

VRC33

DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]

96 DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]

95 DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]

94 DSPI_B_PCS[0] / GPIO[105]

93 VDDEH6B

92 DSPI_B_PCS[1] / GPIO[106]

91 VSS

90 DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]

89 DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]

88 DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]

87 DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]

86 VDD

(see signal details, pin 14)

(see signal details, pin 15)

eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]

eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]

(see signal details, pin 18)

(see signal details, pin 19)

(see signal details, pin 20)

(see signal details, pin 21)

VSS

144-Pin

LQFP

signal details:

pin 14: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]

pin 15: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]

pin 18: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]

pin 19: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140]

pin 20: eTPU_A[25] / IRQ[13] / SCK_C_LVDS+ / GPIO[139]

pin 21: eTPU_A[24] / IRQ[12] / SCK_C_LVDS– / GPIO[138]

pin 23: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]

(see signal details, pin 23)

VDDEH1A

(see signal details, pin 25)

VDD

85 RSTOUT

84 CAN_C_TX / GPIO[87]

83 SCI_A_TX / eMIOS[13] / GPIO[89]

82 SCI_A_RX / eMIOS[15] / GPIO[90]

81 CAN_C_RX / GPIO[88]

80 RESET

79 VSS

78 VDDEH6A

77 VSSPLL

76 XTAL

eTPU_A[21] / IRQ[9] / GPIO[135]

eTPU_A[20] / IRQ[8] / GPIO[134]

eTPU_A[19] / GPIO[133]

eTPU_A[18] / GPIO[132]

eTPU_A[17] / GPIO[131]

eTPU_A[16] / GPIO[130]

eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]

VDDEH1B

pin 25: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136]

pin 35: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]

75 EXTAL / EXTCLK

74 VDDPLL

73 VSS

(see signal details, pin 35)

VSS

Figure 2. 144-pin LQFP pinout (top view; all 144-pin devices)

3.2

176 LQFP pinout (MPC5634M)

Figure 3 shows the 176-pin LQFP pinout for the MPC5634M (1536 KB flash memory).

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

AN[18]

AN[17]

NIC

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

TMS

AN[16]

TDI / eMIOS[5] / GPIO[232]

eTPU_A[4] / GPIO[227]

AN[11] / ANZ

AN[9] / ANX

TCK

VSS

VDDA

VSSA

eTPU_A[2] / GPIO[231]

AN[39] / AN[10] / ANY

AN[38] / AN[8] / ANW

VDDREG

VDDEH7

eTPU_A[29] / GPIO[225]

TDO / eMIOS[6] / GPIO[228]

VRCCTL

GPIO[219]

VSTBY

JCOMP

VRC33

ALT_EVTO

ALT_MCKO

VDDE12

VSS

ALT_MSEO[0]

VDDE12

ALT_MSEO[1]

ALT_MDO[0]

ALT_EVTI

176 - Pin

LQFP

ALT_MDO[1]

VSS

ALT_MDO[2]

DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]

ALT_MDO[3]

DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]

(see signal details, pin 21)

(see signal details, pin 22)

(see signal details, pin 23)

(see signal details, pin 24)

(see signal details, pin 25)

(see signal details, pin 26)

(see signal details, pin 27)

(see signal details, pin 28)

VSS

DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]

DSPI_B_PCS[0] / GPIO[105]

signal details:

VDDEH6B

DSPI_B_PCS[1] / GPIO[106]

pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]

pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]

pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]

VSS

DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]

DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]

DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]

pin 24: eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]

DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]

(see signal details, pin 30)

VDDEH1A

(see signal details, pin 32)

VDD

RSTOUT

pin 25: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]

CAN_C_TX / GPIO[87]

pin 26: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140]

pin 27: eTPU_A[25] / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]

pin 28: eTPU_A[24] / IRQ[12] / DSPI_C_SCK_LVDS– / GPIO[138]

pin 30: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]

pin 32: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136]

pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]

SCI_A_TX / eMIOS[13] / GPIO[89]

eTPU_A[21] / IRQ[9] / GPIO[135]

eTPU_A[20] / IRQ[8] / GPIO[134]

eTPU_A[19] / GPIO[133]

eTPU_A[18] / GPIO[132]

eTPU_A[17] / GPIO[131]

eTPU_A[16] / GPIO[130]

(see signal details, pin 40)

VDDEH1B

SCI_A_RX / eMIOS[15] / GPIO[90]

CAN_C_RX / GPIO[88]

RESET

VSS

VDDEH6A

VSSPLL

XTAL

EXTAL / EXTCLK

VDDPLL

VSS

(see signal details, pin 42)

VSS

pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]

NIC

Note: Pins marked “NIC” have no internal connection.

Figure 3. 176-pin LQFP pinout (MPC5634M; top view)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

3.3

176 LQFP pinout (MPC5633M)

Figure 4 shows the pinout for the 176-pin LQFP for the MPC5633M (1024 KB flash memory).

AN[18]

AN[17]

NIC

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

TMS

AN[16]

TDI / eMIOS[5] / GPIO[232]

AN[11] / ANZ

AN[9] / ANX

eTPU_A[4] / GPIO[227]

TCK

VSS

VDDA

VSSA

eTPU_A[2] / GPIO[231]

AN[39] / AN[10] / ANY

AN[38] / AN[8] / ANW

VDDREG

VDDEH7

eTPU_A[29] / GPIO[225]

TDO / eMIOS[6] / GPIO[228]

VRCCTL

GPIO[219]

VSTBY

JCOMP

VRC33

ALT_EVTO

ALT_MCKO

VDDE12

VSS

ALT_MSEO[0]

VDDE12

ALT_MSEO[1]

ALT_MDO[0]

ALT_EVTI

176-Pin

LQFP

ALT_MDO[1]

VSS

ALT_MDO[2]

DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]

ALT_MDO[3]

DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]

(see signal details, pin 21)

(see signal details, pin 22)

(see signal details, pin 23)

(see signal details, pin 24)

(see signal details, pin 25)

(see signal details, pin 26)

(see signal details, pin 27)

(see signal details, pin 28)

VSS

DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]

DSPI_B_PCS[0] / GPIO[105]

signal details:

VDDEH6B

DSPI_B_PCS[1] / GPIO[106]

Pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]

Pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]

Pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]

VSS

DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]

DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]

DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]

DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]

Pin 24: eTPU_A[28]/ DSPI_C_PCS[1] / GPIO[142]

(see signal details, pin 30)

VDDEH1A

(see signal details, pin 32)

VDD

RSTOUT

Pin 25: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]

CAN_C_TX / GPIO[87]

Pin 26: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS- / GPIO[140]

Pin 27: eTPU_A[25] / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]

Pin 28: eTPU_A[24] / IRQ[12] / DSPI_C_SCK_LVDS- / GPIO[138]

Pin 30: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]

Pin 32: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136]

Pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]

SCI_A_TX / eMIOS[13] / GPIO[89]

eTPU_A[21] / IRQ[9] / GPIO[135]

eTPU_A[20] / IRQ[8] / GPIO[134]

eTPU_A[19] / GPIO[133]

eTPU_A[18] / GPIO[132]

eTPU_A[17] / GPIO[131]

eTPU_A[16] / GPIO[130]

(see signal details, pin 40)

VDDEH1B

SCI_A_RX / eMIOS[15] / GPIO[90]

CAN_C_RX / GPIO[88]

RESET

VSS

VDDEH6A

VSSPLL

XTAL

EXTAL / EXTCLK

VDDPLL

VSS

(see signal details, pin 42)

VSS

Pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]

NIC

Notes:

1. Pins marked “NIC” have no internal connection.

2. Pins marked “NC” are not functional pins but may be connected to internal circuitry. Connections to external

circuits or other pins on this device can result in unpredictable system behavior or damage.

Figure 4. 176-pin LQFP pinout (MPC5633M; top view)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

3.4

208 MAPBGA ballmap (MPC5634M)

Figure 5 shows the 208-pin MAPBGA ballmap for the MPC5634M (1536 KB flash memory) as viewed from above.

AN5

ALT_

MDO2

ALT_

MDO0

VSS

AN9

AN11

VDDA1

AN21

VSSA1

AN0

AN1

AN4

AN16

AN2

VRH

AN22

AN7

AN24

VRL

AN27

AN28

AN32

AN31

VSSA0

VDDA0

AN33

AN35

AN12- SDS

AN13-SDO

AN14-SDI

VDDEH7

VRC33

VSS

VDD

TCK

ALT_

MDO3

ALT_

MDO1

VDD

VSS

AN38

REFBYPC

AN3

AN25

AN23

AN30

AN15

FCK

ALT_

MSEO0

VSTBY

VDD

VSS

AN17

AN34

AN18

VSS

TMS

TDI

VRC33

AN39

VDD

VSS

AN6

VSS

ALT_EVTO

ALT_EVTI

NIC

ALT_

MSEO1

ETPUA30

ETPUA28

ETPUA24

ETPUA23

ETPUA20

ETPUA16

ETPUA12

ETPUA10

ETPUA8

ETPUA3

ETPUA31

ETPUA29

ETPUA27

ETPUA22

ETPUA19

ETPUA15

ETPUA11

ETPUA9

ETPUA4

ETPUA2

VSS

AN37

VDD

VDDE7

VDDEH6

ETPUA26

ETPUA25

ETPUA17

ETPUA14

ETPUA7

ETPUA6

ETPUA1

ETPUA0

VSS

AN36

TDO

ALT_MCKO

JCOMP

DSPI_B_

SOUT

DSPI_B_

PCS3

DSPI_B_

SIN

DSPI_B_

PCS0

ETPUA21

ETPUA18

ETPUA13

VDDEH1

ETPUA0

ETPUA5

VSS

DSPI_B_

PCS4

DSPI_B_

PCS2

DSPI_B_

PCS1

GPIO99

DSPI_B_

PCS5

DSPI_B_

SCK

SCI_A_TX

SCI_A_RX

GPIO98

RSTOUT

CAN_C_

VDDREG

RESET

CAN_C_

SCI_B_TX

SCI_B_RX

VSS

WKPCFG

BOOTCFG1

PLLREF

VRCCTL

VSS

VSSPLL

EXTAL

XTAL

VDD

VRC33

VDDE7

EMIOS2

EMIOS10

EMIOS8

VDDEH1/6

eTPU_A29

EMIOS14

EMIOS15

EMIOS12

eTPU_A19

eTPU_A21

EMIOS23

eTPU_A13

VRC33

NIC

CAN_A_

VDD

GPIO207

EMIOS4

EMIOS1

NIC

eTPU_A2

VDD

NIC

CAN_A_

NIC

VDD

GPIO206

EMIOS0

NIC

EMIOS9

EMIOS11

EMIOS13

eTPU_A27

NIC

VDD

VSS

VDD

VDDPLL

VSS

VDD

NIC

GPIO219

eTPU_A25

eTPU_A4

NIC

VDDE5

CLKOUT

Pins marked “NIC” have no internal connection.

This ball may be changed to “NC” (no connection) in a future revision.

eTPU output only channel.

Figure 5. 208-pin MAPBGA ballmap (MPC5634M; top view)

3.5

208 MAPBGA ballmap (MPC5633M only)

Figure 6 shows the 208-pin MAPBGA ballmap for the MPC5633M (1024 KB flash memory) as viewed from above.

AN5

ALT_

MDO2

ALT_

MDO0

VSS

AN9

AN11

AN38

VSS

VDD

VDDA1

AN21

AN17

VSS

VSSA1

AN0

AN1

AN4

AN16

AN2

VRH

AN22

AN7

AN24

VRL

AN27

AN28

AN32

AN31

VSSA0

VDDA0

AN33

AN35

AN12-SDS

AN13-SDO

AN14-SDI

VDDEH7

VRC33

VSS

VDD

TCK

ALT_

MDO3

ALT_

MDO1

VDD

VSS

REFBYPC

AN3

AN25

AN23

AN30

AN15

FCK

ALT_

MSEO0

VSTBY

VDD

AN34

AN18

VSS

TMS

TDI

VRC33

AN39

AN6

VSS

ALT_EVTO

NIC

ALT_

EVTI

ALT_

MSEO1

ETPUA30

ETPUA28

ETPUA24

ETPUA23

ETPUA20

ETPUA16

ETPUA12

ETPUA10

ETPUA8

ETPUA3

ETPUA31

ETPUA29

ETPUA27

ETPUA22

ETPUA19

ETPUA15

ETPUA11

ETPUA9

ETPUA4

ETPUA2

VSS

VDD

VDDE7

VDDEH6

ETPUA26

ETPUA25

ETPUA17

ETPUA14

ETPUA7

ETPUA6

ETPUA1

ETPUA0

VSS

TDO

ALT_MCKO

JCOMP

DSPI_B_

SOUT

DSPI_B_

PCS3

DSPI_B_

SIN

DSPI_B_

PCS0

ETPUA21

ETPUA18

ETPUA13

VDDEH1

ETPUA0

ETPUA5

VSS

DSPI_B_

PCS4

DSPI_B_

PCS2

DSPI_B_

PCS1

DSPI_B_

PCS5

DSPI_B_

SCK

SCI_A_TX

SCI_A_RX

CAN_C_

RSTOUT

WKPCFG

VDDREG

RESET

VSSPLL

EXTAL

XTAL

CAN_C_

SCI_B_TX

SCI_B_RX

VSS

PLLREF

VRCCTL

VSS

BOOTCFG1

VDD

VRC33

VDDE7

EMIOS2

EMIOS10

EMIOS8

EMIOS11

VDDEH1/6

EMIOS12

eTPUA19

eTPUA21

VRC33

NIC

eTPUA29

eTPUA2

CAN_A_

VDD

NIC

VDD

NIC

eTPUA27

CAN_A_

NIC

VDD

EMIOS4

NIC

EMIOS9

EMIOS14

EMIOS23

VDD

VSS

VDD

VDDPLL

VSS

eTPUA4

VSS

VDD

NIC

EMIOS0

GPIO219

eTPUA25

eTPUA13

NIC

VDDE5

CLKOUT

Pins marked “NIC” have no internal connection.

Pins marked “NC” may be connected to internal circuitry. Connections to external circuits or other pins on this device can result in unpredictable system behavior or damage.

This ball may be changed to “NC” (no connection) in a future revision.

eTPU output only channel.

Figure 6. 208-pin MAPBGA ballmap (MPC5633M; top view)

3.6

Signal summary

Table 2. MPC563xM signal properties

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

Dedicated GPIO

GPIO[98]

GPIO

PCR[98]

PCR[99]

PCR[206]

PCR[207]

—

I/O

VDDEH7

Slow

– / Up

GPIO[98]/Up

GPIO[99]/Up

GPIO[206]/Up

GPIO[207]/Up

—

141⁷

142⁷

143⁷

144⁷

J15⁸

H13⁸

R4⁸

GPIO[99]

VDDEH7

Slow

GPIO[206]⁹

GPIO[207]⁹

VDDEH7

Slow

VDDEH7

Slow

P5⁸

Reset / Configuration

RESET

External Reset Input

External Reset Output

—

VDDEH6a

Slow

I / Up

RESET /

102

L16

K15

M14

RSTOUT

PCR[230]

PCR[208]

VDDEH6a

Slow

RSTOUT/

Low

RSTOUT/

High

PLLREF

IRQ[4]

ETRIG[2]

GPIO[208]

FMPLL Mode Selection

External Interrupt Request

eQADC Trigger Input

GPIO

011

010

100

000

VDDEH6a

Slow

PLLREF / Up

– / Up

– / Down

– / Up

I/O

BOOTCFG1

IRQ[3]

ETRIG[3]

GPIO[212]

Boot Config. Input

External Interrupt Request

eQADC Trigger Input

GPIO

PCR[212]

PCR[213]

011

010

100

000

VDDEH6a BOOTCFG1 /

Slow

M15

L15

Down

I/O

WKPCFG

NMI

DSPI_B_SOUT

GPIO[213]

Weak Pull Config. Input

Non-Maskable Interrupt

DSPI_B Data Output

GPIO

VDDEH6a

Slow

WKPCFG /

I/O

Calibration¹⁰

CAL_ADDR[12:15]¹¹

Calibration Address Bus

PCR[340]

—

VDDE12

Fast

O / Low

CAL_ADDR /

Low

—

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

CAL_ADDR[16]²¹

ALT_MDO[0]¹²

Calibration Address Bus

Nexus Msg Data Out

PCR[345]

PCR[344]

—

VDDE12¹³

VDDE7¹⁴

Fast

O / Low¹⁵

MDO /

—

A14

B14

A13

B13

—

ALT_ADDR¹²

Low

CAL_ADDR[17]²¹

ALT_MDO[1]¹²

Calibration Address Bus

Nexus Msg Data Out

VDDE12¹³

VDDE7¹⁴

Fast

O / Low¹⁵

O / Low

ALT_MDO /

CAL_ADDR¹²

Low

CAL_ADDR[18]²¹

ALT_MDO[2]¹²

Calibration Address Bus

Nexus Msg Data Out

VDDE12¹³

VDDE7¹⁴

Fast

ALT_MDO /

CAL_ADDR¹²

Low

CAL_ADDR[19]²¹

ALT_MDO[3]¹²

Calibration Address Bus

Nexus Msg Data Out

VDDE12¹³

VDDE7¹⁴

Fast

ALT_MDO /

CAL_ADDR¹²

Low

CAL_ADDR[20:27]

ALT_MDO[4:11]

Calibration Address Bus

Nexus Msg Data Out

VDDE12¹³

Fast

ALT_MDO /

CAL_ADDR¹⁶

Low

—

CAL_ADDR[28]²¹

ALT_MSEO[0]¹²

Calibration Address Bus

Nexus Msg Start/End Out

VDDE12¹³

VDDE7¹⁴

Fast

O / Low¹⁷

ALT_MSEO¹⁶

CAL_ADDR¹⁷

Low

118

117

116

120

C15

E16

E15

D15

F15

CAL_ADDR[29]²¹

ALT_MSEO[1]¹²

Calibration Address Bus

Nexus Msg Start/End Out

VDDE12¹³

VDDE7¹⁴

Fast

ALT_MSEO¹⁶

CAL_ADDR¹⁷

Low

CAL_ADDR[30]²¹

ALT_EVTI¹²

Calibration Address Bus

Nexus Event In

VDDE12¹³

VDDE7¹⁴

Fast

—

ALT_EVTI /

CAL_ADDR¹⁹

ALT_EVTO

ALT_MCKO

Nexus Event Out

VDDE12¹³

VDDE7¹⁴

Fast

O / Low

ALT_EVTO /

High

Nexus Msg Clock Out

VDDE12¹³

VDDE7¹⁴

Fast

ALT_MCKO /

Enabled

NEXUSCFG¹¹

CAL_CS[0]¹¹

Nexus/Calibration bus

selector

—

VDDE12

Fast

I / Down

O / High

NEXUSCFG /

Down

—

Calibration Chip Selects

PCR[336]

PCR[338]

VDDE12

Fast

CAL_CS / High

CAL_CS[2]¹¹

CAL_ADDR[10]

Calibration Chip Selects

Calibration Address Bus

VDDE12

Fast

CAL_CS / High

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

CAL_CS[3]¹¹

CAL_ADDR[11]

Calibration Chip Selects

Calibration Address Bus

PCR[339]

PCR[341]

PCR[342]

PCR[343]

PCR[342]

VDDE12

Fast

O / High

– / Up

CAL_CS / High

– / Up

—

CAL_DATA[0:9]¹¹

Calibration Data Bus

Calibration Output Enable

Calibration Read/Write

I/O

VDDE12

Fast

CAL_DATA[10:15]¹¹

CAL_OE¹¹

VDDE12

Fast

– / Up

—

VDDE12

Fast

O / High

CAL_OE / High

CAL_RD_WR¹¹

CAL_TS_ALE¹¹

CAL_WE_BE[0:1]¹¹

VDDE12

Fast

CAL_RD_WR

/High

Calibration Transfer Start

Address Latch Enable

TS=0b1

ALE=0b0

VDDE12

Fast

CAL_TS / High

Calibration Write Enable

Byte Enable

—

VDDE12

Fast

CAL_WE /

High

NEXUS²⁰

EVTI²¹

eTPU_A[2]

GPIO[231]

Nexus Event In

eTPU A Ch.

GPIO

PCR[231]

PCR[227]

I/O

VDDEH7

Multi-V

– / –

103

106

126

129

P10

T10

EVTO ²¹

eTPU_A[4]

GPIO[227]

Nexus Event Out

eTPU A Ch.

GPIO

01²²

I/O

VDDEH7

Multi-V

I / Up

MCKO²¹

GPIO[219]

Nexus Msg Clock Out

GPIO

PCR[219]

PCR[220]

N/A²²

I/O

VDDEH7

Multi-V

– / –

122

135

MDO[0]²¹

eTPU_A[13]

GPIO[220]

Nexus Msg Data Out

eTPU A Ch.

GPIO

I/O

VDDEH7

Multi-V

110

T11

MDO[1]²¹

eTPU_A[19]

GPIO[221]

Nexus Msg Data Out

eTPU A Ch.

GPIO

PCR[221]

PCR[222]

01²²

I/O

VDDEH7

Multi-V

– / –

111

112

136

137

N11

P11

MDO[2]²¹

eTPU_A[21]

GPIO[222]

Nexus Msg Data Out

eTPU A Ch.

GPIO

01²²

I/O

VDDEH7

Multi-V

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

MDO[3]²¹

eTPU_A[25]

GPIO[223]

Nexus Msg Data Out

eTPU A Ch.

GPIO

PCR[223]

PCR[224]

PCR[225]

01²²

I/O

VDDEH7

Multi-V

– / –

114

109

101

139

134

124

R10

MSEO[0]²¹

eTPU_A[27]

GPIO[224]

Nexus Msg Start/End Out

eTPU A Ch.

GPIO

01²²

I/O

VDDEH7

Multi-V

– / –

MSEO[1]²¹

eTPU_A[29]

GPIO[225]

Nexus Msg Start/End Out

eTPU A Ch.

GPIO

01²²

I/O

VDDEH7

Multi-V

JTAG / TEST

TCK

JTAG Test Clock Input

—

VDDEH7

Multi-V

TCK / Down

– / –

TCK / Down

– / –

105

107

128

130

C16

E14

TDI²³

eMIOS[5]

GPIO[232]

JTAG Test Data Input

eMIOS Ch.

GPIO

PCR[232]

01²⁴

I/O

VDDEH7

Multi-V

TDO²³

eMIOS[6]

GPIO[228]

JTAG Test Data Output

eMIOS Ch.

GPIO

PCR[228]

01²⁴

I/O

VDDEH7

Multi-V

– / –

100

123

F14

TMS

JTAG Test Mode Select Input

JTAG TAP Controller Enable

—

VDDEH7

Multi-V

TMS / Up

108

131

121

D14

F16

JCOMP

VDDEH7

Multi-V

JCOMP /

Down

JCOMP / Down

CAN

CAN_A_TX

SCI_A_TX

GPIO[83]

CAN_A Transmit

eSCI_A Transmit

GPIO

PCR[83]

PCR[84]

I/O

VDDEH6a

Slow

– / Up

– / Up²⁵

– / Up

P12

R12

CAN_A_RX

SCI_A_RX

GPIO[84]

CAN_A Receive

eSCI_A Receive

GPIO

VDDEH6a

Slow

I/O

CAN_C_TX

GPIO[87]

CAN_C Transmit

GPIO

PCR[87]

PCR[88]

I/O

VDDEH6a

Medium

– / Up

101

K13

L14

CAN_C_RX

GPIO[88]

CAN_C Receive

GPIO

VDDEH6a

Slow

I/O

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

eSCI

SCI_A_TX

eMIOS[13]

GPIO[89]

eSCI_A Transmit

eMIOS Ch.

GPIO

PCR[89]

PCR[90]

I/O

VDDEH6a

Slow

– / Up

100

J14

SCI_A_RX²⁶

eMIOS[15]

GPIO[90]

eSCI_A Receive

eMIOS Ch.

GPIO

I/O

VDDEH6a

Slow

K14

SCI_B_TX

GPIO[91]

eSCI_B Transmit

GPIO

PCR[91]

PCR[92]

I/O

VDDEH6a

Slow

– / Up

L13

SCI_B_RX

GPIO[92]

eSCI_B Receive

GPIO

VDDEH6a

Slow

M13

I/O

DSPI

DSPI_B_SCK

DSPI_C_PCS[1]

GPIO[102]

DSPI_B Clock

DSPI_C Periph Chip Select

GPIO

PCR[102]

PCR[103]

PCR[104]

I/O

VDDEH6b

Medium

– / Up

106

112

113

J16

G15

G13

DSPI_B_SIN

DSPI_C_PCS[2]

GPIO[103]

DSPI_B Data Input

DSPI_C Periph Chip Select

GPIO

I/O

VDDEH6b

Medium

DSPI_B_SOUT

DSPI_C_PCS[5]

GPIO[104]

DSPI_B Data Output

DSPI_C Periph Chip Select

GPIO

I/O

VDDEH6b

Medium

DSPI_B_PCS[0]

GPIO[105]

DSPI_B Periph Chip Select

GPIO

PCR[105]

PCR[106]

PCR[107]

I/O

VDDEH6b

Medium

– / Up

111

109

107

G16

H16

H15

DSPI_B_PCS[1]

GPIO[106]

DSPI_B Periph Chip Select

GPIO

I/O

VDDEH6b

Medium

DSPI_B_PCS[2]

DSPI_C_SOUT

GPIO[107]

DSPI_B Periph Chip Select

DSPI_C Data Output

GPIO

I/O

VDDEH6b

Medium

DSPI_B_PCS[3]

DSPI_C_SIN

GPIO[108]

DSPI_B Periph Chip Select

DSPI_C Data Input

GPIO

PCR[108]

PCR[109]

I/O

VDDEH6b

Medium

– / Up

114

105

G14

H14

DSPI_B_PCS[4]

DSPI_C_SCK

GPIO[109]

DSPI_B Periph Chip Select

DSPI_C Clock

GPIO

I/O

VDDEH6b

Medium

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

DSPI_B_PCS[5]

DSPI_C_PCS[0]

GPIO[110]

DSPI_B Periph Chip Select

DSPI_C Periph Chip Select

GPIO

PCR[110]

I/O

VDDEH6b

Medium

– / Up

104

J13

eQADC

AN[0]²⁷

DAN0+

Single Ended Analog Input

Positive Terminal Diff. Input

—

VDDA

I / –

AN[0] / –

AN[1] / –

AN[2] / –

AN[3] / –

AN[4] / –

AN[5] / –

AN[6] / –

AN[7] / –

143

142

141

140

139

138

137

136

172

171

170

169

168

167

166

165

AN[1]²⁷

DAN0-

Single Ended Analog Input

Negative Terminal Diff. Input

AN[2]²⁷

DAN1+

Single Ended Analog Input

Positive Terminal Diff. Input

AN[3]²⁷

DAN1-

Single Ended Analog Input

Negative Terminal Diff. Input

AN[4]²⁷

DAN2+

Single Ended Analog Input

Positive Terminal Diff. Input

AN[5]²⁷

DAN2-

Single Ended Analog Input

Negative Terminal Diff. Input

AN[6]²⁷

DAN3+

Single Ended Analog Input

Positive Terminal Diff. Input

AN[7]²⁷

DAN3-

Single Ended Analog Input

Negative Terminal Diff. Input

AN[8]

See AN[38]-AN[8]-ANW

AN[9]

ANX

Single Ended Analog Input

External Multiplexed Analog

Input

—

VDDA

I / –

AN[9] / –

AN[10]

See AN[39]-AN[10]-ANY

AN[11]

ANZ

Single Ended Analog Input

External Multiplexed Analog

Input

—

VDDA

I / –

AN[11] / –

AN[12] / –

AN[12]

MA[0]

ETPU_A[19]

SDS

Single Ended Analog Input

Mux Address

ETPU_A Ch.

PCR[215]

011

010

100

000

VDDEH7

119

148

A12

eQADC Serial Data Strobe

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

AN[13]

MA[1]

ETPU_A[21]

SDO

Single Ended Analog Input

Mux Address

ETPU_A Ch.

PCR[216]

PCR[217]

PCR[218]

011

010

100

000

VDDEH7

I / –

AN[13] / –

AN[14] / –

AN[15] / –

118

117

116

147

146

145

B12

C12

C13

eQADC Serial Data Out

AN[14]

MA[2]

ETPU_A[27]

SDI

Single Ended Analog Input

Mux Address

ETPU_A Ch.

011

010

100

000

I / –

eQADC Serial Data In

AN[15]

FCK

ETPU_A[29]

Single Ended Analog Input

eQADC Free Running Clock

ETPU_A Ch.

011

010

000

AN[16]

AN[17]

AN[18]

AN[21]

AN[22]

AN[23]

AN[24]

AN[25]

AN[27]

AN[28]

AN[30]

AN[31]

AN[32]

AN[33]

AN[34]

AN[35]

AN[36]

AN[37]

Single Ended Analog Input

—

VDDA

I / –

AN[x] / –

144

132

131

130

129

128

127

126

125

124

123

122

121

—

173

161

160

159

158

157

156

155

154

153

152

151

150

174⁷

175⁷

A10

B10

D10

C10

C11

D11

F4⁸

E3⁸

—

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

AN[38]-AN[8]-

ANW

Single Ended Analog Input

Multiplexed Analog Input

—

VDDA

I / –

AN[38] / –

AN[39] / –

AN[39]-AN[10]-

ANY

Single Ended Analog Input

Multiplexed Analog Input

VRH

Voltage Reference High

Voltage Reference Low

Bypass Capacitor Input

—

VDDA

VSSA0

VRL

– / –

VRH

VRL

134

133

135

163

162

164

VRL

REFBYPC

eTPU2

eTPU_A[0]

eTPU_A[12]

eTPU_A[19]

GPIO[114]

eTPU_A Ch.

GPIO

PCR[114]

011

010

100

000

I/O

VDDEH1b

Slow

– / WKPCFG

L4, N3

I/O

eTPU_A[1]

eTPU_A[13]

GPIO[115]

eTPU_A Ch.

GPIO

PCR[115]

PCR[116]

PCR[117]

PCR[118]

PCR[119]

I/O

VDDEH1b

Slow

– / WKPCFG

eTPU_A[2]

eTPU_A[14]

GPIO[116]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eTPU_A[3]

eTPU_A[15]

GPIO[117]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eTPU_A[4]

eTPU_A[16]

GPIO[118]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eTPU_A[5]

eTPU_A[17]

DSPI_B_SCK_LVDS-

GPIO[119]

eTPU_A Ch.

DSPI_B CLOCK LVDS-

GPIO

001

010

100

000

I/O

VDDEH1b

Slow

I/O

eTPU_A[6]

eTPU_A[18]

DSPI_B_SCK_LVDS+

GPIO[120]

eTPU_A Ch.

DSPI_B Clock LVDS+

GPIO

PCR[120]

001

010

100

000

I/O

VDDEH1b

Medium

– / WKPCFG

I/O

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

eTPU_A[7]

eTPU_A[19]

DSPI_B_SOUT_LVDS- DSPI_B Data Output LVDS-

eTPU_A Ch.

PCR[121]

PCR[122]

0001

0010

0100

1000

0000

I/O

VDDEH1b

Slow

– / WKPCFG

eTPU_A[6]

GPIO[121]

eTPU_A Ch.

GPIO

eTPU_A[8]

eTPU_A[20]

eTPU_A Ch.

001

010

100

000

I/O

VDDEH1b

Slow

– / WKPCFG

DSPI_B_SOUT_LVDS+ DSPI_B Data Output LVDS+

GPIO[122]

GPIO

I/O

eTPU_A[9]

eTPU_A[21]

GPIO[123]

eTPU_A Ch.

GPIO

PCR[123]

PCR[124]

PCR[125]

PCR[126]

PCR[127]

PCR[128]

I/O

VDDEH1b

Slow

– / WKPCFG

eTPU_A[10]

eTPU_A[22]

GPIO[124]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eTPU_A[11]

eTPU_A[23]

GPIO[125]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eTPU_A[12]

DSPI_B_PCS[1]

GPIO[126]

eTPU_A Ch.

DSPI_B Periph Chip Select

GPIO

I/O

VDDEH1b

Medium

– / WKPCFG – / WKPCFG

eTPU_A[13]

DSPI_B_PCS[3]

GPIO[127]

eTPU_A Ch.

DSPI_B Periph Chip Select

GPIO

I/O

VDDEH1b

Medium

– / WKPCFG

eTPU_A[14]

DSPI_B_PCS[4]

eTPU_A[9]

eTPU_A Ch.

DSPI_B Periph Chip Select

eTPU_A Ch.

001

010

100

000

I/O

VDDEH1b

Medium

GPIO[128]

GPIO

I/O

eTPU_A[15]

DSPI_B_PCS[5]

GPIO[129]

eTPU_A Ch.

DSPI_B Periph Chip Select

GPIO

PCR[129]

I/O

VDDEH1b

Medium

– / WKPCFG

eTPU_A[16]

GPIO[130]

eTPU_A Ch.

GPIO

PCR[130]

PCR[131]

I/O

VDDEH1b

Slow

– / WKPCFG

eTPU_A[17]

GPIO[131]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

eTPU_A[18]

GPIO[132]

eTPU_A Ch.

GPIO

PCR[132]

PCR[133]

PCR[134]

I/O

VDDEH1b

Slow

– / WKPCFG

eTPU_A[19]

GPIO[133]

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eTPU_A[20]

IRQ[8]

GPIO[134]

eTPU_A Ch.

External Interrupt Request

GPIO

I/O

VDDEH1b

Slow

eTPU_A[21]

IRQ[9]

GPIO[135]

eTPU_A Ch.

External Interrupt Request

GPIO

PCR[135]

PCR[136]

I/O

VDDEH1a

Slow

– / WKPCFG

eTPU_A[22]

IRQ[10]

eTPU_A[17]

GPIO[136]

eTPU_A Ch.

001

010

100

000

I/O

VDDEH1a

Slow

External Interrupt Request

eTPU_A Ch. External

GPIO

I/O

eTPU_A[23]

IRQ[11]

eTPU_A[21]

GPIO[137]

eTPU_A Ch.

PCR[137]

PCR[138]

PCR[139]

PCR[140]

PCR[141]

001

010

100

000

I/O

VDDEH1a

Slow

– / WKPCFG

External Interrupt Request

eTPU_A Ch. External

GPIO

I/O

eTPU_A[24]²⁸

IRQ[12]

DSPI_C_SCK_LVDS-

GPIO[138]

eTPU_A Ch.

001

010

100

000

I/O

VDDEH1a

Slow

External Interrupt Request

DSPI_C Clock LVDS-

GPIO

I/O

eTPU_A[25]²⁸

IRQ[13]

DSPI_C_SCK_LVDS+

GPIO[139]

eTPU_A Ch.

001

010

100

000

I/O

VDDEH1a

Medium

External Interrupt Request

DSPI _C Clock LVDS+

GPIO

I/O

eTPU_A[26]²⁸

IRQ[14]

DSPI_C_SOUT_LVDS- DSPI_C Data Output LVDS-

eTPU_A Ch.

External Interrupt Request

001

010

100

000

I/O

VDDEH1a

Slow

GPIO[140]

GPIO

I/O

eTPU_A[27]²⁸

IRQ[15]

DSPI_C_SOUT_LVDS+ DSPI_C Data Output LVDS+

DSPI_B_SOUT

GPIO[141]

eTPU_A Ch.

External Interrupt Request

0001

0010

0100

1000

0000

I/O

VDDEH1a

Slow

DSPI_B Data Output

GPIO

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

eTPU_A[28]²⁸

DSPI_C_PCS[1]

GPIO[142]

eTPU_A Ch. (Input and

Output)

DSPI_C Periph Chip Select

GPIO

PCR[142]

PCR[143]

PCR[144]

PCR[145]

I/O

VDDEH1a

Medium

– / WKPCFG

eTPU_A[29]²⁸

DSPI_C_PCS[2]

GPIO[143]

eTPU_A Ch. (Input and

Output)

DSPI_C Periph Chip Select

GPIO

I/O

VDDEH1a

Medium

– / WKPCFG

eTPU_A[30]

DSPI_C_PCS[3]

eTPU_A[11]

GPIO[144]

eTPU_A Ch.

DSPI_C Periph Chip Select

eTPU_A Ch.

011

010

001

000

I/O

VDDEH1a

Medium

GPIO

I/O

eTPU_A[31]

DSPI_C_PCS[4]

eTPU_A[13]

GPIO[145]

eTPU_A Ch.

DSPI_C Periph Chip Select

eTPU_A Ch.

011

010

001

000

I/O

VDDEH1a

Medium

GPIO

I/O

eMIOS

eMIOS[0]

eMIOS Ch.

eTPU_A Ch.

GPIO

PCR[179]

001

010

100

000

I/O

VDDEH1b

Slow

– / WKPCFG

eTPU_A[0]

eTPU_A[25]²⁹

GPIO[179]

I/O

eMIOS[1]

eTPU_A[1]

GPIO[180]

eMIOS Ch.

eTPU_A Ch.

GPIO

PCR[180]

PCR[181]

PCR[183]

PCR[187]

I/O

VDDEH1b

Slow

– / WKPCFG

—

64⁷

T5⁸

eMIOS[2]

eTPU_A[2]

GPIO[181]

eMIOS Ch.

eTPU_A Ch.

GPIO

I/O

VDDEH1b

Slow

eMIOS[4]

eTPU_A[4]

GPIO[183]

eMIOS Ch.

eTPU_A Ch.

GPIO

I/O

VDDEH6a

Slow

eMIOS[8]

eMIOS Ch.

eTPU_A Ch.

eSCI_B Transmit

GPIO

001

010

100

000

I/O

VDDEH6a

Slow

eTPU_A[8]³⁰

SCI_B_TX

GPIO[187]

I/O

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

eMIOS[9]

eMIOS Ch.

PCR[188]

001

010

100

000

I/O

VDDEH6a

Slow

– / WKPCFG

eTPU_A[9]³⁰

SCI_B_RX

GPIO[188]

eTPU_A Ch.

eSCI_B Receive

GPIO

I/O

eMIOS[10]

GPIO[189]

eMIOS Ch.

GPIO

PCR[189]

PCR[190]

PCR[191]

I/O

VDDEH6a

Slow

– / WKPCFG

eMIOS[11]

GPIO[190]

eMIOS Ch.

GPIO

I/O

VDDEH6a

Slow

eMIOS[12]

eMIOS Ch.

001

010

100

000

I/O

VDDEH6a

Medium

N10

DSPI_C_SOUT

eTPU_A[27]

GPIO[191]

DSPI C Data Output

eTPU_A Ch.

GPIO

I/O

eMIOS[13]

GPIO[192]

eMIOS Ch.

GPIO

PCR[192]

PCR[193]

I/O

VDDEH6a

– / WKPCFG

—

77⁷

T8⁸

eMIOS[14]

IRQ[0]

eTPU_A[29]

GPIO[193]

eMIOS Ch.

External Interrupt Request

eTPU_A Ch.

001

010

100

000

VDDEH6a

Slow

GPIO

I/O

eMIOS[15]

IRQ[1]

GPIO[194]

eMIOS Ch.

External Interrupt Request

GPIO

PCR[194]

PCR[202]

I/O

VDDEH6a

Slow

– / WKPCFG

—

79⁷

T9⁸

R11

eMIOS[23]

GPIO[202]

eMIOS Ch.

GPIO

I/O

VDDEH6a

Slow

Clock Synthesizer

XTAL

Crystal Oscillator Output

—

VDDEH6a

O / –

I / –

XTAL³¹/ –

P16

N16

EXTAL

EXTCLK

Crystal Oscillator Input

External Clock Input

VDDEH6a

EXTAL³²/ –

CLKOUT

System Clock Output

PCR[229]

—

VDDE5

Fast

CLKOUT /

Enabled

CLKOUT /

Enabled

—

T14

Power / Ground

VDDPLL

PLL Supply Voltage

PLL Ground

—

VDDPLL

(1.2V)

I / –

—

R16

M16

VSSPLL³³

VSSPLL

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

VSTBY

VRC33

VRCCTL

VDDA³⁴

VDDA0

VSSA0

VDDA1

VSSA1

VSSA³⁵

VDDREG

VDD

Power Supply for Standby

RAM

—

VSTBY

VRC33

I / –

O / –

I / –

—

3.3V Voltage Regulator

Bypass Capacitor

A15, D1,

N6, N12

Voltage Regulator Control

Output

N14

Analog Power Input for

eQADC

VDDA (5.0 V)

VDDA

—

Analog Power Input for

eQADC

—

B11

A11

Analog Ground Input for

eQADC

VSSA

Analog Power Input for

eQADC

VDDA

Analog Ground Input for

eQADC

VSSA

Analog Ground Input for

eQADC

VSSA

—

Voltage Regulator Supply

VDDREG

(5.0 V)

K16

Internal Logic Supply Input

VDD (1.2 V)

26, 53, 33, 62, B1,B16,C2,

86, 120 103, D3, E4, N5,

149 P4,P13,R3,

R14, T2,

T15

Table 2. MPC563xM signal properties (continued)

Pad

Pin No.

176

Config.

(PCR)²

PCR PA

Field³

I/O

Type

Voltage⁴/

Pad Type

Function / State

After Reset⁶

Name

Function¹

Reset State⁵

144

208 MAPB

LQFP LQFP

VSS

Ground

—

–

VSS0

I / –

—

22, 36, 15, 29, A1, A16, B2,

48, 59, 43, 57,

73, 79, 72, 90,

B15, C3,

C14, D4,

D13, G7,

G8, G9,

G10, H7,

H8, H9,

91,

104,

115

96,

108,

115⁷,

127,

133, H10, J7, J8,

140 J9, J10, K7,

K8, K9, K10,

N4, N13,

P3,P14,R2,

R15, T1,

T16

VDDEH1A³⁶

VDDEH1B³⁶

I/O Supply Input

—

VDDEH1³⁷

(3.3V – 5.0V)

I / –

—

24, 34, 31, 41

VDDE5

I/O Supply Input

—

VDDE5

I / –

—

T13

—

VDDEH6a^{38, 39}

VDDEH6b³⁹

VDDEH6

(3.3V – 5.0V)

78, 93,

95,

110, 74

VDDEH6

VDDEH7

I/O Supply Input

—

VDDEH6

I / –

—

F13

D12

VDDEH7⁴⁰

(3.3V – 5.0V)

102,

113

125,

138

VDDE7⁴¹

I/O Supply Input

—

VDDE7

(3.3V)

I / –

—

16,

E13, P6

119⁷

For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary

function or GPIO is done in the SIU except where explicitly noted.

Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example,

PCR[190] refers to the SIU register named SIU_PCR190.

The Pad Configuration Register (PCR) PA field is used by software to select pin function.

The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V

range (–10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/– 10%).

Terminology is O — output, I — input, Up — weak pull up enabled, Down — weak pull down enabled, Low — output driven low, High — output driven high.

A dash for the function in this column denotes that both the input and output buffer are turned off.

Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off.

Not available on 1 MB version of 176-pin package.

Not available on 1 MB version of 208-pin package.

The GPIO functions on GPIO[206] and GPIO[207] can be selected as trigger functions in the SIU for the ADC by making the proper selections in the

SIU_ETISR and SIU_ISEL3 registers in the SIU.

¹⁰Some signals in this section are available only on calibration package.

¹¹These pins are only available in the 496 CSP/MAPBGA calibration/development package.

¹²On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the

176-pin and 208-pin packages, the Nexus function on this pin is enabled permanently. Do not connect the Nexus MDO or MSEO pins directly to a power

supply or ground.

¹³In the calibration package, the I/O segment containing this pin is called VDDE12.

¹⁴208-ball BGA package only

¹⁵When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until

the crystal oscillator becomes stable, at which time it is then negated.

¹⁶The function of this pin is Nexus when NEXUSCFG is high.

¹⁷High when the pin is configured to Nexus, low otherwise.

¹⁸O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.

¹⁹ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI/Up otherwise.

²⁰In 176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function

²¹This signal is not available in the 176-pin and 208-pin packages.

²²The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.

²³TDI and TDO are required for JTAG operation.

²⁴The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.

²⁵The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.

²⁶Connect an external 10K pull-up resistor to the SCI_A_RX pin to ensure that the pin is driven high during CAN serial boot.

²⁷For pins AN[0:7], during and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors

are disabled when the system clock propagates through the device.

²⁸ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.

²⁹eTPU_A[25] is an output only function.

³⁰Only the output channels of eTPU[8:9] are connected to pins.

³¹The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function

and should be grounded.

³²The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid

operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.

³³VSSPLL and VSSREG are connected to the same pin.

³⁴This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.

³⁵This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.

³⁶VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy

naming, however they should be considered as the same signal in this document.

³⁷LVDS pins will not work at 3.3 V.

³⁸The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for

analog input function.

³⁹VDDEH6A and VDDEH6B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however

they should be considered as the same signal in this document.

⁴⁰If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived

from the 5 volt power supply.

⁴¹In the calibration package this signal is named VDDE12.

Table 3. Pad types

Pad Type

Name

Supply Voltage

Slow

Medium

Fast

pad_ssr_hv

pad_msr_hv

pad_fc

3.0 V – 5.25 V

3.0 V – 3.6 V

MultiV

pad_multv_hv

3.0 V – 5.25 V (high swing mode)

4.5 V – 5.25 V (low swing mode)

Analog

LVDS

pad_ae_hv

pad_lo_lv

0.0 – 5.25 V

—

Pinout and signal description

3.7

Signal details

Table 4 contains details on the multiplexed signals that appear in Table 2, “MPC563xM signal properties”.

Table 4. Signal details

Signal

Module or Function

Description

CLKOUT

EXTAL

Clock Generation

MPC5634M clock output for the external/calibration bus

interface

Clock Generation

Input pin for an external crystal oscillator or an external clock

source based on the value driven on the PLLREF pin at reset.

EXTCLK

PLLREF

Clock Generation

External clock input

PLLREF is used to select whether the oscillator operates in xtal

mode or external reference mode from reset. PLLREF=0 selects

external reference mode.

XTAL

Clock Generation

DSPI

Crystal oscillator input

SCK_B_LVDS–

SCK_B_LVDS+

LVDS pair used for DSPI_B TSB mode transmission

SOUT_B_LVDS–

SOUT_B_LVDS+

DSPI

LVDS pair used for DSPI_B TSB mode transmission

LVDS pair used for DSPI_C TSB mode transmission

SCK_C_LVDS–

SCK_C_LVDS+

DSPI

SOUT_C_LVDS–

SOUT_C_LVDS+

DSPI

PCS_B[0]

PCS_C[0]

DSPI_B – DSPI_C

Calibration Bus

Peripheral chip select when device is in master mode—slave

select when used in slave mode

PCS_B[1:5]

PCS_C[1:5]

Peripheral chip select when device is in master mode—not used

in slave mode

SCK_B

SCK_C

DSPI clock—output when device is in master mode; input when

in slave mode

SIN_B

SIN_C

DSPI data in

SOUT_B

SOUT_C

DSPI data out

CAL_ADDR[12:30]

The CAL_ADDR[12:30] signals specify the physical address of

the bus transaction.

CAL_CS[0:3]

CSx is asserted by the master to indicate that this transaction is

targeted for a particular memory bank on the Primary external

bus.

CAL_DATA[0:15]

CAL_OE

Calibration Bus

The CAL_DATA[0:15] signals contain the data to be transferred

for the current transaction.

OE is used to indicate when an external memory is permitted to

drive back read data. External memories must have their data

output buffers off when OE is negated. OE is only asserted for

chip-select accesses.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

Table 4. Signal details (continued)

Signal

Module or Function

Description

CAL_RD_WR

Calibration Bus

RD_WR indicates whether the current transaction is a read

access or a write access.

CAL_TS_ALE

Calibration Bus

The Transfer Start signal (TS) is asserted by the MPC5634M to

indicate the start of a transfer.

The Address Latch Enable (ALE) signal is used to demultiplex

the address from the data bus.

CAL_EVTO

CAL_MCKO

NEXUSCFG

eMIOS[0:23]

AN[0:39]

Calibration Bus

Nexus Event Out

Nexus Message Clock Out

Nexus/Calibration Bus Nexus/Calibration Bus selector

eMIOS

eQADC

eMIOS I/O channels

Single-ended analog inputs for analog-to-digital converter

eQADC free running clock for eQADC SSI.

FCK

MA[0:2]

These three control bits are output to enable the selection for an

external Analog Mux for expansion channels.

REFBYPC

SDI

eQADC

Bypass capacitor input

Serial data in

eQADC

SDO

eQADC

Serial data out

SDS

eQADC

Serial data select

VRH

eQADC

Voltage reference high input

Voltage reference low input

eSCI receive

VRL

eQADC

SCI_A_RX

SCI_B_RX

eSCI_A – eSCI_B

SCI_A_TX

SCI_B_TX

eSCI_A – eSCI_B

eSCI transmit

ETPU_A[0:31]

eTPU

eTPU I/O channel

FlexCAN transmit

CAN_A_TX

CAN_C_TX

FlexCan_A –

FlexCAN_C

CAN_A_RX

CAN_C_RX

FlexCAN_A –

FlexCAN_C

FlexCAN receive

JCOMP

TCK

JTAG

Enables the JTAG TAP controller.

Clock input for the on-chip test and debug logic.

TDI

Serial test instruction and data input for the on-chip test and

debug logic.

TDO

TMS

JTAG

Serial test data output for the on-chip test logic.

Controls test mode operations for the on-chip test and debug

logic.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

Table 4. Signal details (continued)

Signal

Module or Function

Description

EVTI

Nexus

EVTI is an input that is read on the negation of RESET to enable

or disable the Nexus Debug port. After reset, the EVTI pin is

used to initiate program synchronization messages or generate

a breakpoint.

EVTO

Nexus

Output that provides timing to a development tool for a single

watchpoint or breakpoint occurrence.

MCKO

MCKO is a free running clock output to the development tools

which is used for timing of the MDO and MSEO signals.

MDO[3:0]

Trace message output to development tools. This pin also

indicates the status of the crystal oscillator clock following a

power-on reset, when MDO[0] is driven high until the crystal

oscillator clock achieves stability and is then negated.

MSEO[1:0]

Nexus

Output pin—Indicates the start or end of the variable length

message on the MDO pins

BOOTCFG[1]

SIU – Configuration

The BOOTCFG1 pin is sampled during the assertion of the

RSTOUT signal, and the value is used to update the RSR and

the BAM boot mode

The following values are for BOOTCFG[0:1}:

0 Boot from internal flash memory

1 FlexCAN/eSCI boot

WKPCFG

SIU – Configuration

The WKPCFG pin is applied at the assertion of the internal reset

signal (assertion of RSTOUT), and is sampled 4 clock cycles

before the negation of the RSTOUT pin.

The value is used to configure whether the eTPU and eMIOS

pins are connected to internal weak pull up or weak pull down

devices after reset. The value latched on the WKPCFG pin at

reset is stored in the Reset Status Register (RSR), and is

updated for all reset sources except the Debug Port Reset and

Software External Reset.

0: Weak pulldown applied to eTPU and eMIOS pins at reset

1: Weak pullup applied to eTPU and eMIOS pins at reset.

ETRIG[2:3]

IRQ[0:15]

SIU – eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx

SIU – External

Interrupts

The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select

IRQs.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

Table 4. Signal details (continued)

Module or Function Description

Signal

NMI

SIU – External

Interrupts

Non-Maskable Interrupt

GPIO[n]

SIU – GPIO

Configurable general purpose I/O pins. Each GPIO input and

output is separately controlled by an 8-bit input (GPDI) or output

(GPDO) register. Additionally, each GPIO pins is configured

using a dedicated SIU_PCR register.

The GPIO pins are generally multiplexed with other I/O pin

functions.

RESET

SIU – Reset

The RESET pin is an active low input. The RESET pin is

asserted by an external device during a power-on or external

reset. The internal reset signal asserts only if the RESET pin

asserts for 10 clock cycles. Assertion of the RESET pin while the

device is in reset causes the reset cycle to start over.

The RESET pin has a glitch detector which detects spikes

greater than two clock cycles in duration that fall below the

switch point of the input buffer logic of the VDDEH input pins.

The switch point lies between the maximum VIL and minimum

VIH specifications for the VDDEH input pins.

RSTOUT

SIU – Reset

The RSTOUT pin is an active low output that uses a push/pull

configuration. The RSTOUT pin is driven to the low state by the

MCU for all internal and external reset sources. There is a delay

between initiation of the reset and the assertion of the RSTOUT

pin.

Table 5 gives the power/ground segmentation of the MPC563x MCU. Each segment provides the power and ground for the

given set of I/O pins, and can be powered by any of the allowed voltages regardless of the power on the other segments.

Table 5. MPC563x Power/Ground Segmentation

144-LQFP 176-LQFP 208-BGA

Power

Segment

Voltage

Range¹

I/O Pins Powered

by Segment

Number

VDDA0

B11

5.0 V

AN[0:7], AN[9], AN[11],

AN[16:18], AN[21:25],

AN[27:28], AN[30:37],

AN38, AN39, VRL,

REFBYPC,

VRH

VDDE5

—

T13

1.8 V –

3.3 V

CLKOUT

VDDEH1

(a,b)

24, 34

31, 41

3.3 V –

5.0 V

PCKCFG[2],

eTPU_A[0:31],

eMIOS[0:2]

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Pinout and signal description

Table 5. MPC563x Power/Ground Segmentation (continued)

144-LQFP 176-LQFP 208-BGA

Power

Segment

Voltage

Range¹

I/O Pins Powered

by Segment

Number

VDDEH6

(a,b)

78, 93

95, 110

F13

3.3 V –

5.0 V

RESET, RSTOUT,

WKPCFG, BOOTCFG1,

PLLREF, SCK_B,

PCKCFG[0],

CAN_A_TX, CAN_A_RX,

CAN_C_TX, CAN_C_RX,

SCI_A_TX, SCI_A_RX,

SCI_B_TX, SCI_B_RX,

SCK_B, SIN_B, SOUT_B,

DSPI_B_PCS_B[0:5],

eMIOS[4],

eMIOS[8:15], eMIOS[23],

XTAL, EXTAL

VDDEH7²

102, 113

125, 138

D12

3.3 V –

5.0 V

PCKCFG[1],

MDO[0:3], EVTI, EVTO,

MCKO, MSEO[0:1], TDO,

TDI, TMS, TCK, JCOMP,

AN[12:15]

(GPIO[98:99],

GPIO[206:207])

VDDE12³

VDDE7

—

16, 119

E13, P6

1.8 V –

3.3 V

CAL_ADDR[12:30],

CAL_DATA[0:15],

CAL_CS[0], CAL_CS[2:3],

CAL_RD_WR,

CAL_WE[0:1], CAL_OE,

CAL_TS, ALT_MCKO,

ALT_EVTO, NEXUSCFG

These are nominal voltages. All VDDE and VDDEH voltages are –5%, +10% (VDDE 1.62 V to 3.6 V,

VDDEH 3.0 V to 5.5 V). VDDA is +5%, –10%.

The VDDEH7 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but

must meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.

In the calibration package this signal is named VDDE12; it is named VDDE7 in all other packages.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications for the MPC5634M series of MCUs.

The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon

these specifications will be met. Finalized specifications will be published after complete characterization and device

qualifications have been completed.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller

Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol

“SR” for System Requirement is included in the Symbol column.

4.1

Parameter classification

The electrical parameters shown in this document are guaranteed by various methods. To provide a better understanding, the

classifications listed in Table 6 are used and the parameters are tagged accordingly in the tables. Note that only controller

characteristics (“CC”) are classified. System requirements (“SR”) are operating conditions that must be provided to ensure

normal device operation.

Table 6. Parameter classifications

Classification tag

Tag description

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

4.2

Maximum ratings

Table 7. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit

min

max

V_DD

V_FLASH

V_STBY

SR 1.2 V core supply voltage²

SR Flash core voltage³

– 0.3

1.32

5.5

SR SRAM standby voltage⁴

5.5

V_DDPLL

SR Clock synthesizer voltage

1.32

3.6

V_RC33

SR Voltage regulator control

input voltage

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 7. Absolute maximum ratings (continued)

Value

Symbol

Parameter

Conditions

Unit

min

max

V_DDA

SR Analog supply voltage⁴

SR I/O supply voltage⁶

SR I/O supply voltage⁴

Reference to V_SSA

– 0.3

5.5

3.6

5.5

V_DDE

V_DDEH

V_IN

SR DC input voltage⁷

V_DDEHpowered I/O

pads

–1.0⁸

V_DDEH+ 0.3 V⁹

V_DDEpowered I/O pads –1.0¹⁰

V_DDE+ 0.3 V¹⁰

V_DDA+ 0.3 V

5.5

V_DDApowered I/O pads

–1.0

V_DDREG

V_RH

SR Voltage regulator supply

voltage⁶

– 0.3

SR Analog reference high

voltage

Reference to VRL

– 0.3

5.5

V_SS– V_SSA

SR V_SSdifferential voltage

SR V_REFdifferential voltage⁶

– 0.1

– 0.3

0.1

5.5

0.3

V_RH– V_RL

V_RL– V_SSA

SR VRL to V_SSAdifferential

voltage

_SSPLL– V_SSSR V_SSPLLto V_SSdifferential

– 0.1

– 3

0.1

voltage

I_MAXD

I_MAXA

T_J

SR Maximum DC digital input

current¹¹

Per pin, applies to all

digital pins

^oC

SR Maximum DC analog input Per pin, applies to all

—

current¹²

analog pins

SR Maximum operating

temperature range¹³– die

junction temperature

– 40.0

150.0

T_STG

T_SDR

SR Storage temperature range

– 55.0

—

150.0

260.0

^oC

SR Maximum solder

temperature¹⁴

MSL

SR Moisture sensitivity level¹⁵

—

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect

device reliability or cause permanent damage to the device.

Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.

The V_FLASHsupply is connected to V_DDEH1

Allowed 6.8 V for 10 hours cumulative time, remaining time at 5 V +10%.

The pin named as V_RC33is internally connected to the pads V_FLASHand V_RC33in the 144 LQFP package. These

limits apply when the internal regulator is disabled and V_RC33power is supplied externally.

All functional non-supply I/O pins are clamped to V_SSand V_DDE, or V_DDEH

AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of

60 hours over the complete lifetime of the device (injection current not limited for this duration).

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.

Internal structures hold the input voltage less than the maximum voltage on all pads powered by V_DDEHsupplies, if

the maximum injection current specification is met (2 mA for all pins) and V_DDEHis within the operating voltage

specifications.

¹⁰Internal structures hold the input voltage less than the maximum voltage on all pads powered by V_DDEsupplies, if the

maximum injection current specification is met (2 mA for all pins) and V_DDEis within the operating voltage

specifications.

¹¹Total injection current for all pins (including both digital and analog) must not exceed 25 mA.

¹²Total injection current for all analog input pins must not exceed 15 mA.

¹³Lifetime operation at these specification limits is not guaranteed.

¹⁴Solder profile per CDF-AEC-Q100.

¹⁵Moisture sensitivity per JEDEC test method A112.

4.3

Thermal characteristics

Table 8. Thermal characteristics for 144-pin LQFP

Symbol

R_JA

Parameter

Conditions

Value

Unit

CC D Junction-to-Ambient, Natural Convection¹

CC D Junction-to-Ambient, Natural Convection²

CC D Junction-to-Ambient (@200 ft/min)²

CC D Junction-to-Board²

Single layer board – 1s

Four layer board – 2s2p

Single layer board –1s

Four layer board – 2s2p

°C/W

R_JA

R_JMA

R_JB

R_JCtop

_JT

CC D Junction-to-Case (Top)³

CC D Junction-to-Package Top, Natural

Convection⁴

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board

meets JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization

parameter is written as Psi-JT.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 9. Thermal characteristics for 176-pin LQFP

Symbol

R_JA

Parameter

Conditions

Value

Unit

CC D Junction-to-Ambient, Natural Convection²

CC D Junction-to-Moving-Air, Ambient²

Single layer board - 1s

Four layer board - 2s2p

°C/W

R_JA

R_JMA

@200 ft./min., single layer

board - 1s

R_JMA

CC D Junction-to-Moving-Air, Ambient²

@200 ft./min., four layer

board - 2s2p

°C/W

R_JB

R_JCtop

_JT

CC D Junction-to-Board³

CC D Junction-to-Case⁴

°C/W

CC D Junction-to-Package Top, Natural

Convection⁵

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board

meets JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization

parameter is written as Psi-JT.

Table 10. Thermal characteristics for 208-pin MAPBGA

Symbol

R_JA

Parameter

Conditions

Value

Unit

CC D Junction-to-ambient, natural convection^2,3One layer board - 1s

°C/W

R_JMA

R_JA

R_JMA

R_JB

R_JC

_JT

CC D Junction-to-ambient natural convection^2,4

CC D Junction-to-ambient (@200 ft/min)^2,4

CC D Junction-to-board⁵

Four layer board - 2s2p

Single layer board

Four layer board 2s2p

Four layer board - 2s2p

CC D Junction-to-case⁶

CC D Junction-to-package top natural convection⁷

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate

method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter

is written as Psi-JT.

4.3.1

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T , can be obtained from the equation:

T = T + (R

* P )

Eqn. 1

JA

where:

T = ambient temperature for the package ( C)

= junction-to-ambient thermal resistance ( C/W)

JA

P = power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for

estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a

four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance

is not a constant. The thermal resistance depends on the:

•

Construction of the application board (number of planes)

Effective size of the board which cools the component

Quality of the thermal and electrical connections to the planes

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package

to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance

between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit

board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

•

One oz. (35 micron nominal thickness) internal planes

Components are well separated

Overall power dissipation on the board is less than 0.02 W/cm2

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the

ambient temperature varies widely within the application. For many natural convection and especially closed box applications,

the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the

device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R

* P )

Eqn. 2

JB

where:

T = board temperature for the package perimeter ( C)

= junction-to-board thermal resistance ( C/W) per JESD51-8S

JB

P = power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction

temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to

a board with internal planes.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal

resistance:

= R

+ R

CA

Eqn. 3

JA

JC

where:

= junction-to-ambient thermal resistance ( C/W)

JA

JC

CA

= junction-to-case thermal resistance ( C/W)

= case to ambient thermal resistance ( C/W)

is device related and is not affected by other factors. The thermal environment can be controlled to change the

JC

case-to-ambient thermal resistance, R

. For example, change the air flow around the device, add a heat sink, change the

CA

mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding

the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat

sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the

junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a

substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the

thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple

estimations and for computational fluid dynamics (CFD) thermal models.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization

parameter ( ) to determine the junction temperature by measuring the temperature at the top center of the package case using

the following equation:

T = T + ( x P )

Eqn. 4

where:

= thermocouple temperature on top of the package ( C)



= thermal characterization parameter ( C/W)

= power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests

on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from

the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling

effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

USA

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or

303-397-7956.

JEDEC specifications are available on the web at http://www.jedec.org.

•

C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine

Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

•

G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications”, Electronic

Packaging and Production, pp. 53-58, March 1998.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

•

B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application

in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

4.4

Electromagnetic Interference (EMI) characteristics

Table 11. EMI testing specifications

Level

(Typ)

Symbol

Parameter

Conditions

Device

Configuration, test

conditions and EM

testing per standard

IEC61967-2;Supply Frequency = 80

Voltage = 5.0V DC,

Ambient

f_OSC/f_BUS

Frequency

Unit

Radiated

Emissions

V_EME

Oscillator

Frequency = 8

MHz;

150 kHz – 50 MHz

50–150 MHz

150–500 MHz

500–1000 MHz

IEC Level

dBV

System Bus

MHz;

No PLL

Frequency

Modulation

—

Temperature =

25°C, Worst-case

Orientation

Oscillator

Frequency = 8

MHz;

System Bus

Frequency = 80

MHz;

1% PLL

Frequency

Modulation

150 kHz – 50 MHz

50–150 MHz

150–500 MHz

500–1000 MHz

IEC Level

dBV

—

IEC Classification Level: L = 24dBuV; K = 30dBuV.

4.5

Electromagnetic static discharge (ESD) characteristics

1,2

Table 12. ESD ratings

Symbol

Parameter

Conditions

Value

Unit

—

SR ESD for Human Body Model (HBM)

SR HBM circuit description

—

2000

1500

100

500

750



—

SR ESD for field induced charge Model (FCDM) All pins

Corner pins

—

SR Number of pulses per pin

SR Number of pulses

Positive pulses (HBM)

Negative pulses (HBM)

—

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification

requirements, which includes the complete DC parametric and functional testing at room temperature and hot

temperature.”

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.6

Power Management Control (PMC) and Power On Reset (POR)

electrical specifications

Table 13. PMC Operating conditions and external regulators supply voltage

Name

Jtemp

Parameter

Min

Typ

Max

Unit

SR — Junction temperature

–40

150

5.25

1.32

°C

Vddreg

Vdd

SR — PMC 5 V supply voltage VDDREG

4.75¹

1.26³

SR — Core supply voltage 1.2 V VDD when external

regulator is used without disabling the internal

regulator (PMC unit turned on, LVI monitor

active)²

1.3

—

SR — Core supply voltage 1.2 V VDD when external

regulator is used with a disabled internal

regulator (PMC unit turned-off, LVI monitor

disabled)

1.14

1.2

1.32

Ivdd

SR — Voltage regulator core supply maximum DC

output current⁴

400

3.3

—

Vdd33

SR — Regulated 3.3 V supply voltage when external

regulator is used without disabling the internal

regulator (PMC unit turned-on, internal 3.3V

regulator enabled, LVI

3.45

3.6

monitor active)⁵

—

SR — Regulated 3.3 V supply voltage when external

regulator is used with a disabled internal

regulator (PMC unit turned-off, LVI monitor

disabled)

3.3

—

3.6

—

SR — Voltage regulator 3.3 V supply maximum

required DC output current

During start up operation the minimum required voltage to come out of reset state is 4.6 V.

An internal regulator controller can be used to regulate core supply.

The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.

The onchip regulator can support a minimum of 400 ma although the worst case core current is 180 ma.

An internal regulator can be used to regulate 3.3 V supply.

Table 14. PMC electrical characteristics

Name

Vbg

Parameter

Min

Typ

Max

Unit

Notes

CC C Nominal bandgap voltage

reference

—

1.219

—

Untrimmed bandgap

reference voltage

Vbg–7%

Vbg

Vbg+6%

Trimmed bandgap

reference voltage (5 V,

27 °C)¹

Vbg–10mV

Vbg+10mV

—

CC C Bandgap reference

temperature variation

—

100

—

ppm

/°C

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 14. PMC electrical characteristics (continued)

Name

Parameter

Min

Typ

Max

Unit

Notes

—

CC C Bandgap reference supply

voltage variation

—

3000

—

ppm

Vdd

—

CC C Nominal VDD core supply

internal regulator target

—

1.28

Vdd

—

DC output voltage²

Nominal VDD core supply

internal regulator target DC

output voltage variation at

power-on reset

Vdd – 6%

Vdd + 10%

—

Nominal VDD core supply

internal regulator target DC

output voltage variation

after power-on reset

Vdd – 10³

Vdd

Vdd + 3%

—

CC C Trimming step Vdd

—

Ivrcctl

CC C Voltage regulator controller

for core supply maximum

DC output current

Lvi1p2

—

CC C Nominal LVI for rising core

supply^4,5

—

1.160

1.200

—

CC C Variation of LVI for rising

core supply at power-on

reset^5,6

1.120

1.280

—

CC C Variation of LVI for rising

core supply after power-on

reset^5,6

Lvi1p2–3% Lvi1p2

Lvi1p2+3%

—

CC C Trimming step LVI core

supply⁵

—

Lvi1p2_h CC C LVI core supply hysteresis⁵

—

Por1.2V_r CC C POR 1.2 V rising

0.709

—

CC C POR 1.2 V rising variation Por1.2V_r– Por1.2V_r Por1.2V_r+

35%

4b Por1.2V_f CC C POR 1.2 V falling

—

0.638

—

CC C POR 1.2 V falling variation Por1.2V_f– Por1.2V_f Por1.2V_f+

35%

Vdd33

CC C Nominal 3.3 V supply

internal regulator DC output

voltage

—

3.39

—

Nominal 3.3 V supply

internal regulator DC output

voltage variation at

Vdd33 –

8.5%

Vdd33

Vdd3 + 7%

power-on reset⁶

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 14. PMC electrical characteristics (continued)

Name

Parameter

Min

Typ

Max

Unit

Notes

—

Nominal 3.3 V supply

internal regulator DC output

voltage variation after

power-on reset

Vdd33 –

7.5%

Vdd33

Vdd33 +

With internal

load up

to Idd3p3

—

CC D Voltage regulator 3.3 V

output impedance at

—



maximum DC load

Idd3p3

Voltage regulator 3.3 V

maximum DC output

current

—

5e Vdd33 ILim⁶CC C Voltage regulator 3.3 V DC

current limit

—

130

—

Lvi3p3

CC C Nominal LVI for rising 3.3 V

supply⁵

3.090

The Lvi3p3

specs are also

valid for the

Vddeh LVI

—

CC C Variation of LVI for rising

3.3 V supply at power-on

reset⁵

Lvi3p3–6% Lvi3p3

Lvi3p3–3% Lvi3p3

Lvi3p3+6%

Lvi3p3+3%

See note ⁷

CC C Variation of LVI for rising

3.3 V supply after power-on

reset⁵

See note 7

CC C Trimming step LVI 3.3 V⁵

—

Lvi3p3_h CC C LVI 3.3 V hysteresis⁵

Por3.3V_r CC C Nominal POR for rising

3.3 V supply

2.07

The 3.3V POR

specs

are also valid

for the

Vddeh POR

—

CC C Variation of POR for rising Por3.3V_r– Por3.3V_r Por3.3V_r+

3.3 V supply

35%

7b Por3.3V_f CC C Nominal POR for falling

3.3 V supply

—

1.95

—

Lvi5p0

—

CC C Variation of POR for falling Por3.3V_f– Por3.3V_f Por3.3V_f+

3.3 V supply

35%

CC C Nominal LVI for rising 5 V

VDDREG supply⁵

—

4.290

—

CC C Variation of LVI for rising

5 V VDDREG supply at

power-on reset⁵

Lvi5p0–6% Lvi5p0

Lvi5p0–3% Lvi5p0

Lvi5p0+6%

Lvi5p0+3%

—

CC C Variation of LVI for rising

5 V VDDREG supply

power-on reset⁵

CC C Trimming step LVI 5 V⁵

—

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 14. PMC electrical characteristics (continued)

Name

Parameter

Min

Typ

Max

Unit

Notes

Lvi5p0_h CC C LVI 5 V hysteresis⁵

—

Por5V_r CC C Nominal POR for rising 5 V

VDDREG supply

2.67

—

CC C Variation of POR for rising Por5V_r – Por5V_r Por5V_r +

5 V VDDREG supply

35%

50%

Por5V_f CC C Nominal POR for falling 5 V

VDDREG supply

—

2.47

—

CC C Variation of POR for falling Por5V_f – Por5V_f Por5V_f +

5 V VDDREG supply 35% 50%

The limits will be reviewed after data collection from 3 different lots in a full production environment.

Using external ballast transistor.

Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.

LVI for falling supply is calculated as LVI rising - LVI hysteresis.

The internal voltage regulator can be disabled by tying the VDDREG pin to ground. When the internal voltage

regulator is disabled, the LVI specifications are not applicable because all LVI monitors are disabled. POR

specifications remain valid when the internal voltage regulator is disabled as long as VDDEH and VDD33 supplies

are within the required ranges.

This parameter is the “inrush” current of the internal 3.3V regulator when it is turned on. This spec. is the current at

which the regulator will go into current limit mode.

Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to

minimum and maximum Vdd33 DC target respectively.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.6.1

Regulator example

Keep inductance from 5V supply

to the transistor collector and

VDDREG below 1 H if not using R

V_DDREG

5V from

power supply

Required only

C_REG

if R is used

R_C

C_C

MCU

V_RCCTL

R_B

C_B

Keep inductance

below 20 nH

R_E

V_DD

V_SS

C_E

C_D

Figure 7. Core voltage regulator controller external components preferred configuration

There are three options for the bypassing and compensation networks for the 1.2V regulator controller. The component values

in the following table are the same for all PMC network requirements.

Table 15. Required external PMC component values

Component

Pass Transistor

Symbol

Minimum

Typical

Maximum

Units

Comment

NJD2873 or

BCP68

VDDREG capacitor

C_REG

µF



X7R,

-50%/+35%

Pass transistor Collector C_C

bypass capacitor

13.3

5.6

X7R,

-50%/+35%

Collector resistor¹

R_C

1.1

—

The collector resistor may not be required. It depends on the allowable power dissipation of the pass transistor (T1).

Table 16, Table 17 and Table 18 show the required component values for the three different options.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Component

Table 16. Network 1 component values

Symbol

Minimum

Typical

Maximum

Units

Comment

Transistor emitter bypass C_E

capacitance

4 x 2.35

1 x 5

4 x 4.7

1 x 10

4 x 6.35

1 x 13.5

µF

X7R, -50%/+35%

R_ESR

C_D

m

Equivalent ESR of

C_Ecapacitors

MCU decoupling

capacitor

4 x 50

4 x 100

4 x 135

X7R, -50%/+35%

Base "snubber" capacitor C_B

Base "snubber" resistor R_B

1.1

6.12

2.2

6.8

2.97

7.48

µF



X7R, -50%/+35%

±10%

Emitter resistor

R_E



Not required

(short)

Table 17. Network 2 component values

Component

Symbol

Minimum

Typical

Maximum

Units

Comment

Transistor emitter bypass C_E

capacitance

3 x 2.35

1 x 5

3 x 4.7

1 x 10

3 x 6.35

1 x 13.5

µF

X7R, -50%/+35%

R_ESR

C_D

m

Equivalent ESR of

C_Ecapacitors

MCU decoupling

capacitor

4 x 50

4 x 100

4 x 135

X7R, -50%/+35%

Base "snubber" capacitor C_B

Base "snubber" resistor R_B

1.1

2.2

2.97

µF



X7R, -50%/+35%

±10%

Emitter resistor

R_E

0.252

0.280

0.308



Not required

(short)

The following component configuration is acceptable when using the BCP68 transistor, however, is not recommended for new

designs. Either option 1 or option 2 should be used for new designs. This option should not be used with the NJD2873 transistor.

Table 18. Network 3 component values

Component

Symbol

Minimum

Typical

Maximum

Units

Comment

Transistor emitter bypass C_E

capacitance

4 x 3.4

4 x 6.8

4 x 9.18

µF

X7R, -50%/+35%

R_ESR

m

Equivalent ESR of

C_Ecapacitors

MCU decoupling

capacitor

C_D

4 x 110

4 x 220

4 x 297

X7R, -50%/+35%

Base "snubber" capacitor C_B

Base "snubber" resistor R_B

1.1

13.5

2.2

2.97

16.5

µF



X7R, -50%/+35%

±10%

Emitter resistor

R_E



Not required

(short)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.6.2

Recommended power transistors

The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor

BCP68T1 or NJD2873 as well as Philips Semiconductor BCP68. The collector of the external transistor is preferably

connected to the same voltage supply source as the output stage of the regulator.

Table 19. Recommended operating characteristics

Symbol

Parameter

Value

Unit

h_FE() DC current gain (Beta)

60 – 550

—

P_D

Absolute minimum power dissipation

>1.0

(1.5 preferred)

I_CMaxDCMinimum peak collector current

1.0

VCE_SATCollector-to-emitter saturation voltage

200–600¹

V_BE

Base-to-emitter voltage

0.4–1.0

Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCE_SAT

4.7

Power up/down sequencing

There is no power sequencing required among power sources during power up and power down, in order to operate within

specification but use of the following sequence is strongly recommended when the internal regulator is bypassed:

5 V  3.3 V and 1.2 V

This is also the normal sequence when the internal regulator is enabled.

Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,

the state of the I/O pins during power up/down varies according to table Table 20 for all pins with fast pads and Table 21 for all

pins with medium, slow and multi-voltage pads.

Table 20. Power sequence pin states for fast pads

V_DDE

V_RC33

V_DD

Fast (pad_fc)

LOW

V_DDE

LOW

HIGH

LOW

V_RC33

LOW

V_DD

HIGH IMPEDANCE

FUNCTIONAL

Table 21. Power sequence pin states for medium, slow and multi-voltage pads

Medium (pad_msr_hv)

V_DDEH

V_DD

Slow (pad_ssr_hv)

Multi-voltage (pad_multv_hv)

LOW

V_DDEH

LOW

V_DD

HIGH IMPEDANCE

FUNCTIONAL

1.If an external 3.3V external regulator is used to supply current to the 1.2V pass transistor and this supply also supplies

current for the other 3.3V supplies, then the 5V supply must always be greater than or equal to the external 3.3V supply.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.8

DC electrical specifications

Table 22. DC electrical specifications

Value²

typ

Symbol

Parameter

Conditions

Unit

min

max

V_DD

SR — Core supply voltage

SR — I/O supply voltage

SR — 3.3 V external voltage⁴

SR — Analog supply voltage

SR — Analog input voltage⁶

SR — V_SSdifferential voltage

—

1.14

1.62

3.0

—

1.32

3.6³

V_DDE

V_DDEH

V_RC33

V_DDA

5.25

3.0

3.6

4.75⁵

5.25

V_INDC

_SS– V_SSA

V_RL

V_SSA– 0.3

–100

V_DDA+0.3

100

SR — Analog reference low

voltage

V_SSA

V_SSA+0.1

_RL– V_SSA

V_RH

SR — V_RLdifferential voltage

—

–100

—

100

SR — Analog reference high

voltage

V_DDA– 0.1

V_DDA

_RH– V_RL

SR — V_REFdifferential

voltage

—

4.75

1.14

—

5.25

1.32

V_DDF

SR — Flash operating

voltage ⁷

V_FLASH

SR — Flash read voltage

4.75

0.95

—

5.25

1.2

V_STBY

SR — SRAM standby voltage Unregulated

mode

Regulated

mode

2.0

—

5.5

5.25

V_DDREG

V_DDPLL

_SSPLL– V_SS

V_{IL_S}

SR — Voltage regulator

supply voltage⁹

—

4.75

SR — Clock synthesizer

operating voltage

1.14

1.32

SR — V_SSPLLto V_SS

differential voltage

–100

100

CC C Slow/medium pad I/O Hysteresis

V_SS–0.3

0.35*V_DDEH

0.40*V_DDEH

0.35*V_DDE

0.40*V_DDE

input low voltage

enabled

hysteresis

disabled

V_{IL_F}

CC C Fast pad I/O input low Hysteresis

voltage

enabled

hysteresis

disabled

V_SS–0.3

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 22. DC electrical specifications (continued)

Value²

Symbol

Parameter

Conditions

Unit

max

min

typ

V_{IL_LS}

Multi-voltage pad I/O Hysteresis

V_SS–0.3

—

0.8

input low voltage in

low-swing

enabled

Hysteresis

disabled

_SS–0.3

—

1.1

mode^10,11,12,13

V_{IL_HS}

CC C Multi-voltage pad I/O Hysteresis

0.35 V_DDEH

0.4 V_DDEH

V_DDEH+0.3

V_DDE+0.3

V_DDEH+0.3

0.2*V_DDEH

input low voltage in

high-swing mode

enabled

Hysteresis

disabled

V_SS–0.3

0.65 V_DDEH

0.55 V_DDEH

0.65 V_DDE

0.55 V_DDE

2.5

V_{IH_S}

CC C Slow/medium pad I/O Hysteresis

input high voltage

enabled

hysteresis

disabled

V_{IH_F}

CC C Fast pad I/O input high Hysteresis

voltage

enabled

hysteresis

disabled

V_{IH_LS}

V_{IH_HS}

V_{OL_S}

CC C Multi-voltage pad I/O Hysteresis

input high voltage in

low-swing

enabled

Hysteresis

disabled

2.2

mode^{10,11,12,13,14}

CC C Multi-voltage pad I/O Hysteresis

0.65 V_DDEH

0.55 V_DDEH

—

input high voltage in

enabled

high-swing mode¹⁵

Hysteresis

disabled

CC P Slow/medium

—

multi-voltage pad I/O

output low voltage^18,16

V_{OL_F}

CC P Fast pad I/O output low

voltage^17,18

—

0.2*V_DDE

0.6

V_{OL_LS}

CC P Multi-voltage pad I/O

output low voltage in

low-swing

_OL= 2 mA

mode^{10,11,12,13,17}

V_{OL_HS}

V_{OH_S}

V_{OH_F}

CC P Multi-voltage pad I/O

output low voltage in

—

0.2 V_DDEH

high-swing mode¹⁷

CC P Slow/medium pad I/O

output high

0.8 V_DDEH

—

voltage^18,16

CC P Fast pad I/O output

high voltage^17,18

0.8 V_DDE

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 22. DC electrical specifications (continued)

Value²

Symbol

Parameter

Conditions

Unit

min

typ

max

V_{OH_LS}

CC P Multi-voltage pad I/O

output high voltage in

low-swing

I_{OH_LS}

2.1

—

3.7

0.5 mA

Min V_DDEH

4.75 V

mode^{10,11,12,13,17}

V_{OH_HS}

CC P Multi-voltage pad I/O

output high voltage in

—

0.8 V_DDEH

—

high-swing mode¹⁷

V_{HYS_S}

CC C Slow/medium/multi-vol

tage I/O input

—

0.1 * V_DDEH

hysteresis

V_{HYS_F}

CC C Fast I/O input

hysteresis

—

0.1 * V_DDE

0.25

—

V_{HYS_LS}

CC C Low-Swing-Mode

hysteresis

Multi-Voltage I/O Input enabled

Hysteresis

_DD+I_DDPLL

CC P Operating current

1.2 V supplies

V_DD= 1.32 V,

80 MHz

—

195

135

_DD= 1.32 V,

60 MHz

_DD= 1.32 V,

40 MHz

I_DDSTBY

T Operating current 1 V T_J= 25 ^oC

supplies

—

100

700

µA

A

T_J= 55 ^oC

T_J=150 ^oC

I_DDSTBY150

CC P Operating current

I_DDSLOW

I_DDSTOP

CC P V_DDlow-power mode Slow mode²⁰

operating current @

Stop mode²¹

1.32 V

4 22

I_DD33

T Operating current

3.3 V supplies @

80 MHz

V_RC33

—

I_DDA

I_REF

I_DDREG

CC P Operating current

V_DDA

—

5.0 V supplies @

Analog

reference

1.0

80 MHz

supply current

V_DDREG

—

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 22. DC electrical specifications (continued)

Value²

typ

Symbol

Parameter

Conditions

Unit

max

min

I_DDH1

CC D Operating current

V_DDEH1

V_DDEH6

V_DDEH7

V_DDE7

—

See note ²³

I_DDH6

I_DDH7

I_DD7

I_DDH9

I_DD12

V_DDE²³supplies @

80 MHz

V_DDEH9

V_DDE12

I_{ACT_S}

CC C Slow/mediumI/Oweak 3.0 V – 3.6 V

pull up/down current²⁴

A

4.75 V –

5.25 V

200

I_{ACT_F}

CC D Fast I/O weak pull

up/down current²⁴

1.62 V –

1.98 V

—

120

139

2.25 V –

2.75 V

3.0 V – 3.6 V

—

158

I_{ACT_MV_PU}

CC C Multi-voltagepadweak V_DDEH

A

pullup current

3.0–3.6 V¹⁰

pad_multv_hv,

all process

corners,

high swing

mode only

4.75 V –

5.25 V

—

200

I_{ACT_MV_PD}

CC C Multivoltage pad weak V_DDEH

A

pulldown current

3.0–3.6 V¹⁰

pad_multv_hv,

all process

corners,

high swing

mode only

4.75 V –

5.25 V

—

200

2.5

1.0

250

I_{INACT_D}

I_IC

CC P I/O input leakage

current²⁵

—

–2.5

–1.0

–250

A

T DC injection current

(per pin)

I_{INACT_A}

CC P Analog input current,

channel off, AN[0:7],

AN38, AN39²⁶

P Analog input current,

channel off, all other

analog pins (ANx)²⁶

—

–150

—

150

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 22. DC electrical specifications (continued)

Value²

Symbol

Parameter

Conditions

Unit

min

typ

max

C_L

CC D Load capacitance (fast DSC(PCR[8:9

—

I/O)²⁷

]) = 0b00

DSC(PCR[8:9

]) = 0b01

—

DSC(PCR[8:9

]) = 0b10

DSC(PCR[8:9

]) = 0b11

C_IN

CC D Input capacitance

(digital pins)

—

C_{IN_A}

C_{IN_M}

CC D Input capacitance

(analog pins)

CC D Input capacitance

(digital and analog

pins²⁸

)

R_PUPD200K

CC P Weak Pull-Up/Down

Resistance^29,30

—

130

—

280

k

200 k Option

R_PUPDMATCH

R_PUPD100K

CC C 200K Option

–2.5

2.5

CC P Weak Pull-Up/Down

Resistance^29,30

140

k

100 k Option

R_PUPDMATCH

R_PUPD5K

CC C 100K Option

–2.5

1.4

2.5

7.5

CC D Weak Pull-Up/Down

Resistance²⁹

5 V ± 5%

supply

—

k

5 k Option

T_A(T_Lto T_H)

SR — Operating temperature

range - ambient

—

–40.0

—

125.0

^C

(packaged)

—

SR — Slew rate on power

supply pins

V/ms

These specifications are design targets and subject to change per device characterization.

TBD: To Be Defined.

V_DDEmust be lower than V_RC33, otherwise there is additional leakage on pins supplied by V_DDE

These specifications apply when V_RC33is supplied externally, after disabling the internal regulator (V_DDREG= 0).

ADC is functional with 4 V  V_DDA 4.75 V but with derated accuracy. This means the ADC will continue to function

at full speed with no bad behavior, but the accuracy will be degraded.

Internal structures hold the input voltage less than V_DDA+ 1.0 V on all pads powered by V_DDAsupplies, if the

maximum injection current specification is met (3 mA for all pins) and V_DDAis within the operating voltage

specifications.

The V_DDFsupply is connected to V_DDin the package substrate. This specification applies to calibration package

devices only.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

V_FLASHis only available in the calibration package.

Regulator is functional, with derated performance, with supply voltage down to 4.0 V.

¹⁰Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.

¹¹The slew rate (SRC) setting must be 0b11 when in low-swing mode.

¹²While in low-swing mode there are no restrictions in transitioning to high-swing mode.

¹³Pin in low-swing mode can accept a 5 V input.

¹⁴Values are pending characterization.

¹⁵Pin in low-swing mode can accept a 5 V input.

Characterization based capability:

IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;

IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V

¹⁷Characterization based capability:

IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;

IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;

IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V

¹⁸All VOL/VOH values 100% tested with ± 2 mA load.

¹⁹Run mode as follows:

System clock = 40/60/80 MHz + FM 2%

Code executed from flash memory

ADC0 at 16 MHz with DMA enabled

ADC1 at 8 MHz

eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz

eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz

CAN configured for a bit rate of 500 kHz

DSPI configured in master mode with a bit rate of 2 MHz

eSCI transmission configured with a bit rate of 100 kHz

²⁰Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive

code, 4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.

²¹Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules

stopped.

²²When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should

not be powered by the internal regulator. The internal regulator can be used as a reference for an external debugger.

²³Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a

particular I/O segment, and the voltage of the I/O segment. See Table 23 for values to calculate power dissipation for

specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions

for each pin on the segment.

²⁴Absolute value of current, measured at V_ILand V_IH.

²⁵Weak pull up/down inactive. Measured at V_DDE= 3.6 V and V_DDEH= 5.25 V. Applies to pad types: fast (pad_fc).

²⁶Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half

for each 8 to 12 ^oC, in the ambient temperature range of 50 to 125 ^oC. Applies to pad types: pad_a and pad_ae.

²⁷Applies to CLKOUT, external bus pins, and Nexus pins.

²⁸Applies to the FCK, SDI, SDO, and SDS pins.

²⁹This programmable option applies only to eQADC differential input channels and is used for biasing and sensor

diagnostics.

³⁰When the pull-up and pull-down of the same nominal 200 K or 100 K value are both enabled, assuming no

interference from external devices, the resulting pad voltage will be 0.5*V_DDE± 2.5%

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.9

I/O Pad current specifications

NOTE

MPC5634M devices use two sets of I/O pads (5 V and 3.3 V). See Table 2 and Table 3 in

Section 3.6, “Signal summary, for the pad type associated with each signal.

The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption

is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 23 based on

the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load

parameters that fall outside the values given in Table 23.

Table 23. I/O pad average I

specifications

DDE

Period

(ns)

Load²V_DDE

Drive/Slew

Rate Select

_DDEAvg

(mA)³

_DDERMS

(mA)

Pad Type

Symbol

(pF)

(V)

Slow

I_{DRV_SSR_HV}

130

650

840

200

5.25

3.6

2.5

—

0.5

—

1.5

—

Medium

I_{DRV_MSR_HV}

—

5.3

—

317

425

1.1

—

Fast

I_{DRV_FC}

22.7

12.1

8.3

68.3

41.1

27.7

14.3

3.6

4.44

12.5

7.3

1.98

5.25

18.6

12.6

6.4

—

5.42

2.84

21.2⁴

MultiV I_{DRV_MULTV_HV}CC

(High

Swing

—

6.2⁴

1.1⁴

—

Mode)

300

—

4.0⁴

—

MultiV I_{DRV_MULTV_HV}CC

(Low

Swing

Mode)

20.2⁶

—

Numbers from simulations at best case process, 150 °C.

All loads are lumped.

Average current is for pad configured as output only.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Ratio from 5.5 V pad spec to 5.25 V data sheet.

Not specified.

Low swing mode is not a strong function of V_DDE

4.9.1

I/O pad VRC33 current specifications

The power consumption of the VRC33 supply is dependent on the usage of the pins on all I/O segments. The power

consumption is the sum of all output pin V currents for all I/O segments. The output pin V current can be calculated

RC33

from Table 24 based on the voltage, frequency, and load on all medium, slow, and multv_hv pins. The output pin VRC33 current

can be calculated from Table 25 based on the voltage, frequency, and load on all fast pins. Use linear scaling to calculate pin

currents for voltage, frequency, and load parameters that fall outside the values given in Table 24 and Table 25.

Table 24. I/O pad V

average I

specifications

DDE

RC33

Period

(ns)

Load²

(pF)

Slew Rate

Select

_DD33Avg

(µA)

I_DD33RMS

(µA)

Pad Type

Symbol

Slow

I_{DRV_SSR_HV}

100

200

800

0.8

0.04

0.06

0.009

2.75

0.11

0.02

0.01

2.75

0.11

0.02

0.01

2.75

0.11

0.02

0.01

235.7

87.4

47.4

200

Medium

I_{DRV_MSR_HV}

258

100

500

76.5

56.2

258

200

MultiV³(High I_{DRV_MULTV_HV}CC

Swing Mode)

100

500

76.5

56.2

258

200

MultiV⁴(Low I_{DRV_MULTV_HV}CC

Swing Mode)

100

500

76.5

56.2

These are typical values that are estimated from simulation and not tested. Currents apply to output pins

only.

All loads are lumped.

Average current is for pad configured as output only.

In low swing mode, multi-voltage pads (pad_multv_hv) must operate in highest slew rate setting.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 25. V

pad average DC current

RC33

Pad

Type

Period

(ns)

Load²

(pF)

V_RC33

(V)

V_DDE

(V)

Drive

Select

I_DD33Avg I_DD33RMS

Symbol

(µA)

3.6

2.35

1.75

1.41

1.06

1.75

1.32

1.14

0.95

6.12

4.3

3.6

3.43

2.9

3.6

Fast

I_{DRV_FC}

1.98

4.56

3.44

2.95

2.62

These are typical values that are estimated from simulation and not tested. Currents apply to output pins

only.

All loads are lumped.

4.9.2

LVDS pad specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI

module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.

1, 2

Table 26. DSPI LVDS pad specification

Min.

Value

Typ.

Value

Max.

Value

Characteristic

Symbol

Condition

Unit

Data Rate

Data Frequency

F_LVDSCLK

MHz

Driver Specs

Differential output voltage

V_OD

SRC=0b00 or

0b11

150

430

SRC=0b01

SRC=0b10

155

0.8

340

480

1.6

Common mode voltage

(LVDS), V_OS

V_OS

1.2

Rise/Fall time

T_R/T_F

T_PLH

Propagation delay (Low to

High)

Propagation delay (High to

Low)

T_PHL

10 Delay (H/L), sync Mode

t_PDSYNC

11 Delay, Z to Normal (High/Low) T_DZ

500

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

1, 2

Table 26. DSPI LVDS pad specification

(continued)

12 Diff Skew Itphla-tplhbI or

Itplhb-tphlaI

T_SKEW

0.5

Termination

13 Trans. Line (differential Zo)

14 Temperature

100

105

150



–40

C

These are typical values that are estimated from simulation.

These specifications are subject to change per device characterization.

Preliminary target values. Actual specifications to be determined.

4.10 Oscillator and PLLMRFM electrical characteristics

Table 27. PLLMRFM electrical specifications

(V_DDPLL=1.14 V to 1.32 V, V_SS= V_SSPLL= 0 V, T_A= T_Lto T_H)

Value

Symbol

Parameter

Conditions

Unit

min

max

f_{ref_crystal}

f_{ref_ext}

CC D PLL reference frequency range²

Crystal reference

External reference

—

MHz

f_{pll_in}

Phase detector input frequency range

(after pre-divider)

MHz

f_vco

f_sys

VCO frequency range³

—

256

512

MHz

CC C On-chip PLL frequency²

System frequency in bypass mode⁴

Crystal reference

External reference

—

t_CYC

CC D System clock period

—

1.6

1.2

–5

1 / f_sys

3.7

f_LORL

f_LORH

CC D Loss of reference frequency window⁵

Lower limit

Upper limit

—

MHz

f_SCM

Self-clocked mode frequency ^6,7

MHz

C_JITTER

CLKOUT period Peak-to-peak (clock

f_SYSmaximum

% f_CLKO

jitter^8,9,10,11

edge to clock edge)

Long-term jitter (avg.

over 2 ms interval)

–6

—

t_cst

Crystal start-up time ^{12, 13}

—

V_IHEXT

EXTAL input high voltage

Crystal Mode¹⁴

0.8  Vxtal  1.5V¹⁵

Vxtal +

0.4

External Reference^14,V_RC33/2

V_RC33

+ 0.4

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 27. PLLMRFM electrical specifications

(V_DDPLL=1.14 V to 1.32 V, V_SS= V_SSPLL= 0 V, T_A= T_Lto T_H) (continued)

Value

Symbol

Parameter

Conditions

Unit

min

max

V_ILEXT

EXTAL input low voltage

Crystal Mode¹⁴

—

Vxtal –

0.4

0.65Vxtal1.25V¹⁵

External Reference^14,

V_RC33/2

– 0.4

—

XTAL load capacitance¹²

4 MHz

8 MHz

12 MHz

16 MHz

20 MHz

t_lpll

t_dc

f_LCK

f_UL

f_CS

PLL lock time ^{12, 17}

—

200

s

Duty cycle of reference

Frequency LOCK range

Frequency un-LOCK range

—

–6

–18

±0.25

–0.5

—

% f_sys

%f_sys

CC D Modulation Depth

Center spread

Down Spread

—

±4.0

–8.0

100

f_DS

f_MOD

CC D Modulation frequency¹⁸

kHz

All values given are initial design targets and subject to change.

Considering operation with PLL not bypassed.

f_VCOis calculated as follows:

— In Legacy Mode f_VCO= (f_crystal/ (PREDIV + 1)) * (4 * (MFD + 4))

— In Enhanced Mode fvco = (f_crystal/ (EPREDIV + 1)) * (EMFD + 4)

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the

f_LORwindow.

f_VCOself clock range is 20–150 MHz. f_SCMrepresents f_SYSafter PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_SYS

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.

Noise injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency increase the

C_JITTERpercentage for a given interval.

¹⁰Proper PC board layout procedures must be followed to achieve specifications.

¹¹Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C_JITTERand

either f_CSor f_DS(depending on whether center spread or down spread modulation is enabled).

¹²This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for

this PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.

¹³Proper PC board layout procedures must be followed to achieve specifications.

¹⁴This parameter is guaranteed by design rather than 100% tested.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

¹⁵Vxtal range is preliminary and subject to change pending characterization data.

cannot exceed V_RC33in external reference mode.

IHEXT

¹⁷This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in

the synthesizer control register (SYNCR).

¹⁸Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz.

4.11 Temperature sensor electrical characteristics

Table 28. Temperature sensor electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

min

typical

max

—

CC C Temperature

monitoring range

–40

—

150

°C

—

CC C Sensitivity

CC Accuracy

—

6.3

—

mV/°C

°C

T_J= –40 to 150 °C

–10

4.12 eQADC electrical characteristics

NOTE

ADC performance is affected by several environmental elements, such as quality of the

input signal source, presence of noise sources and quality of the PCB layout.

The DC or Static parameters (DNL, INL, OFFSET, GAIN, and TUE) are measured using

methods that provide a very accurate evaluation using averaging.

The AC or Dynamic parameters (SNR, THD, SFDR, SINAD) are determined using a full

scale peak-peak sinewave of 1kHz frequency at the input of the ADC.

Table 29. eQADC conversion specifications (operating)

Value

Symbol

Parameter

Unit

min

max

f_ADCLK

SR — ADC clock (ADCLK) frequency

CC D Conversion cycles

MHz

2 + 13

128 + 14

ADCLK

cycles

T_SR

—

CC C Stop mode recovery time¹

CC D Resolution²

—

1.25

—

160

s

OFFNC

OFFWC

GAINNC

GAINWC

I_INJ

CC C Offset error without calibration

CC C Offset error with calibration

CC C Full scale gain error without calibration

CC C Full scale gain error with calibration

Counts

–4

–160

–4

Disruptive input injection current ^{3, 4, 5, 6}

–3

E_INJ

Incremental error due to injection current^6,7,8

–4

Counts

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 29. eQADC conversion specifications (operating) (continued)

Value

Symbol

Parameter

Unit

min

max

TUE8

CC C Total unadjusted error (TUE) at 8 MHz⁹

CC C Total unadjusted error at 16 MHz¹⁰

–4

–8

Counts

TUE16

SNR

Signal to Noise Ratio¹¹

55.2

70.0

65.0

55.0

8.8

THD

Total Harmonic Distorsion

SFDR

Spurious Free Dynamic Range

Signal to Noise and Distorsion

Effective Number of Bits

SINAD

ENOB

Counts

GAINVGA1

–

Variable gain amplifier accuracy (gain=1)¹²

–

INL

8 MHz ADC

–4

–8

Counts¹³

Counts

16 MHz ADC

8 MHz ADC

16 MHz ADC

DNL

–3¹⁴

3¹⁴

GAINVGA2

GAINVGA4

Variable gain amplifier accuracy (gain=2)¹²

–

INL

8 MHz ADC

–5

–8

–3

Counts

16 MHz ADC

8 MHz ADC

16 MHz ADC

DNL

Variable gain amplifier accuracy (gain=4)¹²

INL

8 MHz ADC

–7

–8

–4

–

Counts

16 MHz ADC

8 MHz ADC

16 MHz ADC

DNL

DIFF_max

DIFF_max2

DIFF_max4

DIFF_cmv

CC C Maximum differential voltage

(DANx+ - DANx-) or (DANx- -

DANx+)

PREGAIN set

to 1X setting

(VRH -

VRL)/2

PREGAIN set

to 2X setting

–

(VRH -

VRL)/4

PREGAIN set

to 4X setting

(VRH -

VRL)/8

CC C Differential input Common mode

voltage (DANx- + DANx+)/2¹⁵

(VRH -

VRL)/2 -

(VRH -

VRL)/2 +

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the

time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.

At V_RH– V_RL= 5.12 V, one count = 1.25 mV. Without using pregain.

Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs

greater then V_RHand 0x0 for values less then V_RL. Other channels are not affected by non-disruptive conditions.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within

the limit do not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values using V_POSCLAMP= V_DDA+ 0.5 V and V_NEGCLAMP= – 0.3 V, then use the larger of the

calculated values.

Condition applies to two adjacent pins at injection limits.

Performance expected with production silicon.

All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; I_INJ=I_INJMAX,I_INJMIN.

TUE is tested by averaging 10 samples.

¹⁰TUE is tested by averaging three samples.

These values can be significantly improved by using three samples of averaging. Input frequency of 1 kHz was used

as the reference for the Signal to Noise Ratio.

¹²Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1,

2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as

indicated.

¹³At V_RH– V_RL= 5.12 V, one LSB = 1.25 mV.

¹⁴Guaranteed 10-bit monotonicity.

¹⁵Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately

if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the

common mode voltage of the differential signal violates the Differential Input common mode voltage specification.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.13 Platform flash controller electrical characteristics

Table 30. APC, RWSC, WWSC settings vs. frequency of operation

Target Max Frequency

APC²

RWSC²

WWSC

(MHz)

21³

41³

62³

82³

All

000

001

010

011

111

000

001

010

011

111

Illegal combinations exist, all entries must be taken from the same row

APC must be equal to RWSC

Maximum Frequency includes FM modulation

4.14 Flash memory electrical characteristics

Table 31. Program and erase specifications

Typical

Value¹

Initial

Symbol

Parameter

Min Value

Max³

Unit

Max²

T_dwprogram

T_16kpperase

T_32kpperase

T_64kpperase

T_128kpperase

Double Word (64 bits) Program Time⁴

16 KB Block Pre-program and Erase Time

32 KB Block Pre-program and Erase Time

64 KB Block Pre-program and Erase Time

128 KB Block Pre-program and Erase Time

—

500

600

900

1300

500

s

300

400

600

800

5000

7500

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to

change pending device characterization.

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program & erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

Actual hardware programming times. This does not include software overhead.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 32. Flash module life

Value

Unit

Typ

Symbol

Parameter

Conditions

Min

100,000

P/E

C Number of program/erase cycles per block

for 16 Kbyte blocks over the operating

temperature range (T_J)

—

cycles

P/E

C Number of program/erase cycles per block

for 32 and 64 Kbyte blocks over operating

temperature range (T_J)

10,000 100,000 cycles

C Number of program/erase cycles per block

for 128 Kbyte blocks over the operating

temperature range (T_J)

1,000

100,000 cycles

Retention C Minimum data retention at 85 °C average

ambient temperature¹

Blocks with 0 – 1,000

P/E cycles

—

years

Blocks with 10,000 P/E

cycles

Blocks with 100,000 P/E

cycles

Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.15 AC specifications

4.15.1 Pad AC specifications

1,2

Table 33. Pad AC specifications (5.0 V)

Output Delay (ns)^3,4

Low-to-High /

4 5

SRC/DSC

Rise/Fall Edge ( )

Drive Load

(pF)

Name

High-to-Low

Min

4.6/3.7

13/10

Max

12/12

32/32

Min

2.2/2.2

9/9

Max

MSB,LSB

7/7

11⁹

22/22

200

N/A

10¹⁰

Medium^6,7,8

12/13

23/23

69/71

95/90

7.3/5.7

24/19

28/34

52/59

5.6/6

11/14

34/35

44/51

4.4/4.3

17/15

15/15

31/31

74/74

96/96

14/14

42/42

200

152/165

205/220

19/18

200

11⁹

10¹⁰

58/58

200

N/A

Slow^8,11

26/27

49/45

61/69

13/13

27/23

34/34

61/61

200

115/115

320/330

420/420

10.3/8.9

137/142

182/172

4.1/3.6

72/74

164/164

200/200

8/8

90/85

200

3.28/2.98

11⁹

10¹⁰

10.4/10.2 24.2/23.6 12.7/11.54

N/A

29/29

200

MultiV¹²

(High Swing Mode)

8.38/6.11 16/12.9

15.9/13.6 31/28.5

5.48/4.81

14.6/13.1

11/11

31/31

63/63

200

61.7/10.4 92.2/24.3 42.0/12.2

132.6/

85.5/37.3

57.7/46.4

85/85

7/7

200

78.9

MultiV

(Low Swing Mode)

2.31/2.34 7.62/6.33 1.26/1.67

N/A

11⁹

Fast¹³

pad_i_hv¹⁴

pull_hv

0.5/0.5

1.9/1.9

6000

0.3/0.3

—

1.5/1.5

0.5

N/A

5000/5000

These are worst case values that are estimated from simulation and not tested. Values in the table are simulated

at f_SYS= 80 MHz, V_DD= 1.14 V to 1.32 V, V_DDE= 1.62 V to 1.98 V, V_DDEH= 4.5 V to 5.25 V, T_A= T_Lto T_H.

TBD: To Be Defined.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output

pads

Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

Output delay is shown in Figure 8. Add a maximum of one system clock to the output delay for delay with respect

to system clock.

Can be used on the tester.

¹⁰This drive select value is not supported. If selected, it will be approximately equal to 11.

¹¹Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

¹²Selectable high/low swing IO pad with selectable slew in high swing mode only.

¹³Fast pads are 3.3 V pads.

¹⁴Stand alone input buffer. Also has weak pull-up/pull-down.

Table 34. Pad AC specifications (3.3 V)

Output Delay (ns)^2,3

Low-to-High /

High-to-Low

Rise/Fall Edge (ns)^3,4

SRC/DSC

Drive Load

(pF)

Pad Type

Min

Max

Min

Max

MSB,LSB

Medium^5,6,7

5.8/4.4

16/13

18/17

46/49

2.7/2.1

10/10

34/34

11⁸

11.2/8.6

200

N/A

10⁹

14/16

27/27

37/45

69/82

6.5/6.7

15/13

38/38

53/46

5.5/4.1

21/16

19/19

43/43

200

83/86

200/210

270/285

27/28

86/86

113/109

9.2/6.9

30/23

120/120

20/20

200

Slow^7,10

81/87

63/63

200

N/A

10⁹

31/31

58/52

80/90

144/155

415/415

533/540

3.7/3.1

46/49

15.4/15.4

32/26

42/42

82/85

200

162/168

216/205

80/82

190/190

250/250

10/10

106/95

200

MultiV^7,11

(High Swing Mode)

11⁸

37/37

200

N/A

10⁹

15/15

46/46

200

210

295

100/100

134/134

200

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 34. Pad AC specifications (3.3 V) (continued)

Output Delay (ns)^2,3

Low-to-High /

High-to-Low

Rise/Fall Edge (ns)^3,4

SRC/DSC

MSB,LSB

Drive Load

(pF)

Pad Type

Min

Max

Min

Max

2.5/2.5

3/3

1.2/1.2

0.5

Fast

1.2/1.2

11⁸

N/A

pad_i_hv¹²

0.5/0.5

0.4/0.4

1.5/1.5

pull_hv

6000

5000/5000

These are worst case values that are estimated from simulation and not tested. The values in the table are

simulated at f_SYS= 80 MHz, V_DD= 1.14 V to 1.32 V, V_DDE= 3 V to 3.6 V, V_DDEH= 3 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output

pads

Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

Output delay is shown in Figure 8. Add a maximum of one system clock to the output delay for delay with respect

to system clock.

Can be used on the tester

This drive select value is not supported. If selected, it will be approximately equal to 11.

¹⁰Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

¹¹Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

¹²Stand alone input buffer. Also has weak pull-up/pull-down.

Table 35. Pad AC specifications (1.8 V)

Output Delay (ns)^1,2

Low-to-High /

High-to-Low

Rise/Fall Edge (ns)³

SRC/DSC

MSB,LSB

Drive Load

(pF)

Pad Type

Min

Max

Min

Max

3.0/3.0

2.0/1.5

Fast

11⁴

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Can be used on the tester.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

DDE

Pad

Data Input

Rising

Edge

Output

Delay

Falling

Edge

Output

Delay

Pad

Output

Figure 8. Pad output delay

4.16 AC timing

4.16.1 IEEE 1149.1 interface timing

Table 36. JTAG pin AC electrical characteristics

Min.

Value

Max.

Value

Symbol

t_JCYC

Characteristic

TCK Cycle Time

Unit

100

—

t_JDC

TCK Clock Pulse Width

t_TCKRISE

TCK Rise and Fall Times (40% – 70%)

TMS, TDI Data Setup Time

TMS, TDI Data Hold Time

t_{TMSS, TDIS}

—

_TMSH,t_TDIH

—

t_TDOV

TCK Low to TDO Data Valid

t_TDOI

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

TCK Low to TDO Data Invalid

TCK Low to TDO High Impedance

JCOMP Assertion Time

—

100

—

JCOMP Setup Time to TCK Low

TCK Falling Edge to Output Valid

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Table 36. JTAG pin AC electrical characteristics (continued)

Min.

Value

Max.

Value

Symbol

t_BSDVZ

Characteristic

Unit

TCK Falling Edge to Output Valid out of High

Impedance

—

t_BSDHZ

t_BSDST

t_BSDHT

TCK Falling Edge to Output High Impedance

Boundary Scan Input Valid to TCK Rising Edge

—

TCK Rising Edge to Boundary Scan Input

Invalid

JTAG timing specified at V_DD= 1.14 V to 1.32 V, V_DDEH= 4.5 V to 5.25 V with multi-voltage pads programmed to

Low-Swing mode, T_A= T_Lto T_H,and C_L= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG

boundary scan only. See Table 37 for functional specifications.

TCK

Figure 9. JTAG test clock input timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

TCK

TMS, TDI

TDO

Figure 10. JTAG test access port timing

TCK

JCOMP

Figure 11. JTAG JCOMP timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

TCK

Output

Signals

Output

Signals

Input

Signals

Figure 12. JTAG boundary scan timing

4.16.2 Nexus timing

Table 37. Nexus debug port timing

Symbol

t_MCYC

t_MDC

Characteristic

MCKO Cycle Time

Min. Value Max. Value

Unit

2^2,3

100⁴

t_CYC

Absolute Minimum MCKO Cycle Time

MCKO Duty Cycle

—

0.2

—

t_MDOV

t_MSEOV

t_EVTOV

t_EVTIPW

MCKO Low to MDO Data Valid⁵

MCKO Low to MSEO Data Valid⁵

MCKO Low to EVTO Data Valid⁵

EVTI Pulse Width

– 0.1

0.1

t_MCYC

t_TCYC

t_MCYC

– 0.1

4.0

t_EVTOPWCC

EVTO Pulse Width

—

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Min. Value Max. Value Unit

Table 37. Nexus debug port timing (continued)

Symbol

t_TCYC

t_TDC

Characteristic

TCK Cycle Time

4^6,7

100⁸

—

t_CYC

Absolute Minimum TCK Cycle Time

TCK Duty Cycle

t_NTDIS

t_NTDIH

t_NTMSS

t_NTMSH

t_JOV

TDI Data Setup Time

TDI Data Hold Time

TMS Data Setup Time

TMS Data Hold Time

TCK Low to TDO Data Valid

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing

specified at V_DD= 1.14 V to 1.32 V, V_DDEH= 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing

mode, T_A= TL to TH, and CL = 30 pF with DSC = 0b10.

Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum

setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the

Absolute minimum MCKO period specification.

This may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending

on the actual system frequency being used.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that

is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system

frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the

Absolute minimum TCK period specification.

This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability

of the design (system frequency / 4) depending on the actual system frequency being used.

MCKO

MDO

MSEO

EVTO

Output Data Valid

Figure 13. Nexus output timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

TCK

EVTI

EVTO

Figure 14. Nexus event trigger and test clock timings

TCK

TMS, TDI

TDO

Figure 15. Nexus TDI, TMS, TDO timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.16.3 Calibration bus interface timing

Table 38. Calibration bus operation timing

66 MHz (ext. bus)²

Symbol

Characteristic

Unit

Notes

Min

Max

T_C

CLKOUT Period

15.2

—

ns Signals are

measured at 50%

V_DDE

t_CDCCC

t_CRTCC

t_CFTCC

t_COHCC

CLKOUT duty cycle

CLKOUT rise time

CLKOUT fall time

45%

—

55%

T_C

—

CLKOUT Posedge to Output Signal

Invalid or High Z(Hold Time)

1.0⁴/1.5

—

ns Hold time selectable

via

SIU_ECCR[EBTS]

bit:

EBTS=0: 1.0ns

EBTS=1: 1.5ns

ADDR[8:31]

CS[0:3]

DATA[0:31]

RD_WR

WE[0:3]/BE[0:3]

t_COVCC

CLKOUT Posedge to Output Signal Valid

(Output Delay)

—

6.0⁴/7.0

ns Output valid time

selectable via

SIU_ECCR[EBTS]

bit:

ADDR[8:31]

CS[0:3]

DATA[0:31]

EBTS=0: 5.5ns

EBTS=1: 6.5ns

RD_WR

WE[0:3]/BE[0:3]

t_CISCC

t_CIHCC

t_APWCC

Input Signal Valid to CLKOUT Posedge

(Setup Time)

5.0

1.0

—

DATA[0:31]

CLKOUT Posedge to Input Signal Invalid

(Hold Time)

DATA[0:31]

ALE Pulse Width⁵

6.5

—

10 t_AAICC

ALE Negated to Address Invalid⁵

Calibration bus timing specified at f_SYS= 80 MHz, V_DD= 1.14 V to 1.32 V, V_DDE= 1.62 V to 3.6 V (unless stated

otherwise), T_A= T_Lto T_H, and C_L= 30 pF with DSC = 0b10.

The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz.

Refer to Fast Pad timing in Table 34 and Table 35 (different values for 3.3 V vs. 1.8 V).

The EBTS=0 timings are only valid/ tested at V_DDE=2.25–3.6 V, whereas EBTS=1 timings are valid/tested at

1.6–3.6 V.

Measured at 50% of ALE.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

Voh_f

VDDE/2

Vol_f

CLKOUT

Figure 16. CLKOUT timing

VDDE/2

CLKOUT

VDDE/2

OUTPUT

BUS

VDDE/2

OUTPUT

SIGNAL

VDDE/2

OUTPUT

SIGNAL

VDDE/2

Figure 17. Synchronous output timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

CLKOUT

VDDE/2

INPUT

BUS

VDDE/2

INPUT

SIGNAL

VDDE/2

Figure 18. Synchronous input timing

ipg_clk

CLKOUT

ALE

A/D

DATA

ADDR

Figure 19. ALE signal timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

4.16.4 eMIOS timing

Table 39. eMIOS timing

Characteristic

Min.

Value

Max.

Value

Symbol

Unit

t_MIPW

eMIOS Input Pulse Width

eMIOS Output Pulse Width

—

t_CYC

t_MOPW

eMIOS timing specified at f_SYS= 80 MHz, V_DD= 1.14 V to 1.32 V, V_DDEH= 4.5 V to 5.25 V, T_A= T_Lto T_H, and C_L

= 50 pF with SRC = 0b00.

4.16.5 DSPI timing

1,2

Table 40. DSPI timing

40 MHz

60 MHz

80 MHz

Symbol

Characteristic

Unit

Min.

Max.

Min.

Max.

Min.

Max.

t_SCK

SCK Cycle Time^3,4

PCS to SCK Delay⁵

After SCK Delay⁶

SCK Duty Cycle

48.8 ns 5.8 ms 28.4 ns 3.5 ms 24.4 ns 2.9 ms

—

t_CSC

t_ASC

t_SDC

—

(½t_SC) – (½t_SC) + (½t_SC) – (½t_SC) + (½t_SC) – (½t_SC) +

t_A

Slave Access Time

(SS active to SOUT

driven)

—

t_DIS

Slave SOUT Disable

Time

—

(SS inactive to SOUT

High-Z or invalid)

t_PCSC

t_PASC

t_SUI

PCSx to PCSS time

PCSS to PCSx time

—

Data Setup Time for Inputs

Master (MTFE = 0)

Slave

—

Master (MTFE = 1,

CPHA = 0)⁷

–4

Master (MTFE = 1,

CPHA = 1)

—

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

1,2

Table 40. DSPI timing (continued)

40 MHz 60 MHz

80 MHz

Unit

Symbol

Characteristic

Min.

Max.

Min.

Max.

Min.

Max.

t_HI

t_SUO

t_HO

Data Hold Time for Inputs

Master (MTFE = 0)

Slave

–4

—

–4

—

–4

—

Master (MTFE = 1,

CPHA = 0)⁷

Master (MTFE = 1,

CPHA = 1)

–4

—

–4

—

–4

—

Data Valid (after SCK edge)

Master (MTFE = 0)

Slave

—

Master (MTFE = 1,

CPHA=0)

Master (MTFE = 1,

CPHA=1)

—

Data Hold Time for Outputs

Master (MTFE = 0)

Slave

–5

5.5

—

–5

5.5

—

–5

5.5

—

Master (MTFE = 1,

CPHA = 0)

Master (MTFE = 1,

CPHA = 1)

–5

—

–5

—

–5

—

All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad

types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25

V, TA = TL to TH, and CL = 50 pF with SRC = 0b11.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency

modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 62 MHz parts allow for a 60 MHz system

clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are

calculated based on two MPC5634M devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

Electrical characteristics

These numbers

reference Table 40.

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Last Data

SIN

First Data

Data

First Data

Last Data

SOUT

Figure 20. DSPI classic SPI timing – master, CPHA = 0

These numbers

reference Table 40.

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Data

First Data

Last Data

SIN

SOUT

Last Data

First Data

Figure 21. DSPI classic SPI timing – master, CPHA = 1

MPC5634M Microcontroller Data Sheet, Rev. 9

100

Freescale Semiconductor

Electrical characteristics

These numbers

reference Table 40.

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

Data

First Data

Last Data

SOUT

SIN

Data

Last Data

First Data

Figure 22. DSPI classic SPI timing – slave, CPHA = 0

These numbers

reference Table 40.

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

Last Data

Data

SOUT

SIN

First Data

Last Data

First Data

Figure 23. DSPI classic SPI timing – slave, CPHA = 1

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

101

Electrical characteristics

These numbers

reference Table 40.

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

First Data

Last Data

Data

SOUT

First Data

Data

Figure 24. DSPI modified transfer format timing – master, CPHA = 0

These numbers

reference Table 40.

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

Last Data

First Data

Data

First Data

Last Data

SOUT

Figure 25. DSPI modified transfer format timing – master, CPHA = 1

MPC5634M Microcontroller Data Sheet, Rev. 9

102

Freescale Semiconductor

Electrical characteristics

These numbers

reference Table 40.

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

First Data

Data

Last Data

SOUT

SIN

Last Data

First Data

Figure 26. DSPI modified transfer format timing – slave, CPHA =0

These numbers

reference Table 40.

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

Last Data

First Data

Data

SOUT

SIN

First Data

Last Data

Figure 27. DSPI modified transfer format timing – slave, CPHA =1

PCSS

PCSx

Figure 28. DSPI PCS strobe (PCSS) timing

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

103

Electrical characteristics

4.16.6 eQADC SSI timing

Table 41. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)

CLOAD = 25pF on all outputs. Pad drive strength set to maximum.

Symbol

Rating

Min

Typ

Max

Unit

f_FCKCC

t_FCKCC

t_FCKHTCC

t_FCKLTCC

t_{SDS_LL}CC

t_{SDO_LL}CC

t_DVFECC

FCK Frequency ^{2, 3}

1/17 f_{SYS_CLK}

2 t_{SYS_CLK}

t_{SYS_CLK} 6.5

–7.5

12 f_{SYS_CLK}

17t_{SYS_CLK}

_9*t_{SYS_CLK} 6.5

_8*t_{SYS_CLK} 6.5

+7.5

Hertz

seconds

FCK Period (t_FCK= 1/ f_FCK

Clock (FCK) High Time

Clock (FCK) Low Time

SDS Lead/Lag Time

SDO Lead/Lag Time

)

–7.5

+7.5

Data Valid from FCK Falling Edge

(t_FCKLT+t_{SDO_LL}

)

t_{EQ SU}CC

eQADC Data Setup Time (Inputs)

eQADC Data Hold Time (Inputs)

t_{EQ_HO}CC

SS timing specified at f_SYS= 80 MHz, V_DD= 1.14 V to 1.32 V, V_DDEH= 4.5 V to 5.25 V, T_A= T_Lto T_H, and C_L= 50 pF

with SRC = 0b00.

Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.

FCK duty is not 50% when it is generated through the division of the system clock by an odd number.

FCK

SDS

25th

1st (MSB)

2nd

26th

SDO

External Device Data Sample at

FCK Falling Edge

1st (MSB)

2nd

25th

26th

SDI

eQADC Data Sample at

FCK Rising Edge

Figure 29. eQADC SSI timing

MPC5634M Microcontroller Data Sheet, Rev. 9

104

Freescale Semiconductor

Packages

5.1

5.1.1

Package mechanical data

144 LQFP

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

105

Packages

Figure 30. 144 LQFP package mechanical drawing (part 1)

MPC5634M Microcontroller Data Sheet, Rev. 9

106

Freescale Semiconductor

Packages

Figure 31. 144 LQFP package mechanical drawing (part 2)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

107

Packages

Figure 32. 144 LQFP package mechanical drawing (part 3)

MPC5634M Microcontroller Data Sheet, Rev. 9

108

Freescale Semiconductor

Packages

5.1.2

176 LQFP

176

Figure 33. 176 LQFP package mechanical drawing (part 1)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

109

Packages

Figure 34. 176 LQFP package mechanical drawing (part 2)

MPC5634M Microcontroller Data Sheet, Rev. 9

110

Freescale Semiconductor

Packages

Figure 35. 176 LQFP package mechanical drawing (part 3)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

111

Packages

5.1.3

208 MAPBGA

Figure 36. 208 MAPBGA package mechanical drawing (part 1)

MPC5634M Microcontroller Data Sheet, Rev. 9

112

Freescale Semiconductor

Packages

Figure 37. 208 MAPBGA package mechanical drawing (part 2)

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

113

Ordering information

Table 42 shows the orderable part numbers for the MPC5634M series.

Table 42. Orderable part number summary

Flash/SRAM

(Kbytes)

Speed

(MHz)

Part Number

Package

SPC5632MF2MLQ60

SPC5632MF2MLQ40

SPC5633MF2MMG80

SPC5633MF2MLU80

SPC5633MF2MLQ80

SPC5633MF2MMG60

SPC5633MF2MLU60

SPC5633MF2MLQ60

SPC5633MF2MLQ40

SPC5634MF2MMG80

SPC5634MF2MLU80

SPC5634MF2MLQ80

SPC5634MF2MMG60

SPC5634MF2MLU60

SPC5634MF2MLQ60

SPC563M60L3CPBY

SPC563M60L3CPAY

768 / 48

144 LQFP Pb-free

208 MAPBGA Pb-free

176 LQFP Pb-free

144 LQFP Pb-free

208 MAPBGA Pb-free

176 LQFP Pb-free

144 LQFP Pb-free

208 MAPBGA Pb-free

176 LQFP Pb-free

144 LQFP Pb-free

208 MAPBGA Pb-free

176 LQFP Pb-free

144 LQFP Pb-free

1024 / 64

1536 / 94

MPC5634M Microcontroller Data Sheet, Rev. 9

114

Freescale Semiconductor

Ordering information

Example code:

Qualification Status

Power Architecture Core

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Fab/Mask rev.

Temperature Spec.

Package Code

Maximum Frequency

Tape and Reel

Package Code

Flash Size (z3 core)

2 = 768 KB

3 = 1 MB

Qualification Status

LQ = 144 LQFP

LU = 176 LQFP

MG = 208 MAPBGA

M = MC status

S = Auto qualified

P = PC status

4 = 1.5 MB

Automotive Platform

56 = Power Architecture in 90 nm

57 = Power Architecture in 55 nm

Maximum Frequency

40 = 40 MHz

60 = 60 MHz

Product Family

M = MPC5634M

80 = 80 MHz

Fab/Mask rev.

F2 = ATMC Rev. 2

Core Version

3 = e200z3

Temperature Spec.

M = –40 °C to 150 °C

Figure 38. Commercial product code structure

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

115

Document revision history

Table 43 summarizes revisions to this document.

Table 43. Revision history

Description of Changes

Revision

Date

Rev. 1

Rev. 2

4/2008

Initial release

12/2008

• Maximum amount of flash increased from 1 MB to 1.5 MB. Flash memory type has

changed. Rev. 1 and later devices use LC flash instead of FL flash.

• Additional packages offered—now includes100 LQFP and 176 LQFP. Please note that

the pinouts can vary for the same package depending on the amount of flash memory

included in the device.

• Device comparison table added.

• Feature details section added

• Signal summary table expanded. Now includes PCR register numbers and signal

selection values and pin numbers for all production packages.

• Electrical characteristics updated.

• DSPI timing data added for 40 MHz and 60 MHz.

• Thermal characteristics data updated. Data added for 100- and 176-pin packages.

• DSPI LVDS pad specifications added.

Rev. 3

2/2009

Electrical characteristics updated

• Flash memory electrical characteristics updated for LC flash

• Power management control (PMC) and Power on Reset (POR) specifications updated

• EMI characteristics data added

• Maximum ratings updated

• I/O pad current specifications updated

• I/O Pad VRC33 current specifications added

• Temperature sensor electrical characteristics added

Pad type added to “Voltage” column of signal summary table

Many signal names have changed to make them more understandable

• DSPI: PCS_C[n] is now DSPI_C_PCS[n]; SOUT_C is now DSPI_C_SOUT, SIN_C is

now DSPI_C_SIN, and SCK_C is now DSPI_C_SCK

• CAN: CNTXB is now CAN_B_TX and CNRXB is now CAN_B_RC

• SCI: RXDB is now SCI_B_RX and TXDB is now SCI_B_TX

• In cases where multiple instances of the same IP block is incorporated into the device,

e.g., 2 SCI blocks, the above nomenclature applies to all blocks

“No connect” pins on pinouts clarified

• Pins labelled “NIC” have no internal connection and should be tied to ground

• Pins labelled “NC” are not functional pins but may be connected to internal circuits

They are to be left floating

Some of the longer multiplexed signal names appearing on pinouts have been moved to

the inside of the package body to avoid having to use smaller fonts

Orderable parts table updated

Part number decoder added

MPC5634M Microcontroller Data Sheet, Rev. 9

116

Freescale Semiconductor

Document revision history

Table 43. Revision history (continued)

Description of Changes

Revision

Date

Rev.4

12/2009

208-pin MAPBGA ballmap for the MPC5633M (1024 KB flash memory) has changed.

Power Management Control (PMC) and Power On Reset (POR) electrical specifications

updated

Temperature sensor data added

Specifications now indicate how each controller characteristic parameter is guaranteed.

I/O pad current specifications updated

I/O Pad VRC33 current specifications updated

PAD AC characteristics updated

VGA gain specifications added to eQADC electrical characteristics

DC electrical specifications updated:

• Footnote added to RPUPD100K and RPUPD200K: When the pull-up and pull-down of

the same nominal 200 K or 100 K value are both enabled, assuming no

interference from other devices, the resulting pad voltage will be 0.5*VDDE ± 2.5%

• I_OLcondition added to V_{OL_LS}

• I_OHcondition added to V_{OH_LS}

• Minimum V_{OH_LS}is 2.3 V (was 2.7 V).

• Separate I_DDPLLremoved from I_DDspec because we can only measure I_DD+ I_DDPLL

I_DDincreased by 15 mA (to 195 mA) to account for I_DDPLL. I_DDnow documented as

I_DD+ I_DDPLL. Footnote added detailing runtime configuration used to measure

I_DD+ I_DDPLL

• Specifications for I_DDSTBYand I_DDSTBY150reformatted to make more clear.

• V_STBYis now specified by two ranges. The area in between those ranges is

indeterminate.

LVDS pad specifications updated:

• Min value for V_ODat SRC=0b01 is 90 mV (was 120); and 160 mV (was 180) at

SRC = 0b10

Changes to Signal Properties table:

• VDDE7 removed as voltage segment from Calibration bus pins. Calibration bus pins

are powered by VDDE12 only.

• GPIO[139] and GPIO[87] pins changed to Medium pads

• Some signal names have changed on 176-pin QFP package pinout: “CAL_x” signals

renamed to “ALT_x”.

Changes to Pad Types table:

• Column heading changed from “Voltage” to “Supply Voltage”

• MultiV pad high swing mode voltage changed to 3.0 V – 5.25 V (was 4.5 V – 5.25 V)

• MultiV pad low swing mode voltage changed to 4.5 V – 5.25 V (was 3.0 V – 3.6 V)

Signal details table added

Power/ground segmentation table added

100-pin package is no longer available

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

117

Document revision history

Table 43. Revision history (continued)

Description of Changes

Revision

Date

Rev. 5

04/2010

Updates to features list:

• MMU is 16-entry (previously noted as 8-entry)

• ECSM features include single-bit error correction reporting

• eTPU2 is object code compatible with previous eTPU versions

Updates to feature details:

• Programming feature: eTPU2 channel flags can be tested

Pinout/ballmap changes:

144 pin LQFP package:

• Pin 46 is now VDDEH1B (was VDDEH4A)

• Pin 61 is now VDDEH6A (was VDDEH4B)

176 pin LQFP package (1.5M devices)

• Pin 55 is now VDDEH1B (was VDDEH4A)

• Pin 74 is now VDDEH6A (was VDDEH4B)

176 pin LQFP package (1.5M devices)

• Pin 55 is now VDDEH1B (was VDDEH4A)

• Pin 74 is now VDDEH6A (was VDDEH4B)

208 ball BGA package (all devices)

Ball N9 changed to VDDEH1/6 (was VDDEH6). In a future revision of the device this may

be changed to NC (no connect).

Changes to calibration ball names on devices with 1 MB flash memory:

• CAL_MDO0 changed to ALT_MDO0

• CAL_MDO1 changed to ALT_MDO1

• CAL_MDO2 changed to ALT_MDO2

• CAL_MDO3 changed to ALT_MDO3

• CAL_MSEO0 changed to ALT_MSEO0

• CAL_MSEO1 changed to ALT_MSEO1

• CAL_EVTI changed to ALT_EVTI

• CAL_EVTO changed to ALT_EVTO

• CAL_MCKO changed to ALT_MCKO

Power/ground segment changes:

• The following pins are on VDDE7 I/O segment only on the 208-ball BGA package:

ALT_MDO[0:3], ALT_MSEO[0:1], ALT_EVTI, ALT_EVTO, ALT_MCKO.

• Power segments VDDEH4, VDDEH4A and VDDEH4B have been removed.

CLKOUT power segment is VDDE5 (was VDDE12)

Thermal characteristics for 176-pin LQFP updated (all parameter values)

MPC5634M Microcontroller Data Sheet, Rev. 9

118

Freescale Semiconductor

Document revision history

Table 43. Revision history (continued)

Description of Changes

Revision

Date

Rev. 5

(cont.)

04/2010

PMC Operating conditions and external regulators supply voltage specifications updated

• (2) PMC 5 V supply voltage VDDREG min value is 4.5 V (was 4.75 V)

PMC electrical characteristics specifications updated

• (1d) Bandgap reference supply voltage variation is 3000 ppm/V (was 1500 ppm/V)

• (5a) Nominal 3.3 V supply internal regulator DC output voltage variation at power-on

reset min value is Vdd33-8.5% (was unspecified previously)

• (5a) Nominal 3.3 V supply internal regulator DC output voltage variation at power-on

reset max value is Vdd3+7% (was unspecified previously)

• (9a) Variation of POR for rising 5 V VDDREG supply max value is Por5V_r + 50% (was

Por5V_r + 35%)

• (9c) Variation of POR for falling 5 V VDDREG supply max value is Por5V_f + 50% (was

Por5V_f + 35%)

• (9c) note added: Minimum loading (<10 mA) for reading trim values from flash,

powering internal RC oscillator, and IO consumption during POR.

“Core Voltage Regulator Controller External Components Preferred Configuration” circuit

diagram updated

Changes to DC Electrical Specifications:

• Footnote added to V_DDE. V_DDEmust be less than V_RC33or there is additional leakage

on pins supplied by V_DDE

• Low range SRAM standby voltage (V_STBY) minimum changed to 0.95 V (was 0.9 V)

• Low range SRAM standby voltage (V_STBY) maximum changed to 1.2 V (was 1.3 V)

• High range SRAM standby voltage (V_STBY) minimum changed to 2.0 V (was 2.5 V)

• V_{IL_LS}max value (Hysteresis disabled) changed to 0.9 V (was 1.1 V)

• V_{OH_LS}min value changed to 2 V (was 2.3 V)

• I_DDSLOWmax value is 50 mA

• I_DDSTOPmax value is 50 mA

• I_DDAmax value is 30 mA (was 15.0 mA)

• I_DD4and V_DDEH4removed—they no longer exist

I/O pad average I_DDEspecifications table updated

I/O pad V_RC33average I_DDEspecifications table updated

LVDS pad specifications table updated

• V_OSmin value is 0.9 V (was 1.075 V)

• V_OSmax value is 1.6 V (was 1.325 V)

Updates to PLLMRFM electrical specifications:

• Maximum values for XTAL load capacitance added. The maximum value varies with

frequency.

• For a 20 MHz crystal the maximum load should be 17 pF.

Temperature sensor accuracy is ±10 °C (was ±5 °C)

Updates to eQADC conversion specifications (operating):

• Offset error without calibration max value is 160 (was 100)

• Full scale gain error without calibration min value is –160 (was –120)

Changes to Platform flash controller electrical characteristics:

• APC, RWSC, WWSC settings vs. frequency of operation table updated

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

119

Document revision history

Table 43. Revision history (continued)

Description of Changes

Revision

Date

Rev. 5

(cont.)

04/2010

Changes to flash memory specifications:

• T_BKPRG64 KB specification removed (not present in this device)

• T_64kpperasespecification added

• Flash module life P/E spec for 32 Kbyte blocks also applies to 64 Kbyte blocks

Pad AC specifications (3.3 V) table updated

Rev. 6

04/2010

“Core Voltage Regulator Controller External Components Preferred Configuration” circuit

diagram updated.

• Clarification added to note: Emitter and collector capacitors (6.8 F and 10 F) should

be matched (same type) and ESR should be lower than 200 mW. (Added emphasis

that only 6.8 F emitter capacitors need to be matched with collector capacitor.

• 220 F emitter capacitors changed to 220 nF.

Rev. 7

Rev. 8

4/2010

No specification or product information changes:

• Mechanical outline drawings section renamed to “Packages” and restructured.

•

01/2011

Removed the 208 BGA package from the device-summary table.

Revised the “PMC Operating conditions and external regulators supply voltage” table.

Revised the “PMC electrical characteristics” table.

Revised the pad AC specifications.

Revised the “DC electrical specifications” table.

Revised the “DSPI LVDS pad specification” table:

Revised the “PLLMRFM electrical specifications” table.

Change to “Temperature sensor electrical characteristics” table:

• Accuracy is guaranteed by production test

Revised the “eQADC conversion specifications (operating)” table.

Changes to “Calibration bus operation timing“ table:

• CLKOUT period is guaranteed by production test. All other parameters are guaranteed

by design

Changes to “Program and erase specifications“ table in “Flash memory electrical

characteristics” section.

• Deleted Bank Program (512KB) (T_BKPRG) parameter

• TYP P/E values added for 32- and 64 KB blocks and for 128 KB blocks.

Changes to Recommended operating characteristics for external power transistor:

• VCESAT should be between 200 and 600 mV

• VBE should be 0.4V to 1.0V

Removed footnote 8 from Vddeh in Maximum ratings.

Deleted engineering names for pads in Power UP/DOWN Sequencing Section

Changed “sin_c” to DSPI_C_SIN” and “sck_c” to DSPI_C_SCK” on 144 pin LQFP

package.

Updated the “Electromagnetic Interference Characteristics” table to reflect new parameter

levels, test conditions.

In the “APC, RWSC, WWSC settings vs. frequency of operation” table, changed 82 MHz

entry for WWC from “11” to “01”, added an extra row for “All 111 111 11”

MPC5634M Microcontroller Data Sheet, Rev. 9

120

Freescale Semiconductor

Document revision history

Table 43. Revision history (continued)

Revision

Date

Description of Changes

Rev 9

05/2012

In Section 4.6.1, “Regulator example

• Updated ,Figure 7 “Core voltage regulator controller external components preferred

configuration” to show R_C, R_B, R_E, C_C, C_B, C_E, C_Dand C_REG

• Added Table 15 “Required external PMC component values”, Table 16 “Network 1

component values”, Table 17 “Network 2 component values” and Table 18 “Network 3

component values”.

Updated Table 1:

Number of eMIOS channels changed from ‘8’ to ‘16’ for MPC5632M.

In Section 4.2, “Maximum ratings, Table 7

• V_FLASHmaximum value changed from 3.6V to 5.5V and changed table note3 to:

“The V_FLASHsupply is connected to V_DDEH

”

• Removed table note 4, “Allowed 5.3 V for 10 hours cumulative time, remaining time at

3.3 V +10%”

In Section 4.12, “eQADC electrical characteristics:

• Added note.

• In Table 29, additional five parameters added (SNR, THD, SFDR, SINAD and ENOB)

and added footnotes # 9,10 and 11.

MPC5634M Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor

121

Document revision history

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Rev. 9

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