935319753557 [NXP]
Power Supply Management Circuit;
| 型号： | 935319753557 |
| 厂家： | 
NXP |
| 描述： | Power Supply Management Circuit |
| 文件： | 总159页 (文件大小：10075K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC34708
Rev. 11.0, 11/2013
escale Semiconductor
Technical Data
Power Management Integrated
Circuit (PMIC) for i.MX50/53
Families
34708
The MC34708 is the Power Management Integrated Circuit (PMIC)
designed specifically for use with the Freescale i.MX50 and i.MX53
families. This device is powered by SMARTMOS technology.
POWER MANAGEMENT
Features
• Six multi-mode buck regulators for direct supply of the processor
core, memory, and peripherals
• Boost regulator for USB OTG support
• Eight regulators with internal and external pass devices for thermal
budget optimization
VK SUFFIX (PB-FREE)
VM SUFFIX (PB-FREE)
98ASA00299D
98ASA00312D
206 MAPBGA
206 MAPBGA
• USB/UART/Audio switching for mini-micro USB connector
• 10-bit ADC for monitoring battery and other inputs
• Real time clock and crystal oscillator circuitry with coin cell backup/
charger
8.0 X 8.0 (0.5 MM PITCH) 13.0 X 13.0 (0.8 MM PITCH)
Applications
• SPI/I2C bus for control and register interface
Tablets
Smart Mobile Devices
Portable Navigation Devices
ꢒꢓꢎꢔꢕꢖꢇꢗ
ꢀꢌꢱꢉꢊꢌ
ꢀꢁꢄꢁ
ꢖꢖꢗ
ꢖꢈꢉꢊꢉꢟ
ꢂꢟꢔꢠꢙꢚꢉꢌꢡꢉꢊꢙ
ꢅꢆꢇꢈ
ꢋꢘꢙꢅꢐ
ꢚꢀ
ꢋꢌꢌꢍꢎꢏꢄꢐꢑꢃꢍꢍꢐꢄ
ꢥꢖꢣ
ꢅꢌꢈꢌ
ꢅꢘꢙꢚꢍꢌꢛ
ꢕꢘꢤꢒꢗꢋꢚꢔꢈ
ꢁꢔꢠꢘꢟꢒ
ꢂꢘꢋꢉꢒꢘꢋꢝꢟꢔꢈ
ꢥꢁꢆꢐ
ꢖꢈꢉꢊꢉꢟ
ꢜꢟꢢꢉꢊ
ꢎꢉꢌꢠꢚꢎꢟꢋꢉꢙ
ꢖꢜꢗꢝꢗꢞꢀ
ꢥꢖꢣ
ꢗꢝꢓ
ꢥꢖꢣꢒꢖꢢꢘꢈꢤꢎ
ꢃꢇꢈꢉꢊꢋꢌꢍ
ꢀꢎꢌꢊꢏꢉꢊ
ꢜꢟꢢꢉꢊ
ꢇꢀꢛꢜꢝꢞꢟ
ꢏꢐꢠꢃꢄꢎꢇꢡꢂꢢ
ꢚꢀ
ꢂꢘꢒꢗꢟꢋꢒꢣꢌꢈꢈꢉꢊꢛ
ꢯꢉꢋꢉꢊꢌꢍꢒꢜꢔꢊꢚꢟꢙꢉ
ꢂꢃꢅꢒꢅꢊꢘꢰꢉꢊ
ꢐꢟꢔꢤꢎ
ꢖꢤꢊꢉꢉꢋ
ꢀꢟꢘꢋꢒꢀꢉꢍꢍ
ꢣꢌꢈꢈꢉꢊꢛ
ꢦꢞ
ꢀꢁꢂꢃꢄꢅꢁꢆ
ꢦ
ꢦꢦ
ꢪ
ꢞ
ꢦꢭ
ꢨ
ꢩ
ꢮ
ꢫ
ꢬ
ꢧ
ꢆꢐꢀ
Figure 1. MC34708 Simplified Application Diagram
There are no disclaimers required on the Final publication of a data sheet.
© Freescale Semiconductor, Inc., 2011-2013. All rights reserved.
Table of Contents
1
2
Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Format and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Simplified Internal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
4
5
5.2.1
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3.2
5.3.3
General PMIC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 Startup Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Bias and References Block Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3 Clocking and Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.1
7.3.2
7.3.3
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SRTC Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Coin Cell Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.1
7.4.2
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupt Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Buck Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Boost Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Linear Regulators (LDOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.6 Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.7 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Dedicated Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Touch Screen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.8 Auxiliary Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.8.1
7.8.2
7.8.3
7.8.4
General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
General Purpose LED Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Mini/Micro USB Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
7.9 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.9.1
7.9.2
7.9.3
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SPI/I2C Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.10 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.10.1 Register Set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.10.2 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.10.3 SPI/I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.10.4 SPI Register’s Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.3 MC34708 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
General Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Parallel Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Differential Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Switching Regulator Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
8.4 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.4.1
8.4.2
Rating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Estimation of Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9
Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.1 206-pin MAPBGA (8 x 8), 0.5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.2 206-pin MAPBGA (13 x 13), 0.8 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10 Reference Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
MC34708
Analog Integrated Circuit Device Data
3
Freescale Semiconductor
Orderable Parts
1
Orderable Parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are
provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part
number search for the following device numbers.
Table 1. Orderable Part Variations
Part Number (1)
MC34708VK
Temperature (T )
Package
A
206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch
206 MAPBGA - 13 x 13 mm - 0.8 mm pitch
-40 to 85 °C
MC34708VM
Notes
1. To Order parts in Tape & Reel, add the R2 suffix to the part number.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
Part Identification
2
Part Identification
This section provides an explanation of the part numbers and their alpha numeric breakdown.
2.1
Description
Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to
determine the specific part you have received.
2.2
Format and Examples
Part numbers for a given device have the following format, followed by a device example:
Table 2 - Part Numbering - Analog:
MC tt xxx r v PP RR - MC34708VKR2
2.3
Fields
These tables list the possible values for each field in the part number (not all combinations are valid).
Table 2: Part Numbering - Analog
FIELD
MC
DESCRIPTION
VALUES
• MC- Qualified Standard
• PC- Prototype Device
Product Category
tt
xxx
r
Temperature Range
Product Number
Revision
• 34 = -40 °C to 105 °C
• Assigned by Marketing
• (default blank)
v
Variation
• (default blank)
PP
RR
Package Identifier
Tape and Reel Indicator
• Varies by package
• R2 = 13 inch reel hub size
MC34708
Analog Integrated Circuit Device Data
5
Freescale Semiconductor
Internal Block Diagram
3
Internal Block Diagram
3.1
Simplified Internal Diagram
SW1IN
SW1ALX
GNDSW1A
SW1FB
O/P
Drive
Input/Battery
Monitoring
General Purpose
LED Drivers
SW1
Dual Phase
GP
2000 mA
Buck
SW1CFG
SW1VSSSNS
LICELL, UID, Die Temp, GPO4
Voltage /
Current
GNDADC
SW1BLX
O/P
Sensing &
Translation
10 Bit GP
ADC
Drive
GNDSW1B
A/D Result
DVS
CONTROL
ADIN9
ADIN10
ADIN11
SW1PWGD
A/D
Control
SW2IN
SW2LX
GNDSW2
SW2FB
MUX
O/P
Drive
SW2
ADIN12/TSX1
ADIN13/TSX2
ADIN14/TSY1
ADIN15/TSY2
TSREF
LP
`
1000 mA
SW2PGD
Buck
Touch
Screen
Interface
Die Temp &
Thermal Warning
Detection
SW3IN
To Interrupt
Section
SW3
INT MEM
500 mA
Buck
O/P
Drive
SW3LX
GNDSW3
SW3FB
BPTHERM
NTCREF
SW4AIN
SW4ALX
GNDSW4A
SW4AFB
O/P
Drive
BATTISNSCCP
SW4
Dual Phase
DDR
BATTISNSCCN
CFP
SW4CFG
1000 mA
Buck
Package Pin Legend
SW4BIN
CFN
SW4BLX
GNDSW4B
SW4BFB
O/P
Drive
Output Pin
Input Pin
SPIVCC
Shift Register
Bi-directional Pin
CS
SPI
Interface
+
Muxed
I2C
Optional
Interface
SW5IN
CLK
SW5
I/O
1000 mA
Buck
O/P
Drive
SW5LX
GNDSW5
SW5FB
SPI
MOSI
MISO
To Enables & Control
Registers
GNDSPI
Shift Register
SWBSTIN
SWBSTLX
SWBSTFB
O/P
Drive
SWBST
380 mA
Boost
VALWAYS
VCORE
GNDSWBST
MC34708
VCOREDIG
VDDLP
Reference
Generation
VINREFDDR
VHALF
SPI Control
VCOREREF
GNDCORE
GNDREF
VREFDDR
10mA
VREFDDR
SPKR
SPKL
MIC
VINPLL
VPLL
VPLL
50 mA
Pass
FET
VUSB2DRV
VUSB2
TXD
RXD
Pass
FET
VUSB2
350mA
VBUS/ID
Detectors, Host
Auto detection
DPLUS
DMINUS
VDACDRV
VDAC
VDAC
250mA
UART Switches
Audio Switches
To
Trimmed
Circuits
DP
DM
SPI
Trim-In-Package
Control
Logic
VINGEN1
VGEN1
VGEN1
250mA
Pass
FET
GNDUSB
UID
VBUS
Startup
Sequencer
Decode
Trim?
OVP
Control
Logic
VGEN2DRV
VGEN2
PUMSx
PLL
Switchers
Pass
FET
VGEN2
250mA
VINUSB
VUSB
Monitor
Timer
VUSB
Regulator
RTC +
Calibration
32 KHz
Internal
Osc
LDOVDD
SPI Result
Registers
Interrupt
Inputs
Enables &
Control
32 KHz
Buffers
Best
of
Supply
GNDREG1
GNDREG2
GNDREF1
GNDREF2
BP
LCELL
Switch
LICELL
PWM
Outputs
32 KHz
Crystal
Osc
GPIO Control
Li Cell
Charger
Digital Core
VSRTC
Figure 2. Simplified Internal Block Diagram
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Pin Connections
4
Pin Connections
4.1
Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
C
D
TRICKLESEL
GNDACHRG
BATT
CFP
BP
VBUSVIN
CHRGLX
GNDCHRG
LEDVDD
LICELL
PWM1
GPIOVDD
PUMS4
AUXVIN
AUXVIN
VAUX
AUXVIN
AUXVIN
GOTG
PRETMR
SUBSANA3
GAUX
BPTHERM
NTCREF
SDWNB
INT
CFN
GBAT
VBUSVIN
VBUSVIN
VBUSVIN
BATTISNSP
BATTISNSN
GLBRST
MIC
CHRGLX
CHRGLX
GNDCHRG
GNDCHRG
GNDCHRG
SUBSPWR1
SUBSPWR1
SUBSPWR1
SUBSPWR1
SUBSPWR1
SUBSPWR1
SW1VSSSNS
CHRGLEDG
PWM2
GPIOLV1
GPIOLV3
GPIOLV2
GPIOLV0
GNDREF2
SW3FB
GNDGPIO
PUMS1
PUMS3
GNDSW2
SW2LX
PUMS2
GNDSW2
SW2LX
SUBSANA2
GNDSW2
SW2LX
CHRGFB
BPSNS
CHRGLX
ICTEST
PUMS5
E
F
RESETB
MISO
GNDCTRL
GNDSPI
CS
PWRON2
MOSI
BATTISNSCCN
BATTISNSCCP
ITRIC
CHRGLEDR
SW2FB
SW2IN
SW2IN
SW2IN
SPIVCC
RXD
RESETBMCU
TXD
SUBSPWR1
PWRON1
SUBSPWR1
SUBSPWR1
SUBSPWR1
GNDREF1
SWBSTIN
GNDSWBST
SWBSTFB
VPLL
SWBSTIN
GNDSWBST
CLK32K
GNDSW3
SW3LX
GNDSW3
SW3LX
G
H
J
CLK
VINUSB
UID
SW2PWGD
CLK32KMCU
VDACDRV
VHALF
VBUS
VUSB
VALWAYS
VDDLP
TSX1
SUBSREF
STANDBY
SUBSPWR1
TSY2
CLK32KVCC
VINPLL
SW3IN
SW3IN
DM
SPKR
VCOREDIG
VCORE
GNDUSB
TSY1
VSRTC
SWBSTLX
GNDRTC
LDOVDD
VUSB2DRV
VINGEN1
GNDSW1B
GNDSW1B
SWBSTLX
SUBSLDO
XTAL2
K
L
DP
SPKL
ADIN10
ADIN9
VGEN2
VDAC
GNDREG1
VUSB2
DPLUS
DMINUS
VCOREREF
TSREF
GNDCORE
GNDREF
GNDADC
GNDSW4A
SW4ALX
WDI
TSX2
ADIN11
SUBSPWR1
SW5FB
SW1CFG
SW1FB
VINREFDDR
SW1PWGD
SW1IN
GNDREG2
M
N
P
R
SW4CFG
VGEN1
XTAL1
GNDADC
GNDADC
SW4AIN
GNDADC
GNDADC
SW4BIN
SW5IN
SW5LX
SW5LX
SW5LX
GNDSW5
GNDSW5
GNDSW5
SW1IN
SW1IN
SW1IN
SUBSANA1
SW1BLX
SW1BLX
VGEN2DRV
VREFDDR
SW4BFB
SW4BLX
SW4AFB
SW5IN
GNDSW1A
GNDSW1A
SW1ALX
SW1ALX
GNDSW4B
SW5IN
Legend
LDOs
Switching Regulators
Control Logic
Misc
RTC
Ground
USB
ADC
SPI/I2C
No Connect
No Ball
Figure 3. Top View Ballmap
MC34708
Analog Integrated Circuit Device Data
7
Freescale Semiconductor
Pin Connections
4.2
Pin Definitions
Table 3. MC34708 Pin Definitions
Pin
Pin Number
Pin Name
Definition
Function
Charger (Function no longer supported on MC34708)
Charger Not supported.
A7, B7, C7,
D7
VBUSVIN
AUXVIN
VAUX
NC
NC
NC
No Connect
Charger Not supported.
No Connect
B1, B2, C1,
C2
Charger Not supported.
No Connect
D1
Charger Not supported.
No Connect
A8, B8, C8,
D8
CHRGLX
CHRGFB
GOTG
NC
I
Connect to BATT pin
C5
D2
Charger Not supported.
No Connect
NC
Charger Not supported.
No Connect
D3
GAUX
NC
I
BP sense point
C6
A6
BPSNS
1. Application supply point
2. Input supply to the IC core circuitry
3. Application supply voltage sense
BP
I
Connect to GND
B6
E8
GBAT
ITRIC
O
Charger Not supported.
No Connect
NC
Battery current sensing point.(Optional)
E7
F7
A4
BATTISNSP
BATTISNSN
I
I
If required, connect a 20 m sense resistor between BATTISNSP and BATTISNSN
Battery current sensing point (Optional)
If required, connect a 20 m sense resistor between BATTISNSP and BATTISNSN
1. Battery positive terminal
2. Battery current sensing point 2
3. Battery supply voltage sense
BATT
I
Coulomb counter Not supported.
No Connect
F6
E6
BATTISNSCCP
BATTISNSCCN
NC
NC
Coulomb counter Not supported.
No Connect
Connect to VCOREDIG
Connect to Ground
A2
B3
A5
TRICKLESEL
PRETMR
I
I
Coulomb Counter Not supported.
No Connect
CFP
CFN
NC
NC
Coulomb Counter Not supported.
No Connect
B5
LED supply
A10
E10
LEDVDD
O
I
Red LED driver
CHRGLEDR
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
Pin Connections
Table 3. MC34708 Pin Definitions (continued)
Pin
Pin Number
Pin Name
Definition
Function
Green LED driver
Analog ground
B10
A3
CHRGLEDG
GNDACHRG
I
GND
A9, B9, C9,
D9
Ground
GNDCHRG
GND
Charger Not supported.
No Connect
C4
NTCREF
NC
I
Connect to Ground
B4
IC Core
K3
BPTHERM
Regulated supply for the IC analog core circuitry
Regulated supply for the IC digital core circuitry
Always on supply for internal core circuitry
Main bandgap reference
VCORE
VCOREDIG
VALWAYS
VCOREREF
VDDLP
O
O
J3
H4
O
N1
O
VDDLP reference
J4
O
Ground for the IC core circuitry
L2
GNDCORE
GNDREF
GND
GND
Ground reference for the IC core circuitry
M2
Switching Regulators
N11, N12,
SW1 input
SW1IN
I
P12, R12
P11, R11
M10
SW1A switch node connection
SW1 feedback
SW1ALX
SW1FB
O
I
Ground for SW1A
P10, R10
L9
GNDSW1A
SW1VSSSNS
SW1PWGD
SW1BLX
GND
GND
O
SW1 sense
Powergood signal for SW1
SW1B switch node connection
Ground for SW1B
M11
P13, R13
P14, R14
L10
O
GNDSW1B
SW1CFG
GND
I
SW1A/B mode configuration
E13, E14,
E15
SW2 input
SW2IN
I
D13, D14,
D15
SW2 switch node connection
SW2 feedback
SW2LX
SW2FB
O
I
E12
C13, C14,
C15
Ground for SW2
GNDSW2
GND
Powergood signal for SW2
SW3 input
G10
H14, H15
G14, G15
G11
SW2PWGD
SW3IN
O
I
SW3 switch node connection
SW3 feedback
SW3LX
O
SW3FB
I
Ground for SW3
F14, F15
F11
GNDSW3
GNDREF2
SW4AIN
GND
GND
I
Ground reference for switching regulators
SW4A input
R3
MC34708
Analog Integrated Circuit Device Data
9
Freescale Semiconductor
Pin Connections
Table 3. MC34708 Pin Definitions (continued)
Pin
Pin Number
Pin Name
Definition
Function
SW4A switch node connection
SW4A feedback
R2
SW4ALX
SW4AFB
GNDSW4A
SW4BIN
O
P6
I
Ground for SW4A
SW4B input
P2
R4
GND
I
SW4B switch node connection
SW4B feedback
R5
SW4BLX
SW4BFB
GNDSW4B
SW4CFG
SW5IN
O
P5
I
Ground for SW4B
SW4A/B mode configuration
SW5 input
R6
GND
M6
I
N7, P7, R7
N8, P8, R8
M7
I
SW5 output
SW5LX
O
SW5 feedback
SW5FB
I
GND
GND
I
Ground for SW5
N9, P9, R9
L8
GNDSW5
GNDREF1
SWBSTIN
SWBSTLX
SWBSTFB
GNDSWBST
Ground reference for Switching Regulators
Boost Regulator BP supply
F12, F13
J14, J15
H12
SWBST switch node connection
Boost Regulator feedback
O
I
Ground for boost Regulator
G12, G13
LDO Regulators
L11
GND
VREFDDR input supply
VINREFDDR
VREFDDR
VHALF
I
VREFDDR regulator output
Half supply reference for VREFDDR
VPLL input supply
P15
O
O
I
K10
J11
VINPLL
VPLL regulator output
J12
VPLL
O
O
O
Drive output for VDAC regulator using external PNP device
VDAC regulator output
J10
VDACDRV
VDAC
K12
Supply pin for VUSB2, VDAC, and VGEN2. Must always be connected to the same supply as
the PNP emitter. Recommended to use BP as the LDOVDD supply. See Figure 38 for a typical
connection diagram.
L14
LDOVDD
I
1. VUSB2 input using internal PMOS FET
2. Drive output for VUSB2 regulator using external PNP device
VUSB2 regulator output
M14
I
O
VUSB2DRV
L13
N14
M13
N15
VUSB2
VINGEN1
VGEN1
O
VGEN1 input supply
I
VGEN1 regulator output
O
1. VGEN2 input using internal PMOS FET
2. Drive output for VGEN2 regulator using external PNP device
VGEN2 regulator output
I
VGEN2DRV
O
K11
J13
K13
VGEN2
VSRTC
O
Output regulator for SRTC module on processor
Ground for regulators 1
O
GNDREG1
GND
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
Pin Connections
Table 3. MC34708 Pin Definitions (continued)
Pin
Pin Number
Pin Name
Definition
Function
Ground for regulators 2
Supply for GPIO
L12
A13
GNDREG2
GPIOVDD
GPIOLV0
GPIOLV1
GPIOLV2
GPIOLV3
PWM1
GND
I
General purpose input/output 0
General purpose input/output 1
General purpose input/output 2
General purpose input/output 3
PWM output 1
E11
I/O
I/O
I/O
I/O
O
B11
D11
C11
A12
PWM output 2
C10
PWM2
O
GPIO ground
B12
GNDGPIO
-
Control Logic
A11
1. Coin cell supply input
LICELL
I/O
2. Coin cell charger output
32.768 kHz Oscillator crystal connection 1
32.768 kHz Oscillator crystal connection 2
Ground for the RTC block
M15
L15
K14
H11
H13
H10
E1
XTAL1
XTAL2
I
I
GNDRTC
CLK32KVCC
CLK32K
CLK32KMCU
RESETB
RESETBMCU
WDI
GND
Supply voltage for 32 kHz buffer
32 kHz Clock output for peripherals
32 kHz Clock output for processor
Reset output for peripherals
Reset output for processor
I
O
O
O
F5
O
Watchdog input
L4
I
Standby input signal from processor
Interrupt to processor
J5
STANDBY
INT
I
E4
O
Power on/off button connection 1
Power on/off button connection 2
Global Reset
G8
PWRON1
PWRON2
GLBRST
PUMS1
PUMS2
PUMS3
PUMS4
PUMS5
ICTEST
GNDCTRL
SPIVCC
CS
I
E3
I
G7
I
Power up mode supply setting 1
Power up mode supply setting 2
Power up mode supply setting 3
Power up mode supply setting 4
Power up mode supply setting 5
C12
B14
B13
A14
D12
D10
E2
I
I
I
I
I
Connect to ground for normal mode operation.
Ground for control logic
I
GND
Supply for SPI bus
F4
I
I
Primary SPI select input
Primary SPI clock input
G2
G1
CLK
I
Primary SPI write input
F3
MOSI
I
Primary SPI read output
F1
MISO
O
MC34708
Analog Integrated Circuit Device Data
11
Freescale Semiconductor
Pin Connections
Table 3. MC34708 Pin Definitions (continued)
Pin
Pin Number
Pin Name
Definition
Function
Indication of imminent system shutdown
Ground for SPI interface
D4
SDWNB
GNDSPI
O
F2
GND
USB (2)
USB OTG transceiver cable ID
USB Ground
H3
UID
GNDUSB
DP
I/O
GND
I/O
I/O
I/O
I/O
O
L3
USB Data +
K1
USB Data –
J1
DM
Processor D+
Processor D-
L1
DPLUS
DMINUS
RXD
M1
UART Receive
UART Transmit
Mic output
G4
G5
TXD
I/O
O
H7
MIC
Speaker right
Speaker left
J2
SPKR
SPKL
VBUS
VUSB
VINUSB
I
K2
I
USB transceiver cable interface VBUS & OTG supply output
USB transceiver regulator output
H1
I/O
O
H2
Input option for VUSB; tie to SWBST at top level.
G3
I
A to D Converter
ADC generic input channel 9
K7
K6
L6
ADIN9
ADIN10
ADIN11
I
I
ADC generic input channel 10,
ADC generic input channel 11
I
Touch Screen Interface X1 or ADC generic input channel 12
Touch Screen Interface X2 or ADC generic input channel 13
Touch Screen Interface Y1 or ADC generic input channel 14
Touch Screen Interface Y2 or ADC generic input channel 15
Touch Screen Reference
K4
L5
J7
J6
P1
TSX1/ADIN12
TSX2/ADIN13
TSY1/ADIN14
TSY2/ADIN15
TSREF
I
I
I
I
O
N2, N3, N4,
P3, P4
Ground for ADC
GNDADC
GND
Thermal Grounds
Substrate ground connection for reference circuitry
H5
SUBSREF
GND
GND
E9, F8,F9,
L7, G9, H6,
H8, H9, J8,
J9, K8, K9
Substrate ground connection for power devices SW1, SW4, SW5
SUBSPWR1
K15
N13
B15
SUBSLDO
SUBSANA1
SUBSANA2
GND
GND
GND
Substrate ground connection for all LDOs
Substrate ground connection for analog circuitry of SW1, SW4, SW5
Substrate ground connection for analog circuitry of SW2, SW3, SWBST
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
Pin Connections
Table 3. MC34708 Pin Definitions (continued)
Pin
Pin Number
Pin Name
Definition
Function
C3
SUBSANA3
GND
Substrate ground connection for analog circuitry
Notes
2. In applications without USB support, leave all USB pins unconnected.
MC34708
Analog Integrated Circuit Device Data
13
Freescale Semiconductor
General Product Characteristics
5
General Product Characteristics
5.1
Maximum Ratings
Table 4. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
Description (Rating)
Max.
Unit
Notes
ELECTRICAL RATINGS
Input Supply Pins
• BATT, BP, BPSNS
• LICELL
V
VBATT, VBP
VLICELL
,
4.8
4.8
Input Sense Pins
V
• CHRGFB
7.5
5.5
• BATTISNSP, BATTISNSN
LED Drivers Pins
V
V
• CHRGLEDR, CHRGLEDG
7.5
IC Core Reference
• VCOREREF
• VCOREDIG, VDDLP
• VCORE
1.5
1.65
3.6
• VALWAYS
7.5
Switching Regulators Pins
• SWxIN, SWxLX, SWBSTFB
• SWxFB, SWxPWGD, SWxCFG
• SWBSTLX
V
V
5.5
3.6
7.5
LDO Regulator Pins
• VREFDDR, VHALF
1.5
2.5
3.6
4.8
5.5
• VPLL, VGEN1, VINGEN1, VSRTC
• VINREFDDR,VDAC, VUSB2, VGEN2,
• VINPLL, VDACDRV, VUSB2DRV, VGEN2DRV
• LDOVDD
GPIO Pins
V
V
• GPIOVDD, GPIOLVx, PWMx
2.5
Control Logic Pins
• ICTEST
1.8
2.5
3.6
•
XTAL1, XTAL2
• CLK32KVCC, CLK32K, CLK32KMCU, WDI, STANDBY,INT, PWRON1,
PWRON2, GLBRST, PUMSx, SPIVCC, CS, CLK, MOSI, MISO, SDWNB
Mini/Micro USB Interface Pins
V
V
• VBUS input sense pin
20
3.6
5.5
• VUSB
• UID, DP, DM, DPLUS, DMINUS, RXD, TXD, MIC, SPKR, SPKL, VINUSB
ADC Interface Pins
• ADINx, TSX1/ADIN12, TSX2/ADIN13, TSY1/ADIN14, TSY2/ADIN15, TSREF
4.8
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
General Product Characteristics
Table 4. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
Description (Rating)
Max.
Unit
Notes
V
VESD
ESD Ratings
• Human Body Model All pins
(3)
(3)
(4)
(4)
2000
500
• Charge Device Model All pins
15000
8000
• Air Gap Discharge Model for UID, VBUS, DP, and DM pins
• Human Body Model (HBM) for UID, VBUS, DP, and DM pins
Notes
3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
4. Need external ESD protection diode array to meet IEC1000-4-2 15000 V Air Gap discharge and 8000 V HBM requirements.
(CZAP = 150 pF, RZAP = 330 ohm).
5.2
Thermal Characteristics
Table 5. Thermal Ratings
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
THERMAL RATINGS
Ambient Operating Temperature Range
Operating Junction Temperature Range
-40
-40
-65
-
°C
°C
TA
TJ
85
125
(5)
Storage Temperature Range
°C
°C
TST
150
(6), (7)
Peak Package Reflow Temperature During Reflow
TPPRT
Note 7
8.0 X 8.0 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
(8), (9)
(8), (10)
(8), (10)
(8), (10)
Junction to Ambient Natural Convection
• Single layer board (1s)
-
93
53
80
49
RθJA
°C/W
°C/W
°C/W
°C/W
-
Junction to Ambient Natural Convection
• Four layer board (2s2p)
RθJMA
RθJMA
RθJMA
-
-
Junction to Ambient (@200 ft/min.)
• Single layer board (1s)
Junction to Ambient (@200 ft/min.)
• Four layer board (2s2p)
-
-
-
(11)
(12)
(13)
Junction to Board
Junction to Case
34
25
RθJB
RθJC
θJT
°C/W
°C/W
°C/W
Junction to Package Top
• Natural Convection
3.0
13 X 13 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
-
-
(8), (9)
Junction to Ambient Natural Convection
• Single layer board (1s)
57
36
°C/W
°C/W
RθJA
(8), (9),
(10)
Junction to Ambient Natural Convection
• Four layer board (2s2p)
RθJMA
MC34708
Analog Integrated Circuit Device Data
15
Freescale Semiconductor
General Product Characteristics
Table 5. Thermal Ratings (continued)
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
-
(8), (10)
Junction to Ambient (@200 ft/min.)
• Single layer board (1s)
48
°C/W
RθJMA
-
(8), (10)
Junction to Ambient (@200 ft/min.)
• Four layer board (2s2p)
32
°C/W
RθJMA
-
-
-
(11)
(12)
(13)
Junction to Board
Junction to Case
22
15
°C/W
°C/W
°C/W
RθJB
RθJC
θJT
Junction to Package Top
• Natural Convection
3.0
Notes
5. Do not operate above 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause a malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
8. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
9. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
10. Per JEDEC JESD51-6 with the board horizontal.
11. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
13. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
General Product Characteristics
5.2.1
Power Dissipation
During operation, the temperature of the die should not exceed the maximum junction temperature. To optimize the thermal
management scheme and avoid overheating, the MC34708 PMIC provides a thermal management system. The thermal
protection is based on a circuit with a voltage output proportional to the absolute temperature.This voltage can be read out via
the ADC for specific temperature readouts, see Channel 3 Die Temperature.
The ADEN SPI bit must be set = 1 to enable the comparators for the thermal monitoring (THERM110, THERM120, THERM125,
THERM130, and thermal shutdown). With ADEN = 0 the thermal monitors and thermal shutdown are disabled. Interrupts
THERM110, THERM120, THERM125, and THERM130 will be generated when respectively crossing in either direction the
thresholds specified in Table 6. The temperature range can be determined by reading the THERMxxxS bits.
Thermal protection is integrated to power off the MC34708 PMIC in case of over dissipation. This thermal protection will act above
the maximum junction temperature to avoid any unwanted power downs. The protection is debounced for 8.0 ms in order to
suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism and therefore the application
design should be dimensioned such that this protection is not tripped under normal conditions. The temperature thresholds and
the sense bit assignment are listed in Table 6
.
Table 6. Thermal Protection Thresholds
Parameter
Thermal 110 °C threshold (THERM110)
Min
Typ
Max
Units
Notes
105
115
120
125
2.0
110
120
125
130
-
115
125
130
135
4.0
°C
°C
°C
°C
°C
°C
Thermal 120 °C threshold (THERM120)
Thermal 125 °C threshold (THERM125)
Thermal 130 °C threshold (THERM130)
Thermal warning hysteresis
(14)
Thermal protection threshold
130
140
150
Notes
14. Equivalent to approx. 30 mW min, 60 mW max
The THERM1xx thresholds are debounced by the SPI bits DIE_TEMP_DB[1:0], which are programmable from 100 s to 4.0 ms
(4.0 ms by default), see Table 7. When the die temperature crosses these thresholds, the corresponding sense bit will change,
and an interrupt will be generated to notify the software the hardware is reaching its thermal limit.
Table 7. Die Temp Debounce Settings
DIE_TEMP_DB [1:0]
Time
Units
00
01
0.100
1.0
ms
ms
ms
ms
10
2.5
11 (default)
4.0
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
General Product Characteristics
5.3
Electrical Characteristics
5.3.1
Recommended Operating Conditions
Table 8. Recommended Operating Conditions
Symbol
Description (Rating)
Main Input Supply
Min.
Max.
Unit
Notes
VBP
VLICELL
TA
3.0
1.8
-40
4.5
3.6
85
V
V
LICELL Backup Battery
Ambient Temperature
°C
5.3.2
General PMIC Specifications
Table 9. Pin Logic Thresholds
Internal
Termination (19)
Max (22)
Pin Name
Parameter
Input Low
Load Condition
Min
Unit
Notes
(16)
(16)
(21)
(21)
47 kOhm
1.0 MOhm
-
0.0
1.0
0.0
0.9
0.0
0.3
VCOREDIG
0.3
V
V
V
V
V
V
V
V
V
V
PWRON1, PWRON2,
GLBRST
Pull-up
Input High
Input Low
STANDBY, WDI
CLK32K
Weak Pull-down
CMOS
Input High
Output Low
Output High
Output Low
Output High
Output Low
-
3.6
-100 A
100 A
-100 A
100 A
-2.0 mA
Open Drain
0.2
CLK32KVCC - 0.2
CLK32KVCC
0.2
0.0
CLK32KMCU
CMOS
VSRTC - 0.2
VSRTC
0.4
(20)
(20)
RESETB,
Open Drain
0.0
-
RESETBMCU,
SDWNB, SW1PWGD,
SW2PWGD
3.6
Output High
Input Low
-
0.0
0.3 * GPIOVDD
GPIOVDD + 0.3
0.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Input High
Output Low
Output High
Output Low
Output High
Output Low
Output High
Input Low
-
0.7 * GPIOVDD
CMOS
-
0.0
GPIOLV1,2,3,4
-
GPIOVDD - 0.2
GPIOVDD
0.4
-2.0 mA
0
Open Drain
CMOS
Open Drain
-
GPIOVDD + 0.3
0.2
-
-
-
-
-
-
-
-
0.0
PWM1, PWM2
CLK, MOSI
CS
GPIOVDD - 0.2
GPIOVDD
0.3 * SPIVCC
SPIVCC + 0.3
0.4
(15)
(15)
(15)
(15)
0.0
Input High
Input Low
0.7 * SPIVCC
0.0
Weak Pull-down
Input High
Input Low
1.1
0.0
SPIVCC + 0.3
0.3 * VCOREDIG
VCOREDIG
(15) (23)
,
Weak Pull-down
on CS
CS, MOSI (at Booting
for SPI / I2C decoding)
(15) (23)
Input High
0.7 * VCOREDIG
,
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
General Product Characteristics
Table 9. Pin Logic Thresholds
Internal
Termination (19)
Max (22)
Pin Name
Parameter
Load Condition
Min
Unit
Notes
-100 A
0.0
0.2
V
MISO
Output Low
(15) (24)
MISO, INT
CMOS
100 A
SPIVCC - 0.2
SPIVCC
0.3
V
V
V
MISO
Output High
(15) (24)
(17)
(17)
Input Low
PUMSxS = 0
-
-
0.0
1.0
PUMS1,2,3,4,5
ICTEST
Input High
VCOREDIG
PUMSxS = 1
(18)
(18)
Input Low
Input High
Input Low
Input Mid
Input High
-
-
-
-
-
0.0
1.1
0.0
1.3
2.5
0.3
1.7
0.3
2.0
3.1
V
V
V
V
V
SW1CFG, SW4CFG
Notes
15. SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V
16. Input has internal pull-up to VCOREDIG equivalent to 200 kOhm
17. Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration
18. Input state is not latched
19. A weak pull-down represents a nominal internal pull-down of 100 nA unless otherwise noted
20. RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open drain outputs, external pull-ups are required
21. SPIVCC needs to remain enabled for proper detection of WDI High to avoid involuntary shutdown
22. The maximum should never exceed the maximum rating of the pin as given in Pin Connections
23. The weak pull-down on CS is disabled if a VIH is detected at startup to avoid extra consumption in I2C mode
24. The output drive strength is programmable
MC34708
Analog Integrated Circuit Device Data
19
Freescale Semiconductor
General Product Characteristics
5.3.3
Current Consumption
The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary
table follows for standard use cases.
Table 10. Current Consumption Summary (27)
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Mode
Description
Typ
Max
Unit
Notes
All blocks disabled, no main battery attached, coin cell is attached to LICELL
(at 25 °C only)
4.0
8.0
A
• RTC Logic
RTC / Power
cut
• VSRTC
• 32 kHz Oscillator
• Clk32KMCU buffer active(10 pF load)
All blocks disabled, main battery attached
• Digital Core
20
55
A
A
• RTC Logic
OFF (good
battery)
• VSRTC
• 32 kHz Oscillator
• CLK32KMCU buffer active (10 pF load)
Low Power Mode (Standby pin asserted and ON_STBY_LP=1)
340
424
• Digital Core
• RTC Logic
• VCORE Module
• VSRTC
• CLK32KMCU/CLK32K active (10 pF load)
LPM ON
Standby
• 32 kHz Oscillator
• IREF
• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM (26),(30)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC
in low power mode (25),(28)
• Mini-USB
• Digital Core
480
561
A
• RTC Logic
• VCORE module
• VSRTC
• CLK32KMCU/CLK32K active (10 pF load)
• 32 kHz Oscillator
• Digital
ON Standby
• IREF
• SW1, SW2, SW3 SW4A, SW4B, SW5 in PFM (26),(30)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on
in low power mode (26),(28)
• Mini-USB
• PLL (for mini USB)
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
General Product Characteristics
Table 10. Current Consumption Summary (27)
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Typical use case
1600
3000
A
• Digital Core
• RTC Logic
• VCORE Module
• VSRTC CLK32KMCU/CLK32K active (10 pf)
• 32 kHz Oscillator
• IREF
ON
• SW1, SW2, SW3 SW4A, SW4B, SW5 in Apskip SWBST (26),(29),(30)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on
in low power mode (25),(28)
• Digital
• PLL
• Mini-USB
Notes
25. Equivalent to approx. 30 mW min, 60 mW max
26. Current in RTC Mode is from LICELL=2.5 V; in all other modes from BP = 3.6 V.
27. External loads are not included (1)
28. VUSB2, VGEN2 external pass PNPs
29. SWBST in auto mode
30. SW4A output 2.5 V
MC34708
Analog Integrated Circuit Device Data
21
Freescale Semiconductor
General Description
6
General Description
6.1
Features
Power Generation
• Six Buck Switching Regulators
• Two Single/Dual Phase Buck Regulators
• Three Single Phase Buck Regulators
• PFM/Auto Pulse Skip/PWM Operation Mode
• Dynamic Voltage Scaling
• 5 V Boost Regulator
• USB On-the-go Support
• Eight LDO Regulators
• Two with Selectable Internal or External Pass Devices
• Five with Embedded Pass Devices
• One with an External PNP Device
Analog to Digital Converter
• Seven General Purpose Channels
• Internal Dedicated Channels
• Resistive Touchscreen Interface
Auxiliary Circuits
• Mini/Micro USB Switch
• Bidirectional Audio/Data/UART
• Accessory Identification Circuit
• General Purpose I/Os
• PWM Outputs
• Two general purpose LED Drivers.
Clocking and Oscillators
• Real Time clock
• Time and day Counters
• Time of day Alarm
• 32.768 kHz Crystal Oscillator
• Coin Cell Battery Backup and Charger
Serial Interface
• SPI
• I2C
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
General Description
6.2
Block Diagram
SIX BUCK
REGULATORS
Processor Core
Split Power Domains
DDR Memory
I/O
5 V BOOST
REGULATOR
USB On The Go
Supply
MINI/MICRO USB
INTERFACE
USB/UART/Audio
Auto Accessory Detect
EIGHT LDO
REGULATORS
Peripherals
10-BIT ADC CORE
General Purpose
Resistive Touch
Screen Interface
GENERAL PURPOSE
I/O & PWM OUTPUTS
Dual LED Indicator
MC34708
32.768 kHz CRYSTAL
OSCILLATOR
Real Time Clock
SRTC Support with
Coin Cell Charger
BIAS &
REFERENCES
Trimmed Bandgap
CONTROL
INTERFACE
SPI/I2C
POWER CONTROL
LOGIC
State Machine
Figure 4. Functional Block Diagram
6.3
Functional Description
The MC34708 Power Management Integrated Circuit (PMIC) represents a complete system power solution in a single package.
Designed specifically for use with the Freescale i.MX50/53 families. The MC34708 integrates six multi-mode buck regulators and
eight LDO regulators for direct supply of the processor core, memory and peripherals.
The USB switch enables the use of a single, mini or micro USB connector for USB, UART and audio connections, switching the
relevant signals to the connector depending on the type of device connected. In addition, the MC34708 also integrates a real
time clock, coin cell charger, a 13-channel 10-bit ADC, 5 V USB Boost regulator, two PWM outputs, touch-screen interface, status
LED drivers and four GPIOs.
MC34708
Analog Integrated Circuit Device Data
23
Freescale Semiconductor
Functional Block Description
7
Functional Block Description
7.1
Startup Requirements
When power is applied, there is an initial delay of 8.0 ms during which the core circuitry is enabled. The switching and linear
regulators are then sequentially enabled in time slot steps of 2.0 ms. This allows the PMIC to limit the inrush current.
The outputs of the switching regulators not enabled are discharged with weak pull-downs on the output to ensure a proper power-
up sequence. Any undervoltage detection at BP is masked while the power-up sequencer is running. When the switching
regulators are enabled, they will start in PWM mode. After 3.0 ms, the switching regulators will transition to the mode
programmed in the SPI register map.
The Power-up mode select pins PUMSx (x = 1, 2, 3, 4, and 5) are used to configure the start-up characteristics of the regulators.
Supply enabling and output level options are selected by hardwiring the PUMSx pins. It is recommended to minimize the load
during system boot-up by supplying only the essential voltage domains. This allows the start-up transients to be minimized after
which the rest of the system power tree can be brought up by software. The PUMSx pins also allow optimization of the supply
sequence and default values. Software code can load the required programmable options without any change to hardware.
The state of the PUMSx pins are latched before any of the regulators are enabled, with the exception of VCORE. PUMSx options
and start-up configurations are robust to a PCUT event, whether occurring during normal operation or during the 8.0 ms of pre-
sequencer initialization, i.e. the system will not end up in an unexpected / undesirable consumption state.
Table 11 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled.
Table 11. Power Up Defaults
53
LPM
53
DDR2
53
DDR3
53
LVDDR3
53
LVDDR2
50
50
50
50
50
50
i.MX
Reserved
MDDR LPDDR2 LPDDR2 MDDR LPDDR2 MDDR
PUMS[4:1]
0000-0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PUMS5=0
VUSB2
VGEN2
Ext PNP Ext PNP Ext PNP
Ext PNP
Ext PNP
Ext PNP
Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP
Reserved
Reserved
PUMS5=1
VUSB2
VGEN2
Internal
Internal
Internal
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
Internal
Internal
Internal
Internal
PMOS
PMOS
PMOS
PMOS
PMOS
PMOS
PMOS
PMOS
SW1A
(VDDGP)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.1
1.1
1.1
1.1
1.3
1.3
1.8
1.8
1.8
1.1
1.1
1.3
1.2
1.5
1.5
1.8
1.1
1.1
1.1
1.1
1.3
1.2
1.2
1.2
1.8
1.1
1.1
1.2
1.2
1.8
1.8
1.8
1.1
1.1
1.2
1.2
1.2
1.2
1.8
1.1
1.1
1.2
1.2
3.15
1.2
1.8
1.1
1.1
1.2
1.2
3.15
1.8
1.8
1.1
1.1
1.2
1.2
3.15
1.2
1.8
1.1
1.1
1.2
1.2
3.15
1.8
1.8
SW1B
(VDDGP)
(31)
SW2
1.225
1.2
1.3
(VCC)
(31)
SW3
1.2
(VDDA)
(31)
SW4A
1.5
1.35
1.35
1.8
(DDR/SYS)
(31)
SW4B
1.5
(DDR/SYS)
(31)
SW5
1.8
(I/O)
SWBST
Reserved
Reserved
Reserved
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
Off
3.3
2.5
(32)
VUSB
VUSB2
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
Functional Block Description
Table 11. Power Up Defaults
53
LPM
53
DDR2
53
DDR3
53
LVDDR3
53
LVDDR2
50
50
50
50
50
50
i.MX
Reserved
MDDR LPDDR2 LPDDR2 MDDR LPDDR2 MDDR
VSRTC
VPLL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.2
1.3
1.8
1.3
1.8
1.3
1.8
1.3
1.8
1.2
1.8
On
2.5
1.2
3.1
1.2
1.8
On
2.5
1.2
3.1
1.2
1.8
On
2.5
1.2
3.1
1.2
1.8
On
2.5
1.2
3.1
1.2
1.8
On
2.5
1.2
2.5
1.2
1.8
On
2.5
1.2
2.5
1.8
VREFDDR
VDAC
On
On
On
On
On
2.775
1.2
2.775
1.3
2.775
1.3
2.775
1.3
2.775
1.3
VGEN1
VGEN2
Notes
2.5
2.5
2.5
2.5
2.5
31. The SWx node are activated in APS mode when enabled by the startup sequencer.
32. VUSB regulator is only enabled if 5.0 V is present on VBUS. By default VUSB will be supplied by VBUS. SWBST = 5.0 V powers up as
does VUSB, regardless of 5.0 V present on UVBUS. By default VUSB is supplied by SWBST.
The power up sequence is shown in Tables 12 and 13. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer
startup.
Table 12. Power Up Sequence i.MX53
Tap x 2.0 ms
PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53)
0
1
2
3
4
5
6
7
8
9
SW2 (VCC)
VPLL (NVCC_CKIH = 1.8 V)
VGEN2 (VDD_REG= 2.5 V, external PNP
SW3 (VDDA)
SW1A/B (VDDGP)
SW4A/B, VREFDDR (DDR/SYS)
SW5 (I/O), VGEN1
VUSB (33), VUSB2
VDAC
Notes:
33. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By
default VUSB will be supplied by the VBUS pin.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
Functional Block Description
Table 13. Power Up Sequence i.MX50
Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53)
0
1
2
3
4
5
6
7
8
9
SW2
SW3
SW1A/B
VDAC
SW4A/B, VREFDDR
SW5
VGEN2, VUSB2
VPLL
VGEN1
VUSB (34)
Notes:
34. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By
default VUSB will be supplied by the VBUS pin.
7.2
Bias and References Block Description and Application
Information
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The
bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on
the performance of VCORE and the bandgap. No external DC loading is allowed on VCORE, VCOREDIG, and REFCORE.
VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Table 14 shows the main characteristics of the
core circuitry.
Table 14. Core Voltages Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VCOREDIG (DIGITAL CORE SUPPLY)
Output voltage
• ON mode
VCOREDIG
V
(35)
-
-
1.5
1.2
-
-
• OFF mode with good battery and RTC mode
VCOREDIG bypass capacitor
CCOREDIG
-
1.0
-
F
VDDLP (DIGITAL CORE SUPPLY - LOWER POWER)
Output voltage
• ON mode with good battery
VDDLP
V
(36)
-
-
-
1.5
1.2
1.2
-
-
-
• OFF mode with good battery
• RTC mode
(37)
VDDLP bypass capacitor
CDDLP
-
100
-
pF
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
Functional Block Description
Table 14. Core Voltages Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VCORE (ANALOG CORE SUPPLY)
Output voltage
VCORE
V
(35)
• ON mode
-
-
2.775
0.0
-
-
• OFF and RTC mode
VCORE bypass capacitor
CCORE
-
1.0
-
F
VCOREREF (BANDGAP VOLTAGE/ REGULATOR REFERENCE)
(35)
Output voltage
VCOREREF
-
-
-
-
1.2
0.5
-
-
-
-
V
Absolute Accuracy
Temperature Drift
%
%
0.25
100
VCOREREF bypass capacitor
CCOREREF
Notes
nF
35. 3.0 V < BP < 4.5 V, no external loading on VCOREDIG, VDDLP, VCORE, or VCOREREF. Extended operation down to UVDET, but no
system malfunction.
36. Powered by VCOREDIG
37. Maximum capacitance on VDDLP should not exceed 1000 pF, including the board capacitance.
7.3
Clocking and Oscillators
Clock Generation
7.3.1
A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal
oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running
(for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead.
Support is also provided for an external Secure Real Time Clock (SRTC) which may be integrated on a companion system
processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the
CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented.
7.3.1.1
Clocking Scheme
The internal 32 kHz oscillator is an integrated backup for the crystal oscillator, and provides a 32.768 kHz nominal frequency at
60% accuracy, if running. The internal oscillator only runs if a valid supply is available at BP, and would not be used as long as
the crystal oscillator is active. In absence of a valid supply at the BP supply node, the crystal oscillator will continue to operate
as it is powered from the coin cell battery. All control functions will run off the crystal derived frequency, occasionally referred to
as “32 kHz” for brevity’s sake.
During the switch-over between the two clock sources (such as when the crystal oscillator is starting up), the output clock is
maintained at a stable active low or high phase of the internal 32 kHz clock to avoid any clocking glitches. If the XTAL clock
source suddenly disappears during operation, the IC will revert back to the internal clock source. Given the unpredictable nature
of the event and the startup times involved, the clock may be absent long enough for the application to shutdown during this
transition due to various reasons, for example a sag in the regulator output voltage or absence of a signal on the clock output pins.
A status bit, CLKS, is available to indicate to the processor which clock is currently selected: CLKS = 0 when the internal RC is
used and CLKS = 1 if the crystal source is used. The CLKI interrupt bit will be set whenever a change in the clock source occurs,
and an interrupt will be generated if the corresponding CLKM mask bit is cleared.
MC34708
Analog Integrated Circuit Device Data
27
Freescale Semiconductor
Functional Block Description
7.3.1.2
Oscillator Specifications
The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or
equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations. Ensure that
the chosen crystal has a typical drive level of 0.5 µW or above to ensure proper operation of the crystal oscillator. Using a crystal
with a lower drive level can cause overtone oscillations.
The electrical characteristics of the 32 kHz Crystal oscillator are given in the following table, taking into account the crystal
characteristics noted above. The oscillator accuracy depends largely on the temperature characteristics of the crystal. Application
circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/
or tuning). Additionally, a clock calibration system is provided to adjust the 32.768 cycle counter that generates the 1.0 Hz timer
and RTC registers; see SRTC Support for more detail.
Table 15. Oscillator and Clock Main Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
OSCILLATOR AND CLOCK OUTPUT
Operating Voltage
VINRTC
V
• Oscillator and RTC Block from BP
1.8
1.8
-
-
4.5
3.6
• Oscillator and RTC Block from LICELL
Operating Current Crystal Oscillator and RTC Module
IINRTC
A
• All blocks disabled, no main battery attached, coin cell is attached
to LICELL
-
2.0
5.0
RTC oscillator startup time
• Upon application of power
tSTART-RTC
sec
V
-
-
-
1.0
0.2
Output Low
VRTCLO
• CLK32K Output sink 100 A
• CLK32KMCU Output source 50 A
0.0
Output High
VRTCHI
V
• CLK32K Output source 100 A
CLK32K
VCC -0.2
-
-
CLK32K
VCC
VSRTC-0.2
VSRTC
• CLK32KMCU Output sink 50 A
CLK32K Rise and Fall Time, CL = 50 pF
• CLK32KDRV [1:0] = 00
tCLK32KET
ns
-
-
-
-
6.0
2.5
3.0
2.0
-
-
-
-
• CLK32KDRV [1:0] = 01 (default)
• CLK32KDRV [1:0] = 10
• CLK32KDRV [1:0] = 11
CLK32KMCU Rise and Fall Time
• CL = 12 pF
tCKL32K
ns
%
MCUET
-
22
-
-
CLK32KDC/
CLK32K
MCUDC
CLK32K and CLK32KMCU Output Duty Cycle
• Crystal on XTAL1, XTAL2 pins
45
55
RMS Output Jitter
ns
RMS
• 1 Sigma for Gaussian distribution
-
-
30
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
Functional Block Description
7.3.2
SRTC Support
When configured for DRM mode (SPI bit DRM = 1), the CLK32KMCU driver will be kept enabled through all operational states
to ensure the SRTC module always has its reference clock. If DRM = 0, the CLK32KMCU driver will not be maintained in the Off
state.
It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed
for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of the MC34708
PMIC, so it is in effect, a parallel path for the power key. The MC34708 PMIC will not be able to discern the turn on event from
a normal power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated
locally.
Open Drain output for RTC wake-up
34708
32 kHz
SPIVCC=1.8 V
Processor
Core Supply
SOG Supply
I/O
VCOREDIG
PWRONx
V
GP Domain=1.1 V
LP Dominant=1.2 V
COREDIG
On
Detect
SRTC
HP-RC
Best of
Supply
On/Off
Button
VSRTC=1.2 V
V
&
SRTC
32 kHz for
DSM timing
Detect
LP-RTC
CKIL: VSRTC
CLK32KMCU
+
-
Main
Battery
Coin Cell
Battery
+
-
0.1 F
Figure 5. SRTC Block Diagram
7.3.2.1
VSRTC
The VSRTC regulator provides the CLK32KMCU output level. Additionally, it is used to bias the Low Power SRTC domain of the
SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected.
The VSRTC regulator cannot be disabled.
Depending on the configuration of the PUMS[4:0] pins, the VSRTC voltage will be set to 1.3 or 1.2 V. With PUMS[4:0] = (0110,
0111, 1000, or 1001) VSRTC will be set to 1.3 V in ON mode (ON, ON Standby and ON Standby Low Power modes). In OFF
and Coin Cell modes the VSRTC voltage will drop to 1.2 V with the PUMS[4:0] = (0110, 0111, 1000, or 1001). With PUMS[4:0]
≠ (0110, 0111, 1000, or 1001), VSRTC will be set to 1.2 V for all modes (ON, ON Standby, LPM ON Standby, OFF, and Coin Cell).
Table 16. VSRTC Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
GENERAL
VSRTCIN
Characteristic
Min
Typ
Max
Unit Notes
Operating Input Voltage Range VINMIN to VINMAX
• Valid Coin Cell range
V
1.8
1.8
-
-
3.6
4.5
• Valid BP
(38)
Operating Current Load Range ILMIN to ILMAX
Bypass Capacitor Value
ISRTC
0.0
-
-
50
-
A
COSRTC
0.1
F
MC34708
Analog Integrated Circuit Device Data
29
Freescale Semiconductor
Functional Block Description
Table 16. VSRTC Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VSRTC - ACTIVE MODE - DC
Output Voltage VOUT
VSRTC
1.15
1.20
1.28
V
• VINMIN < VIN < VINMAX
• ILMIN < IL < ILMAX
• Off and coincell mode
Output Voltage VOUT
VSRTC
1.15
1.25
1.2
1.3
1.25
1.35
V
V
• VINMIN < VIN < VINMAX
• ILMIN < IL < ILMAX
• PUMS[4:0] (0110, 0111, 1000, 1001)
• On mode (On, Standby, Standby LPM)
Output Voltage VOUT
VSRTC
• VINMIN < VIN < VINMAX
• ILMIN < IL < ILMAX
• PUMS[4:0] = (0110, 0111, 1000, 1001)
• On mode (On, Standby, Standby LPM)
ISRTCQ
Active Mode Quiescent Current
VINMIN < VIN < VINMAX, IL = 0
A
• VSRTC = 1.2 V
• VSRTC = 1.3 V
-
-
1.7
2.7
-
-
Notes
38. Valid for BP > 2.4 V and/or LICELL > 2.0 V.
7.3.2.2
Real Time Clock
A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz
crystal oscillator for the time base and is powered by the coin cell backup supply when BP has dropped below operational range.
In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1
(defaults on at power up).
Time and Day Counters
The 32.768 kHz clock is divided down to a 1.0 Hz time tick which drives a 17 bit Time Of Day (TOD) counter. The TOD counter
counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments
the 15 bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1HZI
interrupt if unmasked.
Time Of Day Alarm
A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already
on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is
equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated.
Timer Reset
As long as the supply at BP is valid, the real time clock will be supplied from VCOREDIG. If BP is not valid, the real time clock
can be backed up from a coin cell via the LICELL pin. When the VSRTC voltage drops to the range of 0.9 - 0.8 V, the RTCPORB
reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with
RTCPORB. To inform the processor the contents of the RTC are no longer valid due to the reset, a timer reset interrupt function
is implemented with the RTCRSTI bit.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
Functional Block Description
RTC Timer Calibration
A clock calibration system is provided to adjust the 32.768 cycle counter that generates the 1.0 Hz timer for RTC timing registers.
The general implementation relies on the system processor to measure the 32.768 kHz crystal oscillator against a higher
frequency and more accurate system clock such as a TCXO. If the RTC timer needs a correction, a 5-bit 2’s complement
calibration word can be sent via the SPI to compensate the RTC for inaccuracy in its reference oscillator.
Table 17. RTC Calibration Settings
Code in RTCCAL[4:0]
Correction in Counts per 32768 Relative correction in ppm
01111
00011
00001
00000
11111
11101
10001
10000
+15
+3
+1
0
+458
+92
+31
0
-1
-31
-3
-92
-15
-16
-458
-488
The available correction range should be sufficient to ensure drift accuracy in compliance with standards for DRM time keeping.
Note that the 32.768 kHz oscillator is not affected by RTCCAL settings; calibration is only applied to the RTC time base counter.
Therefore, the frequency at the clock output CLK32K is not affected.
The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode.
Table 18. RTC Calibration Enabling
RTCCALMODE
Function
RTC Calibration disabled (default)
00
01
10
11
RTC Calibration enabled in all modes except coin cell only
Reserved for future use. Do not use.
RTC Calibration enabled in all modes
The RTC Calibration circuitry can be automatically disabled when main battery contact is lost or if it is so deeply discharged that
the RTC power draw is switched to the coin cell (configured with RTCCALMODE=01).
Because of the low RTC consumption, RTC accuracy can be maintained through long periods of the application being shut down,
even after the main battery has discharged. However, the calibration can only be as good as the RTCCAL data provided, so
occasional refreshing is recommended to ensure any drift influencing environmental factors have not skewed the clock beyond
desired tolerances.
MC34708
Analog Integrated Circuit Device Data
31
Freescale Semiconductor
Functional Block Description
7.3.3
Coin Cell Battery Backup
The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged,
removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the
LICELL for backup power. This switch over occurs for a BP below 1.8 V threshold with LICELL greater than BP. A small capacitor
should be placed from LICELL to ground under all circumstances.
Upon initial insertion of the coin cell, it is not immediately connected to the on chip circuitry. The cell gets connected when the IC
powers on, or after enabling the coin cell charger when the IC was already on.
The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically
used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit. The coin cell voltage is
programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the ON state where the charge
current is fixed at ICOINHI.
If COINCHEN=1 when the system goes into Off or User Off state, the coin cell charger will continue to charge to the predefined
voltage setting but at a lower maximum current ICOINLO. This compensates for self discharge of the coin cell and ensures if and/
or when the main cell gets depleted, the coin cell will be topped off for maximum RTC retention. The coin cell charging will be
stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs.
Table 19. Coin Cell Voltage Specifications
VCOIN[2:0]
Output Voltage
000
001
010
011
100
101
110
111
2.50
2.70
2.80
2.90
3.00
3.10
3.20
3.30
Table 20. Coin Cell Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
COIN CELL CHARGER
Voltage Accuracy
VLICELLACC
-
-
-
100
60
-
-
-
mV
A
A
Coin Cell Charge Current in On and Watchdog modes ICOINHI
ILICELLON
Coin Cell Charge Current in Off, cold start/warm start, and Low Power Off
modes (User Off / Memory Hold) ICOINLO
ILICELLOFF
10
Current Accuracy
ILICELACC
COLICELL
-
-
-
30
100
4.7
-
-
-
%
nF
F
LICELL Bypass Capacitor
LICELL Bypass Capacitor as coin cell replacement
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
Functional Block Description
7.4
Interrupt Management
7.4.1
Control
The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor
by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C.
Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt
can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line to go
low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,
the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the
device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked
interrupt bit was already high, the interrupt line will go high after unmasking.
The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources.
They are read only, and not latched or clearable.
Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period
before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table later in
this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
7.4.2
Interrupt Bit Summary
Table 21 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions,
refer to the related chapters.
Table 21. Interrupt, Mask and Sense Bits
Debounce
Time
Interrupt
Mask
Sense
Purpose
Trigger
ADCDONEI
TSDONEI
ADCDONEM
TSDONEM
-
-
-
ADC has finished requested conversions L2H
0
0
Touch screen has finished conversion
Touch screen pen detect
L2H
TSPENDET
TSPENDETM
Dual
Dual
1.0 ms
VBUS over-voltage
Programmable
SUP_OVP_DB
USBOVP
LOWBATT
USBDET
USBOVPM
LOWBATTM
USBDETM
USBOVPS
-
Sense is 1 if above threshold.
Low battery detect
Programmable
VBATTDB
H2L
Sense is 1 if below LOWBAT threshold
USB VBUS detect
Programmable
VBUSDB
USBDETS
Dual
Sense is 1 if detected
Stuck_Key_RCV Stuck_Key_RCV_m
-
-
Stuck key has recovered
Stuck key detected
L2H
L2H
Stuck_Key
Stuck_Key_m
ADC result changed
ADC_Change
ADC_Change_m
ADC_STATUS
L2H
Sense is 1 if conversion is completed, 0 if
in progress
Unknown_Atta
LKR
Unknown_Atta_m
LKR_m
-
-
-
-
-
Unknown accessory detected
Remote control long key is released
Remote control long key is pressed
Remote control key is pressed
Accessory detached
L2H
L2H
L2H
L2H
L2H
LKP
LKP_m
KP
KP_m
Detach
Detach_m
MC34708
Analog Integrated Circuit Device Data
33
Freescale Semiconductor
Functional Block Description
Table 21. Interrupt, Mask and Sense Bits
Interrupt Mask Sense
Attach Attach_m
Debounce
Time
Purpose
Accessory attached
Trigger
L2H
-
ID_GNDS
Sense is 1 if ID pin is grounded
Sense is 1 if ID pin is floating
ID_FLOATS
Sense is 1 if ID resistance detection is
complete
ID_DET_ENDS
VBUS_DET_ENDS Sense is 1 if VBUS PTSI is complete
min. 4.0 ms
max 8.0 ms
SCPI
SCPM
-
Regulator short-circuit protection tripped
L2H
1HZI
1HZM
-
-
1.0 Hz time tick
L2H
L2H
H2L
L2H
H2L
L2H
L2H
L2H
L2H
L2H
L2H
0
TODAI
TODAM
Time of day alarm
0
30 ms (39)
Power on button 1 event
PWRON1I
PWRON2I
PWRON1M
PWRON2M
PWRON1S
PWRON2S
Sense is 1 if PWRON1 is high
30 ms
30 ms (39)
Power on button 2 event
Sense is 1 if PWRON2 is high
30 ms
SYSRSTI
WDIRESETI
PCI
SYSRSTM
WDIRESETM
PCM
-
-
-
System reset through PWRONx pins
WDI silent system restart
Power cut event
0
0
0
0
0
WARMI
WARMM
Warm Start event
MEMHLDI
MEMHLDM
Memory Hold event
32 kHz clock source change
Sense is 1 if source is XTAL
CLKI
CLKM
CLKS
Dual
L2H
Dual
0
0
RTCRSTI
THERM110
RTCRSTM
THERM110M
-
RTC reset has occurred
Thermal 110C threshold
Programmable
DIE_TEMP_DB
THERM110S
Sense is 1 if above threshold
Thermal 120C threshold
Programmable
DIE_TEMP_DB
THERM120
THERM125
THERM130
THERM120M
THERM125M
THERM120S
THERM125S
Dual
Dual
Dual
Sense is 1 if above threshold
Thermal 125C threshold
Programmable
DIE_TEMP_DB
Sense is 1 if above threshold
Thermal 130C threshold
Programmable
DIE_TEMP_DB
THERM130M
GPIOLVxM
THERM130S
GPIOLVxS
Sense is 1 if above threshold
GPIOLVxI
Notes
General Purpose input interrupt
Programmable Programmable
39. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Turn On Events for details.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
Functional Block Description
7.5
Power Generation
The MC34708 PMIC provides reference and supply voltages for the application processor as well as peripheral devices.
Six buck (step down) converters and one boost (step up) converter are included. One of the buck regulators can be configured
in dual phase, single phase mode, or operate as separate independent outputs (in this case, there are six buck converters). The
buck converters provide the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage
scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. The boost converter
supplies the VUSB regulator for the USB PHY on the processor. The VUSB regulator is powered from the boost to ensure
sufficient headroom for the LDO through the normal discharge range of the main battery.
Linear regulators could be supplied directly from the battery or from one of the switching regulator, and provide supplies for IO
and peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. Naming conventions are suggestive of typical or possible
use case applications, but the switching and linear regulators may be utilized for other system power requirements within the
guidelines of specified capabilities.
Four general purpose I/Os are available. When configured as inputs they can be used as external interrupts.
7.5.1
Power Tree
Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges.
Table 22 summarizes the available power supplies.
Table 22. Power Tree Summary
Supply
Purpose (typical application)
Buck regulator for processor VDDGP domain
Buck regulator for processor VCC domain
Buck regulator for processor VDD domain and peripherals
Buck regulator for DDR memory and peripherals
Buck regulator for DDR memory and peripherals
Buck regulator for I/O domain
Output Voltage (in V)
Load Capability (in mA)
SW1
SW2
0.650 - 1.4375
0.650 - 1.4375
2000
1000
500
500
500
1000
380
0.05
50
SW3
0.650 - 1.425
SW4A
SW4B
SW5
1.200 – 1.85: 2.5/3.15
1.200 – 1.85: 2.5/3.15
1.200 – 1.85
Boost regulator for USB OTG
SWBST
VSRTC
VPLL
5.00/5.05/5.10/5.15
1.2
Secure Real Time Clock supply
Quiet Analog supply
1.2/1.25/1.5/1.8
DDR Ref supply
VREFDDR
VDAC
0.6-0.9
10
TV DAC supply, external PNP
2.5/2.6/2.7/2.775
2.5/2.6/2.75/3.0
250
65
VUSB/peripherals supply, internal PMOS
VUSB/peripherals external PNP
VUSB2
VGEN1
VGEN2
VUSB
2.5/2.6/2.75/3.0
350
250
50
General peripherals supply #1
1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55
2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3
2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3
3.3
General peripherals supply #2, internal PMOS
General peripherals supply #2, external PNP
USB Transceiver supply
250
100
MC34708
Analog Integrated Circuit Device Data
35
Freescale Semiconductor
Functional Block Description
7.5.2
Modes of Operation
The MC34708 PMIC is fully programmable via the SPI/I2C interface and associated register map. Additional communication is
provided by direct logic interfacing, including interrupt, watchdog, and reset. Default startup of the device is selectable by
hardwiring the Power Up Mode Select (PUMS) pins.
Power cycling of the application is driven by the MC34708 PMIC. It has the interfaces for the power buttons and dedicated
signaling interfacing with the processor. It also ensures the supply of the Real Time Clock (RTC), critical internal logic, and other
circuits from the coin cell, in case of brief interruptions from the main battery. A charger for the coin cell is included to ensure it
is kept topped off until needed.
The MC34708 PMIC provides the timekeeping, based on an integrated low power oscillator running with a standard crystal. This
oscillator is used for internal clocking, the control logic, and as a reference for the switcher PLL. The timekeeping includes time
of day, calendar, and alarm, and is backed up by coin cell. The clock is driven to the processor for reference and deep sleep
mode clocking.
From any state: Loss of Power with PCEN=0
PCT[7:0] Expired
Thermal Protection Trip, or System Reset
Off
Unqual’d
Turn On
WDI Low,
WDIRESET=0
WDI Low
Unqual’d
Turn On
Turn On
Event
WDIRESET=1
and PCMAXCNT
is exceeded
Start Up States
Reset Timer
Expired
Reset Timer
Expired
Cold
Start
Warm
Start
Watchdog
WDI Low
WDIRESET=1
and PCMAXCNT
is not exceeded
Watchdog Timer
Expired
On
PCUT Timeout
PCT[7:0]
Expired
PCUTEXPB
cleared to 0
Processor Request
for User Off:
Turn On Event
(Warm Start)
Turn On Event
(Warm Boot)
USEROFFSPI=1
Low Power
Off States
Warm Start
Not
Enabled
Warm Start
Enabled
Memory
Hold
User
Off
User Off
Wait
WARMEN=1
WARMEN=0
Application of Power
before PCUT Timer
PCT[7:0] expiration
(PCEN=1 and
From any state: Loss of Power
with Power Cuts enabled
(PCEN=1) and PCMAXCNT
not exceeded
PCMAXCNT not
exceeded)
Internal
MemHold
Power
Cut
Legend and Notes (refer to text for additional details)
Blue Box = Steady State, no specific timer is running
Green Circle = Transitional State, a specific timer is running, see text
Dashed Boxes = Grouping of States for clarification
WDI has influence only in the “On” state
Complete loss of BP and coin cell power is not represented in the state machine
Figure 6. Power Control State Machine Flow Diagram
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
Functional Block Description
The following are text descriptions of the power states of the system for additional details of the state machine to complement
the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states and the interrupt
line INT is kept low in all states except for Watchdog and On.
7.5.2.1
Coin Cell
The RTC module is powered from either the battery or the coin cell, due to insufficient voltage at VALWAYS, and the IC is not in
a Power Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires VALWAYS restoration
with a threshold above UVDET. RESETB and RESETBMCU are held low in this mode.
The RTC module remains active (32 kHz oscillator + RTC timers), along with VALWAYS level detection to qualify exit to the Off
state. VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration.
If the coin cell is depleted (VSTRC drops to 0.9 - 0.8 V while in the Coin Cell state), a complete system reset will occur. At next
power application / Turn On event, the system will startup reinitialized with all SPI bits including those that reset on RTCPORB
restored to their default states.
7.5.2.2
Off (with good battery)
If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are
powered, all other supplies are inactive. To exit the Off state, a valid turn on event is required. No specific timer is running in this
state. RESETB, RESETBMCU are held low in this state.
If the supply VALWAYS is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core
gets powered from LICELL. The only active circuitry is the RTC module and the VCORE module powering VCOREDIG at 1.5 V.
7.5.2.3
Cold Start
Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms
is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level
BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power Up section
for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts
running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU
become high (open drain output with external pull-ups) when the reset timer expires. The input control pins WDI, and STANDBY
are ignored.
7.5.2.4
Watchdog
The system is fully powered and under SPI/I2C control. RESETB and RESETBMCU are high. The Watchdog timer starts running
when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and
monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state.
7.5.2.5
On Mode
The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in
this state. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5 = 1.8 V); SPIVCC must therefore
remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start
(depending on the configuration; refer to the section on Silent System Restart with WDI Event for details).
7.5.2.6
User Off Wait
The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered
by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power
key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or
Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.
The Wait timer starts running when entering User Off Wait state. This leaves the processor time to suspend or terminate its tasks.
When expired, the Wait state is exited for User Off state or Memory Hold state depending on warm starts being enabled or not
via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.
MC34708
Analog Integrated Circuit Device Data
37
Freescale Semiconductor
Functional Block Description
7.5.2.7
Memory Hold and User Off (Low Power Off States)
As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response
to an intentional turn off by the user. The only exit then will be a turn on event. To the user, the Memory Hold and User Off states
look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in
self-refresh state (Memory Hold and User Off state) as well as powering portions of the processor core for state retention (User
Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing the supply
behavior in the low power Off states. Linear regulators and most functional blocks are disabled (the RTC module, SPI bits
resetting with RTCPORB, and Turn On event detection are maintained).
By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is
applied to the processor’s VCC domain, SW3 supplies the processor’s internal memory/peripherals, and SW4 supplies the
external memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned
loads.
7.5.2.8
Memory Hold
RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To
ensure that SW1, SW2, SW3, and SW5 shut off in Memory Hold, appropriate mode settings should be used such as
SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in
this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.
Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is
set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since
software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.
No specific timer is running in this state.
Buck regulators configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when coming
out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as selected
by the PUMSx pins in the normal time slot affecting them.
7.5.2.9
User Off
RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected
to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM
is set.
The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and/or SW3 supply domains can
be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be
shut down in User Off, its mode bits would typically be set to 0.
Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the
processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used
for very low frequency / low power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the
system left off before the USEROFF command.
Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off
will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with
external memory. No specific timer is running in this mode.
7.5.2.10 Warm Start
Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx
latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to
limit the inrush current; see Startup Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or
SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out
of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the
PUMSx pins in the respective time slot defined in the sequencer selection.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
Functional Block Description
RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts
running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is
generated, and RESETB will go high.
7.5.2.11 Internal MemHold Power Cut
As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power
Cut state if PCUTs are enabled. The backup coin cell will now supply the MC34708 core, along with the 32 kHz crystal oscillator,
the RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as
possible.
Both RESETB and RESETBMCU are tripped, bringing the entire system down, along with the supplies and external clock drivers,
so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start.
If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply
recovery.
7.5.3
Power Control Logic
Power Cut Description
7.5.3.1
When the supply at VALWAYS drops below the UVDET threshold, due to battery bounce or battery removal, the Internal
MemHold Power Cut state is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC
as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled.
The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the
PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed
value, and therefore does not have to be reprogrammed after each power cut.
If power is not re-established above the LOWBATT threshold before the PCUT timer expires, the state machine transitions to the
Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an
“unsuccessful” PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down.
Upon re-application of power before expiration (a “successful PCUT”, defined as VALWAYS first rising above the UVDET
threshold and then battery above the LOWBATT threshold before the PCUT timer expires), a Cold Start is engaged after the
UVTIMER has expired.
In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by
software. The PCI interrupt is cleared by software or when cycling through the Off state.
Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance
of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current
through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power
down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize
the chance of a product falling into and getting stuck in ambulance mode.
First, the successful recovery out of a PCUT requires the VABTT node to rise above LOBATT threshold, providing hysteretic
margin from the LOBATTT (H to L) threshold. Second, the number of times the PCUT mode is entered is counted with the counter
PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through SPI. When the contents of both become equal,
then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires.
After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor
reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the
PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not
enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a
PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1
(See Silent Restart from PCUT Event).
MC34708
Analog Integrated Circuit Device Data
39
Freescale Semiconductor
Functional Block Description
7.5.3.2
Silent Restart from PCUT Event
If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent
restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting
or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB
and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and
PCUTEXPB is still “1”, then the state machine has not transitioned through Off, which confirms the PCT timer has not expired
during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate.
If PCUTEXPB is found to be “0” after the Cold Start where PCI is found to be “1”, then it is inferred the PCT timer has expired
before power was re-established. This indicates an unsuccessful power cut or first power up, so the startup user greeting may
be desirable for playback.
7.5.3.3
Silent System Restart with WDI Event
A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset,
but it is desired to make the reset a silent event so as to happen without user awareness. The default response to WDI going low
is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine will
go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal).
A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is
unrelated to PCUTs, but it shares the PCUT counter so the number of silent system restarts can be limited by the programmable
PCMAXCNT counter.
When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not
be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, software can
discern a silent system restart if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine an
inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine.
A PCUT event does not trip the WDIRESETI bit.
Note that the system response to WDI is gated by the Watchdog timer—once the timer has expired, the system will respond as
programmed by WDIRESET as described above.
Applications should make sure there is time for switching regulator outputs to discharge before re-asserting WDI.
7.5.3.4
Turn On Events
When in Off mode, the circuit can be powered on via a Turn On event. The Turn On events are listed by the following. To indicate
to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events.
Masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. If the part
was already on at the time of the turn on event, the interrupt is still generated.
• Power Button Press: PWRON1 or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I, or
PWRON2I and PWRON1S, or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can
be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e.,
unintentional) key press. BP should be above UVDET to allow a power up. The PWRONxI interrupt is generated for both the
falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising
edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The
PWRONxI interrupt is cleared by software or when cycling through the Off mode.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
Functional Block Description
Table 23. PWRONx Hardware Debounce Bit Settings(40)
Turn On
Debounce (ms)
Falling Edge INT Rising Edge INT
Bits
State
Debounce (ms)
Debounce (ms)
PWRONxDBNC[1:0]
00
01
10
11
0.0
31.25
125
31.25
31.25
125
31.25
31.25
31.25
31.25
750
750
Notes
40. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.
• Battery Attach: This occurs when BP crosses the LOWBATT threshold which is equivalent to attaching a charged battery to
the product.
• USB Attach: VBUS pulled high with corresponding interrupt and sense bits USBDET and USBDETS. This is equivalent to
plugging in a USB cable connected to a host powering the VBUS line. The battery voltage should be above LOWBATT. For
details on the USB detection, see Mini/Micro USB Switch.
• RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset
time. BP should be above LOWBATT. For details and related interrupts, see Real Time Clock.
• System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional
function, see Turn Off Events. BP should be above LOWBATT.
• Global System Reset: The global reset feature powers down the part, resets the SPI registers to their default value including
all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To enable a global reset,
the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled back high (defaults to
12 s). BP should be above LOWBATT.
Table 24. Global Reset Time Settings
Bits
State
Time (s)
GLBRSTTMR[1:0]
00
01
INVALID
4
8
10
11 (default)
12
7.5.3.5
Turn Off Events
• Power Button Press (via WDI): User shutdown of a product is typically done by pressing the power button connected to the
PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off
by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore, under
normal circumstances, not considered as a turn off event for the state machine. However, since the button press power down
is the most common turn off method for end products, it is described in this section as the product implementation for a WDI
initiated Turn Off event. Note that the software can configure a user initiated power down, via a power button press for
transition to a Low Power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state.
• Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is
recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the
PWRONxRSTEN bits. When enabled, a four second long press on the power button will cause the device to go to the Off
mode, and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power up.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
• Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On
event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling
sufficiently to accept a Turn On event. There are no specific interrupts related to this, other than the warning interrupts.
• BP lower than VBAT_TRKL: When the voltage at BP drops below VBAT_TRKL[1:0] - 100mV, the state machine will
transition to the Off mode. The SDWNB pin is used to notify the processor that the PMIC is going to immediately shutdown.
The PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. This signal will then be brought
back high into the power off state.
MC34708
Analog Integrated Circuit Device Data
41
Freescale Semiconductor
Functional Block Description
Table 25. Turn OFF Voltage Threshold
VBAT_TRKL[1:0]
Turn off Voltage threshold
00
01
10
11
2.8
2.9
3.0 (default)
3.1
7.5.3.6
Timers
The different timers as used by the state machine are listed in Table 26. This listing does not include RTC timers for timekeeping.
A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous event, the duration
listed below is therefore the effective minimum time period.
Table 26. Timer Main Characteristics
Timer
Duration
Clock
Under-voltage Timer
Reset Timer
4.0 ms
40 ms
32 k/32
32 k/32
32 k/32
Watchdog Timer
Power Cut Timer
128 ms
Programmable 0 to 8 seconds 32 k/1024
in 31.25 ms steps
7.5.3.6.1
Timing Diagrams
A Turn On event timing diagrams shown in Figure 7.
ow
Turn On Event
WDI Pulled Low
Sequencer time slots
System Core Active
Turn On Verification
Power Up Sequencer
UV Masking
RESETB
INT
WDI
8 ms
8 ms
20 ms
12 ms
128 ms
1- Off
2- Cold Start
3- Watchdog
4- On
3- Watchdog
1- Off
Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high
Turn on Event is based on PWRON being pulled low
... or transition to Off state if WDI remains low
= Indeterminate State
Figure 7. Power Up Timing Diagram
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
Functional Block Description
7.5.3.7
Power Monitoring
The voltage at BATT and BP are monitored by detectors as summarized in Table 27.
Table 27. LOWBATT Detection Thresholds
Threshold in V
L to H transition
(42) (43)
H to L transition
(41)
Bit setting
(42) (43)
(Power on)
,
(Low battery detect)
LOWBATT
3.0
,
UVDET (V)
LOWBATT1
LOWBATT0
LOWBATT
0
0
3.1 (Rising)
3.1
3.2
3.3
3.4
2.65 (Falling)
0
1
1
1
0
1
3.1 (Rising)
3.1
3.2
3.3
2.65 (Falling)
3.1 (Rising)
2.65 (Falling)
3.1 (Rising)
2.65 (Falling)
Notes
41. Default setting for LOWBATT[1:0] is 11.
42. The above specified thresholds are ±50 mV accurate for the indicated transition
43. A hysteresis is applied to the detectors on the order of 100 mV
The UVDET and LOWBATT thresholds are related to the power on/off events as described earlier in this chapter. The LOWBATT
threshold when transitioned from low to a high is used to power on the MC34708. The LOWBATT threshold when transitioned
from high to low, is used as a low battery detect warning. An interrupt LOWBAT is generated when dropping below the high to
low threshold to indicate to the processor the battery is weak and a shutdown is imminent.
The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 28.
Table 28. VBATTDB Debounce Times
VATTDB[1:0]
Debounce Time
00
01
10
11
0 (default)
2 RTC clock cycles
4 RTC clock cycles
8 RTC clock cycles
7.5.3.8
Power Saving
System Standby
7.5.3.8.1
A product may be designed to go into DSM (Deep Sleep Mode) after periods of inactivity, the STANDBY pin is provided for board
level control of timing in and out of such deep sleep modes.
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing
the operating mode of the switching regulators or disabling some regulators. This can be obtained by controlling the STANDBY
pin. The configuration of the regulators in standby is pre-programmed through the SPI.
A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set
and the STANDBY pin asserted a lower power standby will be entered. In the on Standby Low Power mode, the switching
Regulators should all be programmed into PFM mode and the LDO's should be configured to Low Power mode when the
STANDBY pin is asserted. The PLL is disabled in this mode so the mini USB will not be able to detect if an audio device, UART,
or a USB OTG device is attached. It will require the software to wake up occasionally to allow the mini-USB to detect if a device
MC34708
Analog Integrated Circuit Device Data
43
Freescale Semiconductor
Functional Block Description
is attached by de-asserting the STANDBY pin and waking up for a period to see if a device is attached and then re-asserting
Standby if a device has not been detected. If a device has been detected then the software can bring up the appropriate
application etc.
Note the STANDBY pin is programmable for Active High or Active Low polarity, and decoding of a Standby event will take into
account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as active
high throughout this document, but as defined in Table 29, active low operation can be accommodated. Finally, since STANDBY
pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin
level changes.
Table 29. Standby Pin and Polarity Control
STANDBY (Pin)
STANDBYINV (SPI bit)
STANDBY Control(44)
0
0
1
1
0
1
0
1
0
1
1
0
Notes
44. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby
The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start up and in the Watchdog
phase. This allows the system to power up without concern of the required Standby polarities since software can make
adjustments accordingly as soon as it is running.
A command to transition to one of the low power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines
the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power
tree configuration).
7.5.3.8.2
Standby Delay
A provision to delay the Standby response is included. This allows the processor and peripherals, some time after a Standby
instruction has been received, to terminate processes to facilitate seamless Standby exiting and re-entrance into Normal
operating mode.
A programmable delay is provided to hold off the system response to a Standby event. When enabled (STBYDLY = 01, 10, or
11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires.
Note that this delay is applied only when going into Standby, and no delay is applied when coming out of Standby. Also, an
allowance should be accounted for synchronization of the asynchronous Standby event and the internal clocking edges (up to a
full 32 kHz cycle of additional delay).
Table 30. Delay of STANDBY- Initiated Response
STBYDLY[1:0]
Function
No Delay
00
One 32 k period (default)
Two 32 k periods
01
10
11
Three 32 k periods
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
Functional Block Description
7.5.4
Buck Switching Regulators
Six buck switching regulators are provided with integrated power switches and synchronous rectification. In a typical application,
SW1 and SW2 are used for supplying the application processor core power domains. Split power domains allow independent
DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings.
SW3 is used for powering internal processor memory as well as low voltage peripheral devices and interfaces which can run at
the same voltage level. SW4A/B is used for powering external DDR memory as well as low voltage peripheral devices and
interfaces, which can run at the same voltage level. SW5 is used to supply the I/O domain for the system.
The buck regulators are supplied from the system supply BP, which is drawn from the main battery or the external battery charger
(when present).
The switching regulators can operate in different modes depending on the load conditions. These modes can be set through the
SPI/I2C and include a PFM mode, an Automatic Pulse Skipping mode (APS), and a PWM mode. The previous selection is
optimized to maximum battery life based on load conditions.
Table 31. Buck Operating Modes
Mode
Description
The regulator is switched off and the output voltage is discharged
OFF
PFM
The regulator is switched on and set to PFM mode operation. In this mode, the regulator
is always running in PFM mode. Useful at light loads for optimized efficiency.
The regulator is switched on and set to Automatic Pulse Skipping. In this mode the
regulator moves automatically between pulse skipping and full PWM mode depending
on load conditions.
APS
The regulator is switched on and set to PWM mode. In this mode the regulator is always
in full PWM mode operation regardless of load conditions.
PWM
Buck modes of operation are programmable for explicitly defined or load-dependent control.
During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms
(typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the
particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions
between switching modes. The regulators are turned on in APS mode by default. After the start-up sequence is complete, all
switching regulators should be set to PFM/PWM mode, depending on system load for best performance.
Point of load feedback is intended for minimizing errors due to board level IR drops.
7.5.4.1
General Control
Operational modes of the Buck regulators can be controlled by direct SPI programming, altered by the state of the STANDBY
pin, by direct state machine influence (entering Off or low power Off states, for example), or by load current magnitude when so
configured (APS mode). Available modes include PWM, PFM, APS and OFF. For light loading, the regulators should be put into
PFM mode to optimize efficiency.
Provisions are made for maintaining PFM operation in User off and Memhold modes, to support state retention for faster startup
from the Low Power Off modes for Warm Start or Warm Boot. SWxMODE[3:0] bits will be reset to their default values defined by
PUMSx settings by the startup sequencer.
Table 32 summarizes the Buck regulators programmability for Normal and Standby modes.
Table 32. Switching regulator Mode Control for Normal and Standby Operation
SWxMODE[3:0]
Normal Mode
Standby Mode
0000
0001
0010
0011
Off
PWM
Off
Off
Reserved
PFM
Reserved
Off
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
Functional Block Description
Table 32. Switching regulator Mode Control for Normal and Standby Operation
SWxMODE[3:0]
Normal Mode
Standby Mode
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
APS
PWM
Off
PWM
PWM
APS
Off
Off
APS
APS
Reserved
Reserved
Reserved
APS
Reserved
Reserved
Reserved
PFM
PWM
PFM
Reserved
PFM
Reserved
PFM
In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is handled
in a controlled slope manner, see Dynamic Voltage Scaling for details. Each regulator has an associated set of SPI bits for
Standby mode set points. By default, the Standby settings are identical to the non-standby settings which are initially defined by
PUMSx programming.
The actual operating mode of the Switching regulators as a function of the STANDBY pin is not reflected through the SPI. In other
words, the SPI will read back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described
previously.
Two tables follow for mode control in the low power Off states. Note that a low power Off activated SWx should use the Standby
set point as programmed by SWxSTBY[4:0]. The activated regulator(s) will maintain settings for mode and voltage until the next
startup event. When the respective time slot of the startup sequencer is reached for a given regulator, its mode and voltage
settings will be updated the same as if starting out of the Off state (except switching regulators active through a low power Off
mode will not be off when the startup sequencer is started).
Table 33. Switching regulator Control In Memory Hold
SWxMHMODE
Memory Hold Operational Mode (45)
0
1
Off
PFM
Notes:
45. For Memory Hold mode, an activated SWx should use the
Standby set point as programmed by SWxSTBY[4:0].
Table 34. Switching regulator Control In User Off
SWxUOMODE
User Off Operational Mode (46)
0
1
Off
PFM
Notes:
46. For User Off mode, an activated SWx should use the Standby
set point as programmed by SWxSTBY[4:0].
In normal steady state operating mode, the SWxPWGD pin is high. When the SWx set point is changed to a higher or lower set
point, the SWxPWGD pin will go low and will go high again when the higher/lower set point is reached.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
46
Functional Block Description
7.5.4.2
Switching Frequency
A PLL generates the switching system clocking from the 32.768 kHz crystal oscillator reference. The switching frequency can be
programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 35.
Table 35. Buck Regulator Frequency
PLLX
Switching Frequency (Hz)
0
1
2 000 000
4 000 000
The clocking system provides a near instantaneous activation when the Switching regulators are enabled or when exiting PFM
operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1.
7.5.4.3
SW1
SW1 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. It can be operated in single phase/dual
phase mode. The operating mode of the switching regulators is configured by the SW1CFG pin. The SW1CFG pin is sampled
at startup.
Table 36. SW1 Configuration
SW1CFG
VCOREDIG
SW1A/B Configuration Mode
Single Phase Mode
Ground
Dual Phase Mode
BP
SW1IN
SW1AMODE
SW1FAULT
ISENSE
CINSW 1A
Controller
SW1
SW1ALX
Driver
LSW 1A
COSW1A
DSW1
GNDSW1A
SW1FB
Internal
Compensation
SPI
Z2
SPI
Interface
Z1
VREF
EA
DAC
BP
SW1BIN
SW1BMODE
ISENSE
CINSW 1B
Controller
SW1BLX
Driver
SW1BFAULT
GNDSW1B
VCOREDIG
SW1CFG
Figure 8. SW1 Single Phase Output Mode Block Diagram
MC34708
Analog Integrated Circuit Device Data
47
Freescale Semiconductor
Functional Block Description
BP
SW1IN
SW1AMODE
SW1FAULT
ISENSE
CINSW1A
Controller
SW1
SW1ALX
Driver
LSW1A
COSW1A
DSW1A
GNDSW1A
Internal
Compensation
SPI
Z2
SPI
Interface
SW1FB
Z1
VREF
EA
DAC
BP
SW1BIN
SW1BLX
SW1BMODE
ISENSE
CINSW1B
Controller
Driver
LSW 1B
COSW 1B
DSW1B
SW1BFAULT
GNDSW1B
SW1CFG
Figure 9. SW1 Dual Phase Output Mode Block Diagram
The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator
will limit the current through cycle by cycle operation and alert the system through the SW1FAULT SPI bit and issue an SCPI
interrupt via the INT pin.
SW1A/B output voltage is SPI configurable in step sizes of 12.5 mV as shown in the table below. The SPI bits SW1A[5:0] set the
output voltage for both SW1A and SW1B.
Table 37. SW1A/B Output Voltage Programmability
SW1A/B
Output (V)
SW1A/B
Output (V)
Set Point SW1A[5:0]
Set Point SW1A[5:0]
0
1
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
0.6500
0.6625
0.6750
0.6875
0.7000
0.7125
0.7250
0.7375
0.7500
0.7625
0.7750
0.7875
0.8000
32
33
34
35
36
37
38
39
40
41
42
43
44
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
2
3
4
5
6
7
8
9
10
11
12
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
Functional Block Description
Table 37. SW1A/B Output Voltage Programmability
SW1A/B
SW1A/B
Output (V)
Set Point SW1A[5:0]
Set Point SW1A[5:0]
Output (V)
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
Table 38. SW1A/B Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SW1A/B BUCK REGULATOR
Operating Input Voltage
• PWM operation, 0 < IL < IMAX
VSW1IN
V
3.0
2.8
-
-
4.5
4.5
• PFM operation, 0 < IL < ILMAX
(47)
Output Voltage Accuracy
VSW1ACC
mV
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients
Nom-25
Nom-25
Nom
Nom
Nom+25
Nom+25
Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode single/dual phase (parallel)
• SW1 in PFM mode
ISW1
mA
A
-
-
-
2000
-
50
Current Limiter Peak Current Detection
• VIN = 3.6 V, Current through Inductor
ISW1PEAK
-
4.0
-
-
Transient Load Change
• 100 mA/µs
ISW1
A
TRANSIENT
-
-
1.0
25
VSW1OS-
mV
Start-up Overshoot, IL = 0
START
MC34708
Analog Integrated Circuit Device Data
49
Freescale Semiconductor
Functional Block Description
Table 38. SW1A/B Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
Turn-on Time
• Enable to 90% of end value IL = 0
tON-SW1
µs
-
-
500
Switching Frequency
• PLLX = 0
fSW1
ISW1Q
SW1
MHz
µA
-
-
2.0
4.0
-
-
• PLLX = 1
Quiescent Current Consumption
• APS MODE, IL=0 mA
-
-
240
15
-
-
• PFM MODE, IL=0 mA
(48)
Efficiency,
%
• PFM, 0.9 V, 1.0 mA
• PWM, 1.1 V, 200 mA
• PWM, 1.1 V, 800 mA
• PWM, 1.1 V, 1600 mA
-
-
-
-
54
75
81
76
-
-
-
-
Notes:
47. Transient loading for load steps of ILMAX/2.
48. Efficiency numbers at VIN = 3.6 V, excludes the quiescent current
7.5.4.4
SW2
SW2 is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator.
BP
SW2IN
SW2MODE
ISENSE
C
INSW 2
Controller
SW2
SW2LX
Driver
LSW2
DSW 2
COSW2
SW2FAULT
SPI
Interface
GNDSW2
Internal
Compensation
SPI
Z2
SW2FB
Z1
VREF
EA
DAC
Figure 10. SW2 Block Diagram
The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator
will limit the current through cycle by cycle operation, alert the system through the SW2FAULT SPI bit, and issue an SCPI
interrupt via the INT pin
SW2 can be programmed in step sizes of 12.5 mV as shown in Table 39.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
Functional Block Description
Table 39. SW2 Output Voltage Programmability
SW2x
SW2 Output
(V)
Set Point SW2[5:0]
Set Point SW2[5:0]
Output (V)
0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
0.6500
0.6625
0.6750
0.6875
0.7000
0.7125
0.7250
0.7375
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
Functional Block Description
Table 40. SW2 Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SW2 BUCK REGULATOR
Operating Input Voltage
• PWM operation, 0 < IL < IMAX
VSW2IN
V
3.0
2.8
-
-
4.5
4.5
• PFM operation, 0 < IL < ILMAX
(49)
Output Voltage Accuracy
VSW2ACC
mV
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients
Nom-25
Nom-25
Nom
Nom
Nom+25
Nom+25
Continuous Output Load Current, VINMIN < BP < 4.65 V
ISW2
mA
• PWM mode
• PFM mode
-
-
-
1000
-
50
Current Limiter Peak Current Detection
• VIN = 3.6 V Current through Inductor
ISW2PEAK
A
A
-
2.0
-
Transient Load Change
• 100 mA/µs
ISW2
TRANSIENT
-
-
-
-
0.500
25
VSW2OS-
mV
µs
Start-up Overshoot, IL = 0
START
Turn-on Time
tON-SW2
• Enable to 90% of end value IL = 0
-
-
500
Switching Frequency
• PLLX = 0
fSW2
-
-
-
MHz
µA
-
-
2.0
4.0
• PLLX = 1
Quiescent Current Consumption
ISW2Q
• APS MODE, IL = 0 mA; device not switching
• PFM MODE, IL = 0 mA; device not switching
-
-
160
15
-
-
(50)
Efficiency
SW2
%
• PFM, 0.9 V, 1.0 mA
• PWM, 1.2 V, 120 mA
• PWM, 1.2 V, 500 mA
• PWM, 1.2 V, 1000 mA
-
-
-
-
54
75
83
78
-
-
-
-
Notes:
49. Transient loading for load steps of ILMAX/2.
50. Efficiency numbers at VIN = 3.6 V, excludes the quiescent current.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
52
Functional Block Description
7.5.4.5
SW3
SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator.
BP
SW3IN
SW3MODE
ISENSE
C
INSW 3
Controller
SW3
SW3LX
Driver
LSW3
DSW3
COSW3
SW3FAULT
SPI
Interface
GNDSW3
Internal
Compensation
SPI
Z2
SW3FB
Z1
VREF
EA
DAC
Figure 11. SW3 Block Diagram
The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator
will limit the current through cycle by cycle operation and alert the system through the SW3FAULT SPI bit and issue an SCPI
interrupt via the INT pin.
SW3 can be programmed in step sizes of 25 mV as shown in Table 41.
Table 41. SW3 Output Voltage Programmability
Set Point
SW3[4:0]
SW3 Output (V)
Set Point
SW3[4:0]
SW3 Output (V)
0
1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MC34708
Analog Integrated Circuit Device Data
53
Freescale Semiconductor
Functional Block Description
Table 42. SW3 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SW3 BUCK REGULATOR
Operating Input Voltage
• PWM operation, 0 < IL < IMAX
VSW3IN
V
3.0
2.8
-
-
4.5
4.5
• PFM operation, 0 < IL < ILMAX
(51)
Output Voltage Accuracy
VSW3ACC
mV
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients
Nom-3%
Nom-3%
Nom
Nom
Nom+3%
Nom+3%
Continuous Output Load Current, VINMIN < BP < 4.65 V
ISW3
mA
• PWM mode
• PFM mode
-
-
-
500
-
50
Current Limiter Peak Current Detection
• VIN = 3.6 V Current through Inductor
ISW3PEAK
A
-
-
1.0
-
-
Transient Load Change
• 100 mA/µs
ISW3
250
mA
TRANSIENT
VSW3OS-
-
-
-
-
25
mV
µs
Start-up Overshoot, IL = 100 mA/µs
START
Turn-on Time
tON-SW3
• Enable to 90% of end value IL = 0
500
Switching Frequency
• PLLX = 0
fSW3
MHz
µA
-
-
2.0
4.0
-
-
• PLLX = 1
Quiescent Current Consumption
ISW3Q
• APSMODE, IL = 0 mA; device not switching
• PFM MODE, IL = 0 mA; device not switching
-
-
160
15
-
-
(52)
Efficiency,
SW3
%
• PFM, 1.2 V, 1.0 mA
• PWM, 1.2 V, 120 mA
• PWM, 1.2 V, 250 mA
• PWM, 1.2V, 500 mA
-
-
-
-
71
79
82
81
-
-
-
-
Notes:
51. Transient loading for load steps of ILMAX/2
52. Efficiency numbers at VIN = 3.6 V, Excludes the quiescent current,
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
54
Functional Block Description
7.5.4.6
SW4
SW4A/B is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. It can be operated in (single phase/
dual phase mode) or as separate independent outputs. The operating mode of the Switching regulator is configured by the
SW4CFG pin. The SW4CFG pin is sampled at startup.
Table 43. SW4A/B Configuration
SW4CFG
Ground
SW4A/B Configuration Mode
Separate Independent Output
Single Phase
VCOREDIG
VCORE
Dual Phase
BP
SWAIN
SW4AMODE
ISENSE
CINSW 4A
Controller
Driver
SW4A
SW4ALX
LSW4A
COSW4A
DSW 4A
SW4AFAULT
GNDSW4A
SW4AFB
Internal
Compensation
SPI
Z2
Z1
VREF
EA
DAC
SPI
Interface
BP
SW4BIN
SW4BLX
SW4BMODE
ISENSE
CINSW 4B
Controller
Driver
SW4B
LSW4B
COSW 4B
DSW4B
SW4BFAULT
GNDSW4B
Internal
Compensation
SPI
Z2
SW4BFB
SW4CFG
Z1
VREF
EA
DAC
Figure 12. SW4A/B Separate Output Mode Block Diagram
MC34708
Analog Integrated Circuit Device Data
55
Freescale Semiconductor
Functional Block Description
BP
SWAIN
SW4AMODE
SW4AFAULT
ISENSE
CINSW4A
Controller
SW4
SW4ALX
Driver
LSW4A
COSW4a
DSW4
GNDSW4A
Internal
SPI
Compensation
Z2
SW4AFB
Z1
VREF
EA
DAC
SPI
Interface
BP
SW4BIN
SW4BMODE
ISENSE
CINSW4B
Controller
SW4BLX
Driver
SW4BFAULT
GNDSW4B
Internal
SPI
Compensation
Z2
SW4BFB
SW4CFG
Z1
VREF
EA
DAC
VCOREDIG
Figure 13. SW4 Single Phase Output Mode Block Diagram
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
56
Functional Block Description
BP
SWAIN
SW4AMODE
ISENSE
CINSW4A
Controller
SW4
SW4ALX
Driver
LSW4A
COSW4A
DSW4A
SW4AFAULT
GNDSW4A
Internal
SPI
Compensation
Z2
SW4AFB
Z1
VREF
EA
DAC
SPI
Interface
BP
SW4BIN
SW4BMODE
ISENSE
CINSW4B
Controller
SW4BLX
DSW4B
Driver
LSW4B
COSW4B
SW4BFAULT
GNDSW4B
Internal
SPI
Compensation
Z2
SW4BFB
SW4CFG
Z1
VREF
EA
DAC
VCORE
Figure 14. SW4 Dual Phase Output Mode Block Diagram
The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator
will limit the current through cycle by cycle operation and alert the system through the SW4xFAULT SPI bit and issue an SCPI
interrupt via the INT pin.
SW4A/B has a high output range (2.5 V, 3.15 V) and a low output range (1.2 V – 1.85 V). The SW4A/B output range is set by the
PUMS configuration at start-up and cannot be changed dynamically by software. This means if the PUMS are set to allow SW4A
to come up in the high output voltage range, the output can only be changed between 2.5 V or 3.15 V. It cannot be programmed
in the low output range. If software sets the SW4AHI[1:0] = 00 when the PUMS is set to come up in the high voltage range, the
output voltage will only go as low as the lowest setting in the high range, which is 2.5 V. If the PUMS are set to start-up in the low
output voltage range, the voltage is controlled through the SW4x[4:0] bits by software, it cannot be programmed into the high
voltage range. When changing the voltage in either the high or low voltage range, the regulator should be forced into PWM mode
to change the voltage.
Table 44. SW4A/B Output Voltage Select
SW4xHI[1:0]
Set point selected by
Output Voltage
00
01
10
11
SW4x[4:0]
SW4xHI[1:0]
SW4xHI[1:0]
Invalid
See Table 45
2.5 V
3.15 V
Invalid
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
Functional Block Description
Table 45. SW4A/B Output Voltage Programmability
SW4x
SW4x
Output (V)
Set Point SW4x[4:0]
Set Point SW4x[4:0]
Output (V)
0
1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
16
17
18
19
20
21
22
23
24
25
26
-
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
-
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
Table 46. SW4A/B Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SW4A/B Buck Regulator
(54)
Operating Input Voltage
• PWM operation, 0 < IL < IMAX
VSW4IN
V
3.0
2.8
-
-
4.5
4.5
• PFM operation, 0 < IL < ILMAX
(53)
Output Voltage Accuracy
VSW4ACC
mV
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients
Nom-3%
Nom-3%
Nom
Nom
Nom+3%
Nom+3%
Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode (separate)
ISW4
mA
A
-
-
-
-
-
500
1000
-
• PWM mode single/dual phase
• PFM mode
50
Current Limiter Peak Current Detection
ISW4PEAK
• VIN = 3.6 V Current through Inductor (separate)
-
-
1.0
2.0
-
-
• Current through Inductor
Transient Load Change, 100 mA/µs
• Single/Dual Phase
• Separate
iSW4
mA
mV
TRANSIENT
-
-
-
-
500
250
VSW4OS-
-
-
25
Start-up Overshoot, IL = 100 mA/µs
START
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
58
Functional Block Description
Table 46. SW4A/B Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
Turn-on Time
• Enable to 90% of end value IL = 0
tON-SW4
µs
-
-
500
Switching Frequency
• PLLX = 0
fSW4
MHz
µA
-
-
2.0
4.0
-
-
• PLLX = 1
ISW4Q
Quiescent Current Consumption
-
-
-
500
260
15
-
-
-
• APS MODE, IL = 0 mA; High output voltage range (VSW4x = 3.15 V
or 2.5 V) device not switching
• APS MODE, IL = 0 mA; Low output voltage range (VSW4x = 1.3 V).
device not switching
• PFM MODE, IL = 0 mA; device not switching
(55)
Efficiency
SW4
%
• PFM, 3.15 V, 10 mA (A)
• PWM, 3.15 V, 50 mA (A)
• PWM, 3.15 V, 250 mA (A)
• PWM, 3.15 V, 500 mA (A)
• PFM, 1.2 V, 10 mA (B)
• PWM, 1.2 V, 50 mA (B)
• PWM, 1.2 V, 250 mA (B)
• PWM 1.2 V, 500 mA (B)
-
-
-
-
-
-
-
-
79
93
92
82
72
71
81
78
-
-
-
-
-
-
-
-
Notes:
53. Transient loading for load steps of ILMAX / 2.
54. When SW4A/B is set to 3.0 V and above the regulator may drop out of regulation when BP nears the output voltage.
55. Efficiency numbers at VIN = 3.6 V, excludes the quiescent current.
MC34708
Analog Integrated Circuit Device Data
59
Freescale Semiconductor
Functional Block Description
7.5.4.7
SW5
SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator.
BP
SW5IN
SW5MODE
ISENSE
CINSW5
Controller
SW5
SW5LX
Driver
LSW5
COSW5
DSW5
SW5FAULT
SPI
GNDSW5
Interface
Internal
SPI
Compensation
Z2
SW5FB
Z1
VREF
EA
DAC
Figure 15. SW5 Block Diagram
The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator
will limit the current through cycle by cycle operation and alert the system through the SW5FAULT SPI bit and issue an SCPI
interrupt via the INT pin.
SW5 can be programmed in step sizes of 25 mV as shown in Table 47. If the software wants to change the output voltage, after
power up the regulator should be forced into PWM mode to change the voltage.
Table 47. SW5 Output Voltage Programmability
SW5
Output (V)
SW5
Output (V)
Set Point SW5[4:0]
Set Point SW5[4:0]
0
1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
16
17
18
19
20
21
22
23
24
25
26
-
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
-
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
-
-
-
-
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
60
Functional Block Description
Table 48. SW5 Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SW5 BUCK REGULATOR
Operating Input Voltage
• PWM operation, 0 < IL < IMAX
VSW5IN
V
3.0
2.8
-
-
4.5
4.5
• PFM operation, 0 < IL < ILMAX
(56)
Output Voltage Accuracy
VSW5ACC
mV
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients
Nom-3%
Nom-3%
Nom
Nom
Nom+3%
Nom+3%
Continuous Output Load Current, VINMIN < BP < 4.5 V
ISW5
mA
• PWM mode
• PFM mode
-
-
-
1000
-
50
Current Limiter Peak Current Detection
• VIN = 3.6 V Current through Inductor
ISW5PEAK
A
-
1.0
-
Transient Load Change
• 100 mA/µs
ISW5
mA
TRANSIENT
-
-
-
-
500
25
VSW5
mV
µs
Start-up Overshoot, IL = 0
OS-START
Turn-on Time
tON-SW5
• Enable to 90% of end value IL = 0
-
-
500
Switching Frequency
• PLLX = 0
fSW5
MHz
µA
-
-
2.0
4.0
-
-
• PLLX = 1
Quiescent Current Consumption
ISW5Q
• APS MODE, IL = 0 mA; device not switching
• PFM MODE, IL = 0 mA; device not switching
-
-
160
15
-
-
(57)
Efficiency
SW5
%
• PFM, 1.8 V, 1.0 mA
• PWM, 1.8 V, 50 mA
• PWM, 1.8 V, 500 mA
• PWM, 1.8 V, 1000 mA
-
-
-
-
80
79
86
82
-
-
-
-
Notes
56. Transient Loading for load Steps of ILMAX/2
57. Efficiency numbers at VIN = 3.6 V, Excludes the quiescent current.
MC34708
Analog Integrated Circuit Device Data
61
Freescale Semiconductor
Functional Block Description
7.5.4.8
Dynamic Voltage Scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the
processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes,
which could cause logic disruptions on their loads.
Preset operating points for SW1A/B and SW2 can be set up for:
• Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are
governed by the DVS stepping rate shown in the following tables.
• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention
voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by
Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 49.
The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2.
Table 49. DVS Control Logic Table for SW1A/B and SW2
STANDBY
Set Point Selected by
0
1
SWx[4:0]
SWxSTBY[4:0]
Table 50. DVS Speed Selection
SWxDVSSPEED[1:0]
Function
00
01 (default)
10
12.5 mV step each 2.0 s
12.5 mV step each 4.0 s
12.5 mV step each 8.0 s
12.5 mV step each 16.0 s
11
The regulators have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined
by the regulator in PWM mode, however, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS
transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 s, SW4A/B
will step in increments of 25 mV per 8.0 s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when
SW4xHI[1:0]=00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability.
The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby
control.
SW1 and SW2 also contain power good outputs to the application processor. The power good signal is an active high signal.
When SWxPWGD is high, it means the regulator’s output has reached its programmed voltage. The SWxPWGD voltage outputs
will be low during the DVS period and if the current limit is reached on the switching regulator. During the DVS period, the over-
current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period, the
SWxPWGD pin will stay low until the current limit condition is removed.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
62
Functional Block Description
Requested
Set Point
Output Voltage
with light Load
Internally
Controlled Steps
Example
Actual Output
Voltage
Output
Voltage
Init ial
Set Point
Actual
Output Voltage
Internally
Possible
Output Voltage
Window
Controlled Steps
Request for
Higher Voltage
Request for
Lower Voltage
Voltage
Change
Request
Initiated by SPI Programming, Standby Control
SWxPWGD
Figure 16. Voltage Stepping with DVS
7.5.5
Boost Switching Regulator
SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power up, operating at 2.0 MHz.
SWBST supplies the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic
leakage path for a boost regulator will cause the output voltage and SWBSTFB to sit at a Schottky drop below the battery voltage
whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky diode,
inductor, and capacitor are required.
VIN
CINBST
SWBSTIN
SWBSTLX
LBST
DBST
SWBSTMODE
SWBSTFAULT
VOBST
Driver
OC
Controller
SPI/I2C
GNDSWBST
RSENSE
Interface
VREFSC
VREFUV
SC
UV
SWBSTFB
Internal
Compensation
COSWBST
Z2
Z1
EA
VREF
Figure 17. Boost Regulator Architecture
SWBST output voltage programmable via the SWBST[1:0] SPI bits as shown in Table 51.
MC34708
Analog Integrated Circuit Device Data
63
Freescale Semiconductor
Functional Block Description
Table 51. SWBST Voltage Programming
Parameter
Voltage
SWBST Output Voltage
SWBST[1:0]
00
01
10
11
5.000 (default)
5.050
5.100
5.150
SWBST can be controlled by SPI programming in PFM, APS, and Auto mode. Auto mode transitions between PFM and APS
mode based on the load current. By default SWBST is powered up in Auto mode.
Table 52. SWBST Mode Control
Parameter
Voltage
SWBST Mode
SWBSTMODE[1:0]
00
01
10
11
Off
PFM
SWBSTSTBYMODE[1:0]
Auto (default)
APS
Table 53. SWBST Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SWITCH MODE SUPPLY SWBST
(58)
Average Output Voltage
• 3.0 V < VIN < 4.5 V, 0 < IL < ILMAX
VSWBST
V
Nom-4%
-
VNOM
Nom+3%
120 mV
Output Ripple
VSWBSTACC
Vp-p
• 3.0 V < VIN < 4.5 V 0 < IL < ILMAX, excluding reverse recovery of
Schottky diode
-
Average Load Regulation
SWBSTACC
mV/mA
mV
• VIN = 3.6 V, 0 < IL < ILMAX
-
-
-
0.5
50
-
-
-
Average Line Regulation
VSWBST
LINEAREG
• 3.0 V < VIN < 4.5 V IL = ILMAX
Continuous Load Current
ISWBST
mA
• 3.0 V < VIN < 4.5 V, VOUT = 5.0 V
380
Peak Current Limit
ISWBSTPEAK
mA
• At SWBSTIN, VIN = 3.6 V
-
-
1800
-
-
VSWBSTOS-
500
mV
ms
Start-up Overshoot, IL = 0 mA
START
Turn-on Time
tON-SWBST
• Enable to 90% of VOUT IL = 0
-
-
-
2.0
-
Switching Frequency
fSWBST
2.0
MHz
mV
Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs
• Maximum transient Amplitude
VSWBST
TRANSIENT
-
-
300
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
64
Functional Block Description
Table 53. SWBST Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs
• Maximum transient Amplitude
VSWBST
mV
TRANSIENT
-
-
-
-
300
500
Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs
• Time to settle 80% of transient
VSWBST
µs
TRANSIENT
Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs
• Time to settle 80% of transient
VSWBST
ms
TRANSIENT
-
-
20
-
Efficiency, IL = ILMAX
SWBST
65
80
%
Bias Current Consumption
• PFM or Auto mode
ISWBSTBIAS
µA
-
-
35
-
NMOS Off Leakage
ILEAK-SWBST
µA
• SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 0
1.0
6.0
Notes:
58. VIN is the low side of the inductor connected to BP.
7.5.6
Linear Regulators (LDOs)
This section describes the linear regulators provided. For convenience, these regulators are named to indicate their typical or
possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regulator
capabilities.
A low power standby mode controlled by STANDBY is provided for the regulators with an external pass device in which the bias
current is aggressively reduced. This mode is useful for deep sleep operation, where certain supplies cannot be disabled, but
active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited
in this mode.
7.5.6.1
General Guidelines
The following applies to all linear regulators, unless otherwise specified.
• Parametric specifications assume the use of low ESR X5R/X7R ceramic capacitors with 20% accuracy and 15% temperature
spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may
require a larger room temperature nominal capacitance value, to meet performance specs over temperature. Capacitor
derating as a function of DC bias voltage requires special attention. Minimum bypass capacitor guidelines are provided for
stability and transient performance. However, larger values may be applied, but performance metrics may be altered and
generally improved and should be confirmed in system applications.
• Regulators with an external PNP transistor require an equivalent resistance (including the ESR) in series with the output
capacitor, as noted in the specific regulator sections.
• Output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static line
regulation, and static load regulation.
• In the Low-power mode, the output performance is degraded. Only those parameters listed in the Low-power mode section
are guaranteed. In this mode, the output current is limited to much lower levels than in the active mode.
• When a regulator gets disabled, the output will be pulled to ground by an internal pull-down. The pull-down is also activated
when RESETB goes low.
MC34708
Analog Integrated Circuit Device Data
65
Freescale Semiconductor
Functional Block Description
7.5.6.2
LDO Regulator Control
The regulators with embedded pass devices (VPLL, VGEN1, and VUSB) have an adaptive biasing scheme thus, there are no
distinct operating modes such as a Normal mode and a Low Power mode. Therefore, no specific control is required to put these
regulators in a Low Power mode.
The external pass regulator (VDAC) can also operate in a normal and low power mode. However, since a load current detection
cannot be performed for this regulator, the transition between both modes is not automatic and is controlled by setting the
corresponding mode bits for the operational behavior desired.
The regulators VUSB2, and VGEN2 can be configured for using the internal pass device or external pass device as explained in
Supplies. For both configurations, the transition between both modes is controlled by setting the VxMODE bit for the specific
regulator. Therefore, depending on the configuration selected, the automatic Low Power mode determines availability.
The regulators can be disabled and the general purpose outputs can be forced low when going into Standby (note that the
Standby response timing can be altered with the STBYDLY function, as described in the previous section). Each regulator has
an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The actual operating mode of the regulators
as a function of STANDBY is not reflected through SPI. In other words, the SPI will read back what is programmed, not the actual
state.
Table 54. LDO Regulator Control (external pass device LDOs)
VxEN
VxMODE
VxSTBY STANDBY(59)
Regulator Vx
0
1
1
1
1
1
X
0
1
X
0
1
X
0
0
1
1
1
X
X
X
0
1
1
Off
On
Low Power
On
Off
Low Power
Notes
59. STANDBY refers to a Standby event as described earlier
For regulators with internal pass devices, the previous table can be simplified by elimination of the VxMODE column.
Table 55. LDO Regulator Control (internal pass device LDOs)
VxEN
VxSTBY
STANDBY (60)
Regulator Vx
0
1
1
1
X
0
1
1
X
X
0
1
Off
On
On
Off
Notes
60. STANDBY refers to a Standby event as described earlier
7.5.6.3
Transient Response Waveforms
The transient load and line response are specified with the waveforms as depicted in Figure 18. Note that where the transient
load response refers to the overshoot only, so excluding the DC shift itself, the transient line response refers to the sum of both
overshoot and DC shift. This is also valid for the mode transition response.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
66
Functional Block Description
VNOM + 0.8V
IMAX
VIN
ILOAD
0 mA
VNOM + 0.3V
10us
10us
1us
1us
VIN Stimulus for Transient Line
Response
ILOAD Stimulus for Transient Load
Response
IL = 0 mA
IL = IMAX
Overshoot
VOUT
Overshoot
VOUT for Transient Load Response
Active Mode
Low Power Mode
Active Mode
Overshoot
VOUT
Mode Transition
Time
Overshoot
IL < ILMAX
IL < ILMAXLP
IL < ILMAX
V
OUT for Mode Transition Response
(VGEN2, VUSB2, VDAC
)
Figure 18. Transient Waveforms
7.5.6.4
Short-circuit Protection
The higher current LDOs, and those most accessible in product applications, include a short-circuit detection and protection
(VDAC, VUSB, VUSB2, VGEN1, and VGEN2). The short-circuit protection (SCP) system includes debounced fault condition
detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product
damage. If an over-current (short-circuit) condition is detected, typically 20% above ILMAX, the LDO will be disabled by resetting
its VxEN bit, while at the same time, an interrupt SCPI will be generated to flag the fault to the system processor. The SCPI
interrupt is maskable through the SCPM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, then not only is no interrupt generated, but also
the regulators will not automatically be disabled upon a short-circuit detection. Note that by default, the REGSCPEN bit is not
set, so at startup, none of the regulators in an overload condition are disabled.
7.5.6.5
VPLL
VPLL is provided for isolated biasing of the application processors PLLs for clock generation, in support of protocol and peripheral
needs. Depending on the application and power requirements, this supply may be considered for sharing with other loads, but
MC34708
Analog Integrated Circuit Device Data
67
Freescale Semiconductor
Functional Block Description
noise injection must be avoided and filtering added, if necessary to ensure suitable PLL performance. The VPLL regulator has a
dedicated input supply pin.
VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail such as from SW5 for the two lower set points
of each regulator VPLL[1:0] = [00], [01]. In addition, when the two upper set points (VPLL[1:0] = [10],[11]) are used, the VINPLL
inputs can be connected to either BP or a 2.2 V nominal external switched mode power supply rail, to improve power dissipation.
Table 56. VPLL Voltage Control
Parameter Value
Function
ILoad max
Input Supply
VPLL[1:0]
00
output = 1.2 V
50 mA
50 mA
50 mA
50 mA
BP or 1.8 V
BP or 1.8 V
01 output = 1.25 V
10 output = 1.50 V
BP or External switch
BP or External switch
11
output = 1.8 V
Table 57. VPLL Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V,-40 C TA 85 C, unless otherwise noted. Typical values at
BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
GENERAL
VINPLL
Characteristic
Min
Typ
Max
Unit Notes
Operating Input Voltage Range
V
• VPLL all settings, BP biased
UVDET
1.75
-
4.5
4.5
4.5
• VPLL [1:0] = 00, 01 (SW5 = 1.8 V)
• VPLL, [1:0] = 10, 11, External Switch
1.8
2.2
2.15
Operating current Load range
IPLL
-
-
50
mA
V
VPLL ACTIVE MODE – DC
Output Voltage VOUT
VPLL
• VINMIN < VIN < VINMAX
• ILMIN < IL < ILMAX
,
VNOM
– 0.05
VNOM
VNOM
+ 0.05
Load Regulation
VPLL-LOPP
VPLL-LIPP
IPLL-Q
mV/mA
mV
• 1.0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX
-
-
-
0.35
5.0
-
-
-
Line Regulation
• VINMIN < VIN < VINMAX For any ILMIN < IL < ILMAX
Quiescent Current
µA
• VINMIN < VIN < VINMAX IL = 0
8.0
VPLL ACTIVE MODE – AC
PSRR, IL = 75% of ILMAX, 20 Hz to 20 kHz
VPLLPSRR
dB
• VIN = UVDET
-
-
70
75
-
-
• VIN = VNOM + 1.0 V, > UVDET
Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0
tON-VPLL
µs
ms
%
-
0.05
-
-
-
120
10
Turn-off Time
tOFF-VPLL
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0
Start-up Overshoot
VPLLOS-
START
• VIN = VINMIN, VINMAX IL = 0
1.0
2.0
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
68
Functional Block Description
Table 57. VPLL Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V,-40 C TA 85 C, unless otherwise noted. Typical values at
BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
50
Max
70
Unit Notes
Transient Load Response
• VIN = VINMIN, VINMAX
VPLL-LO
mV
TRANSIENT
-
-
Transient Line Response
• IL = 75% of ILMAX
VPLL-LI
mV
TRANSIENT
5.0
8.0
7.5.6.6
VREFDDR
VREFDDR is an internal PMOS half supply Voltage Follower. The output voltage is at one half the input voltage. It’s typical
application is as the VREF for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then
utilizes a voltage follower to drive the load.
Table 58. VREFDDR Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
GENERAL
VREFFDDRIN
IREFDDR
Operating Input Voltage Range VINMIN to VINMAX
Operating Current Load Range ILMIN to ILMAX
1.2
0.0
-
-
1.8
10
V
mA
VREFDDR ACTIVE MODE – DC
Output Voltage VOUT
VREFDDR
V
• VINMIN < VIN < VINMAX ILMIN < IL < ILMAX
-
VIN/2
-
6.5
-
(61)
%
Output Voltage tolerance
VREFDDRTOL
• VINMIN < VIN < VINMAX IL = 1.0 mA
-6.5
-
Load Regulation
VREFDDR
mV/mA
µA
LOPP
• 1.0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX
-
-
5.0
8.0
Quiescent Current
IREFDDRQ
• VINMIN < VIN < VINMAX IL = 0
-
VREFDDR ACTIVE MODE – AC
Turn-on Time
tON-VREFDDR
µs
ms
%
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0
-
-
100
10
2.0
-
Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0
tOFF-
VREFDDR
0.05
-
Start-up Overshoot
VREFDDROS
• VIN = VINMIN, VINMAX IL = 0
-
-
1.0
5.0
Transient Load Response
• VIN = VINMIN, VINMAX
VREFDDRL
mV
TRANSIENT
Notes
61. guaranteed at 25 °C only
MC34708
Analog Integrated Circuit Device Data
69
Freescale Semiconductor
Functional Block Description
7.5.6.7
VUSB2
VUSB2 has an internal PMOS pass FET which will support loads up to 65 mA. To support load currents an external PNP is
provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at higher loads and large
differentials between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The
input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. The external PNP
configuration must be committed as a hardwired board level implementation. The recommended PNP device is the ON
Semiconductor™ NSS12100XV6T1G, which is capable of handling up to 250 mW of continuous dissipation, at minimum footprint
and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is ON
Semiconductor NSS12100UW3TCG. For stability reasons, a total resistance of 50 m 20% in series with the output
capacitance is required. The total resistance includes the ESR of the capacitor plus an external resistance provided by a discrete
resistor or PCB circuit trace.
A short-circuit condition will shut down the VUSB2 regulator and generate an interrupt for SCPI, if REGSCPEN is set.
The nominal output voltage of this regulator is SPI configurable, and can be 2.5 V, 2.6 V, 2.75 V, or 3.0 V. The output current
when working with the internal pass FET is 65 mA, and could be up to 350 mA when working with an external PNP.
Table 59. VUSB2 Voltage Control
ILoad max
Output
Voltage
Parameter Value
VUSB2CONFIG = 0 VUSB2CONFIG = 1
Internal Pass FET
External PNP
VUSB2[1:0] 00
2.5 V
2.6 V
65 mA
65 mA
65 mA
65 mA
350 mA
350 mA
350 mA
350 mA
01
10
11
2.75 V
3.00 V
Table 60. VUSB2 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
GENERAL
VUSB2IN
Characteristic
Min
Typ
Max
Unit Notes
VNOM
0.25
+
-
4.5
V
Operating Input Voltage Range VINMIN to VINMAX
Operating Current Load Range ILMIN to ILMAX
• Internal pass FET
IUSB2
mA
0.0
0.0
-
-
65
• External PNP Not exceeding PNP max power
350
Extended Input Voltage Range
VUSB2IN
V
• Performance may be out of specification
UVDET
-
4.5
VUSB2 ACTIVE MODE - DC
Output Voltage VOUT
VUSB2
VUSB2LOPP
VUSB2LIPP
IUSB2Q
V
mV/mA
mV
• VINMIN < VIN < VINMAX ILMIN < IL < ILMAX
VNOM - 3%
VNOM
0.25
8.0
VNOM + 3%
Load Regulation
• 1.0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX
-
-
-
-
Line Regulation
• VINMIN < VIN < VINMAX For any ILMIN < IL < ILMAX
Active Mode Quiescent Current, VINMIN < VIN < VINMAX
• IL = 0, Internal PMOS configuration
µA
-
-
25
30
-
-
• VINMIN < VIN < VINMAX IL = 0, External PNP configuration
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
70
Functional Block Description
Table 60. VUSB2 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VUSB2 LOW POWER MODE - DC
Output Voltage VOUT
VUSB2
V
• VINMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP
VNOM - 3%
0.0
VNOM
-
VNOM + 3%
3.0
Current Load Range ILMINLP to ILMAXLP
IUSB2
mA
µA
Low Power Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
IUSB2Q
-
8.0
10.5
VUSB2 ACTIVE MODE - AC
PSRR, IL = 75% of ILMAX 20 Hz to 20 kHz
VUSB2PSRR
dB
• VIN = VINMIN + 100 mV
• VIN = VNOM + 1.0 V
-
-
30
30
-
-
Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0
tON-VUSB2
ms
ms
%
-
0.05
-
-
-
1.0
10
Turn-off Time
tOFF-VUSB2
• Disable to 10% of initial value VIN = VINMIN, VINMAX IL = 0
Start-up Overshoot
VUSB2OS-
START
• VIN = VINMIN, VINMAX IL = 0
1.0
2.0
Transient Load Response, VIN = VINMIN, VINMAX
• VUSB2=01, 10, 11
x
VUSB2LO
TRANSIENT
-
-
1.0
50
2.0
70
%
• VUSB2=00
mV
Transient Line Response
• IL = 75% of ILMAX
VUSB2LI
mV
µs
TRANSIENT
-
-
5.0
-
8.0
Mode Transition Time
tMOD-VUSB2
• From low power to active and from active to low power
VIN = VINMIN, VINMAX IL = ILMAXLP
100
Mode Transition Response
VUSBMODE
%
RES
• From low power to active and from active to low power
VIN = VINMIN, VINMAX IL = ILMAXLP
-
1.0
2.0
7.5.6.8
VDAC
The primary applications of this power supply is the TV-DAC. However, these supplies could also be used for other peripherals
if one of these functions is not required. Low Power modes and programmable standby options can be used to optimize power
efficiency during deep sleep modes.
An external PNP is utilized for VDAC to avoid excess on-chip power dissipation at high loads and large differentials between BP
and output settings. External PNP devices must always be connected to the BP line in the application. The recommended PNP
device is the ON Semiconductor NSS12100XV6T1G, which is capable of handling up to 250 mW of continuous dissipation at
minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP
device is ON Semiconductor NSS12100UW3TCG. For stability reasons, a total resistance of 100 m 20% in series with the
output capacitance is required. The total resistance includes the ESR of the capacitor plus an external resistance provided by a
discrete resistor or PCB circuit trace.
A short-circuit condition will shut down the VDAC regulator and generate an interrupt for SCPI, if the REGSCPEN bit is set.
The nominal output voltage of this regulator is SPI configurable, and can be 2.5 V, 2.6 V, 2.7 V, or 2.775 V. The maximum output
current along with an external PNP, is 250 mA.
MC34708
Analog Integrated Circuit Device Data
71
Freescale Semiconductor
Functional Block Description
Table 61. VDAC Voltage Control
Parameter
Value
Output Voltage
ILoad max
VDAC
00
01
10
11
2.500 V
2.600 V
2.700 V
2.775 V
250 mA
250 mA
250 mA
250 mA
Table 62. VDAC Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
GENERAL
VDACIN
Characteristic
Min
Typ
Max
Unit Notes
VNOM
0.25
+
-
4.5
V
Operating Input Voltage Range VINMIN to VINMAX
Operating Current Load Range ILMIN to ILMAX
• Not exceeding PNP max power
IDAC
mA
0.0
-
-
250
4.5
Extended Input Voltage Range
VDACIN
V
• Performance may be out of specification
UVDET
VDAC ACTIVE MODE – DC
Output Voltage VOUT
VDAC
VDACLOPP
VDACLIPP
IDACQ
V
mV/mA
mV
• VINMIN < VIN < VINMAX ILMIN < IL < ILMAX
VNOM – 3%
VNOM
0.20
5.0
VNOM + 3%
Load Regulation
• 1.0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX
-
-
-
-
-
-
Line Regulation
• VINMIN < VIN < VINMAX For any ILMIN < IL < ILMAX
Active Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
µA
30
VDAC LOW POWER MODE – DC - VDACMODE=1
Output Voltage VOUT
VDAC
V
• VINMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP
VNOM – 3%
0.0
VNOM
-
VNOM + 3%
3.0
Current Load Range ILMINLP to ILMAXLP
IDAC
mA
µA
Low Power Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
IDACQ
-
8.0
-
VDAC ACTIVE MODE – AC
PSRR - IL = 75% of ILMAX 20 Hz to 20 kHz
VDACPSRR
dB
• VIN = VINMIN + 100 mV
• VIN = VNOM + 1.0 V
-
-
50
50
-
-
Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0
tON-VDAC
ms
ms
-
-
-
1.0
10
Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0
tOFF-VDAC
0.05
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
72
Functional Block Description
Table 62. VDAC Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VDAC ACTIVE MODE – AC (CONTINUED)
Start-up Overshoot
VDACOS-
%
%
START
• VIN = VINMIN, VINMAX IL = 0
-
-
-
-
-
1.0
1.0
5.0
-
2.0
2.0
8.0
100
2.0
Transient Load Response
• VIN = VINMIN, VINMAX
VDACLO
TRANSIENT
Transient Line Response
• IL = 75% of ILMAX
VDACLI
mV
µs
%
TRANSIENT
Mode Transition Time
tMODE-VDAC
• From low power to active VIN = VINMIN, VINMAX IL = ILMAXLP
Mode Transition Response
VDACMODE
RES
• From low power to active and from active to low power
1.0
VIN = VINMIN, VINMAX IL = ILMAXLP
7.5.6.9
VGEN1, VGEN2
General purpose LDOs, VGEN1, and VGEN2, are provided for expansion of the power tree to support peripheral devices, which
could include EMMC cards, WLAN, BT, GPS, or other functional modules. These regulators include programmable set points for
system flexibility. VGEN1 has an internal PMOS pass FET, and is powered from the SW5 buck for an efficiency advantage and
reduced power dissipation in the pass devices. VGEN2 is powered directly from the battery.
VGEN2 has an internal PMOS pass FET, which will support loads up to 50 mA. For higher current capability, drive for an external
PNP is provided. The external PNP is offered to avoid excess on-chip power dissipation at high loads and large differentials
between BP and the output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for
the PNP option. The external PNP device is always connected to the BP line in the application. The recommended PNP device
is the ON Semiconductor NSS12100XV6T1G which is capable of handling up to 250 mW of continuous dissipation at minimum
footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is
the ON Semiconductor NSS12100UW3TCG. For stability, a total resistance of 60 m 20% in series with the output capacitance
is required. The total resistance includes the ESR of the capacitor plus an external resistance provided by a discrete resistor or
PCB circuit trace.
Table 63. VGEN1 Control Register Bit Assignments
Parameter
Value
Output Voltage
ILoad max
VGEN1[2:0]
000
001
010
011
100
101
110
111
1.2000
1.2500
1.3000
1.3500
1.4000
1.4500
1.5000
1.5500
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
The nominal output voltage of VGEN1 is SPI configurable, and can be 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V, 1.45 V, 1.5 V, or
1.55 V.
MC34708
Analog Integrated Circuit Device Data
73
Freescale Semiconductor
Functional Block Description
The nominal output voltage of VGEN2 is SPI configurable, and can be 2.5 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.15 V, or 3.3 V.
The output current when working with the internal pass FET is 50 mA, and could be up to 250 mA when working with an external
PNP.
Table 64. VGEN2 Control Register Bit Assignments
ILoad max
Output
Voltage
Parameter Value
VGEN2CONFIG=0 VGEN2CONFIG=1
Internal Pass FET
External PNP
VGEN2[2:0]
000
001
010
011
100
101
110
111
2.50
2.70
2.80
2.90
3.00
3.10
3.15
3.30
50 mA
50 mA
50 mA
50 mA
50 mA
50 mA
50 mA
50 mA
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
250 mA
Table 65. VGEN1 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
GENERAL
VGEN1IN
Characteristic
Min
Typ
Max
Unit Notes
Operating Input Voltage Range VINMIN to VINMAX
• All settings
V
1.75
0.0
1.8
-
1.85
250
IGEN1
• Operating Current Load Range ILMIN to ILMAX
mA
VGEN1 ACTIVE MODE – DC
Output Voltage VOUT
VGEN1
VGEN1LOPP
VGEN1LIPP
IGEN1Q
V
mV/mA
mV
• VINMIN < VIN < VINMAX ILMIN < IL < ILMAX
VNOM – 3%
VNOM
0.25
5.0
VNOM + 3%
Load Regulation
• 1.0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX
-
-
-
-
-
-
Line Regulation
• VINMIN < VIN < VINMAX For any ILMIN < IL < ILMAX
Active Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
µA
12
VGEN1 LOW POWER MODE - DC
Output Voltage VOUT
VGEN1
V
• VINMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP
VNOM - 3%
0.0
VNOM
-
VNOM + 3%
3.0
Current Load Range ILMINLP to ILMAXLP
IGEN1
mA
µA
Low Power Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
IGEN1Q
-
12
-
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
74
Functional Block Description
Table 65. VGEN1 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VGEN1 ACTIVE MODE - AC
PSRR
VGEN1PSRR
dB
• IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 000-101
• IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 110-111
-
-
50
45
-
-
Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0
tON-VGEN1
ms
ms
%
-
-
-
1.0
10
Turn-off Time
tOFF-VGEN1
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0
0.01
Start-up Overshoot
VGEN1OS-
START
• VIN = VINMIN, VINMAX, IL = 0
-
-
-
-
1.0
1.0
5.0
-
2.0
2.0
8.0
100
Transient Load Response
• VIN = VINMIN, VINMAX
VGEN1LO
%
TRANSIENT
Transient Line Response
• IL = 75% of ILMAX
VGEN1LI
mV
µs
TRANSIENT
Mode Transition Time
tMODE-VGEN1
• From low power to active and from active to low power
VIN = VINMIN, VINMAX IL = ILMAXLP
Mode Transition Response
VGEN
%
1MODERES
• From low power to active and from active to low power
-
1.0
2.0
VIN = VINMIN, VINMAX IL = ILMAXLP
Table 66. VGEN2 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
VGEN2
Characteristic
Min
Typ
Max
Unit Notes
VGEN2IN
V
Operating Input Voltage Range VINMIN to VINMAX
• All settings, BP biased
VNOM
+0.25
-
4.5
Operating Current Load Range ILMI to ILMAX
• Internal Pass FET
IGEN2
mA
mA
V
0.0
0.0
-
-
-
50
250
4.5
Operating Current Load Range ILMIN to ILMAX
• External PNP, Not exceeding PNP max power
IGEN2
Extended Input Voltage Range
VGEN2IN
• BP Biased, Performance may out of specification for output levels
VGEN2 [2:0] = 010 to 111
UVDET
MC34708
Analog Integrated Circuit Device Data
75
Freescale Semiconductor
Functional Block Description
Table 66. VGEN2 Electrical Specification
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VGEN2 ACTIVE MODE - DC
Output Voltage VOUT
VGEN2
VGEN2LOPP
VGEN2LIPP
IGEN2Q
V
mV/mA
mV
• VINMIN < VIN < VINMAX ILMIN < IL < ILMAX
VNOM - 3%
VNOM
0.20
8.0
VNOM + 3%
Load Regulation
• 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX
-
-
-
-
-
-
Line Regulation
• VINMIN < VIN < VINMAX For any ILMIN < IL < ILMAX
Active Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
µA
30
VGEN2 LOW POWER MODE - DC - VGEN2MODE=1
Output Voltage VOUT
VGEN2
V
• VINMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP
VNOM - 3%
0.0
VNOM
-
VNOM + 3%
3.0
Current Load Range ILMINLP to ILMAXLP
IGEN2
mA
µA
Low Power Mode Quiescent Current
• VINMIN < VIN < VINMAX IL = 0
IGEN2Q
-
8.0
-
VGEN2 ACTIVE MODE - AC
PSRR - IL = 75% of ILmax, 20 Hz to 20 kHz
VGEN2PSRR
dB
• VIN = VINMIN + 100 mV
• VIN = VNOM + 1.0 V
-
-
40
50
-
-
Turn-on Time
tON-VGEN22
ms
ms
%
• Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0
-
-
1.0
10
Turn-off Time
tOFF-VGEN2
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0
0.05
-
Start-up Overshoot
VGEN2OS-
START
• VIN = VINMIN, VINMAX IL = 0
-
-
-
-
-
1.0
1.0
5.0
-
2.0
2.0
8.0
100
2.0
Transient Load Response
• VIN = VINMIN, VINMAX
VGEN2LO
%
TRANSIENT
Transient Line Response
• IL = 75% of ILMAX
VGEN2LI
mV
µs
%
TRANSIENT
Mode Transition Time
tMODE-VGEN2
• From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP
Mode Transition Response
VGEN
2MODERES
• From low power to active and from active to low power
1.0
VIN = VINMIN, VINMAX, IL = ILMAXLP
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
76
Functional Block Description
7.6
Battery Management
BATTERY CHARGER NO LONGER SUPPORTED ON
MC34708.
7.7
Analog to Digital Converter
The ADC core is a 10-bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz.
The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain
errors.
7.7.1
Input Selector
The ADC has 16 input channels. Table 67 gives an overview of the characteristics of each of these channels.
Table 67. ADC Inputs
Channel
Signal read
Battery Voltage (BATTISNSN)
Battery Current (BATTISNSN-BATTISNSP)
Application Supply (BPSNS)
Die temperature
Input Level
Scaling
Scaled Version
0
1
0 – 4.8 V
-80 mV – +80 mV (62)
0 to 4.8 V
-40 – 150 °C
Reserved
0 – 6.0 V
/2
x15
0 – 2.4 V
-1.2 to +1.2 V
0 – 2.4 V
1.2 – 2.4 V
Reserved
0 – 2.4 V
Reserved
Reserved
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
2
/2
3
x1
Reserved
4
Reserved
x0.4
USB Voltage (VBUS)
Reserved
5
6
Reserved
Reserved
0 – 3.6 V
Reserved
Reserved
x2/3
Reserved
7
Coincell Voltage
8
ADIN9 (63)
9
0 – 2.4 V
x1
ADIN10 (63)
10
11
12
13
14
15
0 – 2.4 V
x1
ADIN11 (63)
0 – 2.4 V
x1
ADIN12/TSX1 (64)
ADIN13/TSX2 (64)
ADIN14/TSY1 (64)
ADIN15/TSY2 (64)
0 – 2.4 V
x1/x2
x1/x2
x1/x2
x1/x2
0 – 2.4 V
0 – 2.4 V
0 – 2.4 V
Notes
62. Equivalent to -4.0 A to +4.0 A of current with a 20 mOhm sense resistor.
63. Input must not exceed the BP voltage.
64. Input must not exceed BP or VCORE.
Some of the internal signals are first scaled to adapt the signal range to the input range of the ADC. The battery current is
indirectly read out by the voltage drop over the resistor in the charge path and battery path respectively. For details on scaling,
see Dedicated Readings.
MC34708
Analog Integrated Circuit Device Data
77
Freescale Semiconductor
Functional Block Description
Table 68. ADC Input Specification
Parameter
Condition
Min Typ Max Units
Source Impedance
No bypass capacitor at input
-
-
-
-
5.0
30
kOhm
kOhm
Bypass capacitor at input 10 nF
When exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a full scale. It has
to be noted however, that this full scale does not necessarily yield a 1022 DEC reading due to the offsets and calibration applied.
The same applies for when going below the minimum input where the corresponding 0000 DEC reading may not be returned.
7.7.2
Control
The ADC parameters are programmed by the processor via the SPI. When a reading sequence is finished, an interrupt
ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit.
The ADC is automatically calibrated every time the PMIC is powered on.
The ADC is enabled by setting ADEN bit high. The ADC can start a series of conversions through SPI programming by setting
the ADSTART bit. If the ADEN bit is low, the ADC will be disabled and in low power mode. The ADC is automatically calibrated
every time PMIC is powered.
The conversions will begin after a small analog synchronization of up to 30 microseconds, plus a programmable delay from 0
(default) up to 600 S, by programming the bits ADDLY1[3:0]. The ADDLY2[3:0] controls the delay between each of the
conversions from 0 to 600 S. ADDLY3[3:0] controls the delay after the final conversion, and is only valid when ADCONT is high.
ADDLY1, 2, and 3 are set to 0 by default.
Table 69. ADDLYx[3:0]
ADDLYx[3:0]
Delay in s
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
A maximum of 8 conversions will take place when the ADC is started. The register ADSELx[3:0] selects the channel which the
ADC will read and store in the ADRESULTx register. The ADC will always start at the channel indicated in ADSEL0, and read up
to and including the channel set by the ADSTOP[2:0] bits. For example, when ADSTOP[2:0] = 010, it will request the ADC to
read channels indicated in ADSEL0, ADSEL1, and ADSEL2. When ADSTOP[2:0] = 111, all eight channels programmed by the
value in ADSEL0-7 will be read. When the ADCONT bit is set high, it allows the ADC to continuously loop and read the channels
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
78
Functional Block Description
from address 0 to the stop address programmed in ADSTOP. By default, the ADCONT is set low (disabled). In the continuous
mode, the ADHOLD bit will allow the software to hold the ADC sequencer from updating the results register while the ADC results
are read. Once the sequence of A/D conversions is complete, the ADRESULTx results are stored in 4 SPI registers (ADC 4 -
ADC 7).
7.7.3
Dedicated Readings
7.7.3.1
Channel 0 Battery Voltage
The battery voltage is read at the BATTISNSN pin on channel 0. The battery voltage is first scaled as V(BATT)/2 to fit the input
range of the ADC.
Table 70. Battery Voltage Reading Coding
Conversion Code
Voltage at Input ADC in V Voltage at BATTISNSN in V
ADRESULTx[9:0]
1 111 111 111
1 000 010 100
0 000 000 000
2.400
1.250
0.000
4.800
2.500
0.000
7.7.3.2
Channel 1 Battery Current (Optional)
Battery current is only valid after a battery voltage reading. The current flowing into and out of the battery can be read via the
ADC by monitoring the voltage drop over the sense resistor between BATTISNSN and BATTISNSP.
The voltage difference between BATTISNSN and BATTISNSP is amplified to fit the ADC input range as V(BATTISNSP -
BATTISNSN)*15. Since battery current can flow in both directions, the conversion is read out in 2’s complement. Positive
readings correspond to the current flowing into the battery, and negative readings to the current flowing out of the battery.
Table 71. Battery Current Reading Coding
Conversion
Code ADRESULTx [9:0]
Voltage at input
ADC in mV
Current through
20 mOhm in mA
BATTISNSN–BATTISNSP in mV
Current Flow
0 111 111 111
0 000 000 001
0 000 000 000
1 111 111 111
1 000 000 000
1200.00
2.346
0
80
0.156
0
4000
7.813
0
To battery
To battery
-
-2.346
-1200.00
-0.156
-80
7.813
4000
From battery
From battery
The value of the sense resistor used determines the accuracy of the result, as well as the available conversion range. Note that
excessively high values can impact the operating life of the device due to extra voltage drop across the sense resistor.
If battery current sense is required, add a 20 m resistor between the BATTISNSN and BATTISNSP terminal, as shown in
Figure 19.
MC34708
Analog Integrated Circuit Device Data
79
Freescale Semiconductor
Functional Block Description
BP
R1
20m
C1
10u
C2
10u
Battery
Input/Battery
Monitoring
Figure 19. Input Configuration with Battery Current Sense
7.7.3.3
Channel 2 Application Supply
The application supply voltage is read at the BPSNS pin on channel 2. The battery voltage is first scaled as VBPSNS /2 to fit the
input range of the ADC.
Table 72. Application Supply Voltage Reading Coding
Conversion Code
Voltage at Input ADC in V Voltage at BPSNS in V
ADRESULTx[9:0]
1 111 111 111
1 000 010 101
0 000 000 000
2.400
1.250
0.000
4.800
2.500
0.000
7.7.3.4
Channel 3 Die Temperature
The relation between the read out code and temperature is given in Table 73.
Table 73. Die Temperature Voltage Reading
Parameter
Min
Typ
Max
Unit
Die Temperature Read Out Code at 25 °C
Slope temperature change per LSB
Slope error
-
-
-
680
+0.426
-
-
-
Decimal
°C/LSB
%
5.0
The Actual Die Temperature is obtained as follows: Die Temp = 25 + 0.426 * (ADC Code - 680)
7.7.3.5
Channel 4 Reserved
Channel 4 is reserved.
7.7.3.6
Channel 5 VBUS Voltage
The VBUS voltage is measured at the VBUS pin on channel 5. The VBUS voltage is first scaled in order to fit the input range of
the ADC by multiplying by 0.4.
7.7.3.7
Channel 6 and 7 Reserved
Channel 6 is reserved.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
80
Functional Block Description
7.7.3.8
Channel 8 Coin Cell Voltage
The voltage of the coin cell connected to the LICELL pin can be read on channel 8. Since the voltage range of the coin cell
exceeds the input voltage range of the ADC, the LICELL voltage is scaled as V(LICELL)*2/3. See .
Table 74. Coin Cell Voltage Reading Coding
Conversion Code
Voltage at ADC input (V) Voltage at LICELL (V)
ADRESULTx[9:0]
1 111 111 110
1 000 000 000
0 000 000 000
2.400
1.200
0.000
3.6
1.8
0
7.7.3.9
Channel 9-11 ADIN9-ADIN11
There are 3 general purpose analog input channels that can be measured through the ADIN9-ADIN11 pins.
7.7.3.10 Channel 12-15 ADIN12-ADIN15
If the touch screen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are
respectively mapped on ADC channels 12, 13, 14, and 15.
7.7.4
Touch Screen Interface
The touch screen interface provides all circuitry required for the readout of a 4-wire resistive touch screen. The touch screen X
plate is connected to TSX1 and TSX2, while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as a
reference. Several readout possibilities are offered.
If the touchscreen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are
respectively mapped on ADC channels 12, 13, 14, and 15.
Touch Screen Pen detection bias can be enabled via the TSPENDETEN bit in the AD0 register. When this bit is enabled and a
pen touch is detected, the TSPENDET bit in the Interrupt Status 0 register is set and the INT pin is asserted - unless the interrupt
is masked. Pen detection is only active when TSEN is low.
The reference for the touch screen (Touch Bias) is TSREF and is powered from VCORE. During touch screen operation, TSREF
is a dedicated regulator. No loads other than the touch screen should be connected here. When the ADC performs non touch
screen conversions, the ADC does not rely on TSREF and the reference is disabled.
The readouts are designed such that the on chip switch resistances are of no influence on the overall readout. The readout
scheme does not account for contact resistances, as present in the touch screen connectors. The touch screen readings will
have to be calibrated by the user or the factory, where one has to point with a stylus to the opposite corners of the screen. When
reading the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’ for a coordinate equal to X-, and full
scale ‘1023’ when equal to X+. When reading the Y-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’
for a coordinate equal to Y-, and full scale ‘1023’ when equal to Y+. When reading contact resistance, the 10-bit ADC reading
represents the voltage drop over the contact resistance created by the known current source, multiplied by 2.
The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins, while performing a high-impedance reading
on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2, while reading the
TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 pin of the touch screen and through
the TSX2 pin, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by
the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps determine if the touch
screen is touched with a finger or a stylus.
The TSSELx[1:0] allows the application processor to select its own reading sequence. The TSSELx[1:0] determines what is read
during the touch screen reading sequence, as shown in Table 75. The Touchscreen will always start at TSSEL0 and read up to
and including the channel set by TSSEL at the TSSTOP[2:0] bits. For example when TSSTOP[2:0] = 010, it will request the ADC
to read channels indicated in TSSEL0, TSSEL1, and TSSEL2. When TSSTOP[2:0] = 111, all eight addresses will be read.
MC34708
Analog Integrated Circuit Device Data
81
Freescale Semiconductor
Functional Block Description
Table 75. Touch Screen Action Select
TSSELx[1:0]
Signals Sampled
00
01
10
11
Dummy to discharge TSREF cap
X plate
Y –plate
Contact
The touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to
allow for easier noise rejection. The dummy conversion inserted between the different readings allows the references in the
system to be pre-biased for the change in touch screen plate polarity. It will read out as ‘0’.
A touchscreen reading will take precedence over an ADC sequence. If an ADC reading is triggered during a touchscreen event,
the ADC sequence will be overwritten by the Touchscreen data.
The first Touch screen conversion can be delayed from 0 (default) to 600 s by programming the TSDLY1[3:0] bits. The
TSDLY2[3:0] controls the delay between each of the touch screen conversions from 0 to 600 s. TSDLY[2:0] sets the delay after
the last address is converted. TSDLY1, 2, and 3 are set to 0 by default.
Table 76. TSDLYx[3:0]
TSDLYx[3:0]
Delay in uS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
To perform a touch screen reading, the processor must do the following:
• Enable the touch screen with TSEN
• Select the touch screen sequence by programming the TSSEL0-TSSEL7 SPI bits.
• Program the TSSTOP[2:0]
• Program the delay between the conversion via the TSDLY1 and TSDLY2 settings.
• Trigger the ADC via the TSSTART SPI bit
• Wait for an interrupt indicating the conversion is done TSDONEI
• And then read out the data in the ADRESULTx registers
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
82
Functional Block Description
7.7.5
ADC Specifications
Table 77. ADC Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
ADC
ICONVER
VADCIN
Conversion Current
-
1.0
-
mA
V
Converter Core Input Range
• Single ended voltage readings
• Differential readings
0.0
-
-
2.4
1.2
-1.2
Conversion Time per channel
Integral Non-linearity
Differential Non-linearity
Zero Scale Error (Offset)
Full Scale Error (Gain)
Drift over temperature
Turn on/off time
tCONVERT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
3
s
LSB
LSB
LSB
LSB
LSB
s
1
5
10
10
31
tON-OFF-ADC
BATTERY CURRENT READING(65)
Amplifier Gain
19
-2.0
-
20
-
21
2.0
-
Amplifier Offset
mV
Sense Resistor
20
m
DIE TEMPERATURE VOLTAGE READING
Die Temperature Read Out Code at 25 °C
-
-
-
680
0.426
-
-
-
Decimal
°C/LSB
%
Slope temperature change per LSB
Slope error
5.0
Notes
65. Amplifier Bias Current accounted for in overall ADC current drain
MC34708
Analog Integrated Circuit Device Data
83
Freescale Semiconductor
Functional Block Description
7.8
Auxiliary Circuits
7.8.1
General Purpose I/Os
The MC34708 contains four configurable GPIOs for general purpose use. When configured as outputs, they can be configured
as open-drain (OD) or CMOS (push-pull outputs). These GPIOs are low voltage capable (1.2 or 1.8 V). In open drain
configuration these outputs can only be pulled up to 2.5 V maximum.
Each individual GPIO has a dedicated 16-bit control register. Table 78 provides detailed bit descriptions.
Table 78. GPIOLVx Control
SPI Bit
Description
DIR
GPIOLVx direction
0: Input (default)
1: Output
DIN
DOUT
Input state of the GPIOLVx pin
0: Input low
1: Input High
Output state of GPIOLVx pin
0: Output Low
1: Output High
HYS
Hysteresis
0: CMOS in
1: Hysteresis (default)
DBNC[1:0]
GPIOLVx input debounce time
00: no debounce (default)
01: 10 ms debounce
10: 20 ms debounce
11: 30 mS debounce
INT[1:0]
GPIOLVx interrupt control
00: None (default)
01: Falling edge
10: Rising edge
11: Both edges
PKE
ODE
DSE
PUE
Pad keep enable
0: Off (default)
1: On
Open drain enable
0: CMOS (default)
1: OD
Drive strength enable
0: 4.0 mA (default)
1: 8.0 mA
Pull-up/down enable
0: pull-up/down off
1: pull-up/down on (default)
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
84
Functional Block Description
Table 78. GPIOLVx Control
SPI Bit
Description
PUS[1:0]
Pull-up/Pull-down enable
00: 10 K active pull-down
01: 10 K active pull-up
10: 100 K active pull-down
11: 100 K active pull-up (default)
SRE[1:0]
Slew rate enable
00: slow (default)
01: normal
10: fast
11: very fast
x= 0, 1, 2, or 3
7.8.2
PWM Outputs
There are two PWM outputs on the MC34708. PWM1 and PWM2 are controlled by the PWMxDUTY and PWMxCLKDIV registers
shown in Table 79.The base clock will be the 2.0 MHz divided by 32.
Table 79. PWMx Duty Cycle Programming
PWMxDC[5:0]((66)
)
Duty Cycle
000000
000001
…
0/32, Off (default)
1/32
…
010000
…
16/32
…
31/32
011111
1xxxxx
32/32, Continuously On
Notes
66. “x” represent 1 and 2
32.768 kHz Crystal Oscillator RTC Block Description and Application Information
Table 80. PWMx Clock Divider Programming
PWMxCLKDIV[5:0]((67)
)
Duty Cycle
000000
000001
…
Base Clock
Base Clock / 2
…
001111
…
Base Clock / 16
…
111111
Base Clock / 64
Notes
67. “x” represent 1 and 2
MC34708
Analog Integrated Circuit Device Data
85
Freescale Semiconductor
Functional Block Description
7.8.3
General Purpose LED Drivers
To turn on the LEDs, the following bits must be set, CHRLEDxEN = 1, CHRGLEDOVRD =1, THERM bit = 1, and programming
the duty cycle > 0/32.
Table 81. LED Driver Control
THERM
CHRGLEDxEN(68)
CHRGLEDOVRD
CHRGLEDx(68)
x
0 (default)
0
x
1
1
Off
Off
On
Off
1
x
1
0
0
Notes
68. “x” represents R or G
The general purpose LED drivers, CHRGLEDR, and CHRLEDG are independent current sink channels. Each driver channel
features programmable current levels via CHRGLEDx[1:0], as well as programmable PWM duty cycle settings with
CHRGLEDxDC[5:0]. By a combination of level and PWM settings, each channel provides flexible LED intensity control.
Table 82. General Purpose LED Drivers Current Programming
CHRGLEDx[1:0]
CHRGLEDx Current Level (mA)
00
3.5
7.0 (default)
10
01
10
11
12
“x” represents for R, and G
Table 83. General Purpose LED Drivers Duty Cycle Programming
CHRGLEDxDC[5:0]
Duty Cycle
000000
0/32, Off
000001
1/32
…
…
010000
16/32
…
011111
…
31/32
1xxxxx
32/32, Continuously On
“x” represents R, and G
The general purpose LED drivers include ramp up and ramp down patterns implemented in hardware. Ramping is enabled for
each of the drivers using the corresponding CHRGLEDxRAMP bits, only when the repetition rate is 256 Hz.
The ramp itself is generated by increasing or decreasing the PWM duty cycle with a 1/32 step every 1/64 seconds. The ramp
time is therefore a function of the initial set PWM cycle and the final PWM cycle. As an example, starting from 0/32 and going to
32/32 will take 500 ms, while going to from 8/32 to 16/32 takes 125 ms.
Note that the ramp function is executed upon every change in PWM cycle setting. If a PWM change is programmed via the SPI
when CHRGLEDxRAMP = 0, the change is immediate rather than spread out over a PWM sweep.
In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers
through CHRGLEDxPER[1:0], while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling
in the application, the switching edges of the output drivers are softened.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
86
Functional Block Description
Table 84. General Purpose LED Drivers Period Control
CHRGLEDxPER[1:0]
Repetition Rate
Units
00
01
10
11
256
8.0
1.0
1/2
Hz
Hz
Hz
Hz
Table 85. LED Driver Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, -40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V
and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
General Purpose LED Driver
Absolute Accuracy
-
-
-
-
-
-
30
4.0
1.0
%
%
Matching - At 1.0 V, 12 mA
Leakage - CHRGLEDxDC [5:0]=000000
A
7.8.4
Mini/Micro USB Switch
The MC34708 is able to multiplex the 5 pins to support UART and high-speed USB2.0 data communications, a mono/stereo-
audio/microphone headset, or other accessories. To identify what accessory is plugged into the Mini or Micro-USB connector,
the MC34708 supports various detection mechanisms, including the VBUS detection and ID detection. A highly accurate 5-bit
ADC is offered to distinguish the 32 levels of ID resistance, and to identify the button pressed in a cord remote control, while an
Audio Type 1 cable is attached. After identifying the accessory attached, the MC34708 configures itself to support the accessory
and interrupts a host via the INT pin. The processor can evaluate what caused the interrupt via the SPI/I2C bus. The MC34708
is also able to identify some non-supported accessories, such as video cables, phone-powered devices, etc.
MC34708
Analog Integrated Circuit Device Data
87
Freescale Semiconductor
Functional Block Description
GND
ID
To/From
Mini-USB
ID
Detect
Connector
VBUS
VBUS
Detect
M0
M1
VUSB
Regulator
MOTG
VINUSB
VUSB
SWBST (5.0 V boosted supply)
3.3 V USB Analog supply
VINUSB2
VUSB2
BP
VUSB2
Regulator
2.5V USB Analog supply
TXD
RXD
DP
To/from
Mini-USB
Connector
UART
Switches
DM
To/From
Application
Processor
D+
D-
USB
Switches
SPKR
SPKRL
MIC
To/From
Audio IC
Audio
Switches
VBUS
Figure 20. USB Interface
7.8.4.1
Supplies
The MC34708 provides the regulators required to power the PHY in the i.MX50, i.MX51, and i.MX53 processors, which are
VUSB2 (detailed Linear Regulators (LDOs)), and VUSB. The IC also provides the 5.0 V supply for USB OTG operation.
The VUSB regulator is used to supply 3.3 V to the external USB PHY. The input to the VUSB regulator can be supplied from the
VBUS wire of the cable when supplied by a host (PC or Hub), or by the SWBST voltage via the VINUSB pin. The VUSB regulator
is powered from the SWBST boost supply to ensure OTG current sourcing compliance through the normal discharge range of
the main battery. The VUSBSEL SPI bit is used to make the selection between a host or OTG mode operation.
Table 86. VUSB Input Source Control (69)
Parameter
Value
Function
Powered by Host: VBUS powers VUSB regulator (switch M0 closed and M1 open)
VUSBSEL
0
1
OTG mode: SWBST internally switched to supply the VUSB regulator (switch M1 closed, M0 open), and
SWBST will drive VBUS from the VINUSB pin as long as SPI bit OTGEN is set = 1.
Notes
69. VUSBSEL = 1 and OTGEN = 1 only close the switch between the VINUSB and VBUS pins, but do not enable the SWBST boost
regulator (which should be enabled with SWBSTEN = 1)
The VUSB regulator defaults to ON when PUMS4:1 = [0100], and is supplied by the SWBST output. As shown in Figure 20, this
means the M0 and MOTG switches are open, while the M1 switch is closed.
When PUMS4:1 is not equal to [0100], the VUSB regulator can not be enabled unless 5.0 V is present on the VBUS pin. If VBUS
is detected during a cold start, then the VUSB regulator will be enabled and powered ON in the sequence shown in Startup
Requirements, and it will default to be supplied by the VBUS pin. This means switch M0 is closed and switch M1 and MOTG in
Figure 20 are open. If VBUS is not detected at cold start, then the VUSB regulator cannot be enabled. If VBUS is detected later,
the VUSB regulator will be enabled automatically and supplied from the VBUS pin. The VUSBEN SPI bit is initialized at startup,
based on the PUMS4:1 configuration. With PUMS4:1 not equal to [0100], the VUSBEN SPI bit will default to a 1 on power up and
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
88
Functional Block Description
will reset to a 1, when either RESETB is valid or VBUS is invalid. This allows the VUSBEN regulator to be enabled automatically
if the VUSB regulator was disabled by software. With PUMS4:1 equal to [0100], the VUSBEN bit will be enabled in the power up
sequence.
The MC34708 also supports USB OTG mode by supplying 5.0 V to the VBUS pin. The OTGEN SPI bit along with the VUSBSEL
SPI bit, control switching the SWBST to drive VBUS in OTG mode. When OTGEN = 1 and VUSBSEL = 1, SWBST will be driving
the VBUS (switch M1 and MOTG are closed, and the M0 switch is open). When OTG mode is disabled, the switch (MOTG) from
VINUSB to VBUS will be open.
In OTG mode, the VUSB regulator is enabled by setting the VUSBEN SPI bit to a 1. When SWBST is supplying the VBUS pin
(OTG Mode), it will generate a USBDET interrupt. The USBDET interrupt while in OTG mode should not be interpreted as being
powered by the host by software.
Table 87. VUSB/OTG Switch Configuration
Mode
VUSB powered from VBUS pin
VUSB powered from VINUSB pin
Invalid option
OTGEN VUSBSEL Switches Enabled (Closed) Switches Disabled (Open)
0
0
1
1
0
1
0
1
M0
M1, MOTG
M1
M0, MOTG
-
-
OTG Mode (VUSB powered from VINUSB pin and SWBST
M1, MOTG
M0
Table 88. VUSB Electrical Characteristics
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
VUSB REGULATOR
Operating Input Voltage Range VINMIN to VINMAX
• Supplied by VBUS
VUSBIN
V
4.4
-
5.0
-
5.25
5.75
• Supplied by SWBST
Operating Current Load Range ILMIN to ILMAX
IUSB
0.0
-
100
mA
VUSB ACTIVE MODE - DC
Output Voltage VOUT
VUSB
V
mV/mA
mV
• VINMIN < VIN < VINMAX ILMIN < IL < ILMA
VNOM - 4%
3.3
1.0
-
VNOM + 4%
Load Regulation
VUSBLOPP
VUSBLIPP
tOFF-VUSB
• 0 < IL < ILMAX from DM / DP, For any VINMIN < VIN < VINMAX
-
-
-
-
Line Regulation
• VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX
20
1.3
Turn-off Time
sec
• Disable to 0.8 V, per USB OTG specification parameter
VA_SESS_VLD VIN = VINMIN, VINMAX IL = 0
-
VUSB ACTIVE MODE - AC
PSRR - IL = 75% of ILMAX 20 Hz to 20 kHz
VUSBPSRR
dB
• VIN = VINMIN + 100 mV
-
65
-
7.8.4.2
Accessory Identification
The MC34708 monitors both the ID pin and the VBUS pin. When an accessory attachment is detected, the accessory
identification state machine will enter Active mode to start the identification flow. The ID detection state machine will determine
MC34708
Analog Integrated Circuit Device Data
89
Freescale Semiconductor
Functional Block Description
what ID resistor is attached and the Power Supply Type Identification or PSTI circuit will determine what type of power supply is
connected. The 32 kHz crystal must be placed across the XTAL 1 and XTAL2 pins for the accessory identification to work.
An identification conclusion is made when the identification flow is finished. The corresponding bit in the USB Device Type/Status
register is set to indicate the device type, and the ATTACH bit in the USB Interrupt Status register is set to inform the baseband.
If the attached accessory can't be identified, the Unknown_Atta bit in the USB Interrupt Status register is set.
The MC34708 will automatically detect three types of accessories.
1. Recognized and supported. The following accessories are identified and configured automatically: USB port, UART, Audio
Type 1 cable, TTY accessory, USB jig cables, and UART jig cables.
2. Recognized but not supported. The following accessories can be identified but are not supported by the MC34708 PMIC:
A/V cables, Phone-Powered Devices, Audio Type 2 cables, dedicated charger, USB charger, A/V charger, 5-wire type 1
and type 2 chargers. The PMIC will detect that a charger is attached, when the VBUS voltage transitions above the
setpoint, which is defaulted to 4.35 V. When above this threshold for longer than the debounce period (VBUSDB[1:0]), the
USBDET interrupt is generated and USBDETS is set to a one. When the VBUS input falls below the VBUSTL[2:0]
threshold, the USBDET interrupt is generated immediately without any debounce and the USBDETS bit is low. See
Table 89 and Table 90. The USBOVP interrupt will be triggered when an over-voltage on VBUS (>6.5 V typical) is
detected during a device attach. The over-voltage interrupt is debounce by SUP_OVP_DB[1:0] bits on Table 91.
Table 89. VBUS Debounce Times
VBUSDB[1:0]
Debounce Time (ms)
00
01
10
11
0
10
20
30
Table 90. VBUS High/low Detection Threshold
VBUSTH[2:0]
Voltage
VBUSTL[2:0]
Voltage
000
001
010
011
100
101
110
111
4.05
4.15
000
001
010
011
100
101
110
111
3.55
3.65
4.25
3.75
4.35 (default)
4.45
3.85 (default)
3.95
4.55
4.05
4.65
4.15
4.75
4.25
Table 91. Over-voltage Debounce Time SUP_OVP_DB[1:0]
SUP_OVP_DB[1:0]
Debounce Time
00
01
10
11
0 (default 1.0)
2 RTC clock cycles
4 RTC clock cycles
8 RTC clock cycles (default 2.0)
3. Not recognized accessories. All accessories that are not recognized are identified as unknown accessories.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
90
Functional Block Description
Reset
Yes
Yes
Yes
VBUS_DET?
No
Active
(Identification
Flow)
Detection
Delay
Yes
Yes
ID_FLOAT?
ID_FLOAT?
No
No
Standby
DP 0.6V
No
ID_DET_EN
D?
RID < 100?
Yes
Yes
Yes
DM > 0.8V
ADC = 00000
No
Yes
No
Start ADC to
measure RID
No
No
Video cable?
RID = 75?
DM < 0.4V?
Yes
Yes
USB-OTG
No
A/V_CHG = 1
RID = Video
cable?
Yes
No
ID_FLOAT?
USB host
ID_FLOAT
DM 0.6V
No
Video
cable
No
UART jig
Yes RID = UART
cable w/
jig w/ boot?
boot option
ID_DET_EN
D?
Dedicated
Charger
No
DP < 0.4V?
Yes
No
No
ID_DET_EN
D?
Audio
Type 1
Yes RID = Audio
No
Yes
Type 1 ?
UART jig
cable w/o
boot option
RID = UART
jig w/o boot?
Yes
Yes
Yes
No
USB
Charger
RID
=
Yes
Yes
TTY
Converter
Yes
RID = TTY
Converter?
440k?
USB jig
cable w/
No
RID = USB
jig w/ Boot?
Yes
No
boot option
Phone
Powered
Device
No
RID
=
No
102k?
RID
=
5-Wire
Charger
UART
Cable
Yes RID = UART
USB jig
cable w/o
boot option
200k?
No
Cable?
RID = USB
Yes
jig w/o Boot?
No
No
Audio
Type2
Cable
RID = Audio
Type2
Cable?
No
Yes
No
Unknown
No
Stuck Key
Process
Yes
RID = remote
key?
Figure 21. Identification Flow State Diagram
7.8.4.3
Id Identification
A comparator monitors the ID pin impedance to ground. When a resistor less than 1.0 M is connected between the ID line and
the ground, the ID_FLOATS bit in the Interrupt Sense 0 register will be set to 0. When the resistor is removed, the ID_FLOATS
bit will be set to 1. A falling edge of this bit starts the identification flow, and a rising edge starts the detachment detection flow.
The ID_DET_END signal is used to indicate the end of the identification.
After the ID_FLOATS bit is set to 0, the identification flow is started, and an ADC_EN signal is set to enable an ADC conversion.
A 5-bit ID ADC is used to measure the ID resistance. The ADC is also used to identify what button is pressed in a cord remote
control when the attached accessory is an Audio Type 1 cable.
When the conversion completes, an ADC_STATUS bit is set and the ADC result value is sent to the ADC Manual SW/Result
register. The ADC_EN signal is cleared automatically after the conversion finishes.
If the ID resistance is below 2.0 k, the ADC Result is set to 00000. If the ID line is floating, the ADC Result is set to 11111.
7.8.4.4
Stuck Key Identification
When the ADC conversion is finished and the ADC result is found to be a value corresponding to a remote control key of Audio
Type 1 cable, a stuck key process flow will be initiated to determine whether a remote control key is stuck and to inform the
baseband of the stuck key status.
Figure 22 shows the stuck key process flow. If the stuck key is detected to be released within 1.5 s, the flow will return to re-start
the ID identification flow. Otherwise, a Stuck_Key Interrupt is set. When the key is released, a Stuck_Key_RCV Interrupt is
generated, and the identification flow is re-started to determine the ID resistance of the attached cable.
MC34708
Analog Integrated Circuit Device Data
91
Freescale Semiconductor
Functional Block Description
Figure 22. Stuck Key Process Flow Diagram
7.8.4.5
Power Supply Type Identification
The PSTI (Power Supply Type Identification) circuit is used in Active mode to identify the type of the connected power supply.
The PSTI circuit first detects whether the DP and DM pins are shorted. If the DP and DM pins are found to be shorted, the PSTI
circuit will continue to determine whether DP and DM pins are a forward short or reverse short. The detection result, together
with the ID detection result, is used to determine what powered accessory is connected.
The PSTI circuit is shown in Figure 23. Its operation is described as follows.
When the MC34708 detects the VBUS_DET bit is set, the PSTI identification flow starts.
1. Wait for a Detection Delay tD (programmable in the USB Time Delay register).
2. During tD, check to see whether ID_FLOAT = 0. If yes, then wait for the ID_DET_END to be set and check whether the
attached accessory is an A/V cable.
3. If the result is an A/V cable, set the A/V_CHG and ATTACH interrupt bits, as well as the A/V bit in USB Device Type/Status
register, to inform the baseband and finish the identification flow. If not, go to step 4.
4. Enable the PSTI (PSTI_EN set to '1') at t1. When PSTI_EN rises, the SW1 switch is turned on to drive the VDAT_SRC
data source voltage to DP line. In the meantime, the SW2 switch is turned on so the IDAT_SINK current source sinks a
current from the DM line. At t2, the PSTI starts to compare the DM line voltage with references VDAT_REF and VCR_REF.
If the DM line voltage stays above VDAT_REF, but below VCR_REF for 20 ms continuously before t4, which means the
DP and DM pins are shorted, the DP/DM_short signal is set to '1' at t3. Go to step 5. If the DP and DM are not shorted, the
VBUS detection completes at t4 and the VBUS_DET_END is set to '1'. The state machine will go to step 6 to determine
the type of accessory, based on the DM voltage.
5. The state machine checks if the ID pin is floating. If the ID pin is not floating at t3, the PSTI circuit turns off SW1 and SW2,
and the VBUS detection completes. The VBUS_DET_END is set to '1' and the state machine goes to step 6. If the ID pin
is floating at t3, the PSTI circuit turns off SW1 and SW2, and then turns on SW3 and SW4 to force VDAT_SRC to the DM
pin. If the DP pin is between the two thresholds VDAT_REF and VCR_REF for 20 ms continuously before t6, it means the
DP and DM pins are a reverse short.The DP/DM_reverse_short is set to '1' at t5, the SW3 and SW4 are turned off,
VBUS_DET_END is set to '1', and the state machine goes to step 6. If DP and DM are not a reverse short, the VBUS
detection completes at t6, SW3 and SW4 are turned off, the VBUS_DET_END is set to '1', and the state machine goes to
step 6.
6. The state machine decides on the attached accessory, based on the ID identification, and the VBUS identification results.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
92
Functional Block Description
Figure 23. Power Supply Type Identification Circuit Block Diagram
Figure 24. Operating Waveforms for the PSTI Circuit
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
93
Functional Block Description
Table 92. Timing Delays for PSTI Circuit
Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C TA 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
Switching Delay
t1 - t0 (tD in Default Value is TD = 0100)
ms
tD
• TD = 0000
• TD = 0001
• TD = 0010
• TD = 0011
• TD = 0100
• ...
-
-
100
200
300
400
500
...
-
-
-
-
-
-
-
-
...
-
...
-
• TD = 1111
1600
t2 - t1
tSW
tSW
tSW
tSW
20
20
-
-
-
-
-
-
-
-
ms
ms
ms
ms
t3 - t2
t4 - t1
t6 - t3
100
100
The MC34708 contains registers which hold control and status information. The register map and the description of each register
can be found in the SPI/I2C Register Map section. The details of some important control bits are described as follows.
7.8.4.6
Control Functions
7.8.4.6.1
Timing of the Switching Action (WAIT BIT)
If the WAIT bit is '1' when the Attach interrupt bit is set, the MC34708 waits for a WAIT time before turning on the switches. The
WAIT time is programmed by the Switching Wait bits in the Timing Set 2 register. If the WAIT bit is '0' when the Attach interrupt
is generated, then the MC34708 will not turn on the switches until the WAIT bit is set to '1' by the SPI. Both cases are shown in
Figure 25.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
94
Functional Block Description
Figure 25. Operating Waveforms of the Wait Bit
7.8.4.6.2
Automatic Switching OR Manual Switching (Switch_open & Manual S/W Bits)
When a supported accessory is identified, the default behavior of the MC34708 automatically turns on the corresponding signal
switches. The user can also choose to turn on optional signal switches manually. Switch turn on is controlled by the Manual
S/W bit and the Switch_Open bits in the USB Manual SW/Result and USB Control/Device mode registers respectively.
If the Switch_Open bit is '0', the audio, UART, and USB switches are off.
If Manual S/W = 1, which is its reset value, the switches to be turned on and the outputs of the JIG and BOOT pins are determined
automatically by the Device Mode register, which is the identification result. If Manual S/W = 0, the switches to be turned on are
determined by the values of the USB Manual SW/Result register. The relationship between the values of the USB Manual SW/
Result register and the switches to be turned on is found in SPI/I2C Register Map section.
The values of the Switch_Open and Manual S/W bits will not affect the identification flow and the timing of the signal switching
action of the MC34708. The difference between Manual S/W = 1 and Manual S/W = 0 is what switches are turned on. In both
cases, no switches are turned on in Standby mode. If the Manual S/W bit is changed from '1' to '0' while an accessory is attached,
the already automatically turned on switches will be turned off, and the switches selected manually will be turned on. However,
writing the Manual S/W bit back to '1' in Active mode will not change the switches and outputs status. Setting the
Switch_Open = 1, sets the switches according to the Manual S/W bit.
Raw Data (Raw Data Bit)
The RAW DATA bit functions only when the accessory is Audio Type 1, which supports the remote control key. The RAW DATA
bit determines whether to report the ID pin resistance change to the baseband when any key is pressed. When RAW DATA = 1,
the ADC is enabled only when an ID line event is detected, such as when a key is pressed. In this case, the interrupt bits KP,
LKP, or LKR, and the corresponding button bits in Button 1 and Button 2 registers, will be set accordingly. Detailed behavior
information when RAW DATA = 1 can be found in Audio Type 1 Operation Mode.
Audio Device Type 1 - Audio with or without the Remote Control. When RAW DATA = 0, the ADC is enabled periodically to
calculate the ID line resistance. Any change of ADC Result will set the ADC_Change interrupt bit to inform the baseband. The
baseband can read the ADC result via the SPI. The KP, LKP, or LKR, and the button bits, will not set when RAW DATA = 0. The
period of ADC conversion is determined by the Device Wake-up bits in the USB Timing register. All other behaviors of Audio
MC34708
Analog Integrated Circuit Device Data
95
Freescale Semiconductor
Functional Block Description
Type 1 and other accessories will not be affected by the RAW DATA bit. LKR and the button bits will not set when RAW DATA = 0.
The period of ADC conversion is determined by the Device Wake-up bits in the Timing Set 1 register. All other behaviors of Audio
Type 1 and other accessories will not be affected by the RAW DATA bit.
7.8.4.7
Analog and Digital Switches
The signal switches in the MC34708 are shown in Figure 26. These switches are controlled by the identification result when the
Manual S/W = 1, and by the Manual SW/Result register, when the Manual S/W = 0 is in Active mode. The Switch_Open bit
overrides the switch configuration. When the Switch_Open bit is 0, all switches are turned off. The switches for the SPK_L and
SPK_R are capable of passing signals of 1.5 V, referencing to the GND pin voltage. The SPK_L and SPK_R pins are pulled
down to GND via a 100 k resistor respectively, as shown in Figure 26. When the switches are configured automatically by the
identification result, the configuration of the switches vs. the device type is shown in Table 93.
When detachment of an accessory is detected, the MC34708 will return to Standby mode. In Standby mode, regardless of the
Manual S/W = 1 or Manual S/W = 0 state, all signal switches and are off in the Standby mode. The OUT-to-ground FET is turned
on whenever the FET_ON bit is '0'.
DP
RxD
TxD
SW1
DM
SW2
SW3
D+
SW6
SW7
D-
SW4
SPK_R
SPK_L
SW5
VBUS
MIC
M0
M1
VUSB
LDO
MOTG
VINUSB
Figure 26. Analog and Digital Switches
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
96
Functional Block Description
Table 93. Switch Configuration When Controlled by the Device Type Register
Device Type
Audio
USB
UART
USB CHG
Dedicated CHG
On SW#
Off SW
4, 5, 7
3, 6,
1, 2
3, 6
-
-
-
(70)
MOTG, M0
5WT1 CHG
-
Device Type
5WT2 CHG
JIG_USB_ON
JIG_USB_OFF
JIG_UART_ON
JIG_UART
TTY
On SW#
Off SW
-
-
-
-
3, 6
-
3, 6
4, 5, 7
(70)
MOTG, M0
Notes
70. Switches M0, M1, and MOTG are controlled by software by the OTGEN and VUSBSEL bits.
7.8.4.8
Audio Type 1 Operation Mode
Audio Type 1 accessories have the same interface shown in Figure 27, either stereo or mono, with or without a remote control,
or with or without a microphone. When a device, such as a microphone is not connected to the accessory, the corresponding pin
in the mini-USB connector will be left floating. With the normal operation setting of the control bits, the accessory is identified as
an Audio Type 1 device, the analog switches SW4 and SW7 for SPK_R to DP, SPK_L to DM, and SW5 for VBUS to MIC are
turned on, and the MOTG, and M0 switches are turned off, to isolate the VBUS pin.
The MC34708 supports the remote control key for an Audio Type 1 device. If the RAW DATA = 0, the ADC is turned on
periodically to monitor the ID line change caused by the key press. The period is programmed by the Device Wake-up bits. If the
ADC Result changes, the ADC_Change bit in the USB Interrupt Sense register is set to inform the baseband. If the RAW
DATA = 1, a comparator is enabled to monitor the key press. The timing of the key press when RAW DATA = 1 is shown in
Figure 28. If a key is pressed for a time less than 20 ms, the MC34708 ignores it. If the key is still pressed after 20 ms, the
MC34708 starts a timer to count the time during which the key is kept pressed. There are three conditions according to the press
time: Error key press, short key press, and long key press.
1. Error key press: if the key press time is less than TKP, the Error bit in the USB Button register and the short key press bit
KP in USB Interrupt Sense register are set to indicate an error has occurred. The Error bit is reset to '0' when the USB
Button register is read or the next key press occurs. The KP bit is cleared when the Interrupt 1 register is read.
2. Short key press: if the key press time is between TKP and TLKP, the KP bit and the corresponding button bit in USB
Button are set to inform the baseband. If the ADC result is not one of the ADC values of the 13 buttons, the Unknown bit in
the Button register is set. The INT pin is driven high when the key is released and returns to low when the interrupt register
is read. The KP bit is cleared when the USB Interrupt Sense register is read.
3. Long key press: if the key press time is longer than TLKP, the long key press bit LKP in the USB Interrupt Sense register,
and the corresponding button bit, are set to inform the baseband. If the ADC Result is not one of the ADC values of the 13
buttons, the Unknown bit in the USB Button register is set. When the key is released, the long key release bit LKR in the
Interrupt Status 0 register is set to interrupt the baseband again.
Figure 27. Audio Accessory with Remote Control and Microphone
MC34708
Analog Integrated Circuit Device Data
97
Freescale Semiconductor
Functional Block Description
Baseband
AUDIO ACCESSORY
VBUS
MIC
VBUS
SPKR_R
SPKR_L
DP
D+
D-
DM
ID
ID
ADC
ID Det
GND
GND
SHLD
Figure 28. Operation of the Headset with Remote Control and Microphone
TKP
TLKP
20ms
20ms
Key
Press
Error
KP
Button Register read
INT
Interrupt Status 0 Register KP bit written to a one
KP
Interrupt Status 0 Register KP bit written to a one
INT
LKP
LKR
INT
ADC
Time
Interrupt Status 0 Register
LKR bit written to a one
Interrupt Status0 Register
LKP bit written to a one
Figure 29. Remote Control Key Press Timing
The ID detection circuit continues to be ON for detaching detection in the Active mode, and samples the ID line every interval
programmed by the device wake-up bits in the USB Timing register. When the ID_FLOAT rising edge is detected, the Detach bit
in the USB Interrupt Sense register is set to inform the host the accessory is detached. The MC34708 then enters Standby mode.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
98
Functional Block Description
7.8.4.9
JiG Cable USB and UART
The JIG cable is used for test and development and has an ID resistance to differentiate it from a regular USB cable. The Jig
cable has 2 ID resistance values to resemble a USB JIG type1/2, and 2 ID resistance values to resemble a UART JIG type1/2
cable.
7.8.4.9.1
USB JIG Cable 1 or 2
Under normal operation, setting the control bits when the identified accessory is a USB JIG 1 or 2 cable, both the DPLUS to DP,
the DMINUS to DM switches are switched on.
When SW_HOLD = 0, the switching action of DPLUS to DP, and the DMINUS to DM switches are controlled by the WAIT bit. If
WAIT = 1, the signal switches will be turned ON after a WAIT. If WAIT = 0, the signal switches won't be turned on until the WAIT
2
bit is set to '1' by the SPI/I C. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned
on, once the USB JIG cable is identified.
The ID detector and the VBUS detector both monitor the detachment of the USB JIG cable. The ID detection circuit continues to
be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the Detach bit in the Interrupt Status 0 register
is set to inform the host. When the USBDETS is set to '0', which means either the VBUS power is removed or the cable is
detached, the Detach bit is also set to inform the host. The mini USB interface moves to the Standby mode. If the Detach bit is
set, due to the removing only the VBUS or the ID resistance, and the cable is not detached completely, the identification flow will
be triggered again. The ID_FLOAT bit or USBDETS bit still indicate an accessory is connected when the mini USB interface
moves to the Standby mode. All the signal switches are turned off
7.8.4.9.2
UART JIG Cable 1 or 2
Under normal operation, setting the control bits when the identified accessory is a UART JIG cable 1 or 2, both the RxD to DP
and the TxD to DM switches are switched on.
When SW_HOLD = 0, the switching action of RxD to DP, and the TxD to DM switches, are controlled by the WAIT bit. If WAIT = 1,
the signal switches will be turned on after a WAIT time. If WAIT = 0, the signal switches won't be turned on until the WAIT bit is
2
set to '1' by the SPI/I C. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned on,
once the UART JIG cable is identified.
The ID detection comparator continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the
Detach bit in the Interrupt Status 0 register is set to inform the host the accessory is detached. The mini USB interface then enters
the Standby mode.
7.8.4.10 TTY Operation Mode
A TTY converter is a type of audio accessory. It has its own ID resistance. When a TTY converter is attached, this sets the TTY
bit in the USB Device Type register and the Attach interrupt bit in the Interrupt Status 0 register. During normal operation, when
setting the control bits, the automatic switch configuration of the TTY converter, is similar to that of an Audio Type 1 accessory.
The SPK_R to DP switch, and MIC to VBUS switch are turned on, but the SPK_L to DM switch can only be turned on when
TTY_SKPL bit in USB Control register is manually set to 1. In addition, the MOTG, and M0 switches are turned off to isolate the
VBUS pin.The TTY accessory doesn’t support the remote control key. The Power Save mode operation and the detachment
detection are the same as those of the Audio Type 1 device.
7.8.4.11 UART Operation Mode
During normal operation, when setting the control bits, when the identified accessory is a UART cable, both the RxD and the TxD
switches are switched on (see Figure 30).
The ID detection comparator continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the
Detach bit in the USB interrupt Sense register, is set to inform the host the accessory is detached. The MC34708 USB detection
then enters Standby mode.
MC34708
Analog Integrated Circuit Device Data
99
Freescale Semiconductor
Functional Block Description
Baseband
UART
Cable
UART
Interface
VBUS
Det
VBUS
VBUS
RxD
TxD
DP
D+
D-
UART
DM
ID
ID
ADC
ID Det
`
GND
GND
SHLD
Figure 30. UART Operation
7.8.4.12 USB Host (PC or HUB) Operation Mode
When the attached accessory is a USB host or hub, the ID pin floats. During normal operation, when setting the control bits, both
the D PLUS to DP and the D MINUS to DM switches are switched on (see Figure 31). The mini USB interface sets the bit USB
in the USB Device type register.
When SW_HOLD = 0, the switching action of D+ to DP and the D- to DM switches, are controlled by the WAIT bit. If WAIT = 1,
the signal switches will be turned on after a WAIT time. If WAIT = 0, the signal switches won't be turned on until the WAIT bit is
set to '1' by the SPI. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned on once
the USB host is identified.
After the DPLUS to DP and the DMINUS to DM switches are turned on, the baseband can pull the DPLUS signal high to start
the USB attaching sequence.
The detachment is detected by the falling edge of the USBDETS signal. When the USBDETS falls, the Detach bit is set to inform
the baseband. The MC34708 USB detection then enters the Standby mode.
Baseband
USB
Cable
USB
Host
VBUS
Det
VBUS
VBUS
5V
DPLUS
DP
D+
D-
USB Xcvr
DMINUS
DM
ID
ID
ADC
ID Det
GND
GND
SHLD
Figure 31. USB Operation
7.8.4.13 USB charger or Dedicated Charger Operation Mode
When the attached accessory is a USB Charger or Dedicated Charger, the MC34708 enables the bit USB Charge or the
Dedicated CHG in the USB Device type register. During normal operation when setting of the control bits, the D PLUS and D
MINUS switches are turned on for the USB Charger, but not for the Dedicated Charger.
The VBUS detector is used to monitor the detachment of the charger. The falling edge of USBDETS is an indication of charger
detachment. Unplugging the mini-USB connector and unplugging the AC side, both lead to the same detachment conclusion.
The Detach bit is set to inform the host. The MC34708 USB detection then enters the Standby mode.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
100
Functional Block Description
7.8.4.14 5-Wire Charger or A/V Charger Mode
When the attached accessory is a 5-Wire Charger or A/V Charger, the MC34708 enables the appropriate device type 5.0 W CHG
or A/V in the USB device type register.
The VBUS detector is used to monitor the detachment of the charger. The falling edge of USBDETS is an indication of the charger
detachment. Both unplugging the mini-USB connector and unplugging the ac side lead to the same detachment conclusion. The
Detach bit is set to inform the host. Then the MC34708 USB detection enters the Standby mode.
7.8.4.15 Device Detect Mode
When the Manual SW_B bit is set to 1, the MC34708 automatically detects what device is attached.
7.8.4.16 Unknown Accessory Operation Mode
When an unknown accessory is attached, the ID_FLOAT bit is cleared or the USBDETS bit is set to '1'. Only the Unknown_Atta
bit is set to interrupt the baseband. The Attach bit is not set to distinguish the unknown accessory from the known accessory. No
other actions are taken.The falling edge of the USBDETS or the rising edge of the ID_FLOAT signals can trigger the detachment
detection. The Detach bit is set to inform the detachment of the unknown accessory. The USB detection then enters the Standby
mode.
7.8.4.17 Software Reset
The USB detection supports a software reset, which is realized by writing the Reset bit in the USB Control register to 1. The
consequence of the software reset is the same as the hardware reset. All register bits reset by the Mini-USB will be reset.
Table 94. ID Detection Thresholds
UID Pin External
UID Pin Voltage (71)
0.18 * VCORE < UID < 0.77 * VCORE
0 < UID < 0.12 * VCORE
IDFLOATS IDGNDS IDFACTORYS
Accessory
Connection
Non-USB accessory is attached (per
CEA-936-A spec)
0
0
1
1
1
0
1
1
0
0
0
1
Resistor to Ground
A type plug (USB default slave) is
attached (per CEA-936-A spec)
Grounded
Floating
B type plug (USB Host, OTG default
master or no device) is attached.
0.89 * VCORE < UID < VCORE
3.6 V < UID (1)
Voltage Applied
Notes
Factory mode
71. UID maximum voltage is 5.25 V
7.8.4.18 ID Resistance Value Assignment
The ID resistors used are standard 1% resistors. Table 95 lists the complete 32 ID resistor assignment. Those with the Assigned
Functions filled are ones already used with special functions. The ones reserved can be assigned to other functions.
Table 95. ID Resistance Assignment
Item#
ADC Result
ID Resistance K
Assignment
0
1
2
3
4
00000
00001
00010
00011
00100
<1.9
2.0
Reserved
S0
S1
S2
S3
2.604
3.208
4.014
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
101
Functional Block Description
Table 95. ID Resistance Assignment
Item#
ADC Result
ID Resistance K
Assignment
5
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
4.820
6.03
8.03
10.03
12.03
14.46
17.26
20.5
24.07
28.7
34.0
40.2
49.9
64.9
80.6
102
S4
S5
6
7
S6
8
S7
9
S8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S9
S10
S11
S12
UART JIG Cable 2
UART JIG Cable 1
USB JIG Cable 2
USB JIG Cable 1
Factory Mode
Audio Type 2
PPD
121
Reserved
UART
150
200
5W Type 1
Reserved
Reserved
A/V
255
301
365
442
5W Type 2
Reserved
TTY
523
619
1000
-
Audio Type 1
ID float
The remote control architecture is illustrated in Figure 32. The recommended resistors for the remote control resistor network are
given in Table 96.
ID
R1
R2
R13
R3
…...
R14
SEND/END
HOLD
/
GND
Figure 32. Remote Control Architecture
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
102
Functional Block Description
Table 96. ID Remote Control Values
Resistor
Standard Value K
ID Resistance
R1
R2
2.0
0.604
0.604
0.806
0.806
1.21
2.0
2.0
2.604
3.208
4.014
4.82
R3
R4
R5
R6
6.03
R7
8.03
R8
2.0
10.03
12.03
14.46
17.26
20.5
R9
2.0
R10
R11
R12
R13
R14
2.43
2.8
3.24
3.57
590/976
24.07
614/1000
7.8.4.19 USB Interface Electrical Specifications
Table 97. USB Interface Electrical Characteristics
Characteristics noted under conditions BP = 3.6 V, V
= 5.0 V, -40 C T 85 C, unless otherwise noted. Typical values
A
BUS
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
Power Input
Detection Module Quiescent Current
I
A
DM
• In Standby mode
-
-
-
-
2
3
• When accessory is attached & INT_MASK = ‘1’
125
550
850
160
650
1000
• In Active mode (V < V
)
DD
BUS
• In Active mode (V < V
)
DD
BUS
VBUS Supply Quiescent Current
• In VBUS OTG
I
mA
VBUS
-
-
-
-
1.5
0.5
• In Active mode - Audio or TTY
Accessory Detect Switch
SPK_L and SPK_R Switches
• On resistance (20 Hz to 470 kHz)
• Matching between channels
R
-
-
-
30
3.0
0.3
-
-
-
SPK_ON
R
SPK_ONMCT
• On resistance flatness (from -1.2 to 1.2 V)
R
SPK_ONFLT
D+ and D- Switches
R
• On resistance (0.0 Hz to 240 MHz)
• Matching between channels
• On resistance flatness (from 0.0 to 3.3 V)
-
-
-
5.0
0.1
8.0
1.0
0.4
USB_ON
R
USB_ONMCT
R
USB_ONFLT
0.02
MC34708
Analog Integrated Circuit Device Data
103
Freescale Semiconductor
Functional Block Description
Table 97. USB Interface Electrical Characteristics
Characteristics noted under conditions BP = 3.6 V, V
= 5.0 V, -40 C T 85 C, unless otherwise noted. Typical values
BUS
A
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic
Min
Typ
Max
Unit Notes
RxD and TxD Switches
• On resistance
R
-
-
-
-
60
UART_ON
R
UART_ONFLT
• On resistance flatness (from 0.0 to 3.3 V)
MIC Switches
6.0
• On resistance (at 1.5 V MIC bias voltage)
R
-
-
75
150
-
MIC_ON
Pull-Down Resistors between SPK_L or SPK_R Pins to GND
R
100
k
PD_AUDIO
Signal Voltage Range
• MIC
V
-
-
-
-
1.5
1.5
3.6
• SPK_L, SPK_R
• D+, D-, RxD, TxD
-1.5
-0.3
PSRR - From BP (100 mVrms) to DP/DM Pins
V
dB
%
A_PSRR
• 20 Hz to 20 kHz with 32/16 load.
-
-
-
-
-
-
-
-
-60
0.05
-50
Total Harmonic Distortions
T
HD
• 20 Hz to 20 kHz with 32/16 load.
Crosstalk between Two Channels
V
dB
dB
A_CT
• 20 Hz to 20 kHz with 32/16 load.
Off Channel Isolation
• Less than 1.0 MHz
V
A_ISO
-100
Power Supply Type Identification
Data Source Voltage
V
V
DAT_SRC
• Loaded by 0~200 μA
0.5
0.0
0.3
0.8
0.6
-
0.7
200
0.4
1.0
Data Source Current
Data Detect Voltage
Car Kit Detect Voltage
I
μA
V
DAT_SRC
V
0.35
0.9
DAT_REF
V
V
CR_REF
Data Sink Current
I
μA
DAT_SINK
• DM pin is biased between 0.15 to 3.0 V
65
-
100
8.0
135
-
DP, DM Pin Capacitance
C
R
pF
DP/DM
DP, DM Pin Impedance
M
DP/DM
• All switches are off (Switch_Open = 0)
-
50
-
ID Detection
ID FLOAT Threshold
• Detection threshold
V
V
FLOAT
-
-
2.3
20
-
-
t
ID FLOAT Detection Deglitch Time
ms
ID_FLOAT
IID
Pull-up Current Source
μA
• When ADC Result is 1xxxx
• When ADC Result is 0xxxx
1.9
2.0
32
2.1
30.4
33.6
Video Cable Detection
• Detection current
I
1.0
1.2
50
1.4
mA
mV
mV
VCBL
• Detection voltage low threshold
• Detection voltage high threshold
V
-
-
-
-
VCBL_L
VCBL_H
V
118
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
104
Functional Block Description
Table 97. USB Interface Electrical Characteristics
Characteristics noted under conditions BP = 3.6 V, V
= 5.0 V, -40 C T 85 C, unless otherwise noted. Typical values
A
BUS
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
ID Detection (Continued)
t
Video Cable Detection Time (Video Cable Detection Current Source On
Time)
ms
ms
-
-
20
20
-
-
VCBL
t
Key Press Comparator Debounce Time
RMTCON_DG
7.9
Serial Interfaces
The IC contains a number of programmable registers for control and communication. The majority of registers are accessed
2
through a SPI interface in a typical application. The same register set may alternatively be accessed with an I C interface muxed
2
on SPI pins. Table 98 describes the muxed pin options for the SPI and I C interfaces; further details for each interface mode
follow.
2
Table 98. SPI / I C Bus Configuration
Pin Name
SPI Mode Functionality
I2C Mode Functionality
(72)
(73)
CS
Configuration
SPI Clock
, Chip Select
Configuration
2
CLK
SCL: I C bus clock
MISO
MOSI
Notes
Master In, Slave Out (data output)
Master Out, Slave In (data input)
SDA: Bi-directional serial data line
(74)
A0 Address Selection
72. CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.
2
2
73. CS tied to VCOREDIG at Cold Start, configures the interface for I C mode; the pin is not used in I C mode, other than for configuration.
2
74. In I C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.
7.9.1
SPI Interface
The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers, the resources of
the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on
external signals.
2
Because the SPI interface pins can be reconfigured for reuse as an I C interface, a configuration protocol mandates the CS pin
is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). The state of CS is latched in during
2
the initialization phase of a Cold Start sequence, ensuring the I C bus is configured before the interface is activated. With the CS
pin held low during startup (as would be the case if connected to the CS driver of an unpowered processor due to the integrated
pull down), the bus configuration will be latched for SPI mode.
The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The
addressable register map spans 64 registers of 24 data bits each. The map is not fully populated, but it follows the legacy
conventions for bit positions corresponding to common functionality with previous generation FSL products.
7.9.1.1
SPI Interface Description
For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first.
This is followed by one dead bit to allow for more address decode time. The MC34708 will clock the above bits in on the rising
edge of the SPI clock. The 24 data bits are then driven out on the MISO pin on the falling edge of the SPI clock, so the master
can clock them in on the rising edge of the SPI clock.
MC34708
Analog Integrated Circuit Device Data
105
Freescale Semiconductor
Functional Block Description
For each MOSI SPI transfer, first a one is written to the write/read_b bit if this SPI transfer is to be a write. A zero is written to the
write/read_b bit if this is to be a read command. If a zero is written, then any data sent after the address bits are ignored and the
internal contents of the field addressed do not change when the 32nd CLK is sent.
For a SPI write, the first bit sent to the MC34708 must be a one, indicating a SPI write cycle. Next the six bit address is sent MSB
first. This is followed by one dead bit to allow for more address decode time. The data is then sent MSB first. The SPI data is
written to the SPI register whose address was sent at the start of the SPI cycle on the falling edge of the 32nd SPI clock.
Additionally, whenever a SPI write cycle is taking place the SPI read data is shifted out for the same address as for the write
cycle. Next the 6-bit address is written, MSB first. Finally, data bits are written, MSB first. Once all the data bits are written then
the data is transferred into the actual registers on the falling edge of the 32nd CLK.
The CS polarity is active high. The CS line must remain high during the entire SPI transfer. For a write sequence it is possible for
the written data to be corrupted, if after the falling edge of the 32nd clock the CS goes low before it's required time. CS can go
low before this point and the SPI transaction will be ignored, but after that point the write process is started and cannot be
stopped, because the write strobe pulse is already being generated, and CS going low may cause a runt pulse that may or may
not be wide enough to clock all 24 data bits properly. To start a new SPI transfer, the CS line must be toggled low and then pulled
high again. The MISO line will be tri-stated while CS is low.
The register map includes bits that are read/write, read only, read/write “1” to clear (i.e., Interrupts), and clear on read, reserved,
and unused. Refer to the SPI/I2C Register Map and the individual subcircuit descriptions to determine the read/write capability
of each bit. All unused SPI bits in each register must be written to as zeroes. A SPI read back of the address field and unused
bits are returned as zeroes. To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded
at the beginning of the SPI sequence.
CS
CLK
MOSI
MISO
Write_En
Address5
Addr ess 4
Address3
Address2
Address 1
Address 0
“Dead Bit”
Data 23
Data 23
Data 22
Data 22
Data 1
Data 1
Data 0
Data 0
Figure 33. SPI Transfer Protocol Single Read/Write Access
CS
Preamble
First Address
Preamble Another Address
24 Bits Data
24 Bits Data
MOSI
MISO
24 Bits Data
24 Bits Data
Figure 34. SPI Transfer Protocol Multiple Read/Write Access
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
106
Functional Block Description
7.9.1.2
SPI Timing Requirements
The following diagram and table summarize the SPI timing requirements. The SPI input and output levels are set via the SPIVCC
pin, by connecting it to the desired supply. This would typically be tied to SW5 and programmed for 1.80 V. The strength of the
MISO driver is programmable through the SPIDRV [1:0] bits. See Thermal Protection Thresholds for detailed SPI electrical
characteristics.
t
CLKPER
CS
t
t
DKHIGH
SELLOW
t
t
CLKLOW
SELSU
t
SELHLD
CLK
t
WRTSU
t
WRTHLD
MOSI
MISO
t
t
RDDIS
RDSU
t
RDHLD
t
RDEN
Figure 35. SPI Interface Timing Diagram
(75)
Table 99. SPI Interface Timing Specifications
Parameter
Description
T min (ns)
Time CS has to be high before the first rising edge of CLK
Time CS has to remain high after the last falling edge of CLK
Time CS has to remain low between two transfers
t
15
15
SELSU
t
SELHLD
SELLOW
t
15
Clock period of CLK
t
38
CLKPER
Part of the clock period where CLK has to remain high
Part of the clock period where CLK has to remain low
Time MOSI has to be stable before the next rising edge of CLK
Time MOSI has to remain stable after the rising edge of CLK
Time MISO will be stable before the next rising edge of CLK
Time MISO will remain stable after the falling edge of CLK
Time MISO needs to become active after the rising edge of CS
Time MISO needs to become inactive after the falling edge of CS
t
15
CLKHIGH
t
15
CLKLOW
t
4.0
4.0
4.0
4.0
4.0
4.0
WRTSU
t
WRTHLD
t
RDSU
t
RDHLD
t
RDEN
t
RDDIS
Notes
75. This table reflects a maximum SPI clock frequency of 26 MHz.
MC34708
Analog Integrated Circuit Device Data
107
Freescale Semiconductor
Functional Block Description
7.9.2
I2C Interface
2
7.9.2.1
I C Configuration
2
When configured for I C mode, the interface may be used to access the complete register map previously described for SPI
access. Since SPI configuration is more typical, references within this document will generally refer to the common register set
2
as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I C mode when configured as such.
2
The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I C mode for the interface is
configured by hard-wiring the CS pin to VCOREDIG on the application board. The state of CS is latched in during the initialization
2
phase of a Cold Start sequence, so the I CS bit is defined for bus configuration before the interface is activated. The pull-down
2
on CS will be deactivated if the high state is detected (indicating I C mode).
2
In I C mode, the MISO pin is connected to the bus as an open drain driver, and the logic level is set by an external pull-up. The
2
part can function only as an I C slave device, not as a host.
2
7.9.2.2
I C Device ID
2
I C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for
bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product
supports 7-bit addressing only; support is not provided for 10-bit or general Call addressing.
2
Because the MOSI pin is not utilized for I C communication, it is reassigned for pin programmable address selection by
2
hardwiring to VCOREDIG or GND at the board level when configured for I C mode. MOSI will act as Bit 0 of the address. The
2
I C address assigned to FSL PM ICs (shared amongst our portfolio) is given as follows:
00010-A1-A0, the A1 and A0 bits are allowed to be configured for either 1 or 0. The A1 address bit is internally hardwired as a
“0”, leaving the LSB A0 for board level configuration. The designated address then is defined as: 000100-A0.
2
7.9.2.3
I C Operation
2
The I C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s
operation. (Exceptions to the standard are noted to be 7-bit only addressing, and no support for general Call addressing) Timing
diagrams, electrical specifications, and further details on this bus standard, is available on the internet, by typing
2
“I C specification” in the web search string field.
2
Standard I C protocol utilizes bytes of 8 bits, with an acknowledge bit (ACK) required between each byte. However, the number
of bytes per transfer is unrestricted. The register map is organized in 24 bit registers which corresponds to the 24 bit words
2
supported by the SPI protocol of this product. To ensure that I C operation mimics SPI transactions in behavior of a complete 24
bit word being written in one transaction, software is expected to perform write transactions to the device in 3-byte sequences,
beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third
consecutive byte.
2
Failure to complete a 3-byte write sequence will abort the I C transaction and the register will retain its previous value. This could
be due to a premature STOP command from the master, for example.
2
I C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and
3-bytes will be sent out unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host
sends a master command packet after driving the start condition. The device will respond to the host if the master command
packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK
to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the
transaction.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
108
Functional Block Description
Packet
Type
Device
Address
Register Address
7
0
0
7
0
0
Host SDA
(to MISO)
Continuation
START
0
R / W
A
C
K
A
C
K
Slave SDA
(from MISO)
Host can
also drive
another
Start instead
of Stop
Packet
Type
Master Driven Data
( byte 2 )
Master Driven Data
( byte 1)
Master Driven Data
( byte 0 )
23
16
15
8
7
0
Host SDA
(to MISO)
STOP
A
C
K
A
C
K
A
C
K
Slave SDA
(from MISO)
2
Figure 36. I C 3-byte Write Example
Packet
Type
Device
Address
Register Address
Device Address
23
16
0
15
0
8
7
0
Host SDA
(to MISO)
Continuation
START
0
START
1
R /W
R /W
A
C
K
A
C
K
A
Slave SDA
(from MISO)
C
K
Host can also
drive another
Start instead of
Stop
PMIC Driven Data
PMIC Driven Data
PMIC Driven Data
Packet
Type
( byte 2)
( byte 1 )
( byte 0)
A
C
K
A
C
K
Host SDA
(to MISO)
NA
CK
STOP
23
16
15
8
7
0
Slave SDA
(from MISO)
2
Figure 37. I C 3-byte Read Example
MC34708
Analog Integrated Circuit Device Data
109
Freescale Semiconductor
Functional Block Description
7.9.3
SPI/I2C Specification
2
Table 100. SPI/I C Electrical Characteristics
Characteristics noted under conditions BP = 3.6 V, V
= 5.0 V, -40 C T 85 C, unless otherwise noted. Typical values
BUS
A
at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit Notes
SPI Interface Logic IO
Input Low CS
V
0.0
1.1
0.0
-
-
-
0.4
V
V
V
INCSLO
Input High CS
V
SPIVCC+0.3
0.3*SPIVCC
INCSHI
V
/
INMOSILO
Input Low, MOSI, CLK
V
INCLKLO
V
V
/
0.7*SPIVCC
-
SPIVCC+0.3
V
V
INMOSIHI
Input High, MOSI, CLK
INCLKHI
Output Low MISO, INT
V
/
MISOLO
V
INTLO
• Output sink 100 A
0.0
-
-
0.2
Output High MISO, INT
V
/
SPIVCC-0.2
SPIVCC
V
MISOHI
V
INTHI
• Output source 100 A
SPIVCC Operating Range
V
1.75
-
3.6
V
CC-SPI
MISO Rise and Fall Time, CL = 50 pF, SPIVCC = 1.8 V
• SPIDRV [1:0] = 00
t
ns
MISOET
-
-
-
-
6.0
2.5
3.0
2.0
-
-
-
-
• SPIDRV [1:0] = 01 (default)
• SPIDRV [1:0] = 10
• SPIDRV [1:0] = 11
7.10 Configuration Registers
7.10.1 Register Set structure
The general structure of the register set is given in the following table. Expanded bit descriptions are included in the following
functional sections for application guidance. For brevity’s sake, references are occasionally made herein to the register set as
2
the “SPI map” or “SPI bits”, but note that bit access is also possible through the I C interface option so such references are
implied as generically applicable to the register set accessible by either interface.
Table 101. Register Set
Register
Register
Register
Register
0
1
2
3
4
5
6
7
8
Interrupt Status 0
Interrupt Mask 0
16
17
18
19
20
21
22
23
24
Memory A
Memory B
32
33
34
35
36
37
38
39
40
Regulator Mode 0
GPIOLV0 Control
GPIOLV1 Control
GPIOLV2 Control
GPIOLV3 Control
USB Timing
48
49
50
51
52
53
54
55
56
ADC5
ADC6
Interrupt Sense 0
Interrupt Status 1
Interrupt Mask 1
Memory C
ADC7
Memory C
Input Monitoring
Supply Debounce
VBUS monitoring
LED Control
PWM Control
Unused
RTC Time
Interrupt Sense 1
Power Up Mode Sense
Identification
RTC Alarm
RTC Day
USB Button
RTC Day Alarm
Regulator 1 A/B Voltage
USB Control
Regulator Fault Sense
USB Device Type
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
110
Functional Block Description
Table 101. Register Set
Register
Register
Register
Register
9
Reserved
Reserved
25
26
27
28
29
30
31
Regulator 2 & 3 Voltage
Regulator 4 A/B Voltage
Regulator 5 Voltage
Regulator 1 & 2 Mode
Regulator 3, 4 and 5 Mode
Regulator Setting 0
41
42
43
44
45
46
47
Unused
Unused
ADC 0
ADC 1
ADC 2
ADC 3
ADC4
57
58
59
60
61
62
63
Unused
Unused
Unused
Unused
Unused
Unused
Unused
10
11
12
13
14
15
Reserved
Unused
Power Control 0
Power Control 1
Power Control 2
SWBST Control
7.10.2 Specific Registers
7.10.2.1 IC and Version Identification
The IC and other version details can be read via the identification bits. These are hardwired on the chip and described in
Table 102.
Table 102. IC Revision Bit Assignment
Identifier
Value
Purpose
Represents the full layer revision
XXX
FULL_LAYER_REV[2:0]
•
Pass 2.4 = 010
Represents the metal layer revision
XXX
000
METAL_LAYER_REV[2:0]
FIN[2:0]
•
Pass 2.4 = 100
FIN version
• Pass 2.4 = 000
FAB Version
• Pass 2.4 = 000
000
FAB[2:0]
7.10.2.2 Embedded Memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[23:0],
MEMB[23:0], MEMC[23:0], and MEMD[23:0] is maintained by the coin cell when the main battery is deeply discharged, removed,
or contact-bounced (i.e., during a power cut). The contents of the embedded memory are reset by RTCPORB. A known pattern
can be maintained in these registers to validate confidence in the RTC contents when power is restored after a power cut event.
Alternatively, the banks can be used for any system need for bit retention with coin cell backup.
MC34708
Analog Integrated Circuit Device Data
111
Freescale Semiconductor
Functional Block Description
7.10.3 SPI/I2C Register Map
The complete SPI bitmap is given in Table 103.
2
Table 103. SPI/I C Register Map Legend
Register Types
Register Values
Reset
R/W
R/WM
W1C
RO
Read / Write
0 = low
Bits Loaded at Cold Start based on PUMS Value
Bits Reset by POR or Global Reset
RESETB / Bits Reset by POR or Global
Bits Reset by RTCPORB or Global Reset
Bits Reset by POR or OFFB
Read / Write Modify
Write One to Clear
Read Only
1 = High
X = Variable
NU
Not Used
Bits Reset by RTCPORB Only
MUSBRST
2
Table 104. SPI/I C Register Map
Register
Name
Address
Type
Default
MC34708 SPI Register Map
23
22
21
20
19
18
17
16
UNKNOWN_
ATTA
STUCK_KEY_RCV STUCK_KEY ADC_CHANGE
LKR
LKP
KP
DETACH
Interrupt
Status 0
15
14
-
13
LOWBATT
5
12
-
11
10
9
8
0
W1C h00_00_00
ATTACH
-
-
-
-
Table 105
7
-
6
4
3
USBDET
19
2
TSPENDET
18
1
TSDONEI
17
0
ADCDONEI
16
-
USBOVP
21
-
23
22
20
STUCK_KEY_RCV_
M
ADC_CHANGE_ UNKNOWN_
STUCK_KEY_M
LKR_M
LKP_M
KP_M
DETACH_M
M
ATTA_M
Interrupt
Mask 0
15
14
-
13
12
11
10
9
8
1
R/W hFF_FF_FF
Table 106
ATTACH_M
LOWBATTM
-
4
-
-
-
-
7
-
6
5
USBOVPM
21
3
USBDETM
19
2
TSPENDETM
18
1
TSDONEM
17
0
ADCDONEM
16
-
-
23
22
20
MUSB_ADC_
STATUS
VBUS_DET_
ENDS
-
-
ID_GNDS
ID_FLOATS ID_DET_ENDS
-
Interrupt
Sense 0
15
14
13
12
11
10
9
8
2
RO
h00_00_00
Table 107
-
-
-
-
-
-
-
-
0
7
6
5
4
3
USBDETS
19
2
1
-
-
USBOVPS
-
-
-
-
23
22
21
20
GPIOLV3I
12
18
17
16
-
-
-
GPIOLV2I
11
GPIOLV1I
GPIOLV0I
SCPI
8
Interrupt
Status 1
15
14
13
10
9
WARMI
1
3
W1C h00_00_00
CLKI
THERM130
THERM125
THERM120
4
THERM110
3
MEMHLDI
PCI
0
Table 108
7
6
5
2
RTCRSTI
SYSRSTI
WDIRESTI
PWRON2I
20
PWRON1I
19
-
TODAI
17
1HZI
16
23
22
21
18
-
15
-
-
GPIOLV3M
12
GPIOLV2M
11
GPIOLV1M
GPIOLV0M
9
SCPM
8
Interrupt
Mask 1
14
THERM130M
6
13
THERM125M
5
10
4
R/W h5F_77_FB
CLKM
7
THERM120M
4
THERM110M
3
MEMHLDM
WARMM
1
PCM
0
Table 109
2
RTCRSTM
SYSRSTM
WDIRESTM
PWRON2M
PWRON1M
-
TODAM
1HZM
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
112
Functional Block Description
2
Table 104. SPI/I C Register Map
23
22
21
20
19
18
17
16
-
-
-
GPIOLV3S
GPIOLV2S
GPIOLV1S
GPIOLV0S
-
Interrupt
Sense 1
15
14
13
12
11
10
9
8
5
RO hXX_XX_XX
CLKS
THERM130S
THERM125S
THERM120S
THERM110S
-
-
-
Table 110
7
-
6
-
5
4
3
2
1
0
-
PWRON2S
PWRON1S
-
-
-
23
-
22
-
21
20
19
18
17
16
-
-
-
-
-
-
Power Up
Mode Sense
15
-
14
-
13
12
11
10
9
8
6
RO
h00_00_XX
-
-
-
-
-
-
Table 111
7
6
5
4
PUMS4S
20
3
PUMS3S
19
2
1
0
-
-
PUMS5S
PUMS2S
PUMS1S
ICTESTS
23
22
21
18
17
-
16
PAGE[4:0]
-
-
15
-
14
-
13
-
12
-
11
3
10
FAB[2:0]
2
9
8
FIN[2]
0
Identification
Table 112
7
RW
h00_00_08
7
6
5
4
1
FIN[1:0]
FULL_LAYER_REV[2:0]
METAL_LAYER_REV[2:0]
23
22
21
20
-
19
-
18
-
17
-
16
-
REGSCPEN
-
-
Regulator
Fault Sense
15
14
13
12
11
10
9
8
8
RW h00_XX_XX
-
-
-
VGEN2FAULT VGEN1FAULT VDACFAULT
VUSB2FAULT
VUSBFAULT
Table 113
7
SWBSTFAULT
23
6
SW5FAULT
22
5
SW4BFAULT
21
4
SW4AFAULT
20
3
SW3FAULT
19
2
SW2FAULT
18
1
0
SW1FAULT
16
RSVD
17
-
-
15
14
6
13
5
12
11
10
9
8
9-11
12
13
14
Reserved
NU hXX_XX_XX
7
4
-
3
-
2
1
0
-
-
-
-
-
23
22
-
21
20
-
19
-
18
17
16
-
-
-
-
-
15
14
-
13
12
-
11
-
10
9
8
Unused
NU
h00_00_00
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
COINCHEN
VCOIN[2:0]
-
-
-
Power
Control 0
15
-
14
-
13
-
12
-
11
10
9
8
R/W h00_00_40
-
-
PCUTEXPB
-
Table 118
7
6
5
4
3
2
1
0
-
CLK32KMCUEN USEROFFCLK
DRM
20
-
USEROFFSPI
WARMEN
PCCOUNTEN
PCEN
23
-
22
21
-
19
-
18
-
17
-
16
-
-
Power
Control 1
15
14
13
12
11
10
9
8
R/W h00_00_00
PCMAXCNT[3:0]
PCCOUNT[3:0]
Table 119
7
6
5
4
3
2
1
0
PCT[7:0]
MC34708
Analog Integrated Circuit Device Data
113
Freescale Semiconductor
Functional Block Description
2
Table 104. SPI/I C Register Map
23
22
14
6
21
ON_STBY_LP
13
20
19
-
18
10
17
9
16
-
STBYDLY[1:0]
-
CLKDRV[1:0]
15
-
12
WDIRESET
4
11
-
8
Power
Control 2
15
R/W h40_03_00
SPIDRV[1:0]
STANDBYINV
GLBRSTTMR[1:0]
Table 120
7
5
3
2
1
0
PWRON2
RSTEN
PWRON2DBNC[1:0]
PWRON1BDBNC[1:0]
-
PWRON1RSTEN RESTARTEN
23
15
7
22
21
13
5
20
MEMA[23:16]
19
18
10
2
17
16
14
6
12
11
3
9
8
Memory A
Table 121
16
17
18
19
20
21
22
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
R/W h01_FF_FF
R/W h00_00_00
MEMA[15:8]
MEMA[7:0]
4
1
0
23
15
7
22
14
6
21
13
5
20
19
11
3
18
10
2
17
9
16
8
MEMB[23:16]
12
Memory B
Table 122
MEMB[15:8]
4
1
0
MEMB[7:0]
23
15
7
22
14
6
21
13
5
20
19
11
3
18
10
2
17
9
16
8
MEMC[23:16]
12
Memory C
Table 123
MEMC[15:8]
4
1
0
MEMC[7:0]
23
15
7
22
14
6
21
13
5
20
19
11
3
18
10
2
17
9
16
8
MEMD[23:16]
12
Memory D
Table 124
MEMD[15:8]
4
1
0
MEMD[7:0]
23
22
21
13
5
20
12
4
19
18
10
2
17
9
16
TOD[16]
8
RTCCALMODE[1:0]
RTCCAL[4:0]
15
7
14
11
RTC Time
Table 125
TOD[15:8]
6
3
1
0
TOD[7:0]
23
RTCDIS
15
22
SPARE
14
21
SPARE
13
20
19
SPARE
11
18
SPARE
10
17
SPARE
9
16
TODA[16]
8
SPARE
12
RTC Alarm
Table 126
TODA[15:8]
7
6
5
4
3
2
1
0
TODA[7:0]
23
-
22
-
21
-
20
-
19
18
-
17
-
16
-
-
15
-
14
13
12
11
10
9
8
RTC Day
Table 127
DAY[14:8]
7
6
5
4
3
2
1
0
DAY[7:0]
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
114
Functional Block Description
2
Table 104. SPI/I C Register Map
23
-
22
-
21
-
20
-
19
18
-
17
-
16
-
-
RTC Day
Alarm
15
-
14
13
12
11
10
9
8
23
24
25
26
27
28
29
30
R/W h00_7F_FF
R/WM hXX_XX_XX
R/WM hXX_XX_XX
R/WM hXX_XX_XX
R/WM h00_XX_XX
R/W hEX_XX_8X
R/W hXX_XX_XX
R/WM h00_XX_XX
DAYA[14:8]
Table 128
7
6
5
4
20
12
4
3
2
1
17
9
0
16
8
DAYA[7:0]
23
15
7
22
14
6
21
19
11
3
18
10
2
RSVD[5:0]
RSVD[5:4]
Regulator
1A/B Voltage
13
RSVD[3:0]
SW1ASTBY[5:2]
Table 129
5
1
0
SW1ASTBY[1:0]
SW1A[5:0]
23
-
22
14
6
21
13
5
20
SW3STBY[4:0]
12
19
11
3
18
10
2
17
-
16
SW3[4]
8
Regulator
2&3 Voltage
15
9
SW3[3:0]
SW2STBY[5:2]
Table 130
7
23
15
7
4
20
12
4
1
17
9
0
SW2STBY[1:0]
SW4BHI[1:0]
SW2[5:0]
22
14
6
21
13
5
19
18
10
16
SW4BSTBY[4:0]
SW4B[4]
Regulator 4
Voltage
11
8
SW4B[3:0]
SW4AHI[1:0]
SW4ASTBY[4:3]
Table 131
3
2
1
0
SW4ASTBY[2:0]
SW4A[4:0]
23
22
-
21
-
20
19
-
18
-
17
-
16
-
-
15
-
-
Regulator 5
Voltage
14
13
12
11
10
9
-
8
-
SW5TBY[4:0]
Table 132
7
6
-
5
-
4
3
2
1
0
-
SW5[4:0]
18
23
PLLX
15
22
21
20
19
17
16
PLLEN
14
SW2DVSSPEED[1:0]
SW2UOMODE SW2MHMODE
SW2MODE[3:2]
Regulator
1, 2 Mode
13
-
12
-
11
-
10
-
9
8
-
SW2MODE[1:0]
-
Table 133
7
6
5
4
3
2
1
SW1AMODE[3:0]
17
0
SW1DVSSPEED[1:0]
SW1AUOMODE SW1AMHMODE
23
SW5UOMODE
15
22
21
13
5
20
12
4
19
18
10
16
SW5MHMODE
SW5MODE[3:0]
SW4BUOMODE SW4BMHMODE
Regulator
3, 4, 5 Mode
14
11
9
8
SW4BMODE[3:0]
SW4AUOMODE SW4AMHMODE
SW4AMODE[3:2]
Table 134
7
6
3
2
1
0
SW4AMODE[1:0]
SW3UOMODE SW3MHMODE
SW3MODE[3:0]
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
Regulator
Setting 0
15
-
14
-
13
-
12
11
10
9
8
VGEN2[2]
0
VUSB2[1:0]
VPLL[1:0]
Table 135
7
6
5
4
3
2
1
VGEN2[1:0]
VDAC[1:0]
-
VGEN1[2:0]
MC34708
Analog Integrated Circuit Device Data
115
Freescale Semiconductor
Functional Block Description
2
Table 104. SPI/I C Register Map
23
22
-
21
-
20
19
-
18
-
17
-
16
-
-
-
SWBST
Control
15
14
-
13
-
12
11
-
10
-
9
-
8
-
31
32
33
34
35
36
37
38
R/WM h00_00_XX
R/WM h0X_XX_XX
R/W h00_18_0A
R/W h00_18_0A
R/W h00_18_0A
R/W h00_18_0A
R/W hXX_XX_XX
R/C hXX_XX_XX
-
-
4
Table 136
7
6
5
3
2
1
0
SPARE
SWBSTSTBYMODE[1:0]
SPARE
20
SWBSTMODE[1:0]
SWBST[1:0]
23
22
21
19
18
VUSB2EN
10
17
16
-
-
-
VUSB2MODE VUSB2STBY
VUSB2CONFIG
VPLLSTBY
Regulator
Mode 0
15
14
13
12
11
9
8
VPLLEN
VGEN2MODE
VGEN2STBY
VGEN2EN
VGEN2CONFIG VREFDDREN
-
-
Table 137
7
6
5
4
3
VUSBEN
19
2
1
0
RSVD
VDACMODE
VDACSTBY
VDACEN
VUSBSEL
VGEN1STBY
VGEN1EN
23
22
-
21
20
18
-
17
-
16
SPARE
8
-
-
-
-
GPIOLV0
Control
15
14
13
12
11
10
9
SRE1
SRE0
6
PUS1
PUS0
PUE
3
DSE
2
ODE
1
PKE
0
Table 138
7
5
4
INT1
INT0
22
DBNC1
DBNC0
HYS
19
DOUT
18
DIN
17
-
DIR
16
23
21
20
-
-
-
-
-
-
SPARE
8
GPIOLV1
Control
15
14
13
12
11
10
9
SRE1
SRE0
6
PUS1
PUS0
PUE
3
DSE
2
ODE
1
PKE
0
Table 139
7
5
4
INT1
INT0
22
DBNC1
DBNC0
HYS
19
DOUT
18
DIN
17
-
DIR
16
23
21
20
-
-
-
-
-
-
SPARE
8
GPIOLV2
Control
15
14
13
12
11
10
9
SRE1
SRE0
6
PUS1
PUS0
PUE
3
DSE
2
ODE
1
PKE
0
Table 140
7
5
4
INT1
INT0
22
DBNC1
DBNC0
HYS
19
DOUT
18
DIN
17
-
DIR
16
23
21
20
-
-
-
13
-
12
-
-
SPARE
8
GPIOLV3
Control
15
14
11
10
9
SRE1
SRE0
6
PUS1
5
PUS0
4
PUE
3
DSE
2
ODE
1
PKE
0
Table 141
7
INT1
INT0
22
DBNC1
21
DBNC0
20
HYS
19
DOUT
18
DIN
17
DIR
16
23
READVALID
15
-
-
-
TD[3:0]
14
13
12
11
3
10
9
8
0
USB Timing
Table 142
SWITCHING_WAIT[3:0]
Long_KEY_PRESS[3:0]
7
6
5
4
2
1
KEY_PRESS[3:0]
DEVICE_WAKE_UP[3:0]
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
13
12
S12
4
11
S11
3
10
S10
2
9
8
USB Button
Table 143
UNKNOWN
Error
5
S9
1
S8
0
7
6
S7
S6
S5
S4
S3
S2
S1
S0
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
116
Functional Block Description
2
Table 104. SPI/I C Register Map
23
22
14
21
20
19
18
17
16
VBUS_SWITCHIN
G[1]
READVALID
DM_SWITCHING[2:0]
DP_SWITCHING[2:0]
15
13
12
11
-
10
-
9
8
USB control
Table 144
39
R/W hXX_XX_XX
VBUS_SWITCHING[
0]
-
SW_HOLD
VOTGEN
CLK_RST
7
ACTIVE
23
6
5
TTY_SPKL
21
4
RESET
20
3
2
1
0
RST
22
SWITCH_OPEN RAWDATA
MANUAL_SW_B
WAIT
19
18
-
17
16
USB_ADC_ID_RESULTS[4:0]
UKN_DEVICE
ID_FACTORY
15
UARTJIG2
7
14
13
USBJIG2
5
12
USBJIG1
4
11
AVCHRG
3
10
A/V
2
9
TTY
1
8
PPD
0
USB Device
Type
40
R
hXX_XX_XX
UARTJIG1
Table 145
6
DEDICATED_
CHG
USB OTG
USB CHG
5W CHG
UART
USB
AUDIO_TYPE_2 AUDIO_TYPE_1
23
22
21
20
19
18
-
17
16
-
-
-
-
-
-
-
41
to
15
14
13
12
11
10
-
9
8
Unused
NU
h00_00_00
-
-
-
-
-
-
-
42
7
6
5
4
3
2
1
0
-
23
-
22
-
-
-
19
-
-
-
21
20
18
17
16
SPARE
15
SPARE
14
SPARE
TSPENDETEN
SPARE
11
TSSTOP[2:0]
13
12
TSEN
4
10
SPARE
2
9
8
THERM
0
ADC 0
43
44
45
46
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
Table 147
TSHOLD
7
TSCONT
6
TSSTART
SPARE
3
DIETEMP_EN
5
ADSTOP[2:0]
21
1
ADSTART
17
SPARE
23
ADHOLD
19
ADCONT
18
ADEN
16
22
14
20
12
4
TSDLY3[3:0]
TSDLY2[3:0]
15
7
13
5
11
3
10
2
9
8
0
ADC 1
Table 148
TSDLY1[3:0]
ADDLY3[3:0]
6
1
17
9
ADDLY2[3:0]
22
ADSEL5[3:0]
14
ADSEL3[3:0]
ADDLY1[3:0]
ADSEL4[3:0]
ADSEL2[3:0]
ADSEL0[3:0]
23
15
7
21
13
5
20
12
4
19
11
3
18
10
2
16
8
ADC 2
Table 149
6
1
0
ADSEL1[3:0]
23
22
14
6
21
13
5
20
19
18
10
2
17
9
16
TSSEL7[1:0]
TSSEL6[1:0]
TSSEL5[1:0]
TSSEL4[1:0]
15
7
12
4
11
3
8
0
ADC 3
Table 150
TSSEL3[1:0]
TSSEL2[1:0]
TSSEL1[1:0]
TSSEL0[1:0]
1
ADSEL7[3:0]
ADSEL6[3:0]
MC34708
Analog Integrated Circuit Device Data
117
Freescale Semiconductor
Functional Block Description
2
Table 104. SPI/I C Register Map
23
15
22
14
6
21
20
19
18
10
2
17
16
8
ADRESULT1[9:2]
13
12
-
11
9
ADC 4
47
48
49
50
51
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
R/W h00_00_00
R/W h01_31_7E
Table 151
ADRESULT1[1:0]
-
ADRESULT0[9:6]
7
5
4
3
1
-
0
-
ADRESULT0[5:0]
23
15
22
14
6
21
20
19
18
10
2
17
16
ADRESULT3[9:2]
13
12
-
11
9
8
ADC 5
Table 152
ADRESULT3[1:0]
-
ADRESULT2[9:6]
7
5
4
3
1
-
0
-
ADRESULT2[5:0]
23
15
22
14
6
21
20
19
18
10
2
17
16
ADRESULT5[9:2]
13
12
-
11
9
8
ADC 6
Table 153
ADRESULT5[1:0]
-
ADRESULT4[9:6]
7
5
4
3
1
-
0
-
ADRESULT4[5:0]
23
15
22
14
6
21
20
19
18
10
2
17
16
ADRESULT7[9:2]
13
12
-
11
9
8
ADC 7
Table 154
ADRESULT7[9:2]
-
ADRESULT6[9:6]
7
5
4
3
1
0
-
ADRESULT6[5:0]
-
23
-
22
14
6
21
20
12
4
19
11
18
10
17
16
-
-
-
Input
Monitoring
15
13
9
8
0
-
-
Table 155
7
5
3
CHREN
19
2
-
1
-
LOWBATT[1:0]
21
-
23
-
22
-
20
-
18
17
16
-
-
DIE_TEMP_DB[1:0]
15
14
13
12
11
3
10
9
8
Supply
Debounce
52
R/W h00_03_FD
CHRGLED
OVRD
SUP_OVP_DB[1:0]
-
-
Table 156
7
6
5
4
2
1
17
9
0
-
VBUSDB[1:0]
VBATTDB[1:0]
18
-
-
23
-
22
-
21
20
12
4
19
11
3
16
-
VBUS
monitoring
15
-
14
13
-
10
-
8
-
53
R/W hC0_36_1B
Table 157
7
6
5
2
1
0
-
VBUSTH[2:0]
VBUSTL[2:0]
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
118
Functional Block Description
2
Table 104. SPI/I C Register Map
23
22
21
13
20
12
19
18
17
9
16
CHRGLEDGEN
CHRGLEDG[1:0]
CHRGLEDGDC[5:1]
15
14
11
10
8
LED Control
Table 158
54
R/W h60_06_00
CHRGLEDG
RAMP
CHRGLEDGDC[0]
LEDGPER[1:0]
CHRGLEDREN
CHRGLEDR[1:0]
CHRGLEDRDC[5]
7
6
5
4
3
2
1
0
CHRGLEDR
RAMP
CHRGLEDRDC[4:0]
CHRGLEDRPER[1:0]
23
15
7
22
21
20
12
4
19
11
3
18
17
16
PWM2CLKDIV[5:0]
PWM2DUTY[5:4]
14
13
10
9
8
PWM Control
Table 159
55
R/W h00_00_00
PWM2DUTY[3:0]
PWM1CLKDIV[5:2]
6
5
2
1
0
PWM1CLKDIV[1:0]
PWM1DUTY[5:0]
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
56
to
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
Unused
NU
h00_00_00
63
7
6
5
4
3
2
1
-
0
-
-
-
-
-
-
-
MC34708
Analog Integrated Circuit Device Data
119
Freescale Semiconductor
Functional Block Description
7.10.4 SPI Register’s Bit Description
Table 105. Register 0, Interrupt Status 0
Name
Bit #
R/W
Reset
Default
Description
ADC has finished requested conversions
Touchscreen has finished requested conversions
Touch screen pen detection
USB detect
ADCDONEI
TSDONEI
TSPENDET
USBDET
0
1
2
3
4
5
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RESETB
RESETB
RESETB
OFFB
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reserved
Reserved
NONE
USB over voltage protection
Reserved
USBOVP
RESETB
NONE
Reserved
12:6 RW1C
Low battery threshold warning
Reserved
LOWBATT
Reserved
13
14
15
16
17
18
19
20
21
22
23
RW1C
RW1C
RESETB
NONE
1: accessory attached
ATTACH
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
RW1C MUSBRSTB
1: accessory detached
DETACH
1: remote controller key is pressed
1: remote controller long key is pressed
1: remote controller long key is released
1: an unknown accessory is attached
1: ADC Result has changed when the RAW DATA = 0
1: Stuck key is detected
KP
LKP
LKR
UNKNOWN_ATTA
ADC_CHANGE
STUCK_KEY
STUCK_KEY_RCV
1: Stuck key is recovered
Table 106. Interrupt Mask 0
Name
Bit #
R/W
Reset
Default
Description
ADCDONEI mask bit
TSDONEI mask bit
Touch screen pen detect mask bit
USBDET mask bit
Reserved
ADCDONEM
TSDONEM
TSPENDETM
USBDETM
Reserved
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW1C
R/W
R/W
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
OFFB
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x1
0x0
0x1
0x1
0x1
0x1
0x1
0x1
2
3
4
NONE
USB over voltage protection
Reserved
USBOVPM
Reserved
5
RESETB
NONE
12:6
13
14
15
16
17
18
19
20
LOBATLI mask bit
Reserved
LOWBATTM
Reserved
RESETB
NONE
DETACH mask bit
KP mask bit
ATTACH_M
DETACH_M
KP_M
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
LKP mask bit
LKR mask bit
LKP_M
DETACH mask bit
UNKNOWN_ATTA mask bit
LKR_M
UKNOWN_ATTA_M
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
120
Functional Block Description
Table 106. Interrupt Mask 0
Name
Bit #
R/W
Reset
Default
Description
VBUS power supply type identification completed mask
ID resistance detection finished mask
For future use
ADC_CHANGE_M
STUCK_KEY_M
21
22
23
R/W
R/W
R/W
RESETB
RESETB
RESETB
0x1
0x1
0x1
STUCK_KEY_RCV_M
Table 107. Register 2, Interrupt Sense 0
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
USBDETS
Reserved
2-0
3
R
R
R
R
R
R
R
R
R
R
R
R
0x0
S
USBDET sense bit
NONE
NONE
NONE
NONE
NONE
NONE
Reserved
4
0x0
S
USBOVP sense bit
USBOVPS
Reserved
5
Reserved
6
0x0
0x0
0x0
0x0
0x0
0x0
S
Not available
Unused
7
Reserved
Reserved
9:8
16-10
17
18
19
20
Not available
Unused
VBUS power supply type identification completed sense bit
ID resistance detection finished sense bit
ID float sense bit
VBUS_DET_ENDS
ID_DET_ENDS
ID_FLOATS
ID_GNDS
MUSBRSTB
MUSBRSTB
NONE
ID ground sense bit
0: no
MUSBRSTB
0x0
1: yes
Mini USB ADC conversion status
1: ADC conversion completed
0: ADC conversion in progress
MUSB_ADC_STATUS
Unused
21
R
R
NONE
X
Not available
23-22
0x0
Table 108. Register 3, Interrupt Status 1
Name
Bit #
R/W
Reset
Default
Description
1.0 Hz time tick
1HZI
TODAI
0
1
RW1C RTCPORB
RW1C RTCPORB
R
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
Time of day alarm
Not available
Unused
2
PWRON1 event
PWRON1I
PWRON2I
WDIRESETI
SYSRSTI
RTCRSTI
PCI
3
RW1C
RW1C
OFFB
OFFB
PWRON2 event
4
WDI system reset event
PWRON system reset event
RTC reset event
5
RW1C RTCPORB
RW1C RTCPORB
RW1C RTCPORB
6
7
Power cut event
8
RW1C
OFFB
Warm start event
WARMI
9
RW1C RTCPORB
RW1C RTCPORB
Memory hold event
110 °C thermal threshold
MEMHLDI
THERM110
10
11
RW1C
RESETB
MC34708
Analog Integrated Circuit Device Data
121
Freescale Semiconductor
Functional Block Description
Table 108. Register 3, Interrupt Status 1
Name
Bit #
R/W
Reset
Default
Description
120 °C thermal threshold
THERM120
THERM125
THERM130
CLKI
12
13
14
15
16
17
18
19
20
21
22
23
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
R
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
125 °C thermal threshold
130 °C thermal threshold
Clock source change
Short-circuit protection trip detection
GPIOLV1 interrupt
GPIOLV2 interrupt
GPIOLV3 interrupt
GPIOLV4 interrupt
Not available
SCPI
GPIOLV1I
GPIOLV2I
GPIOLV3I
GPIOLV4I
Unused
Reserved
Reserved
Unused
R
NONE
Not available
R
RESETB
Table 109. Register 4, Interrupt Mask 1
Name
Bit #
R/W
Reset
Default
Description
1HZI mask bit
1HZM
TODAM
0
1
R/W
R/W
R
RTCPORB
RTCPORB
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
TODAI mask bit
Not available
Unused
2
PWRON1 mask bit
PWRON1M
PWRON2M
WDIRESETM
SYSRSTM
RTCRSTM
PCM
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
OFFB
OFFB
PWRON2 mask bit
4
WDIRESETI mask bit
SYSRSTI mask bit
5
RTCPORB
RTCPORB
RTCPORB
OFFB
6
RTCRSTI mask bit
7
PCI mask bit
8
WARMI mask bit
WARMM
9
RTCPORB
RTCPORB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
MEMHLDI mask bit
THERM110 mask bit
THERM120 mask bit
THERM125 mask bit
THERM130 mask bit
CLKI mask bit
MEMHLDM
THERM110M
THERM120M
THERM125M
THERM130M
CLKM
10
11
12
13
14
15
16
17
18
19
20
21
Short-circuit protection trip mask bit
GPIOLV1 interrupt mask bit
GPIOLV2 interrupt mask bit
GPIOLV3 interrupt mask bit
GPIOLV4 interrupt mask bit
Not available
SCPM
GPIOLV1M
GPIOLV2M
GPIOLV3M
GPIOLV4M
Unused
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
122
Functional Block Description
Table 109. Register 4, Interrupt Mask 1
Name
Bit #
R/W
Reset
Default
Description
Description
Reserved
Reserved
Unused
22
23
R
R
NONE
0x0
0x1
Not available
Table 110. Register 5, Interrupt Sense 1
Name
Bit #
R/W
Reset
Default
Not available
Unused
PWRON1S
PWRON2S
Unused
2-0
3
R
R
R
R
R
R
R
R
R
R
R
R
0x0
S
PWRON1I sense bit
PWRON2I sense bit
Not available
NONE
NONE
4
S
10-5
11
0x0
S
THERM110 sense bit
THERM120 sense bit
THERM125 sense bit
THERM130 sense bit
CLKI sense bit
THERM110S
THERM120S
THERM125S
THERM130S
CLKS
NONE
NONE
NONE
NONE
NONE
12
S
13
S
14
S
15
0x0
0x00
0x0
0x0
Not available
Unused
21-16
22
Reserved
Reserved
Unused
NONE
NONE
Not available
23
Table 111. Register 6, Power Up Mode Sense
Default
Name
Bit #
R/W
Reset
Description
(76)
ICTEST sense state
PUMS1 state
PUMS2 state
PUMS3 state
PUMS4 state
PUMS5 state
Not available
Reserved
ICTESTS
PUMS1S
PUMS2S
PUMS3S
PUMS4S
PUMS5S
Unused
0
R
R
R
R
R
R
R
R
R
NONE
NONE
NONE
NONE
NONE
NONE
S
1
L
2
3
L
L
4
L
5
L
8-6
9
0x0
0x0
0x0000
Reserved
Unused
NONE
Not available
23-10
76. L = Loaded PUMSx level at startup.
Table 112. Register 7, Identification
Name
Bit #
R/W
Reset
Default
Description
Metal Layer version
Pass 2.4 =100
METAL_LAYER_REV[2:0] 2-0
R
NONE
X
Full Layer version
Pass 2.4 = 010
FULL_LAYER_REV[2:0]
FIN[2:0]
5-3
8-6
R
R
NONE
NONE
X
X
FIN version
Pass 2.4 = 000
MC34708
Analog Integrated Circuit Device Data
123
Freescale Semiconductor
Functional Block Description
Table 112. Register 7, Identification
Name
Bit #
R/W
Reset
Default
Description
FAB version
FAB[2:0]
11-9
R
NONE
X
Pass 2.4 = 000
Not available
SPI Page
Unused
18-12
R
0x0
0x0
PAGE[4:0]
23-19 R/W
DIGRESETB
Table 113. Register 8, Regulator Fault Sense
Name
Bit #
R/W
Reset
Default
Description
SW1 fault detection
Reserved
SW1FAULT
Reserved
0
1
R
R
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
S
0x0
S
SW2 fault detection
SW3 fault detection
SW4A fault detection
SW4B fault detection
SW5 fault detection
SWBST fault detection
VUSB fault detection
VUSB2 fault detection
VDAC fault detection
VGEN1 fault detection
VGEN2 fault detection
Not available
SW2FAULT
SW3FAULT
SW4AFAULT
SW4BFAULT
SW5FAULT
SWBSTFAULT
VUSBFAULT
VUSB2FAULT
VDACFAULT
VGEN1FAULT
VGEN2FAULT
Unused
2
R
3
R
S
4
R
S
5
R
S
6
R
S
7
R
S
8
R
S
9
R
S
10
11
12
22-13
23
R
S
R
S
R
S
R
0x00
0x0
Regulator short-circuit protect enable
REGSCPEN
R/W
RESETB
Table 114. Register 9, Reserved
Name
Bit #
R/W
Reset
Default
Description
Reserved
Reserved
1-23
R
NONE
0x000020
Table 115. Register 10, Reserved
Name
Bit #
R/W
Reset
Default
Description
Reserved
Reserved
1-23
R
NONE
0x00013A
Table 116. Register 11, Reserved
Name
Bit #
R/W
Reset
Default
Description
Reserved
Reserved
1-23
R
NONE
0x000000
Table 117. Register 12, Unused
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
23-0
R
0x000000
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
124
Functional Block Description
Table 118. Register 13, Power Control 0
Name
Bit #
R/W
Reset
Default
Description
Power cut enable
PCEN
PCCOUNTEN
WARMEN
0
1
R/W
R/W
R/W
R/W
RTCPORB
RTCPORB
RTCPORB
RESETB
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x00
0x0
Power cut counter enable
Warm start enable
2
SPI command for entering user off modes
Keeps VSRTC and CLK32KMCU on for all states
Keeps the CLK32KMCU active during user off
Enables the CLK32KMCU
USEROFFSPI
DRM
3
(77)
4
R/W RTCPORB
USEROFFCLK
CLK32KMCUEN
Unused
5
R/W
R/W
R
RTCPORB
6
RTCPORB
Not available
8-7
9
PCUTEXPB=1 at a startup event indicates the PCUT timer
did not expire (assuming it was set to 1 after booting)
PCUTEXPB
R/W
RTCPORB
Not available
Unused
Reserved
18-10
19
R
R
0x000
0x0
Reserved
NONE
Coin cell charger voltage setting
Coin cell charger enable
VCOIN[2:0]
COINCHEN
22-20 R/W
23 R/W
RTCPORB
RTCPORB
0x00
0x0
Notes:
77. Reset by RTCPORB but not during a GLBRST (global reset)
Table 119. Register 14, Power Control 1
Name
Bit #
R/W
Reset
Default
Description
Power cut timer
PCT[7:0]
PCCOUNT[3:0]
PCMAXCNT[3:0]
Unused
7-0
R/W
R/W
RTCPORB
RTCPORB
RTCPORB
0x00
0x00
0x00
0x00
Power cut counter
11-8
Maximum allowed number of power cuts
Not available
15-12 R/W
23-16
R
Table 120. Register 15, Power Control 2
Name
Bit #
R/W
Reset
Default
Description
Enables automatic restart after a system reset
Enables system reset on PWRON1 pin
Enables system reset on PWRON2 pin
Not available
RESTARTEN
PWRON1RSTEN
PWRON2RSTEN
Unused
0
1
R/W
R/W
R/W
R
RTCPORB
RTCPORB
RTCPORB
0x0
0x0
2
0x0
3
0x0
Sets debounce time on PWRON1 pin
Sets debounce time on PWRON2 pin
Sets Global reset time
PWRON1DBNC[1:0]
PWRON2DBNC[1:0]
GLBRSTTMR[1:0]
STANDBYINV
Unused
5-4
7-6
9-8
10
11
12
R/W
R/W
R/W
R/W
R
RTCPORB
RTCPORB
RTCPORB
RTCPORB
0x00
0x00
0x01
0x0
If set then STANDBY is interpreted as active low
Not available
0x0
Enables system reset through WDI
SPI drive strength
WDIRESET
R/W
RESETB
0x0
SPIDRV[1:0]
14-13 R/W
16-15
RTCPORB
0x01
0x00
Not available
Unused
R
MC34708
Analog Integrated Circuit Device Data
125
Freescale Semiconductor
Functional Block Description
Table 120. Register 15, Power Control 2
Name
Bit #
R/W
Reset
Default
Description
CLK32K and CLK32KMCU drive strength (master control
bits)
CLK32KDRV[1:0]
18-17 R/W
RTCPORB
0x01
Not available
Unused
20-19
21
R
0x00
0x0
On Standby Low Power Mode
0 = Low power mode disabled
1 =Low power mode enabled
ON_STBY_LP
R/W
RESETB
RESETB
Standby delay control
STBYDLY[1:0]
23-22 R/W
0x01
Table 121. Register 16, Memory A
Name
Bit #
R/W
Reset
Default
Description
Backup memory A
MEMA[23:0]
23-0
R/W
RTCPORB
0x000000
Table 122. Register 17, Memory B
Name
Bit #
R/W
Reset
Default
Description
Backup memory B
MEMB[23:0]
23:0
R/W
RTCPORB
0x000000
Table 123. Register 18, Memory C
Name
Bit #
R/W
Reset
Default
Description
Backup memory C
MEMC[23:0]
23-0
R/W
RTCPORB
0x000000
Table 124. Register 19, Memory D
Name
Bit #
R/W
Reset
Default
Description
Backup memory D
MEMD[23:0]
23-0
R/W
RTCPORB
0x000000
Table 125. Register 20, RTC Time
Name
Bit #
R/W
Reset
Default
Description
Time of day counter
(78)
TOD[16:0]
RTCCAL[4:0]
16-0
R/W RTCPORB
0x00000
0x00
(78)
(78)
RTC calibration count
21-17 R/W RTCPORB
23-22 R/W RTCPORB
RTC calibration mode
RTCCALMODE[1:0]
0x0
Notes
78. Reset by RTCPORB but not during a GLBRST (global reset)
Table 126. Register 21, RTC Alarm
Name
Bit #
R/W
Reset
Default
Description
Time of day alarm
(79)
(79)
TODA[16:0]
Unused
16-0
22-17
23
R/W RTCPORB
R
0x1FFFF
0x00
Not available
Disable RTC
RTCDIS
R/W RTCPORB
0x0
Notes
79. Reset by RTCPORB but not during a GLBRST (global reset)
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
126
Functional Block Description
Table 127. Register 22, RTC Day
Name
Bit #
R/W
Reset
Default
Description
Description
Description
(80)
Day counter
Not available
DAY[14:0]
Unused
14-0
R/W RTCPORB
R
0x0000
0x000
23-15
Notes
80. Reset by RTCPORB but not during a GLBRST (global reset)
Table 128. Register 23, RTC Day Alarm
Name
Bit #
R/W
Reset
Default
(81)
Day alarm
DAYA[14:0]
Unused
14-0
R/W RTCPORB
R
0x7FFF
0x000
Not available
23-15
Notes
81. Reset by RTCPORB but not during a GLBRST (global reset)
Table 129. Register 24, Regulator 1A/B Voltage
Name
Bit #
R/W
Reset
Default
SW1 setting in normal mode
SW1 setting in Standby mode
Not available
SW1A[5:0]
SW1ASTBY[5:0]
Reserved
5-0 R/WM
11-6 R/WM
NONE
NONE
NONE
*
*
*
23-12
R
Table 130. Register 25, Regulator 2 & 3 Voltage
Name
Bit #
R/W
Reset
Default
Description
SW2 setting in normal mode
SW2 setting in Standby mode
SW3 setting in normal mode
Not available
SW2[5:0]
SW2STBY[5:0]
SW3[4:0]
5-0 R/WM
11-6 R/WM
16-12 R/WM
NONE
NONE
NONE
*
*
*
Unused
17
22-18 R/WM
23
R
0x0
*
SW3 setting in standby mode
Not available
SW3STBY[4:0]
Unused
NONE
R
0x0
Table 131. Register 26, Regulator 4A/B
Name
Bit #
R/W
Reset
Default
Description
SW4A setting in normal mode
SW4A setting in Standby mode
SW4A high setting
SW4A[0:4]
SW4ASTBY[4:0]
SW4AHI[1:0]
SW4B[4:0]
4-0 R/WM
9-5 R/WM
11-10 R/WM
16-12 R/WM
21-17 R/WM
23-22 R/WM
NONE
NONE
*
*
*
*
*
*
NONE
SW4B setting in normal mode
SW4B setting in Standby mode
SW4B high setting
NONE
SW4BSTBY[4:0]
SW4BHI[1:0]
RESETB
RESETB
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
127
Functional Block Description
Table 132. Register 27, Regulator 5 Voltage
Name
Bit #
R/W
Reset
Default
Description
SW4 setting in normal mode
SW5[4:0]
Unused
4-0 R/WM
9-5
14-10 R/WM
23-15
NONE
*
Not available
R
*
*
SW5 setting in Standby mode
Not available
SW5STBY[4:0]
Unused
NONE
R
0x000
Table 133. Register 28, Regulators 1 & 2 Operating Mode
Name
Bit #
R/W
Reset
Default
Description
SW1A operating mode
SW1A Memory Hold mode
SW1A User Off mode
SW1 DVS1 speed
SW1AMODE[3:0]
SW1AMHMODE
SW1AUOMODE
SW1DVSSPEED[1:0]
Unused
3-0
4
R/W
R/W
R/W
R/W
R
RESETB
OFFB
0xA
0x0
0x0
0x1
0x00
0xA
0x0
0x0
0x01
0x1
0x0
5
OFFB
7-6
13-8
RESETB
Not available
(82)
SW2 operating mode
SW2 Memory Hold mode
SW2 User Off mode
SW2 DVS1 speed
SW2MODE[3:0]
17-14 R/W
RESETB
OFFB
SW2MHMODE
SW2UOMODE
SW2DVSSPEED[1:0]
PLLEN
18
19
R/W
R/W
OFFB
21-20 R/W
RESETB
RESETB
RESETB
PLL enable
22
23
R/W
R/W
PLL multiplication factor
PLLX
Notes
82. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled
switch will default to APS mode for both Normal and Standby operation.
Table 134. Register 29, Regulators 3, 4, and 5 Operating Mode
Name
Bit #
R/W
Reset
Default
Description
SW3 operating mode
SW3MODE[3:0]
SW3MHMODE
SW3UOMODE
SW4AMODE[3:0]
SW4AMHMODE
SW4AUOMODE
SW4BMODE[3:0]
SW4BMHMODE
SW4BUOMODE
3-0
4
R/W
R/W
R/W
R/W
R/W
R/W
RESETB
OFFB
0xA
0x0
0x0
0xA
0x0
0x0
0xA
0x0
0x0
0xA
0x0
0x0
SW3 Memory Hold mode
SW3 User Off mode
5
OFFB
SW4A operating mode
SW4A Memory Hold mode
SW4A User Off mode
SW4B operating mode
SW4B Memory Hold mode
SW4B User Off mode
SW5 operating mode
SW5 Memory Hold mode
SW5 User Off mode
9-6
10
11
RESETB
OFFB
OFFB
15-12 R/W
RESETB
OFFB
16
17
R/W
R/W
OFFB
(83)
SW5MODE[3:0]
SW5MHMODE
SW5UOMODE
21-18 R/W
RESETB
OFFB
22
23
R/W
R/W
OFFB
Notes
83. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled
regulator will default to APS mode for both Normal and Standby operation.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
128
Functional Block Description
Table 135. Register 30, Regulator Setting 0
Name
Bit #
R/W
Reset
Default
Description
VGEN1 setting
Not available
VDAC setting
VGEN2 setting
VPLL setting
VUSB2 setting
Not available
VGEN1[2:0]
Unused
2-0 R/WM
RESETB
*
3
R
0x0
VDAC[1:0]
VGEN2[2:0]
VPLL[1:0]
VUSB2[1:0]
Unused
5-4 R/WM
8-6 R/WM
10-9 R/WM
12-11 R/WM
RESETB
RESETB
RESETB
RESETB
*
*
*
*
23-13
R
0x000
Table 136. Register 31, SWBST Control
Name
Bit #
R/W
Reset
Default
Description
SWBST setting
SWBST mode
Not available
SWBST[1:0]
SWBSTMODE[1:0]
Spare
1-0
3-2
4
R/W
R/W
R/W
R/W
R/W
R
NONE
*
0x2
RESETB
RESETB
RESETB
RESETB
0x0
SWBST standby mode
Not available
SWBSTSTBYMODE[1:0] 6-5
0x2
Spare
7
0x0
Not available
Unused
23-8
0x0000
Table 137. Register 32, Regulator Mode 0
Name
Bit #
R/W
Reset
Default
Description
VGEN1 enable
VGEN1EN
VGEN1STBY
VUSBSEL
VUSBEN
0
1
2
3
R/W
R/W
R/W
R/W
NONE
RESETB
NONE
*
VGEN1 controlled by standby
0x0
*
Slave or Host configuration for VBUS
VUSB enable (PUMS4:1=[0100]). Also reset to 1 by invalid
VBUS
RESETB
0x1
VDAC enable
VDACEN
VDACSTBY
VDACMODE
Unused
4
5
R/W
R/W
R/W
R
NONE
*
VDAC controlled by standby
VDAC operating mode
Not available
RESETB
RESETB
0x0
0x0
0x0
*
6
9-7
10
11
VREFDDR enable
VREFDDREN
VGEN2CONFIG
R/W
R/W
NONE
NONE
PUMS5 Tied to ground = 0: VGEN2 with external PNP
PUMS5 Tied to VCROREDIG =1:VGEN2 internal PMOS
*
VGEN2 enable
VGEN2EN
VGEN2STBY
VGEN2MODE
VPLLEN
12
13
14
15
16
17
R/W
R/W
R/W
R/W
R/W
R/W
NONE
RESETB
RESETB
NONE
*
VGEN2 controlled by standby
VGEN2 operating mode
VPLL enable
0x0
0x0
*
VPLL controlled by standby
VPLLSTBY
RESETB
NONE
0x0
*
PUMS5 Tied to ground = 0: VUSB2 with external PNP
PUMS5 Tied to VCROREDIG =1:VUSB2 internal PMOS
VUSB2CONFIG
VUSB2 enable
VUSB2EN
18
R/W
NONE
*
MC34708
Analog Integrated Circuit Device Data
129
Freescale Semiconductor
Functional Block Description
Table 137. Register 32, Regulator Mode 0
Name
Bit #
R/W
Reset
Default
Description
VUSB2 controlled by standby
VUSB2STBY
VUSB2MODE
Unused
19
20
R/W
R/W
R
RESETB
RESETB
0x0
0x0
0x0
VUSB2 operating mode
Not available
23-21
Table 138. Register 33, GPIOLV0 Control
Name
Bit #
R/W
Reset
Default
Description
GPIOLV0 direction
0: Input
DIR
0
R/W
RESETB
0x0
1: Output
Input state of GPIOLV0 pin
0: Input low
DIN
DOUT
1
2
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x1
0x0
1: Input High
Output state of GPIOLV0 pin
0: Output Low
1: Output High
Hysteresis
HYS
3
0: CMOS in
1: Hysteresis
GPIOLV0 input debounce time
00: no debounce
DBNC[1:0]
5-4
01: 10 ms debounce
10: 20 ms debounce
11: 30 mS debounce
GPIOLV0 interrupt control
00: None
INT[1:0]
7-6
R/W
RESETB
0x0
01: Falling edge
10: Rising edge
11: Both edges
Pad keep enable
0: Off
PKE
ODE
8
9
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x0
0x1
0x3
1: On
Open drain enable
0: CMOS
1: OD
Drive strength enable
0: 4.0 mA
DSE
10
11
1: 8.0 mA
Pull-up/down enable
0: pull-up/down off
PUE
1: pull-up/down on (default)
Pull-up/Pull-down select
00: 10 K pull-down
01: 100 K pull-down
10: 10 K pull-up
PUS[1:0]
13-12 R/W
11: 100 K pull-up
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
130
Functional Block Description
Table 138. Register 33, GPIOLV0 Control
Name
Bit #
R/W
Reset
Default
Description
Slew rate enable
00: slow (default)
01: normal
SRE[1:0]
15-14 R/W
RESETB
0x0
10: fast
11: very fast
Not available
Unused
23-16
R
0x00
Table 139. Register 34, GPIOLV1 Control
Name
Bit #
R/W
Reset
Default
Description
GPIOLV1directon
0: Input
DIR
0
R/W
RESETB
0x0
1: Output
Input state of GPIOLV1 pin
0: Input low
DIN
DOUT
1
2
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x1
0x0
1: Input High
Output state of GPIOLV1 pin
0: Output Low
1: Output High
Hysteresis
HYS
3
0: CMOS in
1: Hysteresis
GPIOLV1 input debounce time
00: no debounce
DBNC[1:0]
5-4
01: 10 ms debounce
10: 20 ms debounce
11: 30 mS debounce
GPIOLV1 interrupt control
00: None
INT[1:0]
7-6
R/W
RESETB
0x0
01: Falling edge
10: Rising edge
11: Both edges
Pad keep enable
0: Off
PKE
ODE
8
9
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x0
0x1
0x3
1: On
Open drain enable
0: CMOS
1: OD
Drive strength enable
0: 4.0 mA
DSE
10
11
1: 8.0 mA
Pull-up/down enable
0: pull-up/down off
PUE
1: pull-up/down on (default)
Pull-up/Pull-down select
00: 10 K pull-down
01: 100 K pull-down
10: 10 K pull-up
PUS[1:0]
13:12 R/W
11: 100 K pull-up
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
131
Functional Block Description
Table 139. Register 34, GPIOLV1 Control
Name
Bit #
R/W
Reset
Default
Description
Slew rate enable
00: slow (default)
01: normal
SRE[1:0]
15-14 R/W
RESETB
0x0
10: fast
11: very fast
Not available
Unused
23-16
R
0x00
Table 140. Register 35, GPIOLV2 Control
Name
Bit #
R/W
Reset
Default
Description
GPIOLV2 direction
0: Input
DIR
0
R/W
RESETB
0x0
1: Output
Input state of GPIOLV2 pin
0: Input low
DIN
DOUT
1
2
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x1
0x0
1: Input High
Output state of GPIOLV2 pin
0: Output Low
1: Output High
Hysteresis
HYS
3
0: CMOS in
1: Hysteresis
GPIOLV2 input debounce time
00: no debounce
DBNC[1:0]
5-4
01: 10 ms debounce
10: 20 ms debounce
11: 30 mS debounce
GPIOLV2 interrupt control
00: None
INT[1:0]
7-6
R/W
RESETB
0x0
01: Falling edge
10: Rising edge
11: Both edges
Pad keep enable
0: Off
PKE
ODE
8
9
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x0
0x1
0x3
1: On
Open drain enable
0: CMOS
1: OD
Drive strength enable
0: 4.0 mA
DSE
10
11
1: 8.0 mA
Pull-up/down enable
0: pull-up/down off
PUE
1: pull-up/down on (default)
Pull-up/Pull-down select
00: 10 K pull-down
01: 100 K pull-down
10: 10 K pull-up
PUS[1:0]
13-12 R/W
11: 100 K pull-up
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
132
Functional Block Description
Table 140. Register 35, GPIOLV2 Control
Name
Bit #
R/W
Reset
Default
Description
Slew rate enable
00: slow (default)
01: normal
SRE[1:0]
15-14 R/W
RESETB
0x0
10: fast
11: very fast
Not available
Unused
23-16
R
0x00
Table 141. Register 36, GPIOLV3 Control
Name
Bit #
R/W
Reset
Default
Description
GPIOLV3 direction
0: Input
DIR
0
R/W
RESETB
0x0
1: Output
Input state of GPIOLV3 pin
0: Input low
DIN
DOUT
1
2
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x1
0x0
1: Input High
Output state of GPIOLV3 pin
0: Output Low
1: Output High
Hysteresis
HYS
3
0: CMOS in
1: Hysteresis
GPIOLV3 input debounce time
00: no debounce
DBNC[1:0]
5-4
01: 10 ms debounce
10: 20 ms debounce
11: 30 mS debounce
GPIOLV3 interrupt control
00: None
INT[1:0]
7-6
R/W
RESETB
0x0
01: Falling edge
10: Rising edge
11: Both edges
Pad keep enable
0: Off
PKE
ODE
8
9
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x0
0x1
0x3
1: On
Open drain enable
0: CMOS
1: OD
Drive strength enable
0: 4.0 mA
DSE
10
11
1: 8.0 mA
Pull-up/down enable
0: pull-up/down off
PUE
1: pull-up/down on (default)
Pull-up/Pull-down select
00: 10 K pull-down
01: 100 K pull-down
10: 10 K pull-up
PUS[1:0]
13-12 R/W
11: 100 K pull-up
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
133
Functional Block Description
Table 141. Register 36, GPIOLV3 Control
Name
Bit #
R/W
Reset
Default
Description
Slew rate enable
00: slow (default)
01: normal
SRE[1:0]
15-14 R/W
RESETB
0x0
10: fast
11: very fast
Not available
Unused
23-16
R
0x00
Table 142. Register 37, USB timing
Name
Bit #
R/W
Reset
Default
Description
The periodical sampling time of the ID line in the Power-Save
DEVICE_WAKE_UP[3:0] 3-0
R/W
MUSBRSTB
0x0
mode and Standby mode; the periodical time of ADC
conversion of the resistance at ID pin when RAW DATA = 0.
0000: 50 ms
0001: 100 ms
0010: 150 ms
0011: 200 ms
0100: 300 ms
Normal key press duration
0000: 100 ms
0001: 200 ms
0010: 300 ms
...
KEYPRESS[3:0]
7-4
R/W
R/W
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
0x0
0x0
0x0
0x0
Long key press duration
0000: 300 ms
0001: 400 ms
0010: 500 ms
...
LONG_KEYPRESS[3:0] 11-8
Waiting time before switching the analog or digital switches:
SWITCHING_WAIT
15-12 R/W
19-16 R/W
0000: 10 ms
0001: 30 ms
0010: 50 ms
...
Time delay to start the powered accessory identification flow
TD
after detecting the bus voltage
0000: 100 ms
0001: 200 ms
0010: 300 ms
0011: 400 ms
0100: 500 ms
...
1111:1600 ms
The time for no activity in the switches before entering the
Power Save mode automatically for Audio Type 1 or TTY
device
0000: 1 s
0001: 2 s
...
1001:10s
...
1111:16 s
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
134
Functional Block Description
Table 142. Register 37, USB timing
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
22-20
23
R
R
0x0
0x0
Read data valid
0: Data not valid
1: Data valid
READVALID
MUSBRSTB
Table 143. Register 38, USB Button
Name
Bit #
R/W
Reset
Default
Description
1: the Send_End button is pressed
1: button 1 is pressed
1: button 2 is pressed
1: button 3 is pressed
1: button 4 is pressed
1: button 5 is pressed
1: button 6 is pressed
1: button 7 is pressed
1: button 8 is pressed
1: button 9 is pressed
1: button 10 is pressed
1: button 11 is pressed
1: button 12 is pressed
1: button error occurred
1: an unknown button is pressed
Not available
Send_End
S1
0
1
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x000
S2
2
S3
3
S4
4
S5
5
S6
6
S7
7
S8
8
S9
9
S10
10
11
12
13
14
23-15
S11
S12
ERROR
UNKNOWN
Unused
Table 144. Register 39, USB Control
Name
Bit #
R/W
Reset
Default
Description
Wait or not to wait for the command from the baseband
before turning on the analog or digital switches for attached
accessory
Wait
0
R/W
MUSBRSTB
0x1
0: Wait until this bit is changed to 1. Turn on the switches
immediately when this bit is changed to 1.
1: Wait for only the time programmed by the Switching Wait
bits in Timing Set 2 register before turning on the switches.
Manual or automatic switching of the switches
0: manual: the switches are controlled by the Manual S/W
registers.
Manual S/W
RAWDATA
1
2
R/W
R/W
MUSBRSTB
MUSBRSTB
0x1
0x1
1: auto: the switches are controlled by the Device Type
registers
Interrupt behavior selection
0: Enable the ADC conversion periodically and report the
ADC Result changes on ID pin to the host.
1: Enable the key press monitor circuit to detect the ID pin
status changes and report the key press events to the host.
MC34708
Analog Integrated Circuit Device Data
135
Freescale Semiconductor
Functional Block Description
Table 144. Register 39, USB Control
Name
Bit #
R/W
Reset
Default
Description
Switch connection selection
SWITCH_OPEN
3
R/W
MUSBRSTB
0x1
0: Open all switches
1: Switch selection according to the Manual S/W bit.
Soft reset. When written to 1, the IC is reset. Once the reset
is complete, the RST bit is set and the RESET bit is cleared
automatically.
RESET
4
RWM MUSBRSTB
0x0
1: to soft-reset the IC
SPK_L to DM switch control
TTY_SPKL
RST
5
6
R/W
R/C
MUSBRSTB
MUSBRSTB
0x0
X
0: Turn off the SPK_L to DM switch
1: Turn on the SPK_L to DM switch for TTY
This bit indicates if a chip reset has occurred. This bit will be
cleared once being read.
0: no.
1: Yes.
Indicate either the device is in Active mode
ACTIVE
7
R/W
MUSBRSTB
X
0: Standby
1: Active
Not available
CLK_RST
VOTGEN
Unused
8
R/C
R/W
R
MUSBRST
RESETB
0x1
0x0
0x0
0x0
0x1
Enables the OTG switch and the GOTG switch
9
Not available
Reserved
10
11
12
Reserved
SWHOLD
R
NONE
Switch Hold
R/W
MUSBRSTB
0: Run state machine and allow detection of accessory
1: Holds off state machine until baseband comes up
Reserved
Reserved
14-13
R
NONE
0x0
0x0
VBUS line switching configuration when Manual S/W = 0
00: open all switches MOTG, M0
VBUS SWITCHING[1:0] 16-15 R/W
MUSBRSTB
01: N/A
10: VBUS connects to MIC. M0, MOTG.
Others: open all switches connected to the VBUS line
DP line switching configuration when Manual S/W = 0
000: open all switches
DP SWITCHING[2:0]
DM SWITCHING[2:0]
READVALID
19-17 R/W
MUSBRSTB
MUSBRSTB
MUSBRSTB
0x0
0x0
0x0
001: DP connected to D+, DM connected to D-
010: DP connected to SPK_R, DM connected to SPK_L
011: DP connected to RxD, DM connected to TxD
Others: open all switches connected to the DP pin and DM
pin
DM line switching configuration when Manual S/W = 0
000: open all switches
22-20 R/W
001: DP connected to D+, DM connected to D-
010: DP connected to SPK_R, DM connected to SPK_L
011: DP connected to RxD, DM connected to TxD
Others: open all switches connected to the DP pin and DM
pin
Read data valid
0: Data not valid
1: Data valid
23
R
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
136
Functional Block Description
Table 145. Register 40, USB Device Type
Name
Bit #
R/W
Reset
Default
Description
1: An audio type 1 accessory is attached
1: An audio type 2 accessory is attached
1: A USB host is attached
Audio Type 1
Audio Type 2
USB
0
1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
MUSBRSTB
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x00
2
1: A UART cable is attached
UART
3
1: A 5-wire charger (type 1 or 2) is attached
1: A USB charger is attached
5W CHG
4
USB CHG
DEDICATED CHG
USB OTG
PPD
5
1: A dedicated charger is attached
1: A USB OTG accessory is attached
1: A phone powered device is attached
1: A TTY converter is attached
1: An audio/video cable is attached
1: An audio/video charger is attached
1: A USB jig cable 1 is attached
1: A USB jig cable 2is attached
1: A UART jig cable 1is attached
1: A UART jig cable 2 is attached
1: A factory cable is attached
6
7
8
TTY
9
A/V
10
11
12
13
14
15
16
17
18
23-19
AVCHRG
USBJIG1
USBJIG2
UARTJIG1
UARTJIG2
ID_FACTORY
UNK_DEVICE
Unused
1: Device not recognized
Not available
ADC result value of the resistance at ID pin
ADCIDRESULT[4:0]
MUSBRSTB
Table 146. Register 41 and 42, Unused
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
0-23
R
0x000000
Table 147. Register 43, ADC 0
Name
Bit #
R/W
Reset
Default
Description
Enables ADC from the low power mode
Request a start of the ADC Reading Sequencer
ADEN
0
1
2
R/W
R/W
R/W
DIGRESETB
DIGRESETB
DIGRESETB
0x0
0x0
0x0
ADSTART
ADCONT
Run ADC reads continuously when high or one time when
low. Note that the TSSTART request will have higher priority
Hold the ADC reading Sequencer while saved ADC results
are read from SPI
ADHOLD
3
R/W
R/W
DIGRESETB
DIGRESETB
0x0
0x0
Channel Selection to stop when complete. Always start at
000 and read up to and including this channel value.
ADSTOP[2:0]
6-4
Not available
Spare
7
8
R/W
R/W
DIGRESETB
DIGRESETB
0x0
0x0
0 = Disable manual LED control.
1= Enable manual LED control
THERM
Not available
Spare
11-9
R/W
DIGRESETB
0x0
MC34708
Analog Integrated Circuit Device Data
137
Freescale Semiconductor
Functional Block Description
Table 147. Register 43, ADC 0
Name
Bit #
R/W
Reset
Default
Description
Enable the Touch screen from low power mode.
TSEN
12
13
R/W
R/W
DIGRESETB
DIGRESETB
0x0
0x0
Request a start of the ADC Reading Sequencer for Touch
screen readings.
TSSTART
Run ADC reads of Touch screen continuously when high or
one time when low.
TSCONT
TSHOLD
14
15
R/W
R/W
DIGRESETB
DIGRESETB
DIGRESETB
0x0
0x0
0x0
Hold the ADC reading Sequencer while saved Touch screen
results are read from SPI
Just like the ADSTOP above, but for the Touchscreen read
programming. This will allow independent code for ADC
Sequence readings and touchscreen ADC Sequence
readings.
TSSTOP[2:0]
18-16 R/W
Not available
Spare
19
20
R/W
R/W
DIGRESETB
DIGRESETB
0x0
0x0
Enable the Touchscreen Pen Detection. Note that TSEN
must be off for Pen Detection.
TSPENDETEN
Not available
Spare
23-21 R/W
DIGRESETB
0x0
Table 148. Register 44, ADC 1
Name
Bit #
R/W
Reset
Default
Description
This will allow delay before the ADC readings.
This will allow delay between each of ADC readings in a set.
ADDLY1[3:0]
ADDLY2[3:0]
ADDLY3[3:0]
3-0
7:4
R/W
R/W
R/W
DIGRESETB
DIGRESETB
DIGRESETB
0x0
0x0
0x0
This will allow delay after the set of ADC readings. This delay
is only valid between subsequent wrap around reading
sequences with ADCONT
11-8
This will allow delay before the ADC Touch screen readings.
This is like the ADDLY1, but allows independent
programming of touchscreen readings from general purpose
ADC readings to prevent code replacement in the system.
TSDLY1[3:0]
TSDLY2[3:0]
15-12 R/W
19-16 R/W
DIGRESETB
DIGRESETB
0x0
0x0
This will allow delay between each of ADC Touch screen
readings in a set. This is like the ADDLY2, but allows
independent programming of touchscreen readings from
general purpose ADC readings to prevent code replacement
in the system.
This will allow delay after the set of ADC Touch screen
readings. This delay is only valid between subsequent wrap
around reading sequences with TSCONT mode. This is like
the ADDLY3, but allows independent programming of
touchscreen readings from general purpose ADC readings
to prevent code replacement in the system.
TSDLY3[3:0]
23-20 R/W
DIGRESETB
0x0
Table 149. Register 45, ADC 2
Name
Bit #
R/W
Reset
Default
Description
Channel Selection to place in ADRESULT0
Channel Selection to place in ADRESULT1
Channel Selection to place in ADRESULT2
Channel Selection to place in ADRESULT3
ADSEL0[3:0]
ADSEL1[3:0]
ADSEL2[3:0]
ADSEL3[3:0]
3-0
7-4
R/W
R/W
R/W
DIGRESETB
DIGRESETB
DIGRESETB
DIGRESETB
0x0
0x0
0x0
0x0
11-8
15-12 R/W
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
138
Functional Block Description
Table 149. Register 45, ADC 2
Name
Bit #
R/W
Reset
Default
Description
Channel Selection to place in ADRESULT4
Channel Selection to place in ADRESULT5
ADSEL4[3:0]
ADSEL5[3:0]
19-16 R/W
23-20 R/W
DIGRESETB
DIGRESETB
0x0
0x0
Table 150. Register 46, ADC 3
Name
Bit #
R/W
Reset
Default
Description
Channel Selection to place in ADRESULT6
Channel Selection to place in ADRESULT7
ADSEL6[3:0]
ADSEL7[3:0]
TSSEL0[1:0]
3-0
7-4
9-8
R/W
R/W
R/W
DIGRESETB
DIGRESETB
DIGRESETB
0x0
0x0
0x0
Touchscreen Selection to place in ADRESULT0.
Select the action for the Touchscreen;
00 = dummy to discharge TSREF capacitance,
01 = to read X-plate, 10 = to read Y-plate, and 11 = to read
Contact.
Touchscreen Selection to place in ADRESULT1.
See TSSEL0 for modes.
TSSEL1[1:0]
TSSEL2[1:0]
TSSEL3[1:0]
TSSEL4[1:0]
TSSEL5[1:0]
TSSEL6[1:0]
TSSEL7[1:0]
11-10 R/W
13-12 R/W
15-14 R/W
17-16 R/W
19-18 R/W
21-20 R/W
23-22 R/W
DIGRESETB
DIGRESETB
DIGRESETB
DIGRESETB
DIGRESETB
DIGRESETB
DIGRESETB
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Touchscreen Selection to place in ADRESULT2.
See TSSEL0 for modes.
Touchscreen Selection to place in ADRESULT3.
See TSSEL0 for modes.
Touchscreen Selection to place in ADRESULT4.
See TSSEL0 for modes.
Touchscreen Selection to place in ADRESULT5.
See TSSEL0 for modes.
Touchscreen Selection to place in ADRESULT6.
See TSSEL0 for modes.
Touchscreen Selection to place in ADRESULT7.
See TSSEL0 for modes.
Table 151. Register 47, ADC 4
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
ADRESULT0[9:0]
Unused
1-0
R
R
R
R
0x0
0x000
0x0
ADC Result for ADSEL0
Not available
11-2
DIGRESETB
DIGRESETB
13-12
23-14
ADC Result for ADSEL1
ADRESULT1[9:0]
0x000
Table 152. Register 48, ADC5
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
ADRESULT2[9:0]
Unused
1-0
R
R
R
R
0x0
0x000
0x0
ADC Result for ADSEL2
Not available
11-2
DIGRESETB
DIGRESETB
13-12
23-14
ADC Result for ADSEL3
ADRESULT3[9:0]
0x000
MC34708
Analog Integrated Circuit Device Data
139
Freescale Semiconductor
Functional Block Description
Table 153. Register 49, ADC6
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
ADRESULT4[9:0]
Unused
1-0
R
R
R
R
0x0
0x000
0x0
ADC Result for ADSEL4
Not available
11-2
DIGRESETB
DIGRESETB
13-12
23-14
ADC Result for ADSEL5
ADRESULT5[9:0}
0x000
Table 154. Register 50, ADC7
Name
Bit #
R/W
Reset
Default
Description
Not available
Unused
ADRESULT6[9:0]
Unused
1:0
R
R
R
R
0x0
0x000
0x0
ADC Result for ADSEL6
Not available
11-2
DIGRESETB
DIGRESETB
13-12
23-14
ADC Result for ADSEL7
ADRESULT7[9:0]
0x000
Table 155. Register 51, Input Monitoring
Name
Bit #
R/W
Reset
Default
Description
Trickle1 to Trickle2 change over threshold
VBAT_TRKL[1:0]
1-0
R/W
RTCPORB
0x0
00: 2.8 V
01: 2.9 V
10: 3.0 V
11: 3.1 V
Reserved
Reserved
CHREN
2
3
R
NONE
0x0
0x1
0x3
Charger enable
R/W
R/W
RTCPORB
RTCPORB
Turn on detection threshold and low battery warning
threshold
LOWBATT[1:0]
5-4
Reserved
Reserved
23-6
R/W
NONE
0x00000
Table 156. Register 52, Input Debounce
Name
Bit #
R/W
Reset
Default
Description
Reserved
Reserved
VBATTDB[1:0]
VBUSDB[1:0]
Reserved
1-0
3-2
5-4
9-6
10
R/W
R/W
R/W
R/W
R/W
NONE
RESETB
RESETB
NONE
0x0
0x3
0x03
0x0
0x0
0x0
0x3
0x3
0x00
Battery voltage debounce
VBUS debounce
Reserved
LED override
CHRGLEDOVRD
Reserved
RESETB
NONE
Reserved
13-11 R/W
15-14 R/W
17-16 R/W
VBUS over voltage debounce
Die Temp Comparator Debounce
Reserved
SUP_OVP_DB[1:0]
DIE_TEMP_DB[1:0]
Reserved
RESETB
RESETB
NONE
23-18
R
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
140
Functional Block Description
Table 157. Register 53, VBUS Monitoring
Name
Bit #
R/W
Reset
Default
Description
VBUS threshold low
VBUS threshold high
Reserved
VBUSTL[2:0]
VBUSTH[2:0]
Reserved
2-0
5-3
R/W
R/W
R/W
RESETB
RESETB
NONE
0x3
0x3
23-6
0x00000
Table 158. Register 54, LED Control
Name
Bit #
R/W
Reset
Default
Description
LED red repetition period
CHRGLEDRPER[1:0]
CHRGLEDRRAMP
CHRGLEDRDC[5:0]
CHRGLEDR[1:0]
1-0
2
R/W
R/W
R/W
R/W
R/W
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
0x0
0x0
0x00
0x3
0x0
0x0
0x0
0x00
0x3
0x0
LED red channel driver ramp enable
LED red channel driver duty cycle
LED red driver current setting
LED red enable
8-3
10-9
11
CHRGLEDREN
LED green repetition period
LED green channel driver ramp enable
LED green channel driver duty cycle
LED green driver current setting
LED green enable
CHRGLEDGPER[1:0]
CHRGLEDGRAMP
CHRGLEDGDC[5:0]
CHRGLEDG[1:0]
CHRGLEDGEN
13-12 R/W
14 R/W
20-15 R/W
22-21 R/W
23
R/W
Table 159. Register 55, PWM Control
Name
Bit #
R/W
Reset
Default
Description
PWM1 Duty Cycle
PWM1DUTY[5:0]
PWMCLKDIV[5:0]
PWM2DUTY[5-0]
PWM2CLKDIV[5:0]
5-0
R/W
R/W
RESETB
RESETB
RESETB
RESETB
0x00
0x00
0x00
0x00
PWM1 Clock Divide Setting
PWM2 Duty Cycle
11-6
17-12 R/W
23-18 R/W
PWM2 Clock Divide Setting
Table 160. Register 56 to 63, Unused
Name
Bit #
R/W
Reset
Default
Description
Unused
0-23
R
0x000000
Not available
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
141
Typical Applications
8
Typical Applications
Figure 38 presents a typical application diagram of the MC34708 PMIC together with its functional components. For details on
component references and additional components such as filters, refer to the individual sections.
8.1
Application Diagram
BP
C1
10u
C2
10u
BP
VCOREDIG
D2
D1
SW1 Output
C5
4.7u
L2
1.0u
BP
SW1IN
2
x22u
SW1ALX
GNDSW1A
SW1FB
O/P
Drive
Input/Battery
Monitoring
General Purpose
LED drivers
C6/C7
SW1
Dual Phase
GP
2000 mA
Buck
SW1CFG
SW1VSSSNS
VCOREDIG
To AP
LICELL, UID, Die Temp, GPO4
D8
Voltage /
Current
GNDADC
SW1BLX
GNDSW1B
O/P
Drive
Sensing
&
R18
100K
10 Bit GP
ADC
A/D Result
Translation
ADIN9
ADIN10
ADIN11
DVS
CONTROL
SW1PWGD
General Purpose ADC Inputs:
i.e., PA thermistor, Light Sensor, Etc.
SW2 Output
C11
C10
4.7u
BP
L4
A/D
Control
1.0u
SW2IN
SW2LX
GNDSW2
SW2FB
SW2PWGD
22u
MUX
O/P
Drive
SW2
ADIN12/TSX1
ADIN13/TSX2
ADIN14/TSY1
D10
R19
100K
LP
Touch
Screen
Interface
`
1000 mA
To AP
BP
Buck
Touch
Screen
SW3 Output
C14 10u
C13
4.7u
L5
1.0u
ADIN15/TSY2
TSREF
Interface
Die Temp
&
Thermal Warning
Detection
SW3IN
C54
To Interrupt
Section
SW3
INT MEM
500 mA
Buck
O/P
Drive
SW3LX
GNDSW3
SW3FB
D11
2.2u
BPTHERM
NTCREF
C16
4.7u
SW4A Output
C17 10u
L6
1.0u
BP
SW4AIN
SW4ALX
GNDSW4A
SW4FBA
O/P
Drive
BATTISNSCCP
D12
SW4
Dual Phase
DDR
BATTISNSCCN
CFP
SW4CFG
1000 mA
Buck
SW4B Output
C20 10u
C19
4.7u
L7
1.0u
Package Pin Legend
BP
BP
SW4BIN
CFN
SW4BLX
GNDSW4B
SW4BFB
O/P
Drive
Output Pin
Input Pin
D13
SPIVCC
Shift Register
Bi-directional Pin
SW5
SW5 Output
C23 22u
C22
4.7u
L8
1.0u
CS
SPI
Interface
+
Muxed
I2C
Optional
Interface
SW5IN
CLK
SW5
I/O
1000 mA
Buck
O/P
Drive
SW5LX
GNDSW5
SW5FB
SPI
D14
SPI
MOSI
MISO
To Enables & Control
Registers
BP
C25
2.2u
L9
2.2u
GNDSPI
Shift Register
SWBSTIN
SWBSTLX
SWBSTFB
SWBST
Output
(Boost)
BP
D3
O/P
Drive
SWBST
380 mA
Boost
C56
VALWAYS
VCORE
1u
GNDSWBST
C26
2x22u
C50
34708
1u
C51
SW4B
C57
VCOREDIG
VDDLP
VINREFDDR
Reference
Generation
1u
C52
SPI Control
C35
100n
C55
100pF
C49
VCOREREF
100n
100n
VHALF
VREFDDR
10mA
GNDCORE
GNDREF
100n
VREFDDR
1u
C28
SPKR
SPKL
MIC
C30
2.2u
VINPLL
VPLL
VPLL
50 mA
BP
Pass
FET
To/From
Audio IC
BP
Q1
C29
VUSB2DRV
VUSB2
TXD
RXD
Pass
FET
VUSB2
350mA
2.2u
VBUS/ID
Detectors, Host
Auto detection
To/From
AP
R22
40m
DPLUS
BP
DMINUS
VDACDRV
VDAC
VDAC
250mA
Q3
UART Switches
Audio Switches
C36
2.2u
To
Trimmed
Circuits
DP
DM
SPI
R23
Trim-In-Package
100m
Control
Logic
To/From
USB Cable
C38
SW5
VINGEN1
VGEN1
VGEN1
250mA
Pass
FET
GNDUSB
UID
2.2u
VBUS
BP
Startup
Sequencer
Decode
Trim?
C34
2.2uF
OVP
Control
Logic
VGEN2DRV
VGEN2
PUMSx
PLL
Switchers
Q5
Pass
FET
VGEN2
250mA
VINUSB
VUSB
Monitor
Timer
SWBST
C47
C41
2.2u
VUSB
Regulator
R24
50m
RTC
Calibration
+
32 KHz
Internal
Osc
LDOVDD
BP
2.2u
SPI Result
Registers
Interrupt
Inputs
Enables &
Control
32 KHz
Buffers
Best
of
Supply
GNDREG1
GNDREG2
GNDREF1
GNDREF2
BP
LCELL
Switch
LICELL
PWM
Outputs
32 KHz
Crystal
Osc
GPIO Control
Li Cell
Charger
Digital Core
Coin Cell
Battery
C46
100n
R4
R20 R3
C43
0.1uF
VDDLP
D16
BP
D15
To/From
AP
1.5V LDO
To AP
To Peripherals
To GND, or
VCOREDIG
VOUT
GND
VIN
CE
LICELL
18p
C45
15p
C44
D17
C59
C58
100nF
100nF
Y1
32.768 KHz
Crystal
Workaround for erratum#23.
On/Off
Button
Reset
button
If back-up coin cell is not present in the application, D16 and D17 are not
required and BP is connected directly to VIN of the LDO
Figure 38. Typical Application Schematic
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
142
Typical Applications
8.2
Bill of Material
The following table provides a complete list of the recommended components on a full featured system using the MC34708
Device. Critical components such as inductors, transistors, and diodes are provided with a recommended part number, but
equivalent components may be used.
(84)
Table 161. MC34708 Bill of Material
Item
Quantity Component
Description
MC34708
Vendor
Comments
Freescale
PMIC
1
1
Battery Interface
10 F
TDK
Battery Filter
2
3
4
5
6
7
1
2
1
1
1
1
C1
R1
20 mOhm
10 F
Battery Sense (Optional for battery current sensing)
BP/ buck charging capacitor
C2
1 uF
VBUS 1 uF input cap
C67
D2
Green LED
Red LED
Green general purpose LED indicator
Red General purpose LED indicator
D1
Miscellaneous
1.0 F
VALWAYS
8
9
1
1
1
1
1
1
1
1
1
1
2
1
C56
C43
C50
C51
C52
C49
C46
Y1
100 nF
VSRTC
1.0 F
VCORE
10
11
12
13
14
15
16
17
18
19
Boost
20
21
22
23
1.0 F
VCOREDIG
100 pF
VDDLP
100 nF
VCOREREF
100 nF
Coin cell
Crystal 32.768 kHz CC7
18 pF
Oscillator
Oscillator load capacitor
Oscillator load capacitor
RESETB, RESETBMCU Pull-ups
SDWNB Pull-up
C44
C45
R3, R4
R20
18 pF
100 k
100 k
2.2 H LPS3015-222ML
Diode BAS52
2.2 F 16 V
Coilcraft
Infineon
Boost Inductor
1
1
1
2
L9
D3
Boost diode
Boost Output Capacitor
Boost Input Capacitor
C26
C25
22 F
MC34708
Analog Integrated Circuit Device Data
143
Freescale Semiconductor
Typical Applications
(84)
Table 161. MC34708 Bill of Material
Item
SW1
Quantity Component
Description
Vendor
Comments
1.0 H VLS201612ET-1R0N TDK
1.0 H VLS252010ET-1R0N TDK
Buck 1 Inductor (I
< 1.6 Amps)
MAX
Optional dual phase Inductor (I
2.0 Amps)
MAX
24
2
L2, L3
1.0 H BRL3225T1ROM
1.0 uH LPS4012-102NL
22 F
Taiyo Yuden Optional single Phase inductor (I
< 1.6 Amps)
MAX
Coilcraft
Optional single phase inductor (I
Buck 1 Output Capacitor
Buck 1 Input Capacitor
SW1LX diode
2.0 Amps)
MAX
25
26
2
1
1
C6, C7
C5
4.7 F
Diode BAS3010-03LRH
Infineon
27
D8
SW2
28
1.0 H VLS252010ET-1R0N TDK
Buck 2 Inductor
1
1
1
1
L4
22 F
Buck 2 Output Capacitor
Buck 2 Input Capacitor
SW2LX diode
29
C11
C10
D10
4.7 F
30
Diode BAS3010-03LRH
Infineon
31
SW3
32
1.0 H VLS201612ET-1R0N TDK
Buck 3 Inductor
1
1
1
1
L5
10 F
Buck 3 Output Capacitor
Buck 3 Input Capacitor
SW3LX diode
33
C14
C13
D11
4.7 F
34
Diode BAS3010-03LRH
Infineon
35
SW4A
36
1.0 H VLS201612ET-1R0N TDK
Buck 4A Inductor
1
0
1
1
1
L6
1.0 H VLS252010ET-1R0N TDK
Optional Inductor
37
10 F
Buck 4A Output Capacitor
Buck 4A Input Capacitor
SW4ALX diode
38
C17
C16
D12
4.7 F
39
Diode BAS3010-03LRH
Infineon
40
SW4B
41
1.0 H VLS201612ET-1R0N TDK
Buck 4B Inductor
1
0
1
1
1
L7
-
1.0 H VLS25010ET-1R0N TDK
Optional Inductor
42
10 F
Buck 4B Output Capacitor
Buck 4B Input Capacitor
SW4BLX diode
43
C20
C19
D13
4.0 F
44
Diode BAS3010-03LRH
Infineon
45
SW5
46
1.0 H VLS252010ET-1R0N TDK
Buck 5 Inductor
1
1
1
L8
22 F
Buck 5 Output Capacitor
Buck 5 Input Capacitor
47
C23
C22
4.7 F
48
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
144
Typical Applications
(84)
Table 161. MC34708 Bill of Material
Item
49
Quantity Component
Description
Vendor
Infineon
Comments
Diode BAS3010-03LRH
SW5LX diode
VPLL
1
1
D14
C30
VPLL
2.2 F
50
VREFDDR
51
100 nF
100 nF
1.0 F
VREFDDR input capacitor
VHALF 0.1 uF caps
VREFDDR
1
1
1
C35
C57
C28
52
53
VDAC
PNP Transistor
• NSS12100UW3
• 2SB1733
On Semi
Rohm
VDAC PNP
VDAC
54
1
Q3
2.2 F
55
56
1
1
C36
R23
Connect this resistor in series with the output capacitor to
provide an extra series resistance of 100 m for LDO
stability.
100 m
VUSB2
PNP transistor
• NSS12100UW3
• 2SB1733
On Semi
Rohm
VUSB2 PNP
VUSB2
57
1
Q1
2.2 F
58
59
1
1
C29
R22
Connect this resistor in series with the output capacitor to
provide an extra series resistance of 40 m for LDO
stability.
40 m
VUSB
60
2.2 F
4.7 F
VUSB
1
1
C47
C38
VGEN1
61
VGEN1
VGEN2
PNP Transistor
• NSS12100UW3
• 2SB1733
On Semi
Rohm
VGEN2 PNP
VGEN2
62
1
Q5
2.2 F
63
64
1
1
C41
R24
Connect this resistor in series with the output capacitor to
provide an extra series resistance of 50 m for LDO
stability.
50 m
WORKAROUNDS
1.5 V LDO
• NCP4682
• NCP4685
On Semi
1.5 V LDO for workaround. See erratum #23 on ER34708
65
1
U2
MC34708
Analog Integrated Circuit Device Data
145
Freescale Semiconductor
Typical Applications
(84)
Table 161. MC34708 Bill of Material
Item
66
Quantity Component
Description
Vendor
Comments
Low voltage Schottky diode
Schottky diode
100 nF
1
1
1
D15
C58
C59
LDO input capacitor
LDO output capacitor
67
100 nF
68
Notes
84. Freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or
tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their
application.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
146
Typical Applications
8.3
MC34708 Layout Guidelines
8.3.1
General board recommendations
1. It is recommended to use an 8 layer board stack-up arranged as follows:
• High current signal
• GND
• Signal
• Power
• Power
• Signal
• GND
• High current signal
2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.
3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
8.3.2
Component Placement
Sense resistors should be placed as Close to the IC as possible. Route the high current path flowing from VBATT to BATTISNSN
as thick and as short as possible to reduce power losses.
8.3.3
General Routing Requirements
1. Some recommended things to keep in mind for manufacturability:
• Via in pads require a 4.5 mil Minimum annular ring. Pad must be 9.0 mils larger than the hole
• Max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils
2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from
power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins.
3. Shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the
ground and power planes shield these traces).
4. Sense pins must be directly connected to the 0.02 Ohm sense resistor R1 (BATTISNSN and BATTISNSP).
5. Avoid coupling trace between important signal/low noise supplies (like VCOREREF, VCORE, VCOREDIG) from any
switching node (i.e. SW1ALXx, SW2LXx, SW3LXx, SW4ALX, SW4BLX, SW5LXx and SWBSTLXx).
6. Make sure all components related to an specific block are referenced to the corresponding ground, e.g. all components
related to the SW1 converter must referenced to GNDSW1A1 and GNDSW1A2.
8.3.4
Parallel Routing Requirements
2
1. SPI/I C signal routing:
• CLK is the fastest signal of the system, so it must be given special care. Here are some tips for routing the communication
signals:
• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to
shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole
signal trace length.
MC34708
Analog Integrated Circuit Device Data
147
Freescale Semiconductor
Typical Applications
Figure 39. Recommended Shielding for Critical Signals.
• These signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane.
• The crystal connected to the XTAL1 and XTAL2 pins must not have a ground plane directly below.
• The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to
each other, or in the same routing layer. If it is necessary to run clock signals parallel to each other, or parallel to any other
signal, then follow a MAX PARALLEL rule as follows:
• Up to 1 inch parallel length – 25 mil minimum separation
• Up to 2 inch parallel length – 50 mil minimum separation
• Up to 3 inch parallel length – 100 mil minimum separation
• Up to 4 inch parallel length – 250 mil minimum separation
• Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals.
Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of
proximity between signals.
2. The R1 resistor must run in parallel to the BATTISNSN and BATTISNSP traces.
8.3.5
Differential Routing
1. DP and DM traces should be routed as 90 ohm differential signals.
2. DPLUS and DMINUS traces should be routed as 90 ohm differential signals.
8.3.6
Switching Regulator Layout Recommendations
1. Per design, the MC34708 is designed to operate with only 1 input bulk capacitor. However, it is recommended to add a
high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the
range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
2. Make high-current ripple traces low inductance (short, high W/L ratio).
3. Make high-current traces wide or copper islands.
4. Make high-current traces SYMETRICAL for dual–phase regulators (SW1, SW4).
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
148
Typical Applications
BP
SWxVIN
CIN_HF
CIN
SWx
SWxLX
Diver Controller
L
COUT
D
GNDSWx
SWxFB
Compensation
Figure 40. Generic Buck Regulator Architecture
Figure 41. Recommended Layout for Switching Regulators.
MC34708
Analog Integrated Circuit Device Data
149
Freescale Semiconductor
Typical Applications
8.4
Thermal Considerations
Rating Data
8.4.1
The thermal rating data of the packages has been simulated with the results listed in Table 5.
Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol R
or θJA (Theta-JA)
θJA
strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. R
or θJMA (Theta-
θJMA
JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced
convection on both 1s and 2s2p test boards. The generic name, Theta-JA, is expected to continue to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org/
8.4.2
Estimation of Junction Temperature
An estimation of the chip junction temperature TJ can be obtained from the equation
T = T + (R
x P )
D
J
A
θJA
with
T = Ambient temperature for the package in °C
A
R = Junction to ambient thermal resistance in °C/W
JA
P = Power dissipation in the package in W
D
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board R
and the
θJA
value obtained on a four layer board R
. Actual application PCBs show a performance close to the simulated four layer board
θJMA
value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the
device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
T = T + (R
x P ) with
D
J
B
θJB
T = Board temperature at the package perimeter in °C
B
R
= Junction to board thermal resistance in °C/W
θJB
P = Power dissipation in the package in W
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
See Thermal Characteristics for more details on thermal management.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
150
Package Mechanical Dimensions
9
Package Mechanical Dimensions
The MC34708 is offered in two pin compatible 206 pin MAPBGA packages, an 8.0x8.0 mm, 0.5 mm pitch package, and a
13x13 mm, 0.8 mm pitch package.
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to
www.freescale.com and perform a keyword search for the drawing’s document number.
Table 162. Package Drawing Information
Package
Suffix
Package Outline Drawing Number
98ASA00312D
98ASA00299D
206-pin MAPBGA (8 x 8), 0.5 mm
206-pin MAPBGA (13 x 13), 0.8 mm
VK
VM
Dimensions shown are provided for reference ONLY (For Layout and Design, refer to the Package Outline Drawing listed in the
following figures).
MC34708
Analog Integrated Circuit Device Data
151
Freescale Semiconductor
Package Mechanical Dimensions
9.1
206-pin MAPBGA (8 x 8), 0.5 mm
VK SUFFIX (PB-FREE)
206-PIN
98ASA00312D
ISSUE 0
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
152
Package Mechanical Dimensions
VK SUFFIX (PB-FREE)
206-PIN
98ASA00312D
ISSUE 0
MC34708
Analog Integrated Circuit Device Data
153
Freescale Semiconductor
Package Mechanical Dimensions
9.2
206-pin MAPBGA (13 x 13), 0.8 mm
VM SUFFIX (PB-FREE)
206-PIN
98ASA00299D
ISSUE A
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
154
Package Mechanical Dimensions
VM SUFFIX (PB-FREE)
206-PIN
98ASA00299D
ISSUE A
MC34708
Analog Integrated Circuit Device Data
155
Freescale Semiconductor
Reference Section
10 Reference Section
Table 163. MC34708 Reference Documents
Reference
Description
MC34708ER
Errata
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
156
Revision History
11 Revision History
.
REVISION
6.0
DATE
DESCRIPTION OF CHANGES
•
Initial release
7/2011
10/2011
•
•
•
•
•
•
•
•
•
•
•
Corrected the two pins SW2PWGD and SDWNB, and associated drawings.
Changed LED Driver Electrical Specifications, VPLL Matching from 3.0 to 4.0%
Changed VPLL Electrical Specification, tON-VPLL from 100 to 120 s
Changed SWBST Electrical Specifications, ILEAK_SWBST from 5.0 to 6.0 A
Added Max limit to Charger Input Current Limit (Using the USB input).
Added note (61) to VREFDDR
Changed RUSB ON value to 5.0 typ, 8.0 max
Set MIC bias to 1.5 V, and changed ON resistance values to 75 typ and 150 max.
Added Efficiency values for all Buck Converter
7.0
Added diodes to the LX pin on SW1, SW2, SW3, SW4A, SW4B, and SW5.
Updated schematics to reflect the LX pin diodes on SW1, SW2, SW3, SW4A, SW4B, and SW5, and
removed the 10 F VBUSVIN input capacitor.
•
•
•
Removed charger and coulomb counter functionality throughout the document. Section 7.6
removed.
Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 38, Figure 20, Figure 26, Figure 28, Figure
30, Figure 31, Figure 40.
Update Table 3
8.0
7/2012
•
Pin function changed to “O” on pins VCORE, VCOREDIG, VALWAYS, VCOREREF, VDDLP,
and TSREF.
•
Pin function to “I” on pins ADIN11, TSX1/ADIN12, TSX2/ADIN13, TSY1/ADIN14 and TSY2/
ADIN15
•
•
Description for unsupported charger and coulomb counter pins modified.
Clarified ICTEST description
•
•
•
•
•
Update Table 4 with maximum pin rating for all blocks.
Added Table 7 “Die Temp Debounce Settings”
Updated thermal monitor operation in section 5.2.1
Removed PRETMR, ITRICKLE, VSRT and ADC specifications in Table 9.
Changed typ current spec for ON Standby (LPM) from 260 uA to 340uA, changed ON Standby
Digital Core from 370uA to 480uA and removed all charger conditions in Table 10.
Updated section 6.1 feature list
•
•
•
•
•
•
•
•
•
Renamed all instances of APSKIP to APS.
Updated Table 15: VSRTC quiescent current to 1.7uA @1.2V setting and 2.7uA @ 1.3V setting.
GLBRSTTMR[1:0], value “00” changed to Invalid option in Table 24.
Removed interrupt, mask and sense bit related to charger and coulomb counter in Table 21.
Changed debounce time for THERMxxx interrupts.
Updated SW4A/B operation and removed 3.3V setting from SW4A/B in section 7.5.4.6
Removed AUX attach in section 7.5.3.4
Replaced “Under Voltage Detection” event in section 7.5.3.5 with “BP lower than VBAT_TRKL”
event.
•
•
•
•
•
•
•
•
•
•
•
Changed UVDET threshold to 3.1V (rising)/ 2.65V (falling) in Table 27
Added PWMPS mode description on Table 31
Changed quiescent currents for all switching regulators ISWxQ in PWMPS and APS modes.
LDO Short Circuit Protection feature no longer supported.
Changed ADC channels 4 and 7 to “Reserved”
Added Figure 19. Added section 7.8.3.
Removed VBATTREMTH specification from Table 77
Removed charger support from section 7.8.4
Removed IVBUS quiescent current specification for dedicated charger condition in Table 97
Updated components to BOM in section 8.2
Updated SPI register map
•
Replaced Figures 42-45 with Table 104 SPI/I2C Register Map
•
Updated Table 101 and Table 104 to match removed functionality
•
Updated Table 105 through Table 158 to match removed functionality
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
157
Revision History
REVISION
DATE
10/2012
DESCRIPTION OF CHANGES
•
•
Corrected pins E14, E15, and F7 in Table 3
Corrected Figure 3, Ball Map.
9.0
•
Update table 3. Pin definition
10
2/2013
•
•
•
Pin TRICKLESEL, Function = I, Description = Connect to VCOREDIG
Pin PRETMR, Function = I, Description = Connect to Ground
Pin BPTHERM, Function = I, Description = Connect to Ground
•
Update Table 4. Maximum rating
•
Update IC core Reference maximum pin voltages.
•
Update LDO regulator maximum pin voltage.
•
•
•
•
•
•
•
Table 5. Note added to restrict operation at maximum temperature ratings.
Table 10. Update Mode descriptions.
Removed PWMPS mode on all Buck Switching regulators.
Corrected SWBST operating mode PWM to APS
Typical short circuit protection defined to 20% above ILMAX
Remove Noise specifications from all LDO regulators.
Removed Short-circuit protection threshold specification from VUSB2, VDAC and VGEN1 and
VUSB.
•
•
•
Removed Spurs specification on VDAC and VGEN1
Changed PSRR specifications for all LDO regulators to typical value only.
Changed typical VPLLPSRR specifications
•
•
VIN=UVDET: from 40 to 70 dB
VIN=VNOM+1.0 V, >UVDET: from 60 to 75 dB
•
•
•
Changed typical VUSB2PSRR specifications
•
•
VIN=VINMIN + 100 mV: from 40 to 30 dB
VIN=VNOM+1.0 V: from 60 to 30 dB
Changed typical VDACPSRR specifications
•
•
VIN=VINMIN + 100 mV: from 40 to 50 dB
VIN=VNOM+1.0 V: from 60 to 50 dB
Changed typical VGEN1PSRR specifications
•
•
VIN=VINMIN + 100 mV: from 60 to 50 dB
VIN=VNOM+1.0 V: from - to 45 dB
•
•
Changed typical VUSBPSRR specifications
VIN=VINMIN + 100 mV: from 40 to 65 dB
Specified total series resistance of VGEN2 output capacitance to 60mΩ ±20% including capacitor
ESR.
•
•
•
•
•
•
•
•
•
•
Changed ADC drift over temperate from 1 to 10 LSB
Update Bill of materials
Corrected sensing point for ADC channel 2, from BP to BPSENSE pin.
Table 81. LED driver control option x00 changed the CHRGLEDx status to Off.
Changed section 7.8.4.15 title to Device Detect mode
Updated figure 38
Updated General Purpose LED Drivers Current Programming
Corrected Table 14 VCOREDIG spec
Modified Table 82 LED current programming
•
No technical changes. Revised back page. Updated document properties. Added SMARTMOS
sentence to first paragraph. Changed to Technical Data.
4/2013
•
•
Updated section Oscillator Specifications.
11
11/2013
Added note (38) to VSRTC Electrical Specifications table.
MC34708
Analog Integrated Circuit Device Data
Freescale Semiconductor
158
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC34708
Rev. 11.0
11/2013
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