935320734518 [NXP]

Brush DC Motor Controller;


型号：	935320734518
厂家：	NXP
描述：	Brush DC Motor Controller 电动机控制
文件：	总20页 (文件大小：837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Document Number: MPC17510

Rev. 6.0, 7/2016

NXP Semiconductors

Technical Data

1.2 A 15 V H-Bridge motor driver IC

17510

The 17510 is a monolithic H-Bridge designed to be used in portable electronic

applications such as digital and SLR cameras to control small DC motors.

The 17510 can operate efficiently with supply voltages as low as 2.0 V to as high

as 15 V. Its low R_DS(on)H-Bridge output MOSFETs (0.45 Ω typical) can provide

continuous motor drive currents of 1.2 A and handle peak currents up to 3.8 A.

It is easily interfaced to low-cost MCUs via parallel 5.0 V compatible logic. The

device can be pulse width modulated (PWMed) at up to 200 kHz.

H-BRIDGE MOTOR DRIVER

This device contains an integrated charge pump and level shifter (for gate drive

voltages), integrated shoot-through current protection (cross-conduction

suppression logic and timing), and undervoltage detection and shutdown

circuitry.

EJ Suffix (Pb-Free)

98ASA00887D

20-pin TSSOP

EJ Suffix (Pb-Free)

98ASH70455A

24-LEAD TSSOP

The 17510 has four operating modes: Forward, Reverse, Brake, and Tri-stated

(high-impedance). This device is powered by SMARTMOS technology.

with exposed pad

Features

• 2.0 V to 15 V continuous operation

• Output current 1.2 A (DC), 3.8 A (peak)

• 450 mΩ R_DS(on)H-Bridge MOSFETs

• 5.0 V TTL-/CMOS-compatible inputs

• PWM frequencies up to 200 kHz

• Undervoltage shutdown

• Cross-conduction suppression

5.0 V

VDD

15 V

17510

C1L

GOUT

C1H

C2L

C2H

CRES

OUT1

MOTOR

GIN

IN1

IN2

OUT2

MCU

GND

Figure 1. 17510 simplified application diagram

Orderable parts

Table 1. Orderable part variations ⁽¹⁾

Part number

Temperature (T )

Package

MPC17510AEJ

MPC17510EJ ⁽²⁾

20 TSSOP (exposed pad)

24 TSSOPW

-30 °C to 65 °C

Notes

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

2. Not recommended for new designs.

17510

NXP Semiconductors

Internal block diagram

C2H

C2L

C1H

C1L

GOUT

CRES

VDD

Charge Pump

Low Voltage

Detector

OUT1

IN1

IN2

Level

Shifter

Predriver

H-Bridge

OUT2

Control

Logic

GIN

PGND

LGND

Figure 2. 17510 simplified internal block diagram

17510

NXP Semiconductors

Pin connections

OUT1

LGND

CRES

GIN

Transparent

top view

VDD

OUT1

LGND

CRES

OUT1

PGND

GIN

VDD

OUT1

PGND

OUT2

PGND

OUT2

IN1

IN2

GOUT

C2H

C2L

IN2

GOUT

C2H

C2L

C1H

C1L

20-Pin TSSOP

24-Pin TSSOPW

Figure 3. 17510 pin connections

3.1

Pin definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.

Table 2. 17510 pin definitions

Pin number

24-Pin TSSOPW 20-Pin TSSOP

Pin number

Pin Name

Formal Name

Definition

1, 5

1,4

OUT1

LGND

Output 1

Driver output 1 pins

Logic ground

Logic Ground

Charge Pump Output

Capacitor Connection

CRES

Charge pump reservoir capacitor pin

4, 7, 20, 22

17, 18

—

No Connect

Output 2

No connection to these pins

Driver output 2 pins

Power ground

15, 16

5, 17

OUT2

PGND

6, 19

Power Ground

Motor Drive Power

Supply

8, 21

6, 18

Motor power supply voltage input pins

IN1

IN2

Input Control 1

Input Control 2

Control signal input 1 pin

Control signal input 2 pin

C1H

C1L

C2L

C2H

GOUT

Charge Pump 1H

Charge Pump 1L

Charge Pump 2L

Charge Pump 2H

Gate Driver Output

Enable Control

Charge pump bucket capacitor 1 (positive pole)

Charge pump bucket capacitor 1 (negative pole)

Charge pump bucket capacitor 2 (negative pole)

Charge pump bucket capacitor 2 (positive pole)

Output gate driver signal to external MOSFET switch

Enable control signal input pin

VDD

GIN

Logic Supply

Control circuit power supply pin

Gate Driver Input

LOW = True control signal for GOUT pin

17510

NXP Semiconductors

Electrical characteristics

Table 3. Maximum ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage

to the device.

Symbol

Ratings

Value

Unit

Notes

Motor Supply Voltage

-0.5 to 16

-0.5 to 13

-0.5 to 16

(3)

V_CRES

Charge Pump Output Voltage

Logic Supply Voltage

Signal Input Voltage (EN, IN1, IN2, GIN)

-0.5 to V +0.5

Driver Output Current

• Continuous

• Peak

1.2

3.8

(4)

(5)

OPK

ESD Voltage

• Human Body Model

• Machine Model

±1900

±130

ESD1

ESD2

Storage Temperature

-65 to 150

-30 to 150

-30 to 65

1.0

°C

STG

Operating Junction Temperature

Operating Ambient Temperature

Power Dissipation

T_A

°C

(6)

(7)

Thermal Resistance

120

°C/W

°C

θJA

Soldering Temperature

260

SOLDER

Notes

3. When supplied externally, connect via 3.0 kΩ resistor.

4. = 25 °C, 10 ms pulse at 200 ms interval.

5. ESD1 testing is performed in accordance with the Human Body Model (C_ZAP= 100 pF, R_ZAP= 1500 Ω), ESD2 testing is performed in accordance

with the Machine Model (C_ZAP= 200 pF, R_ZAP= 0 Ω).

T = 25 °C, R_θJA= 120 °C/W, 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB).

7. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

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NXP Semiconductors

4.1

Static electrical characteristics

Table 4. Static electrical characteristics

Characteristics noted under conditions T_A= 25 °C, V_M= 15 V, V_DD= 5.0 V, GND = 0 V, unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Power

Characteristic

Min.

Typ.

Max.

Unit

Notes

V_M

V_DD

Motor Supply Voltage

Logic Supply Voltage

2.0

4.0

–

5.5

0.1

C1, C2, C3

Capacitor for Charge Pump

0.001

μF

Standby Power Supply Current

• Motor Supply Standby Current

• Logic Supply Standby Current

(8)

(9)

–

0.3

1.0

μA

VMSTBY

VDDSTBY

^IVDD

Logic Supply Current

–

3.3

4.0

Low Voltage Detection Circuit

(10)

(11)

• Detection Voltage (V_DD

• Detection Voltage (V_M)

)

V_DDDET

V_MDET

1.5

4.0

2.5

5.0

3.5

6.0

Driver Output ON Resistance

• V_M= 2.0 V, 8.0 V, 15 V

R_DS(on)

–

0.45

0.55

Gate drive

Gate Drive Voltage

• No Current Load

(12)

V_CRES

13.5

–

Gate Drive Ability (Internally Supplied)

• ^ICRES = -1.0 mA

V_CRESLOAD

11.2

Gate Drive Output

• I_OUT= -50 μA

• I_IN= 50 μA

V_GOUTHIGH

V_GOUTLOW

_CRES-0.5 V_CRES-0.1

V_CRES

LGND

LGND +0.1 LGND+0.5

Control logic

V_IN

Logic Input Voltage (EN, IN1, IN2, GIN)

0.0

–

V_DD

Logic Input Function (4.0 V < V_DD< 5.5 V)

• High Level Input Voltage

• Low Level Input Voltage

• High Level Input Current

• Low Level Input Current

• EN/GIN Pin

V_IH

V_IL

I_IH

I_IL

V_DDx 0.7

–

-50

–

μA

–

-1.0

-200

V_DDx 0.3

1.0

–

I_IL

Notes

8. Excluding pull-up resistor current, including current of gate-drive circuit.

9. _IN= 100 kHz.

10. Detection voltage is defined as when the output becomes high-impedance after V_DDdrops below the detection threshold. When the gate voltage

_CRESis applied from an external source, V_CRES= 7.5 V.

11. I_O= 1.2 A source + sink.

12. Input logic signal not present.

17510

NXP Semiconductors

4.2

Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics

Characteristics noted under conditions T_A= 25 °C, V_M= 15 V, V_DD= 5.0 V, GND = 0 V unless otherwise noted. Typical values noted

reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless otherwise noted.

Symbol

Characteristic

Min.

Typ.

Max.

Unit

Notes

Input (EN, IN1, IN2, GIN)

f_IN

t_R

t_F

Pulse Input Frequency

–

200

kHz

μs

(13)

(15)

Input Pulse Rise Time

Input Pulse Fall Time

1.0 ⁽¹⁴⁾

μs

Output

Propagation Delay Time

• Turn-ON Time

t_PZH

t_PLH

t_PHL

–

0.3

1.2

0.5

1.0

2.0

1.0

μs

• Turn-ON Time

• Turn-OFF Time

GOUT Output Delay Time

• Turn-ON Time

(16)

(17)

t_TON

t_TOFF

–

• Turn-OFF Time

Charge Pump Circuit

• Oscillator Frequency

• Rise Time

f_OSC

100

–

200

0.1

400

1.0

kHz

tV_CRESON

tV_DDDET

Notes

13. Time is defined between 10% and 90%.

Low-voltage Detection Time

–

14. That is, the input waveform slope must be steeper than this.

15. Time is defined between 90% and 10%.

16. Load is 500 pF.

17. Time to charge C_RESto 11 V after application of V_DD

4.3

Timing diagrams

DETON

DETOFF

IN1, IN2, EN

(GIN)

3.5 V

50%

t_{PZH ,}

t_PHL

₍t_TOFF)

1.5 V

t_PLH

₍t_TON)

90%

VDDDET

DET

OUTn

(GOUT)

90%

10%

I_M

(<1.0 μA)

*The last state is “Z”.

Figure 4. t_PLH, t_PHL, and t_PZHtiming

Figure 5. Low-voltage detection timing

17510

NXP Semiconductors

Table 6. Truth table

INPUT

OUTPUT

OUT2

IN1

IN2

GIN

OUT1

GOUT

H = High.

L = Low.

Z = High-impedance.

X = Don’t care.

The GIN pin and EN pin are pulled up to V

with internal resistance.

17510

NXP Semiconductors

Functional description

5.1

Introduction

The 17510 is a monolithic H-Bridge power IC applicable to small DC motors used in portable electronics. The 17510 can operate efficiently

with supply voltages as low as 2.0 V to as high as 15 V, and it can provide continuos motor drive currents of 1.2 A while handling peak

currents up to 3.8 A. It is easily interfaced to low-cost MCUs via parallel 5.0 V-compatible logic. The device can be pulse width modulated

(PWM-ed) at up to 200 kHz. The 17510 has four operating modes: Forward, Reverse, Brake, and Tri-stated (High-impedance).

Basic protection and operational features (direction, dynamic braking, PWM control of speed and torque, main power supply undervoltage

detection and shutdown, logic power supply undervoltage detection and shutdown), in addition to the 1.0 A rms output current capability,

make the 17510 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 17510

devices can be used to control bipolar stepper motors. The 17510 can also be used to excite transformer primary windings with a switched

square wave to produce secondary winding AC currents.

As shown in Figure 2, 17510 simplified internal block diagram, page 3, the 17510 is a monolithic H-Bridge with built-in charge pump

circuitry. For a DC motor to run, the input conditions need to be set as follows: ENable input logic HIGH, one INput logic LOW, and the

other INput logic HIGH (to define output polarity). The 17510 can execute dynamic braking by setting both IN1 and IN2 logic HIGH, causing

both low-side MOSFETs in the output H-Bridge to turn ON. Dynamic braking can also implemented by taking the ENable logic LOW. The

output of the H-Bridge can be set to an open-circuit high-impedance (Z) condition by taking both IN1 and IN2 logic LOW. (refer to Table

6, Truth table, page 8).

The 17510 outputs are capable of providing a continuous DC load current of up to 1.2 A. An internal charge pump supports PWM

frequencies to 200 kHz. The EN pin also controls the charge pump, turning it off when EN = LOW, thus allowing the 17510 to be placed

in a power-conserving sleep mode.

5.2

Functional pin description

5.2.1 Output 1 and output2 (OUT1, OUT2)

The OUT1 and OUT2 pins provide the connection to the internal power MOSFET H-Bridge of the IC. A typical load connected between

these pins would be a small DC motor. These outputs will connect to either VM or PGND, depending on the states of the control inputs

(refer to Table 6, Truth table, page 8).

5.2.2 Power ground and logic ground (PGND, LGND)

The power and logic ground pins (PGND and LGND) should be connected together with a very low-impedance connection.

5.2.3 Charge pump reservoir capacitor (CRES)

The CRES pin provides the connection for the external reservoir capacitor (output of the charge pump). Alternatively this pin can also be

used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. The voltage at the CRES pin

will be approximately three times the V_DDvoltage, as the internal charge pump utilizes a voltage tripler circuit. The V_CRESvoltage is used

by the IC to supply gate drive for the internal power MOSFET H-Bridge.

5.2.4 Motor supply voltage input (VM)

The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or

modulated by the IC as it delivers the power to the load attached between OUT1 and OUT2. All VM pins must be connected together on

the printed circuit board with as short as possible traces offering as low impedance as possible between pins.

VM has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a

tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal

operation according to the established condition of the input pins.

17510

NXP Semiconductors

5.2.5 Control signal input and enable control signal input (IN1, IN2, EN)

The IN1, IN2, and EN pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis.

The IN1, IN2, and EN work together to control OUT1 and OUT2 (refer to Table 6, Truth table).

5.2.6 Gate driver input (GIN)

The GIN input controls the GOUT pin. When GIN is set logic LOW, GOUT supplies a level-shifted high side gate drive signal to an external

MOSFET. When GIN is set logic HIGH, GOUT is set to GND potential.

5.2.7 Charge pump bucket capacitor (C1L, C1H, C2L, C2H)

These two pairs of pins, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge

pump. The typical value for the bucket capacitors is 0.1 μF.

5.2.8 Gate driver output (GOUT)

The GOUT output pin provides a level-shifted, high side gate drive signal to an external MOSFET with C

up to 500 pF.

ISS

5.2.9 Control circuit power supply (VDD)

The VDD pin carries the 5.0 V supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply

voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns

to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of

the input pins.

17510

NXP Semiconductors

Typical applications

Figure 6 shows a typical application for the 17510.

5.0 V

17510

V_DD

GOUT

C1L

C1H

C2L

C2H

CRES

OUT1

OUT2

Motor

Solenoid

GIN

IN1

IN2

MCU

GND

Figure 6. 17510 typical application diagram

6.1

CEMF snubbing techniques

Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads.

Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply pin (VM) (see Figure 7).

5.0 V

VDD

15 V

5.0 V

15 V

17510

C1L

C1H

C2L

C2H

CRES

C1L

C1H

C2L

C2H

CRES

OUT2

OUT1

OUT2

GND

Figure 7. CEMF snubbing techniques

17510

NXP Semiconductors

Packaging

7.1

Package dimensions

For the most current package revision, visit www.nxp.com and perform a keyword search using the “98A” listed below.

17510

NXP Semiconductors

17510

NXP Semiconductors

17510

NXP Semiconductors

17510

NXP Semiconductors

17510

NXP Semiconductors

17510

NXP Semiconductors

17510

NXP Semiconductors

Revision history

Revision

Date

Description of changes

•

Implemented a Revision History page.

Converted to Freescale format, and updated to the prevailing form and style

Added EJ Pb-FREE package

2.0

3.0

4.0

7/2006

1/2007

11/2013

•

Corrected symbol in Table 3, Driver Output ON Resistance from “W” to “Ω”

•

Corrected pin names to match throughout the document

Corrected minor errors in format. No change in technical content

Moved data sheet to Technical Data status

•

Added 98ASA00887D package information and updated tables where applicable

Added MPC17510AEJ to the ordering information

Updated as per PCN # 16724

7/2015

8/2015

5.0

6.0

•

Corrected the 98A package information for 20-pin TSSOP

•

Added EP notation for TSSOP package

Fixed notations for TSSOP in Orderable parts and Pin connections

Updated Packaging 98A drawing for TSSOP

10/2015

7/2016

Removed MPC17510MTB parts from the data sheet. No longer manufactured.

•

Updated to NXP document form and style

17510

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

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Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

Document Number: MPC17510

Rev. 6.0

7/2016

935320734518 [NXP]

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