935320756557_技术文档

Document Number MKE04P80M48SF0

Rev. 5, 01/2019

NXP Semiconductors

Data Sheet: Technical Data

MKE04P80M48SF0

KE04 Sub-Family Data Sheet

Supports the following:

MKE04Z64VLD4(R),

MKE04Z128VLD4(R),

MKE04Z64VQH4(R),

MKE04Z128VQH4(R),

MKE04Z64VLH4(R),

MKE04Z128VLH4(R),

MKE04Z64VLK4(R) and

MKE04Z128VLK4(R)

Key features

• Security and integrity modules

– 80-bit unique identification (ID) number per chip

• Operating characteristics

– Voltage range: 2.7 to 5.5 V

• Human-machine interface

– Flash write voltage range: 2.7 to 5.5 V

– Temperature range (ambient): -40 to 105°C

– Up to 71 general-purpose input/output (GPIO)

– Two 32-bit keyboard interrupt modules (KBI)

– External interrupt (IRQ)

• Performance

– Up to 48 MHz Arm® Cortex-M0+ core

– Single cycle 32-bit x 32-bit multiplier

– Single cycle I/O access port

• Analog modules

– One up to 16-channel 12-bit SAR ADC, operation in

Stop mode, optional hardware trigger (ADC)

– Two analog comparators containing a 6-bit DAC

and programmable reference input (ACMP)

• Memories and memory interfaces

– Up to 128 KB flash

– Up to 16 KB RAM

• Timers

– One 6-channel FlexTimer/PWM (FTM)

– Two 2-channel FlexTimer/PWM (FTM)

– One 2-channel periodic interrupt timer (PIT)

– One pulse width timer (PWT)

– One real-time clock (RTC)

• Clocks

– Oscillator (OSC) - supports 32.768 kHz crystal or 4

MHz to 24 MHz crystal or ceramic resonator; choice

of low power or high gain oscillators

– Internal clock source (ICS) - internal FLL with

internal or external reference, 37.5 kHz pre-trimmed

internal reference for 48 MHz system clock

– Internal 1 kHz low-power oscillator (LPO)

• Communication interfaces

– Two SPI modules (SPI)

– Up to three UART modules (UART)

– Two I2C modules (I2C)

• System peripherals

– Power management module (PMC) with three power

modes: Run, Wait, Stop

• Package options

– 80-pin LQFP

– Low-voltage detection (LVD) with reset or interrupt,

selectable trip points

– 64-pin QFP/LQFP

– 44-pin LQFP

– Watchdog with independent clock source (WDOG)

– Programmable cyclic redundancy check module

(CRC)

– Serial wire debug interface (SWD)

– Aliased SRAM bitband region (BIT-BAND)

– Bit manipulation engine (BME)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

2

NXP Semiconductors

Table of Contents

1 Ordering parts.......................................................................................4

5.2.2 FTM module timing....................................................... 17

5.3 Thermal specifications.................................................................18

5.3.1 Thermal operating requirements.................................... 18

5.3.2 Thermal characteristics.................................................. 19

6 Peripheral operating requirements and behaviors................................ 20

6.1 Core modules............................................................................... 20

6.1.1 SWD electricals .............................................................20

6.2 External oscillator (OSC) and ICS characteristics.......................21

6.3 NVM specifications..................................................................... 23

6.4 Analog..........................................................................................24

6.4.1 ADC characteristics....................................................... 24

6.4.2 Analog comparator (ACMP) electricals.........................27

6.5 Communication interfaces........................................................... 27

6.5.1 SPI switching specifications.......................................... 27

7 Dimensions...........................................................................................30

7.1 Obtaining package dimensions.................................................... 30

8 Pinout................................................................................................... 31

8.1 Signal multiplexing and pin assignments.................................... 31

8.2 Device pin assignment.................................................................33

9 Revision history....................................................................................36

1.1 Determining valid orderable parts............................................... 4

2 Part identification................................................................................. 4

2.1 Description...................................................................................4

2.2 Format..........................................................................................4

2.3 Fields............................................................................................4

2.4 Example....................................................................................... 5

3 Parameter classification........................................................................5

4 Ratings..................................................................................................6

4.1 Thermal handling ratings.............................................................6

4.2 Moisture handling ratings............................................................ 6

4.3 ESD handling ratings...................................................................6

4.4 Voltage and current operating ratings..........................................7

5 General................................................................................................. 7

5.1 Nonswitching electrical specifications........................................ 7

5.1.1 DC characteristics.......................................................... 7

5.1.2 Supply current characteristics........................................ 14

5.1.3 EMC performance..........................................................15

5.2 Switching specifications.............................................................. 16

5.2.1 Control timing................................................................ 16

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

3

Ordering parts

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search for the

following device numbers: KE06Z.

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format:

Q KE## A FFF R T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations

are valid):

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

KE##

A

Kinetis family

Key attribute

• KE04

• Z = M0+ core

• 128 = 128 KB

FFF

R

Program flash memory size

Silicon revision

• (Blank) = Main

• A = Revision after main

T

Temperature range (°C)

Package identifier

• V = –40 to 105

PP

• LD = 44 LQFP (10 mm x 10 mm)

Table continues on the next page...

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

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NXP Semiconductors

Parameter classification

Values

Field

Description

• QH = 64 QFP (14 mm x 14 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• LK = 80 LQFP (14 mm x 14 mm)

CC

N

Maximum CPU frequency (MHz)

Packaging type

• 4 = 48 MHz

• R = Tape and reel

• (Blank) = Trays

2.4 Example

This is an example part number:

MKE06Z128VLK4

3 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods.

To give the customer a better understanding, the following classification is used and the

parameters are tagged accordingly in the tables where appropriate:

Table 1. Parameter classifications

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size

across process variations.

T

Those parameters are achieved by design characterization on a small sample size from typical devices under

typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the

parameter tables where appropriate.

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

5

Ratings

4 Ratings

4.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol

V_HBM

V_CDM

I_LAT

Description

Min.

–6000

–500

–100

Max.

+6000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

Electrostatic discharge voltage, charged-device model

Latch-up current at ambient temperature of 125°C

1

2

3

V

+100

mA

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.

• Test was performed at 125 °C case temperature (Class II).

• I/O pins pass 100 mA I-test with I_DDcurrent limit at 400 mA.

• I/O pins pass +50/-100 mA I-test with I_DDcurrent limit at 1000 mA.

• Supply groups pass 1.5 V_ccmax

.

• RESET pin was only tested with negative I-test due to product conditioning requirement.

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NXP Semiconductors

General

4.4 Voltage and current operating ratings

Absolute maximum ratings are stress ratings only, and functional operation at the

maxima is not guaranteed. Stress beyond the limits specified in the following table may

affect device reliability or cause permanent damage to the device. For functional

operating conditions, refer to the remaining tables in this document.

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid

application of any voltages higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate

logic voltage level (for instance, either V_SSor V_DD) or the programmable pullup resistor

associated with the pin is enabled.

Table 2. Voltage and current operating ratings

Symbol

V_DD

Description

Min.

–0.3

—

Max.

Unit

V

Digital supply voltage

6.0

I_DD

Maximum current into V_DD

Input voltage except true open drain pins

Input voltage of true open drain pins

120

V_DD+ 0.3¹

mA

V

V_IN

–0.3

–25

6

V

I_D

Instantaneous maximum current single pin limit (applies to all

port pins)

25

mA

V_DDA

Analog supply voltage

V_DD– 0.3

V_DD+ 0.3

V

1. Maximum rating of V_DDalso applies to V_IN.

5 General

5.1 Nonswitching electrical specifications

5.1.1 DC characteristics

This section includes information about power supply requirements and I/O pin

characteristics.

Table 3. DC characteristics

Symbol

C

Descriptions

Operating voltage²

Table continues on the next page...

Min

Typical¹

Max

Unit

—

2.7

—

5.5

V

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

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Nonswitching electrical specifications

Table 3. DC characteristics (continued)

Symbol

C

P

Descriptions

Min

Typical¹

Max

—

Unit

V

V_OH

Output All I/O pins, except PTA2 5 V, I_load= –5 mA

V_DD– 0.8

—

high

voltage

and PTA3, standard-

drive strength

C

3 V, I_load= –2.5 mA

—

V

P

C

D

High current drive pins, 5 V, I_load= –20 mA

V_DD– 0.8

—

V

high-drive strength³

3 V, I_load= –10 mA

I_OHT

Output Max total I_OHfor all ports

5 V

3 V

–100

–60

mA

high

current

—

V_OL

P

C

P

C

D

Output

low

voltage

All I/O pins, standard-

drive strength

5 V, I_load= 5 mA

3 V, I_load= 2.5 mA

5 V, I_load=20 mA

3 V, I_load= 10 mA

5 V

—

0.8

100

60

V

High current drive pins,

high-drive strength³

V

I_OLT

V_IH

V_IL

Output Max total I_OLfor all ports

low

current

mA

3 V

P

Input

high

voltage

All digital inputs

4.5≤V_DD<5.5 V

2.7≤V_DD<4.5 V

0.65 × V_DD

0.70 × V_DD

—

V

Input low

voltage

4.5≤V_DD<5.5 V

2.7≤V_DD<4.5 V

—

0.35 ×

V_DD

0.30 ×

V_DD

V_hys

C

P

C

Input

hysteresi

s

All digital inputs

0.06 × V_DD

—

mV

µA

|I_In|

Input

Per pin (pins in high

V_IN= V_DDor V_SS

—

0.1

—

1

leakage impedance input mode)

current

|I_INTOT

|

Total

Pins in high impedance

input mode

2

leakage

combine

d for all

port pins

R_PU

P

Pullup

resistors

All digital inputs, when

enabled (all I/O pins

other than PTA2 and

PTA3)

—

30.0

—

50.0

60.0

kΩ

4

R_PU

P

D

Pullup

resistors

PTA2 and PTA3 pins

kΩ

I_IC

DC

Single pin limit

V_IN< V_SS, V_IN

V_DD

>

-2

-5

—

2

mA

injection

Total MCU limit, includes

sum of all stressed pins

25

current^5,

6, 7

C_In

C

Input capacitance, all pins

RAM retention voltage

—

7

pF

V

V_RAM

2.0

—

1. Typical values are measured at 25 °C. Characterized, not tested.

2. Max power supply ramp rate is 500 V/ms.

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

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NXP Semiconductors

Nonswitching electrical specifications

3. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0 (64-pin and 80-pin packages only), and PTH1 (64-pin and 80-pin

packages only) support high current output.

4. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured

externally on the pin.

5. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to V_SSand V_DD. PTA2 and PTA3 are true

open drain I/O pins that are internally clamped to V_SS

.

6. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger value.

7. Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If the positive injection current (V_In> V_DD) is higher than I_DD, the injection current may flow out of V_DDand could

result in external power supply going out of regulation. Ensure that external V_DDload will shunt current higher than

maximum injection current when the MCU is not consuming power, such as when no system clock is present, or clock rate

is very low (which would reduce overall power consumption).

Table 4. LVD and POR specification

Symbol

V_POR

C

D

C

Description

Min

1.5

4.2

Typ

1.75

4.3

Max

2.0

Unit

V

POR re-arm voltage¹

V_LVDH

Falling low-voltage detect

threshold—high range (LVDV

= 1)²

4.4

V

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

V_HYSH

C

Falling low- Level 1 falling

4.3

4.5

4.6

4.7

—

4.4

4.5

4.6

4.7

4.8

—

V

voltage

warning

threshold—

high range

(LVWV = 00)

Level 2 falling

(LVWV = 01)

Level 3 falling

(LVWV = 10)

4.6

V

Level 4 falling

(LVWV = 11)

4.7

V

High range low-voltage

detect/warning hysteresis

100

2.61

mV

V

V_LVDL

Falling low-voltage detect

threshold—low range (LVDV

= 0)

2.56

2.66

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

V_HYSDL

V_HYSWL

V_BG

C

P

Falling low- Level 1 falling

2.62

2.72

2.82

2.92

—

2.7

2.8

2.9

3.0

40

2.78

2.88

2.98

3.08

—

V

voltage

warning

threshold—

low range

(LVWV = 00)

Level 2 falling

(LVWV = 01)

Level 3 falling

(LVWV = 10)

V

Level 4 falling

(LVWV = 11)

V

Low range low-voltage detect

hysteresis

mV

V

Low range low-voltage

warning hysteresis

Buffered bandgap output ³

—

80

—

1.14

1.16

1.18

1. Maximum is highest voltage that POR is guaranteed.

2. Rising thresholds are falling threshold + hysteresis.

3. voltage Factory trimmed at V_DD= 5.0 V, Temp = 25 °C

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

9

Nonswitching electrical specifications

V_DD-V_OH(V)

I_OH(mA)

Figure 1. Typical V_DD-V_OHVs. I_OH(standard drive strength) (V_DD= 5 V)

V_DD-V_OH(V)

I_OH(mA)

Figure 2. Typical V_DD-V_OHVs. I_OH(standard drive strength) (V_DD= 3 V)

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

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NXP Semiconductors

Nonswitching electrical specifications

V_DD-V_OH(V)

I_OH(mA)

Figure 3. Typical V_DD-V_OHVs. I_OH(high drive strength) (V_DD= 5 V)

V_DD-V_OH(V)

I_OH(mA)

Figure 4. Typical V_DD-V_OHVs. I_OH(high drive strength) (V_DD= 3 V)

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

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Nonswitching electrical specifications

V_OL(V)

I_OL(mA)

Figure 5. Typical V_OLVs. I_OL(standard drive strength) (V_DD= 5 V)

V_OL(V)

I_OL(mA)

Figure 6. Typical V_OLVs. I_OL(standard drive strength) (V_DD= 3 V)

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

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NXP Semiconductors

Nonswitching electrical specifications

V_OL(V)

I_OL(mA)

Figure 7. Typical V_OLVs. I_OL(high drive strength) (V_DD= 5 V)

V_OL(V)

I_OL(mA)

Figure 8. Typical V_OLVs. I_OL(high drive strength) (V_DD= 3 V)

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

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Nonswitching electrical specifications

5.1.2 Supply current characteristics

This section includes information about power supply current in various operating modes.

Table 5. Supply current characteristics

C

Parameter

Symbol

Core/Bus

Freq

V_DD(V)

Typical¹

Max²

Unit

Temp

C

Run supply current FEI

mode, all modules clocks

enabled; run from flash

RI_DD

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

5

11.1

8

—

mA

-40 to 105 °C

5

—

2.4

11

—

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

3

5

3

5

3

5

3

—

7.9

4.9

2.3

7.8

5.5

3.8

2.3

7.7

5.4

3.7

2.2

14.7

9.8

6

—

C

P

C

P

C

P

C

P

C

Run supply current FEI

mode, all modules clocks

disabled and gated; run

from flash

RI_DD

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

mA

-40 to 105 °C

—

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

Run supply current FBE

mode, all modules clocks

enabled; run from RAM

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

14.9

—

2.4

14.6

9.6

5.9

2.3

11.4

7.7

4.7

2.3

11.3

7.6

4.6

2.2

—

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

12.8

—

Run supply current FBE

mode, all modules clocks

disabled and gated; run

from RAM

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

12.5

—

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

9.5

—

Table continues on the next page...

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NXP Semiconductors

Nonswitching electrical specifications

Table 5. Supply current characteristics (continued)

C

Parameter

Symbol

Core/Bus

Freq

V_DD(V)

Typical¹

Max²

Unit

Temp

C

P

C

P

C

P

Wait mode current FEI

mode, all modules clocks

enabled

WI_DD

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

48/24 MHz

24/24 MHz

12/12 MHz

1/1 MHz

—

5

8.4

6.5

4.3

2.4

8.3

6.4

4.2

2.3

2

—

7.2

—

mA

-40 to 105 °C

—

3

—

7

—

Stop mode supply current

no clocks active (except 1

kHz LPO clock)³

SI_DD

—

5

3

105

95

µA

-40 to 105 °C

—

1.9

C

ADC adder to Stop

ADLPC = 1

—

5

3

86

82

—

-40 to 105 °C

ADLSMP = 1

ADCO = 1

MODE = 10B

ADICLK = 11B

ACMP adder to Stop

C

—

5

3

5

3

12

—

µA

-40 to 105 °C

LVD adder to Stop⁴

130

125

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. The Max current is observed at high temperature of 105 °C.

3. RTC adder cause <1 µA I_DDincrease typically, RTC clock source is 1 kHz LPO clock.

4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.

5.1.3 EMC performance

Electromagnetic compatibility (EMC) performance is highly dependent on the

environment in which the MCU resides. Board design and layout, circuit topology

choices, location and characteristics of external components as well as MCU software

operation play a significant role in EMC performance. The system designer must consult

the following applications notes, available on nxp.com for advice and guidance

specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility

• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS

Microcontrollers

• AN1263: Designing for Electromagnetic Compatibility with Single-Chip

Microcontrollers

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

15

Switching specifications

• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based

Applications

• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-

Based Systems

5.1.3.1 EMC radiated emissions operating behaviors

Table 6. EMC radiated emissions operating behaviors for 80-pin LQFP package

Symbol

Description

Frequency

band (MHz)

Typ.

Unit

Notes

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

6

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

11

5

N³

V_RE4

V_{RE_IEC}

2, 4

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of

Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the

measured orientations in each frequency range.

2. V_DD= 5.0 V, T_A= 25 °C, f_OSC= 8 MHz (crystal), f_SYS= 40 MHz, f_BUS= 20 MHz

3. IEC/SAE Level Maximums: N≤12 dBµV, M≤18 dBµV, K≤30 dBµV, I ≤36 dBµV, H≤42 dBµV.

4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method

5.2 Switching specifications

5.2.1 Control timing

Table 7. Control timing

Num

C

D

P

D

Rating

System and core clock

Bus frequency (t_cyc= 1/f_Bus

Symbol

f_Sys

Min

DC

Typical¹

Max

48

Unit

MHz

KHz

ns

1

2

3

4

—

)

f_Bus

DC

24

Internal low power oscillator frequency

External reset pulse width²

f_LPO

0.67

1.5 ×

t_cyc

1.0

—

1.25

—

t_extrst

5

6

D

Reset low drive

t_rstdrv

t_ILIH

34 × t_cyc

100

—

ns

IRQ pulse width

Asynchronous

path²

D

Synchronous path³

t_IHIL

1.5 × t_cyc

—

ns

Table continues on the next page...

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

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NXP Semiconductors

Switching specifications

Table 7. Control timing (continued)

Num

C

Rating

Symbol

Min

Typical¹

Max

Unit

7

D

Keyboard interrupt pulse

Asynchronous

path²

t_ILIH

100

—

ns

width

D

C

Synchronous path

—

t_IHIL

t_Rise

t_Fall

1.5 × t_cyc

—

10.2

9.5

—

ns

8

Port rise and fall time -

Normal drive strength

(load = 50 pF)⁴

—

C

Port rise and fall time -

high drive strength (load =

50 pF)⁴

—

t_Rise

t_Fall

—

5.4

4.6

—

ns

1. Typical values are based on characterization data at V_DD= 5.0 V, 25 °C unless otherwise stated.

2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.

3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

4. Timing is shown with respect to 20% V_DDand 80% V_DDlevels. Temperature range -40 °C to 105 °C.

t_extrst

RESET_b pin

Figure 9. Reset timing

t_IHIL

KBIPx

IRQ/KBIPx

t_ILIH

Figure 10. KBIPx timing

5.2.2 FTM module timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the

fastest clock that can be used as the optional external source to the timer counter. These

synchronizers operate from the current bus rate clock.

Table 8. FTM input timing

C

Function

Symbol

Min

Max

Unit

D

Timer clock

frequency

f_Timer

f_Bus

f_Sys

Hz

D

External clock

frequency

f_TCLK

0

f_Timer/4

Hz

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17

Thermal specifications

Table 8. FTM input timing (continued)

C

Function

Symbol

Min

Max

Unit

, 1

D

External clock

period

t_TCLK

4

—

t_Timer

1

D

External clock high

time

t_clkh

t_clkl

1.5

—

External clock low

time

Input capture pulse

width

t_ICPW

1. t_Timer= 1/f_Timer

t_TCLK

t_clkh

TCLK

t_clkl

Figure 11. Timer external clock

t_ICPW

FTMCHn

t_ICPW

Figure 12. Timer input capture pulse

5.3 Thermal specifications

5.3.1 Thermal operating requirements

Table 9. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

Unit

°C

Notes

Die junction temperature

Ambient temperature

125

105

T_A

°C

1

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis: T_J= T_A+ θ_JAx chip power dissipation

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NXP Semiconductors

Thermal specifications

5.3.2 Thermal characteristics

This section provides information about operating temperature range, power dissipation,

and package thermal resistance. Power dissipation on I/O pins is usually small compared

to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-

determined rather than being controlled by the MCU design. To take P_I/Ointo account in

power calculations, determine the difference between actual pin voltage and V_SSor V_DD

and multiply by the pin current for each I/O pin. Except in cases of unusually high pin

current (heavy loads), the difference between pin voltage and V_SSor V_DDwill be very

small.

Table 10. Thermal attributes

Board type

Symbol

Description

64

64 QFP

44

80

Unit

Notes

LQFP

Single-layer (1S)

R_θJA

Thermal resistance, junction

to ambient (natural

convection)

71

53

59

46

61

75

53

62

47

57

44

47

38

°C/W

1, 2

Four-layer (2s2p)

Single-layer (1S)

Four-layer (2s2p)

R_θJA

Thermal resistance, junction

to ambient (natural

convection)

47

50

41

°C/W

1, 3

R_θJMAThermal resistance, junction

to ambient (200 ft./min. air

speed)

R_θJMAThermal resistance, junction

to ambient (200 ft./min. air

speed)

—

R_θJB

R_θJC

Ψ_JT

Thermal resistance, junction

to board

35

20

5

32

23

8

34

20

5

28

15

3

°C/W

4

5

6

Thermal resistance, junction

to case

Thermal characterization

parameter, junction to

package top outside center

(natural convection)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.

The average chip-junction temperature (T_J) in °C can be obtained from:

T_J= T_A+ (P_D× θ_JA)

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19

Peripheral operating requirements and behaviors

Where:

T_A= Ambient temperature, °C

θ_JA= Package thermal resistance, junction-to-ambient, °C/W

P_D= P_int+ P_I/O

P_int= I_DD× V_DD, Watts - chip internal power

P_I/O= Power dissipation on input and output pins - user determined

For most applications, P_I/O<< P_intand can be neglected. An approximate relationship

between P_Dand T_J(if P_I/Ois neglected) is:

P_D= K ÷ (T_J+ 273 °C)

Solving the equations above for K gives:

K = P_D× (T_A+ 273 °C) + θ_JA× (P_D)²

where K is a constant pertaining to the particular part. K can be determined by measuring

P_D(at equilibrium) for an known T_A. Using this value of K, the values of P_Dand T_Jcan

be obtained by solving the above equations iteratively for any value of T_A.

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 SWD electricals

Table 11. SWD full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

2.7

5.5

V

J1

SWD_CLK frequency of operation

• Serial wire debug

0

24

—

MHz

ns

J2

J3

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1/J1

20

—

ns

J4

J9

SWD_CLK rise and fall times

—

10

3

ns

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

—

J10

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Peripheral operating requirements and behaviors

Table 11. SWD full voltage range electricals (continued)

Symbol

J11

Description

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

Min.

Max.

35

Unit

ns

—

J12

5

—

ns

J2

J4

J3

SWD_CLK (input)

J4

Figure 13. Serial wire clock input timing

SWD_CLK

SWD_DIO

J9

J10

Input data valid

J11

Output data valid

J12

J11

Output data valid

Figure 14. Serial wire data timing

6.2 External oscillator (OSC) and ICS characteristics

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

Num

C

Characteristic

Low range (RANGE = 0)

High range (RANGE = 1)

Symbol

Min

31.25

4

Typical¹

32.768

—

Max

39.0625

24

Unit

kHz

1

Crystal or

resonator

frequency

f_lo

f_hi

MHz

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Peripheral operating requirements and behaviors

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

(continued)

Num

C

D

Characteristic

Symbol

C1, C2

R_F

Min

Typical¹

See Note²

—

Max

Unit

2

3

Load capacitors

Feedback

resistor

Low Frequency, Low-Power

Mode³

—

MΩ

Low Frequency, High-Gain

Mode

10

1

High Frequency, Low-

Power Mode

High Frequency, High-Gain

Mode

1

2

4

5

D

Series resistor -

Low Frequency

Low-Power Mode ³

High-Gain Mode

Low-Power Mode³

R_S

—

0

200

0

—

kΩ

2

Series resistor -

High Frequency

R_S

D

Series resistor -

High

Frequency,

High-Gain Mode

4 MHz

8 MHz

16 MHz

—

0

—

kΩ

6

C

Crystal start-up

time low range

= 32.768 kHz

crystal; High

range = 20 MHz

crystal^4,5

Low range, low power

Low range, high gain

High range, low power

High range, high gain

t_CSTL

—

1000

800

3

—

ms

t_CSTH

1.5

7

8

T

P

Internal reference start-up time

t_IRST

f_{int_t}

—

20

—

50

µs

Internal reference clock (IRC) frequency trim

range

31.25

39.0625

kHz

9

P

Internal

T = 25 °C, V_DD= 5 V

f_{int_ft}

—

37.5

—

kHz

reference clock

frequency,

factory trimmed^,

10

11

P

DCO output

frequency range

FLL reference = fint_t, flo,

or fhi/RDIV

f_dco

40

—

50

MHz

%

Factory trimmed

internal

T = 25 °C, V_DD= 5 V

Δf_{int_ft}

-0.5

0.5

oscillator

accuracy⁶

12

13

C

Deviation of IRC Over temperature range

Δf_{int_t}

-1

—

0.5

%

over

from -40 °C to 105°C

temperature

when trimmed

at T = 25 °C,

V_DD= 5 V

Over temperature range

from 0 °C to 105°C

-0.5

Frequency

accuracy of

DCO output

using factory

trim value

Over temperature range

from -40 °C to 105°C

Δf_{dco_ft}

-1.5

-1

—

1

Over temperature range

from 0 °C to 105°C

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Peripheral operating requirements and behaviors

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

(continued)

Num

14

C

Characteristic

Symbol

t_Acquire

C_Jitter

Min

—

Typical¹

Max

2

Unit

ms

FLL acquisition time^4,7

—

15

Long term jitter of DCO output clock

(averaged over 2 ms interval)⁸

—

0.02

0.2

%f_dco

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. See crystal or resonator manufacturer's recommendation.

3. Load capacitors (C₁,C₂), feedback resistor (R_F) and series resistor (R_S) are incorporated internally when RANGE = HGO =

0.

4. This parameter is characterized and not tested on each device.

5. Proper PC board layout procedures must be followed to achieve specifications.

6. The accuracy is for factory trimmed deviation when performing trim process in NXP, however, the reflow process may

cause an extra 0.5% drift at the room temperature.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or

changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as

the reference, this specification assumes it is already running.

8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_Bus

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via V_DDand V_SSand variation in crystal oscillator frequency increase the C_Jitterpercentage

for a given interval.

OSC

EXTAL

XTAL

R_S

R_F

Crystal or Resonator

C₁

C₂

Figure 15. Typical crystal or resonator circuit

6.3 NVM specifications

This section provides details about program/erase times and program/erase endurance for

the flash memories.

Table 13. Flash characteristics

C

Characteristic

Symbol

Min¹

Typical²

Max³

Unit⁴

D

Supply voltage for program/erase –40

°C to 105 °C

V_prog/erase

2.7

—

5.5

V

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Peripheral operating requirements and behaviors

Table 13. Flash characteristics (continued)

C

D

C

Characteristic

Supply voltage for read operation

NVM Bus frequency

NVM Operating frequency

Erase Verify All Blocks

Erase Verify Flash Block

Erase Verify Flash Section

Read Once

Symbol

V_Read

Min¹

Typical²

Max³

5.5

Unit⁴

V

2.7

—

f_NVMBUS

f_NVMOP

t_VFYALL

t_RD1BLK

t_RD1SEC

t_RDONCE

t_PGM2

1

—

24

MHz

t_cyc

0.8

1

1.05

2605

2579

485

—

t_cyc

—

t_cyc

—

464

t_cyc

Program Flash (2 word)

Program Flash (4 word)

Program Once

0.12

0.21

0.20

95.42

19.10

95.42

—

0.13

0.21

100.18

20.05

100.19

—

0.31

0.49

0.21

100.30

20.09

100.31

482

ms

t_PGM4

ms

t_PGMONCE

t_ERSALL

t_ERSBLK

t_ERSPG

t_UNSECU

t_VFYKEY

t_MLOADU

n_FLPE

ms

Erase All Blocks

ms

Erase Flash Block

ms

Erase Flash Sector

ms

Unsecure Flash

ms

Verify Backdoor Access Key

Set User Margin Level

t_cyc

—

415

t_cyc

FLASH Program/erase endurance T_Lto

T_H= -40 °C to 105 °C

10 k

100 k

—

Cycles

C

Data retention at an average junction

temperature of T_Javg= 85°C after up to

10,000 program/erase cycles

t_{D_ret}

15

100

—

years

1. Minimum times are based on maximum f_NVMOPand maximum f_NVMBUS

2. Typical times are based on typical f_NVMOPand maximum f_NVMBUS

3. Maximum times are based on typical f_NVMOPand typical f_NVMBUSplus aging

4. t_cyc= 1 / f_NVMBUS

Program and erase operations do not require any special power sources other than the

normal V_DDsupply. For more detailed information about program/erase operations, see

the Flash Memory Module section in the reference manual.

6.4 Analog

6.4.1 ADC characteristics

Table 14. 5 V 12-bit ADC operating conditions

Characteri

stic

Conditions

Symbol

Min

Typ¹

Max

Unit

Comment

Reference

potential

• Low

• High

V_REFL

V_REFH

V_SSA

—

V_DDA/2

V_DDA

V

—

V_DDA/2

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 14. 5 V 12-bit ADC operating conditions (continued)

Characteri

stic

Conditions

Symbol

Min

Typ¹

Max

Unit

Comment

Supply

voltage

Absolute

V_DDA

ΔV_DDA

V_ADIN

2.7

—

0

5.5

V

mV

V

—

Delta to V_DD(V_DD-V_DDA

)

-100

V_REFL

+100

V_REFH

Input

—

voltage

Input

capacitance

C_ADIN

R_ADIN

R_AS

—

4.5

3

5.5

5

pF

kΩ

—

Input

resistance

Analog

source

resistance

12-bit mode

f_ADCK> 4 MHz

f_ADCK< 4 MHz

External to

MCU

—

2

5

•

10-bit mode

f_ADCK> 4 MHz

f_ADCK< 4 MHz

—

5

•

10

8-bit mode

(all valid f_ADCK

)

ADC

conversion

clock

High speed (ADLPC=0)

Low power (ADLPC=1)

f_ADCK

0.4

—

8.0

4.0

MHz

—

frequency

1. Typical values assume V_DDA= 5.0 V, Temp = 25°C, f_ADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

SIMPLIFIED

INPUT PIN EQUIVALENT

z _ADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

input

ADC SAR

ENGINE

R _AS

R _ADIN

protection

v _ADIN

C _AS

v _AS

R _ADIN

INPUT PIN

C _ADIN

Figure 16. ADC input impedance equivalency diagram

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Peripheral operating requirements and behaviors

Table 15. 12-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Characteristic

Supply current

ADLPC = 1

Conditions

C

Symbol

Min

Typ¹

Max

Unit

T

I_DDA

—

133

—

µA

ADLSMP = 1

ADCO = 1

Supply current

ADLPC = 1

T

I_DDA

—

218

327

582

—

µA

ADLSMP = 0

ADCO = 1

Supply current

ADLPC = 0

ADLSMP = 1

ADCO = 1

Supply current

ADLPC = 0

990

ADLSMP = 0

ADCO = 1

Supply current

Stop, reset, module

off

T

P

I_DDA

—

2

0.011

3.3

2

1

5

µA

ADC asynchronous High speed (ADLPC

clock source

f_ADACK

MHz

= 0)

Low power (ADLPC

= 1)

1.25

—

3.3

—

Conversion time

(including sample

time)

Short sample

(ADLSMP = 0)

T

t_ADC

20

ADCK

cycles

Long sample

(ADLSMP = 1)

—

40

Sample time

Short sample

(ADLSMP = 0)

t_ADS

—

3.5

23.5

ADCK

cycles

Long sample

—

(ADLSMP = 1)

Total unadjusted

Error²

12-bit mode

10-bit mode

8-bit mode

12-bit mode

10-bit mode

8-bit mode

C

E_TUE

DNL

INL

—

5.0

1.5

0.8

1.5

0.4

0.15

1.5

0.4

0.15

1.0

0.2

—

LSB³

Differential Non-

Liniarity

Integral Non-Linearity 12-bit mode

10-bit mode

8-bit mode

Zero-scale error⁴

12-bit mode

10-bit mode

E_ZS

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Peripheral operating requirements and behaviors

Table 15. 12-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Characteristic

Conditions

8-bit mode

C

D

Symbol

Min

—

Typ¹

Max

—

Unit

0.35

Full-scale error⁵

12-bit mode

10-bit mode

8-bit mode

E_FS

—

2.5

—

LSB³

—

0.3

—

0.25

—

Quantization error

≤12 bit modes

E_Q

E_IL

m

—

0.5

LSB³

mV

Input leakage error⁶all modes

Temp sensor slope -40 °C–25 °C

25 °C–125 °C

Temp sensor voltage 25 °C

I_In* R_AS

3.266

3.638

1.396

—

mV/°C

D

V_TEMP25

V

1. Typical values assume V_DDA= 5.0 V, Temp = 25 °C, f_ADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2. Includes quantization

3. 1 LSB = (V_REFH- V_REFL)/2^N

4. V_ADIN= V_SSA

5. V_ADIN= V_DDA

6. I_In= leakage current (refer to DC characteristics)

6.4.2 Analog comparator (ACMP) electricals

Table 16. Comparator electrical specifications

C

D

T

Characteristic

Supply voltage

Symbol

V_DDA

I_DDA

V_AIN

V_AIO

V_H

Min

2.7

Typical

—

Max

5.5

20

Unit

V

Supply current (Operation mode)

Analog input voltage

—

10

µA

V

D

P

C

T

V_SS- 0.3

—

V_DDA

40

Analog input offset voltage

Analog comparator hysteresis (HYST=0)

Analog comparator hysteresis (HYST=1)

Supply current (Off mode)

Propagation Delay

—

mV

nA

µs

—

15

20

V_H

—

20

30

I_DDAOFF

t_D

—

60

—

C

—

0.4

1

6.5 Communication interfaces

6.5.1 SPI switching specifications

The serial peripheral interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables

provide timing characteristics for classic SPI timing modes. See the SPI chapter of the

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27

Peripheral operating requirements and behaviors

chip's reference manual for information about the modified transfer formats used for

communicating with slower peripheral devices. All timing is shown with respect to 20%

V_DDand 80% V_DD, unless noted, and 25 pF load on all SPI pins. All timing assumes slew

rate control is disabled and high-drive strength is enabled for SPI output pins.

Table 17. SPI master mode timing

Nu

m.

Symbol Description

Min.

Max.

Unit

Comment

1

f_op

Frequency of operation

f_Bus/2048

f_Bus/2

Hz

f_Busis the bus

clock

2

3

t_SPSCK

t_Lead

t_Lag

SPSCK period

Enable lead time

Enable lag time

2 x t_Bus

2048 x t_Bus

ns

t_SPSCK

ns

t_Bus= 1/f_Bus

1/2

—

4

1/2

—

5

t_WSPSCKClock (SPSCK) high or low time

t_Bus– 30

1024 x t_Bus

6

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

8

—

ns

7

ns

8

t_v

—

20

—

25

ns

9

t_HO

t_RI

—

ns

10

t_Bus– 25

ns

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1

SS

(OUTPUT)

3

2

10

11

4

SPSCK

(CPOL=0)

(OUTPUT)

5

10

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

8

MSB IN

LSB IN

9

MOSI

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 17. SPI master mode timing (CPHA=0)

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1

SS

(OUTPUT)

2

10

11

4

3

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

LSB IN

MSB IN

9

8

MOSI

(OUTPUT)

2

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 18. SPI master mode timing (CPHA=1)

Table 18. SPI slave mode timing

Nu

m.

Symbol

Description

Min.

Max.

Unit

Comment

1

f_op

Frequency of operation

0

f_Bus/4

Hz

f_Busis the bus clock as

defined in Control timing.

2

3

4

5

6

7

8

t_SPSCK

t_Lead

t_Lag

SPSCK period

Enable lead time

Enable lag time

4 x t_Bus

—

ns

t_Bus

ns

t_Bus= 1/f_Bus

1

—

t_WSPSCKClock (SPSCK) high or low time

t_Bus- 30

15

—

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

—

ns

25

—

ns

—

t_Bus

ns

Time to data active from

high-impedance state

9

t_dis

Slave MISO disable time

—

t_Bus

ns

Hold time to high-

impedance state

10

11

12

t_v

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

—

0

25

—

ns

—

t_HO

t_RI

—

t_Bus- 25

t_FI

Fall time input

13

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

29

Dimensions

SS

(INPUT)

2

12

13

4

SPSCK

(CPOL=0)

(INPUT)

5

3

SPSCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 19. SPI slave mode timing (CPHA = 0)

SS

(INPUT)

4

2

12

13

3

SPSCK

(CPOL=0)

(INPUT)

5

SPSCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

MISO

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

note

(OUTPUT)

8

6

7

MOSI

(INPUT)

MSB IN

NOTE: Not defined

Figure 20. SPI slave mode timing (CPHA=1)

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

30

NXP Semiconductors

Pinout

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

Then use this document number

98ASS23225W

44-pin LQFP

64-pin QFP

64-pin LQFP

80-pin LQFP

98ASB42844B

98ASS23234W

98ASS23237W

8 Pinout

8.1 Signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

NOTE

VSS and VSSA are internally connected.

VREFH and VDDA are internally connected in 64-pin

packages.

PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 are

high-current drive pins when operated as output.

PTA2 and PTA3 are true open-drain pins when operated as

output.

80

64

44

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP LQFP

/QFP

1

2

3

4

5

6

7

8

9

1

2

1

2

PTD1

DISABLED

VDD

PTD1

KBI0_P25

KBI0_P24

KBI1_P31

KBI1_P30

KBI1_P29

KBI1_P7

FTM2_CH3

FTM2_CH2

PWT_IN1

SPI1_MOSI

SPI1_SCK

PTD0

PTH7

PTH6

PTH5

PTE7

PTH2

VDD

PTD0

PTH7

PTH6

PTH5

PTE7

PTH2

3

—

3

4

—

5

TCLK2

FTM1_CH1

FTM1_CH0

6

4

KBI1_P26

BUSOUT

7

5

VDD

VDDA

8

6

VDDA

VREFH

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

31

Pinout

80

64

44

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP LQFP

/QFP

10

11

12

—

9

—

7

VREFH

VREFL

VSS

10

8

VSS/

VSSA

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

11

12

13

—

14

15

16

17

18

19

20

21

22

23

24

—

25

26

—

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

9

PTB7

PTB6

PTI4

EXTAL

PTB7

KBI0_P15

KBI0_P14

I2C0_SCL

I2C0_SDA

IRQ

EXTAL

XTAL

10

11

—

12

13

14

15

16

17

18

—

19

20

—

21

22

23

24

—

25

26

—

27

28

XTAL

PTB6

PTI4

DISABLED

NMI_b

PTI1

IRQ

UART2_TX

UART2_RX

PTI0

IRQ

PTH1

PTH0

PTE6

PTE5

PTB5

PTB4

PTC3

PTC2

PTD7

PTD6

PTD5

PTI6

PTH1

PTH0

PTE6

PTE5

PTB5

PTB4

PTC3

PTC2

PTD7

PTD6

PTD5

PTI6

KBI1_P25

KBI1_P24

KBI1_P6

KBI1_P5

KBI0_P13

KBI0_P12

KBI0_P19

KBI0_P18

KBI0_P31

KBI0_P30

KBI0_P29

IRQ

FTM2_CH1

FTM2_CH0

FTM2_CH5

FTM2_CH4

FTM2_CH3

FTM2_CH2

UART2_TX

UART2_RX

PWT_IN0

SPI0_PCS

ACMP1_OUT

ACMP1_IN2

ADC0_SE11

ADC0_SE10

SPI0_MISO

NMI_b

ADC0_SE11

ADC0_SE10

DISABLED

ADC0_SE9

ADC0_SE8

DISABLED

ADC0_SE15

ADC0_SE14

ADC0_SE13

ADC0_SE12

ADC0_SE7

ADC0_SE6

ADC0_SE5

ADC0_SE4

DISABLED

ADC0_SE3

ADC0_SE2

DISABLED

VSS

PTI5

IRQ

PTC1

PTC0

PTH4

PTH3

PTF7

PTF6

PTF5

PTF4

PTB3

PTB2

PTB1

PTB0

PTF3

PTF2

PTA7

PTA6

PTE4

VSS

PTC1

PTC0

PTH4

PTH3

PTF7

PTF6

PTF5

PTF4

PTB3

PTB2

PTB1

PTB0

PTF3

PTF2

PTA7

PTA6

PTE4

KBI0_P17

KBI0_P16

KBI1_P28

KBI1_P27

KBI1_P15

KBI1_P14

KBI1_P13

KBI1_P12

KBI0_P11

KBI0_P10

KBI0_P9

KBI0_P8

KBI1_P11

KBI1_P10

KBI0_P7

KBI0_P6

KBI1_P4

FTM2_CH1

FTM2_CH0

I2C1_SCL

I2C1_SDA

ADC0_SE9

ADC0_SE8

ADC0_SE15

ADC0_SE14

ADC0_SE13

ADC0_SE12

ADC0_SE7

ADC0_SE6

ADC0_SE5

ADC0_SE4

SPI0_MOSI

SPI0_SCK

UART0_TX

UART0_RX

UART1_TX

UART1_RX

FTM2_FLT2

FTM2_FLT1

FTM0_CH1

FTM0_CH0

PWT_IN1

ACMP1_IN1

ACMP1_IN0

ADC0_SE3

ADC0_SE2

VSS

VDD

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

32

NXP Semiconductors

Pinout

80

64

44

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP LQFP

/QFP

50

51

52

53

54

55

56

57

58

59

60

61

—

42

43

44

45

46

47

48

49

—

29

30

31

32

33

34

PTG7

DISABLED

ADC0_SE1

PTG7

KBI1_P23

KBI1_P22

KBI1_P21

KBI1_P20

KBI1_P9

KBI1_P8

KBI0_P28

KBI0_P27

KBI0_P26

KBI0_P3

KBI0_P2

KBI0_P1

FTM2_CH5

FTM2_CH4

FTM2_CH3

FTM2_CH2

FTM2_CH1

FTM2_CH0

SPI1_PCS

SPI1_MISO

SPI1_MOSI

SPI1_SCK

PTG6

PTG5

PTG4

PTF1

PTF0

PTD4

PTD3

PTD2

PTA3

PTA2

PTA1

PTG6

PTG5

PTG4

PTF1

PTF0

PTD4

PTD3

PTD2

PTA3

PTA2

PTA1

SPI1_PCS

SPI1_MISO

UART0_TX

UART0_RX

FTM0_CH1

I2C0_SCL

I2C0_SDA

I2C0_

4WSDAOUT

ACMP0_IN1

ACMP0_IN0

ADC0_SE1

ADC0_SE0

62

50

35

PTA0

ADC0_SE0

PTA0

KBI0_P0

FTM0_CH0

I2C0_

4WSCLOUT

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

51

52

—

53

54

—

55

56

57

58

59

60

61

36

37

—

38

—

39

40

41

PTC7

PTC6

PTI3

DISABLED

VSS

PTC7

PTC6

PTI3

KBI0_P23

KBI0_P22

IRQ

UART1_TX

UART1_RX

PTI2

IRQ

PTE3

PTE2

VSS

PTE3

PTE2

KBI1_P3

KBI1_P2

SPI0_PCS

SPI0_MISO

PWT_IN0

VSS

VDD

PTG3

PTG2

PTG1

PTG0

PTE1

PTE0

PTC5

DISABLED

PTG3

PTG2

PTG1

PTG0

PTE1

PTE0

PTC5

KBI1_P19

KBI1_P18

KBI1_P17

KBI1_P16

KBI1_P1

SPI0_MOSI

SPI0_SCK

I2C1_SCL

I2C1_SDA

KBI1_P0

TCLK1

KBI0_P21

FTM1_CH1

RTC_

CLKOUT

78

62

42

PTC4

SWD_CLK

PTC4

KBI0_P20

RTC_

FTM1_CH0

ACMP0_IN2

SWD_CLK

CLKOUT

79

80

63

64

43

44

PTA5

PTA4

RESET_b

SWD_DIO

PTA5

PTA4

KBI0_P5

KBI0_P4

IRQ

TCLK0

RESET_b

SWD_DIO

ACMP0_OUT

8.2 Device pin assignment

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

33

Pinout

1

PTD1

PTD0

PTH7

PTH6

PTH5

PTE7

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

PTA2

PTA3

PTD2

PTD3

PTD4

PTF0

PTF1

PTG4

PTG5

PTG6

PTG7

VDD

2

3

4

5

6

7

PTH2

VDD

8

9

VDDA

VREFH

VREFL

VSS/VSSA

PTB7

10

11

12

13

14

15

16

17

18

19

20

VSS

PTB6

PTE4

PTA6

PTA7

PTF2

PTF3

PTB0

PTB1

PTI4

PTI1

PTI0

PTH1

PTH0

PTE6

Figure 21. 80-pin LQFP package

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

34

NXP Semiconductors

Pinout

PTD1

PTD0

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PTA2

PTA3

PTD2

PTD3

PTD4

PTF0

PTF1

VDD

2

PTH7

3

PTH6

4

PTE7

5

PTH2

6

VDD

7

VDDA/VREFH

VREFL

VSS/VSSA

PTB7

8

9

VSS

10

11

12

13

14

15

16

PTE4

PTA6

PTA7

PTF2

PTF3

PTB0

PTB1

PTB6

PTI4

PTH1

PTH0

PTE6

Figure 22. 64-pin QFP/LQFP packages

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

NXP Semiconductors

35

Revision history

PTA2

PTA3

PTD2

PTD3

PTD4

VDD

33

32

31

30

29

28

27

26

25

PTD1

PTD0

1

2

PTE7

3

PTH2

4

VDD

5

VDDA

VREFL

VSS/VSSA

PTB7

6

VSS

7

PTA6

PTA7

8

9

PTB6

10

11

PTB0

PTB1

24

23

PTI4

Figure 23. 44-pin LQFP package

9 Revision history

The following table provides a revision history for this document.

Table 19. Revision history

Rev. No.

Date

12/2013

3/2014

5/2014

Substantial Changes

Initial NDA release.

1

2

3

Initial public release.

• Updated the Max. of SI_DD

.

• Updated footnote to the V_OH

.

• Corrected Unit in the FTM input timing table.

4

5

07/2016

01/2019

• Added a new section of Thermal operating requirements.

• Corrected pinout diagram for 44-pin LQFP in the Device pin

assignment.

• Added a footnote of "Max power suppply ramp rate is 500 V/ms." to

Operating voltage in the DC characteristics.

• Added a footnote to the Δf_{int_ft}in the External oscillator (OSC) and

ICS characteristics.

KE04 Sub-Family Data Sheet, Rev. 5, 01/2019

36

NXP Semiconductors

Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

How to Reach Us:

Home Page:

nxp.com

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any

particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including "typicals," must be validated for each customer application

by customer's technical experts. NXP does not convey any license under its patent rights nor the

rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be

found at the following address: nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to unidentified

vulnerabilities. Customers are responsible for the design and operation of their applications and

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NXP accepts no liability for any vulnerability that is discovered. Customers should implement

appropriate design and operating safeguards to minimize the risks associated with their applications

and products.

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Document Number MKE04P80M48SF0

Revision 5, 01/2019


型号：	935320756557
厂家：	NXP
描述：	RISC Microcontroller 微控制器
文件：	总37页 (文件大小：770K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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