935320988557 [NXP]
Digital Signal Processor;
| 型号： | 935320988557 |
| 厂家： | 
NXP |
| 描述： | Digital Signal Processor 外围集成电路 |
| 文件： | 总178页 (文件大小：1529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
56F8346/56F8146
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8346
Rev. 15
01/2007
freescale.com
Document Revision History
Version History
Description of Change
Rev 1.0
Rev 2.0
Rev 3.0
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional
grammar issues.
Rev 4.0
Added “Typical Min” values to Table 10-16. Edited grammar, spelling, consistency of
language throughout family. Updated values in Current Consumption per Power Supply Pin,
Table 10-7, Regulator Parameters, Table 10-9, External Clock Operation Timing
Requirements Table 10-13, SPI Timing, Table 10-18, ADC Parameters, Table 10-24, and IO
Loading Coefficients at 10MHz, Table 10-25.
Rev 5.0
Added Part 4.8. Added the word “access” to FM Error Interrupt in Table 4-5. Removed min
and max numbers. Clarified CSBAR 0 and CSBAR 1 reset values in Table 4-10. Removed
min and max numbers, only documenting Typ. numbers for LVI in Table 10-6.
Rev 6.0
Rev 7.0
Updated numbers in Table 10-7 and Table 10-8 with more recent data. Corrected typo in
Table 10-3 in Pd characteristics.
Replaced any reference to Flash Interface Unit with Flash Memory Module. Added note to
VCAP pin in Table 2-2. Removed unneccessary notes in Table 10-12. Corrected temperature
range in Table 10-14. Added ADC calibration information to Table 10-24 and new graphs in
Figure 10-21.
Rev 8.0
Rev 9.0
Clarified Table 10-22. Corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5. Removed text and Table 10-2. Replaced with note to Table 10-1.
Added 56F8146 information; edited to indicate differences in 56F8346 and 56F8146. Refor-
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout family. Clarified I/O power
description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
Added output voltage maximum value and note to clarify in Table 10-1; also removed overall
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
PD in Table 10-3. Corrected note about average value for Flash Data Retention in
Rev 10.0
Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1.
Rev 11.0
Rev 12.0
Updated Table 10-24 to reflect new value for maximum Uncalibrated Gain Error
Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4. Added RoHS-compliance and “pb-free” language to back cover.
Rev 13.0
Updated JTAG ID in Section 6.5.4. Added information/corrected state during reset in
Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing
maximum value to 8.4MHz.
56F8346 Technical Data, Rev. 15
2
Freescale Semiconductor
Preliminary
Document Revision History (Continued)
Description of Change
Version History
Rev 14.0
Rev. 15
Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2
• Added the following note to the description of the TMS signal in Table 2-2:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Added the following note to the description of the TRST signal in Table 2-2:
Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a
debugging environment, TRST may be tied to VSS through a 1K resistor.
Please see http://www.freescale.com for the most current data sheet revision.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
3
56F8346 Technical Data, Rev. 15
4
Freescale Semiconductor
Preliminary
56F8346/56F8146 General Description
Note: Features in italics are NOT available in the 56F8146 device.
• Up to 60 MIPS at 60MHz core frequency
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional On-Chip Regulator
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data memory
• FlexCAN module
• Chip Select Logic for glueless interface to ROM and
SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• 8KB of Data RAM
• 8KB of Boot Flash
• Up to 62 GPIO lines
• Up to two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
• 144-pin LQFP Package
OCR_DIS
EMI_MODE
RSTO
V
2
V
VDD
VSS VDDA
VSSA
PP
CAP
EXTBOOT
5
RESET
4
7
5
2
6
6
JTAG/
EOnCE
Port
PWM Outputs
Current Sense Inputs
or GPIOC
Digital Reg
Analog Reg
PWMA
3
3
Low Voltage
Supervisor
16-Bit
56800E Core
Fault Inputs
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
Bit
Manipulation
Unit
PWM Outputs
PWMB
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Current Sense Inputs
or GPIOD
3
4
Fault Inputs
PAB
PDB
CDBR
CDBW
4
4
AD0
ADCA
AD1
5
4
4
R/W Control
Memory
VREF
XDB2
XAB1
XAB2
6
2
8
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
AD0
AD1
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
External
Address Bus
Switch
ADCB
A8-15 or GPIOA0-7
GPIOB0 or A16
PAB
Temp_Sense
System Bus
Control
PDB
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
4
7
9
CDBR
CDBW
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
External Data
Bus Switch
Data Memory
4K x 16 Flash
8K x 16 RAM
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad
Timer C or
GPIOE
RD
4
2
Bus Control
GPIOD0-1 or CS2-3
PS (CS0) or GPIOD8
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
IPAB
IPWDB
IPRDB
DS (CS1) or GPIOD9
Control
Decoding
Peripherals
Quad
Timer D or
GPIOE
2
2
Clock
resets
PLL
FlexCAN
P
O
R
System
Integration
Module
O
SPI0 or
GPIOE
SCI1 or
GPIOD
SCI0 or
GPIOE
COP/
Interrupt
Clock
XTAL
S
Generator
C
Watchdog Controller
EXTAL
4
2
2
CLKMODE
IRQA IRQB
CLKO
56F8346/56F8146 Block Diagram - 144 LQFP
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
5
Table of Contents
Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . .7
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
1.1
1.2
1.3
56F8346/56F8146 Features . . . . . . . . . . . .7
Device Description. . . . . . . . . . . . . . . . . . . .9
Award-Winning Development
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . 130
Memory Maps . . . . . . . . . . . . . . . . . . . . . 130
Configuration. . . . . . . . . . . . . . . . . . . . . . 130
Environment . . . . . . . . . . . . . . . . . . .11
Architecture Block Diagram . . . . . . . . . . . .11
Product Documentation . . . . . . . . . . . . . . .15
Data Sheet Conventions . . . . . . . . . . . . . .16
1.4
1.5
1.6
Part 9 Joint Test Action Group (JTAG) . . 136
9.1
JTAG Information . . . . . . . . . . . . . . . . . . 136
Part 2 Signal/Connection Descriptions . . . .17
Part 10 Specifications . . . . . . . . . . . . . . . . 136
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . .17
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . .20
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
General Characteristics. . . . . . . . . . . . . . 136
DC Electrical Characteristics. . . . . . . . . . 141
AC Electrical Characteristics. . . . . . . . . . 145
Flash Memory Characteristics. . . . . . . . . 145
External Clock Operation Timing . . . . . . 146
Phase Locked Loop Timing. . . . . . . . . . . 146
Crystal Oscillator Timing . . . . . . . . . . . . . 147
External Memory Interface Timing . . . . . 147
Reset, Stop, Wait, Mode Select, and
Part 3 On-Chip Clock Synthesis (OCCS). . .40
3.1
3.2
3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . .40
External Clock Operation. . . . . . . . . . . . . .40
Registers . . . . . . . . . . . . . . . . . . . . . . . . . .42
Part 4 Memory Map . . . . . . . . . . . . . . . . . . . .42
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . .42
Program Map. . . . . . . . . . . . . . . . . . . . . . .44
Interrupt Vector Table . . . . . . . . . . . . . . . .45
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . .49
Flash Memory Map . . . . . . . . . . . . . . . . . .49
EOnCE Memory Map. . . . . . . . . . . . . . . . .51
Peripheral Memory Mapped Registers . . .52
Factory Programmed Memory. . . . . . . . . .79
Interrupt Timing . . . . . . . . . . . . . . . 150
10.10 Serial Peripheral Interface (SPI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 152
10.11 Quad Timer Timing . . . . . . . . . . . . . . . . . 157
10.12 Quadrature Decoder Timing . . . . . . . . . . 157
10.13 Serial Communication Interface (SCI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 158
10.14 Controller Area Network (CAN) Timing. . 159
10.15 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 159
10.16 Analog-to-Digital Converter (ADC)
Part 5 Interrupt Controller (ITCN). . . . . . . . .79
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . .79
Features. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Functional Description . . . . . . . . . . . . . . . .80
Block Diagram . . . . . . . . . . . . . . . . . . . . . .81
Operating Modes . . . . . . . . . . . . . . . . . . . .81
Register Descriptions. . . . . . . . . . . . . . . . .82
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Parameters. . . . . . . . . . . . . . . . . . . 161
10.17 Equivalent Circuit for ADC Inputs . . . . . . 163
10.18 Power Consumption . . . . . . . . . . . . . . . . 165
Part 11 Packaging . . . . . . . . . . . . . . . . . . . 167
11.1
56F8346 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 167
56F8146 Package and Pin-Out
11.2
Part 6 System Integration Module (SIM) . .109
Information . . . . . . . . . . . . . . . . . . . 169
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Overview . . . . . . . . . . . . . . . . . . . . . . . . .109
Features. . . . . . . . . . . . . . . . . . . . . . . . . .110
Operating Modes . . . . . . . . . . . . . . . . . . .111
Operating Mode Register. . . . . . . . . . . . .111
Register Descriptions. . . . . . . . . . . . . . . .112
Clock Generation Overview. . . . . . . . . . .125
Power-Down Modes Overview . . . . . . . .125
Stop and Wait Mode Disable Function . .126
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Part 12 Design Considerations . . . . . . . . . 174
12.1
12.2
12.3
Thermal Design Considerations . . . . . . . 174
Electrical Design Considerations . . . . . . 175
Power Distribution and I/O Ring
Implementation. . . . . . . . . . . . . . . . 176
Part 13 Ordering Information . . . . . . . . . . 177
Part 7 Security Features . . . . . . . . . . . . . . .127
7.1
7.2
Operation with Security Enabled . . . . . . .127
Flash Access Blocking Mechanisms . . . .127
56F8346 Technical Data, Rev. 15
6
Freescale Semiconductor
Preliminary
56F8346/56F8146 Features
Part 1 Overview
1.1 56F8346/56F8146 Features
1.1.1
Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1 outlines the key differences between the 56F8346 and 56F8146 devices.
Table 1-1 Device Differences
Feature
56F8346
56F8146
Guaranteed Speed
Program RAM
Data Flash
60MHz/60 MIPS
40MHz/40 MIPS
Not Available
Not Available
1 x 6
4KB
8KB
2 x 6
1
PWM
CAN
Not Available
2
Quad Timer
4
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
2 x 4
1
1 x 4
Not Available
5
—
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
7
1.1.3
Memory
Note: Features in italics are NOT available in the 56F8146 device.
•
•
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory, including a low-cost, high-volume Flash solution
— 128KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 8KB of Data RAM
— 8KB of Boot Flash
•
Off-chip memory expansion capabilities programmable for 0 - 30 wait states
— Access up to 1MB of program memory or 1MB of data memory
— Chip select logic for glueless interface to ROM and SRAM
EEPROM emulation capability
•
1.1.4
Peripheral Circuits
Note: Features in italics are NOT available in the 56F8146 device.
•
Pulse Width Modulator:
— In the 56F8346, two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense
inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both
center-aligned and edge-aligned modes
— In the 56F8146, one Pulse Width Modulator module with six PWM outputs, three Current Sense inputs,
and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
•
•
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with
quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channels
2 and 3
Quadrature Decoder:
— In the 56F8346, two four-input Quadrature Decoders or two additional Quad Timers
— In the 56F8146, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A
•
Temperature Sensor diode can be connected, on the board, to any of the ADC inputs to monitor the on-chip
temperature
•
Quad Timer:
— In the 56F8346, four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C
with one pin and Timer D with two pins
— In the 56F8146, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO
Optional On-Chip Regulator
•
•
FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive
56F8346 Technical Data, Rev. 15
8
Freescale Semiconductor
Preliminary
Device Description
•
•
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO
lines)
— In the 56F8346, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
— In the 56F8146, SPI1 can alternately be used only as GPIO
Computer Operating Properly (COP)/Watchdog timer
Two dedicated external interrupt pins
•
•
•
•
•
•
•
62 General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
External reset output pin for system reset
Integrated low-voltage interrupt module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
•
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.5
Energy Information
•
•
•
•
•
•
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8346 and 56F8146 are members of the 56800E core-based family of controllers. Each combines,
on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a
microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because
of its low cost, configuration flexibility, and compact program code, the 56F8346 and 56F8146 are
well-suited for many applications. The devices include many peripherals that are especially useful for
motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and
control, automotive control (56F8346 only), engine management, noise suppression, remote utility
metering, industrial control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.
The 56F8346 and 56F8146 support program execution from either internal or external memories. Two
data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also
provide two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
9
1.2.1
56F8346 Features
The 56F8346 controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable
through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. It also supports program
execution from external memory.
A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software
routines that can be used to program the main Program and Data Flash memory areas. Both Program and
Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size
is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk
or page erased.
A key application-specific feature of the 56F8346 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both
BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance
Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”,
write-once protection feature for key parameters is also included. A patented PWM waveform distortion
correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit
integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to
synchronize the Analog-to-Digital Converters through two channels of Quad Timer C.
The 56F8346 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A
Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal
interrupt controller are a part of the 56F8346.
1.2.2
56F8146 Features
The 56F8146 hybrid controller includes 128KB of Program Flash, programmable through the JTAG port,
with 8KB of Data RAM. It also supports program execution from external memory.
A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software
routines that can be used to program the main Program Flash memory area, which can be independently
bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512
bytes and the Boot Flash memory can also be either bulk or page erased.
56F8346 Technical Data, Rev. 15
10
Freescale Semiconductor
Preliminary
Award-Winning Development Environment
A key application-specific feature of the 56F8146 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and can also support six independent PWM functions to enhance motor control functionality.
Complementary operation permits programmable dead time insertion, distortion correction via current
sensing by software, and separate top and bottom output polarity control. The up-counter value is
programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned
synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of
controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless
DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM
incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to
directly drive standard optoisolators. A “smoke-inhibit”, write-once protection feature for key parameters
is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters
through two channels of Quad Timer C.
The 56F8146 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase
inputs, permitting generation of a number proportional to actual position. Speed computation capabilities
accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder
can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered
to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An
internal interrupt controller is also a part of the 56F8146.
1.3 Award-Winning Development Environment
TM
Processor Expert
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
Note: Features in italics are NOT available in the 56F8146 device and are shaded in the following figures.
The 56F8346/56F8146 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the
56800E system buses communicate with internal memories, the external memory interface and the IPBus
Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of
their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The
figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection
Descriptions, to see which signals are multiplexed with those of other peripherals.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
11
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The
Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions.
In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer
C input channel as indicated. The timer can then be used to introduce a controllable delay before
generating its output signal. The timer output then triggers the ADC. To fully understand this interaction,
please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these
peripherals.
56F8346 Technical Data, Rev. 15
12
Freescale Semiconductor
Preliminary
Architecture Block Diagram
5
JTAG / EOnCE
Boot
Flash
pdb_m[15:0]
pab[20:0]
Program
Flash
Program
RAM
cdbw[13:0]
56800E
EMI
17
16
6
Address
CHIP
TAP
Controller
Data
Control
TAP
Linking
Module
Data
RAM
xab1[23:0]
xab2[23:0]
Data
Flash
External
JTAG
Port
cdbr_m[31:0]
xdb2_m[15:0]
To Flash
Control Logic
IPBus
Bridge
Flash
NOT available on the 56F8146 device.
Interface
Units
IPBus
Figure 1-1 System Bus Interfaces
Note:
Note:
Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished
by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core
and the Flash memories.
The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
13
To/From IPBus Bridge
Interrupt
Controller
CLKGEN
(OSC/PLL)
Low-Voltage Interrupt
Timer A
POR & LVI
System POR
RESET
4
Quadrature Decoder 0
Timer D
SIM
2
COP Reset
Timer B
COP
2
4
FlexCAN
Quadrature Decoder 1
SPI 1
12
PWMA
SYNC Output
13
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
PWMB
SYNC Output
ch3i
ch2i
ch2i
1
Timer C
ch3i
8
ADCB
ADCA
4
SPI0
SCI0
8
2
1
TEMP_SENSE
2
SCI1
Note: ADCA and ADCB use the same volt-
age reference circuit with VREFH, VREFP,
VREFMID, VREFN, and VREFLO pins.
IPBus
NOT available on the 56F8146 device.
Figure 1-2 Peripheral Subsystem
56F8346 Technical Data, Rev. 15
14
Freescale Semiconductor
Preliminary
Product Documentation
Table 1-2 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0] Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
xab1[23:0]
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
to 0.
1.5 Product Documentation
The documents in Table 1-3 are required for a complete description and proper design with the 56F8346
and 56F8146 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor sales offices, Freescale Literature Distribution Centers, or online at
http://www.freescale.com.
Table 1-3 Chip Documentation
Topic
Description
Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E family architecture,
and 16-bit controller core processor and the instruction
set
DSP56800ERM
56F8300 Peripheral User Manual
Detailed description of peripherals of the 56F8300
devices
MC56F8300UM
MC56F83xxBLUM
MC56F8346
56F8300 SCI/CAN Bootloader User
Manual
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
56F8346/56F8146
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
Errata
Details any chip issues that might be present
MC56F8346E
MC56F8146E
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
15
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F8346 Technical Data, Rev. 15
16
Freescale Semiconductor
Preliminary
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8346 and 56F8146 are organized into functional groups, as detailed
in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals
present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of Pins in Package
Functional Group
56F8346
56F8146
Power (VDD or VDDA
)
9
9
Power Option Control
1
6
1
6
Ground (VSS or VSSA
)
Supply Capacitors1 & VPP
6
6
PLL and Clock
4
17
16
6
4
17
16
6
Address Bus
Data Bus
Bus Control
Interrupt and Program Control
Pulse Width Modulator (PWM) Ports
Serial Peripheral Interface (SPI) Port 0
Serial Peripheral Interface (SPI) Port 1
6
6
25
4
13
4
—
4
4
Quadrature Decoder Port 02
4
Quadrature Decoder Port 13
Serial Communications Interface (SCI) Ports
CAN Ports
4
—
4
2
4
—
21
1
Analog to Digital Converter (ADC) Ports
Quad Timer Module Ports
21
3
JTAG/Enhanced On-Chip Emulation (EOnCE)
Temperature Sense
5
5
1
—
5
Dedicated GPIO
—
1. If the on-chip regulator is disabled, the V
pins serve as 2.5V V
power inputs
CAP
DD_CORE
2. Alternately, can function as Quad Timer pins or GPIO
3. Pins in this section can function as Quad Timer, SPI #1, or GPIO
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
17
VDD_IO
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
Power
Power
7
1
1
1
1
1
VDDA_ADC
VDDA_OSC_PLL
VSS
Power
1
5
Ground
Ground
VSSA_ADC
1
SCLK0
1
1
1
1
56F8346
OCR_DIS
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
SPI0 or
GPIO
1
VCAP1 - VCAP
4
2
Other
Supply
Ports
4
2
V
PP1 & VPP
PHASEA1(TB0, SCLK1, GPIOC0)
PHASEB1 (TB1, MOSI1, GPIOC1)
INDEX1 (TB2, MISO1, GPIOC2)
HOME1 (TB3, SS1, GPIOC3)
Quadrature
Decoder 1 or
Quad Timer
B or SPI 1 or
GPIO
1
1
1
1
CLKMODE
EXTAL
XTAL
1
1
1
1
PLL
and
Clock
CLKO
PWMA0 - 5
6
3
3
PWMA or
GPIO
ISA0 - 2 (GPIOC8 - 10)
FAULTA0 - 2
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
GPIOB0 (A16)
6
2
External
Address
Bus
8
1
or GPIO
PWMB0 - 5
6
3
4
PWMB or
GPIO
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
External
Data Bus
or GPIO
D0-D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
7
9
ANA0 - 7
VREF
ADCA
ADCB
8
5
8
RD
WR
1
1
ANB0 - 7
External
Bus
Control or
GPIO
PS (CS0)(GPIOD8)
1
1
2
Temperature
Sensor
TEMP_SENSE
DS (CS1)(GPIOD9)
GPIOD0 - 1 (CS2 - 3)
1
CAN_RX
CAN_TX
1
1
FlexCAN
TXD0 (GPIOE0)
RXD0 (GPIOE1)
SCI 0 or
GPIO
1
1
QUAD
TIMER C and
D or GPIO
TC0 (GPIOE8)
1
2
TD0 - 1 (GPIOE10 - 11)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
1
1
SCI 1
or GPIO
IRQA
1
TCK
TMS
IRQB
1
1
1
EXTBOOT
EMI_MODE
Imterrupt/
Program
Control
1
1
1
1
JTAG/
EOnCE
Port
TDI
TDO
1
RESET
RSTO
1
1
TRST
1
Figure 2-1 56F8346 Signals Identified by Functional Group (144-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8346 Technical Data, Rev. 15
18
Freescale Semiconductor
Preliminary
Introduction
VDD_IO
VDDA_ADC
VDDA_OSC_PLL
VSS
Power
Power
7
1
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
Quadrature
1
1
1
1
Decoder 0
or Quad
Timer A or
GPIO
Power
1
5
Ground
Ground
VSSA_ADC
1
56F8146
SCLK0
OCR_DIS
1
1
1
1
1
MOSI0
SPI0 or
GPIO
VCAP1 - VCAP
4
2
Other
Supply
Ports
MISO0
4
2
V
PP1 & VPP
SS0 (GPIOE7)
CLKMODE
(SCLK1, GPIOC0)
(MOSI1, GPIOC1)
(MISO1, GPIOC2)
(SS1, GPIOC3)
1
1
1
1
1
1
1
1
PLL
and
Clock
EXTAL
XTAL
SPI 1 or
GPIO
CLKO
A0 - A5 (GPIOA8 -
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
GPIOB0 (A16)
6
2
External
Address
Bus
GPIO
(GPIOC8 - 10)
3
8
1
or GPIO
PWMB0 - 5
6
3
4
PWMB or
GPIO
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
External
Data Bus
or GPIO
D0-D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 -
7
9
ANA0 - 7
VREF
ADCA
ADCB
8
RD
WR
1
1
5
8
External
Bus
ANB0 - 7
PS (CS0)(GPIOD8)
1
Control
or GPIO
DS (CS1)(GPIOD9)
GPIOD0 - 1 (CS2 - 3)
1
2
TXD0 (GPIOE0)
RXD0 (GPIOE1)
SCI 0 or
GPIO
1
1
QUAD
TIMER C or
GPIO
TC0 (GPIOE8)
(GPIOE10 - 11)
1
2
TXD1 (GPIOD6)
RXD1 (GPIOD7)
1
1
SCI 1
or GPIO
IRQA
1
TCK
TMS
1
IRQB
1
1
1
1
1
1
JTAG/
EOnCE
Port
EXTBOOT
EMI_MODE
Interrupt/
Program
Control
TDI
TDO
1
RESET
RSTO
1
1
TRST
1
Figure 2-2 56F8146 Signals Identified by Functional Group (144-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
19
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Note: Signals in italics are NOT available in the 56F8146 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
Pin No.
Type
During
Reset
Signal Description
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDDA_ADC
1
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage regulator,
if it is enabled.
16
31
38
66
84
119
102
Supply
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules.
It must be connected to a clean analog power supply.
VDDA_OSC_PLL
80
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power
supply.
VSS
VSS
27
37
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
VSS
63
VSS
69
VSS
144
103
VSSA_ADC
Supply
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
56F8346 Technical Data, Rev. 15
20
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
OCR_DIS
Pin No.
Type
During
Reset
Signal Description
79
Input
Input
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
VCAP
VCAP
VCAP
VCAP
1
2
3
4
51
128
83
Supply
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2μF or greater bypass capacitor in order to
bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to VDD (regulator disabled),
these pins become VDD_CORE and should be connected to a
regulated 2.5V power supply.
15
Note: This bypass is required even if the chip is powered with
an external supply.
V
PP1
125
2
Input
Input
Input
Input
VPP1 - 2 — These pins should be left unconnected as an open
circuit for normal functionality.
VPP
2
CLKMODE
87
Clock Input Mode Selection — This input determines the function
of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
EXTAL
XTAL
82
81
Input
Input
External Crystal Oscillator Input — This input can be connected
to an 8MHz external crystal. Tie this pin low if XTAL is driven by an
external clock source.
Input/
Chip-driven Crystal Oscillator Output — This output connects the internal
Output
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
21
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
CLKO
Pin No.
Type
During
Reset
Signal Description
3
Output
In reset,
output is
disabled
Clock Output — This pin outputs a buffered clock signal. Using
the SIM CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled, CLK_MSTR
(system clock), IPBus clock, oscillator output, prescaler clock and
postscaler clock. Other signals are also available for test purposes.
See Part 6.5.7 for details.
A0
138
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A0 - A5 specify six of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A0 - A5 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA8)
Input/
Port A GPIO — These six GPIO pins can be individually
Output
programmed as input or output pins.
A1
(GPIOA9)
10
11
12
13
14
After reset, the default state is Address Bus.
A2
(GPIOA10)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
A3
(GPIOA11)
Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
A4
(GPIOA12)
A5
(GPIOA13)
56F8346 Technical Data, Rev. 15
22
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
A6
Pin No.
Type
During
Reset
Signal Description
17
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A6 - A7 specify two of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A6 - A7 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOE2)
A7
Schmitt
Input/
Output
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
18
19
After reset, the default state is Address Bus.
(GPIOE3)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
A8
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus— A8 - A15 specify eight of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A8 - A15 and EMI control signals are tri-stated when
the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOA0)
Schmitt
Input/
Output
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
A9
(GPIOA1)
20
21
22
23
24
25
26
After reset, the default state is Address Bus.
A10
(GPIOA2)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
A11
(GPIOA3)
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A12
(GPIOA4)
A13
(GPIOA5)
A14
(GPIOA6)
A15
(GPIOA7)
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
23
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
GPIOB0
Pin No.
Type
During
Reset
Signal Description
33
Schmitt
Input/
Output
Input,
pull-up
enabled
Port B GPIO — This GPIO pin can be programmed as an input or
output pin.
(A16)
Output
Address Bus — A16 specifies one of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A16 and EMI control signals are tri-stated when the
external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
After reset, the start-up state of GPIOB0 (GPIO or address) is
determined as a function of EXTBOOT, EMI_MODE and the Flash
security setting. See Table 4-4 for further information on when this
pin is configured as an address pin at reset. In all cases, this state
may be changed by writing to GPIOB_PER.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
D0
59
Input/
Outpu
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D0 - D6 specify part of the data for external program or
data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), D0-D6 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOF9)
Input/
Port F GPIO — These seven GPIO pins can be individually
Outputt
programmed as input or output pins.
D1
(GPIOF10)
60
72
75
76
77
78
At reset, these pins default to the EMI Data Bus function.
D2
(GPIOF11)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
D3
(GPIOF12)
Example: GPIOF9, clear bit 9 in the GPIOF_PUR register.
D4
(GPIOF13)
D5
(GPIOF14)
D6
(GPIOF15)
56F8346 Technical Data, Rev. 15
24
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
D7
Pin No.
Type
During
Reset
Signal Description
28
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D7 - D14 specify part of the data for external program
or data memory accesses.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOF0)
Input/
Port F GPIO — These eight GPIO pins can be individually
Output
programmed as input or output pins.
D8
(GPIOF1)
29
30
At reset, these pins default to Data Bus functionality.
D9
(GPIOF2)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
D10
(GPIOF3)
32
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
D11
(GPIOF4)
133
134
135
136
137
D12
(GPIOF5)
D13
(GPIOF6)
D14
(GPIOF7)
D15
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D15 specifies part of the data for external program or
data memory accesses.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(GPIOF8)
Input/
Port F GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
At reset, this pin defaults to the Data Bus function.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOF_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
25
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
RD
Pin No.
Type
During
Reset
Signal Description
45
Output
In reset,
output is
disabled,
pull-up is
enabled
Read Enable — RD is asserted during external memory read
cycles. When RD is asserted low, pins D0 - D15 become inputs
and an external device is enabled onto the data bus. When RD is
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn
pins. RD can be connected directly to the OE pin of a static RAM or
ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), RD is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
WR
44
Output
In reset,
output is
disabled,
pull-up is
enabled
Write Enable — WR is asserted during external memory write
cycles. When WR is asserted low, pins D0 - D15 become outputs
and the device puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can
be connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
PS
46
Output
In reset,
output is
disabled,
pull-up is
enabled
Program Memory Select — This signal is actually CS0 in the EMI,
which is programmed at reset for compatibility with the 56F80x PS
signal. PS is asserted low for external program memory access.
(CS0)
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), PS is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the 56F80x
devices.
(GPIOD8)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
56F8346 Technical Data, Rev. 15
26
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
Pin No.
Type
During
Reset
Signal Description
DS
47
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Memory Select — This signal is actually CS1 in the EMI,
which is programmed at reset for compatibility with the 56F80x DS
signal. DS is asserted low for external data memory access.
(CS1)
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), DS is tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the 56F80x
devices.
(GPIOD9)
GPIOD0
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
48
49
Input/
Output
Input,
pull-up
enabled
Port D GPIO — These two GPIO pins can be individually
programmed as input or output pins.
(CS2)
Output
Chip Select — CS2 - CS3 may be programmed within the EMI
module to act as chip selects for specific areas of the external
memory map.
GPIOD1
(CS3)
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS2 - CS3 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
TXD0
4
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI0 transmit data output
(GPIOE0)
Input/
Output
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
27
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
Pin No.
Type
During
Reset
Signal Description
RXD0
5
Input
Input,
pull-up
enabled
Receive Data — SCI0 receive data input
(GPIOE1)
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
TXD1
42
Output
In reset,
output is
disabled,
pull-up is
enabled
Transmit Data — SCI1 transmit data output
(GPIOD6)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
RXD1
43
Input
Input,
pull-up
enabled
Receive Data — SCI1 receive data input
(GPIOD7)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
TMS
121
122
Schmitt
Input
Input,
pulled low
internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor.
Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
123
Schmitt
Input
Input,
pulled high
internally
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
56F8346 Technical Data, Rev. 15
28
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
TDO
Pin No.
Type
During
Reset
Signal Description
124
Output
In reset,
output is
disabled,
pull-up is
enabled
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
TRST
120
Schmitt
Input
Input,
pulled high
internally
Test Reset — As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE module
must not be reset. In this case, assert RESET, but do not assert
TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note: For normal operation, connect TRST directly to VSS. If the
design is to be used in a debugging environment, TRST may be tied to
VSS through a 1K resistor.
PHASEA0
(TA0)
139
Schmitt
Input
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
Schmitt
Input/
TA0 — Timer A, Channel 0
Output
(GPIOC4)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
29
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
PHASEB0
(TA1)
Pin No.
Type
During
Reset
Signal Description
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A, Channel
140
Schmitt
Input
Input,
pull-up
enabled
Schmitt
Input/
Output
(GPIOC5)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
INDEX0
(TA2)
141
Schmitt
Input
Input,
pull-up
enabled
Index — Quadrature Decoder 0, INDEX input
Schmitt
Input/
TA2 — Timer A, Channel 2
Output
(GPOPC6)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is INDEX0.
To deactivate the internal pull-up resistor, clear bit 6 of the
GPIOC_PUR register.
HOME0
(TA3)
142
Schmitt
Input
Input,
pull-up
enabled
Home — Quadrature Decoder 0, HOME input
Schmitt
Input/
TA3 — Timer A, Channel 3
Output
(GPIOC7)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is HOME0.
To deactivate the internal pull-up resistor, clear bit 7 of the
GPIOC_PUR register.
56F8346 Technical Data, Rev. 15
30
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
SCLK0
Pin No.
Type
During
Reset
Signal Description
130
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input.
(GPIOE4)
Schmitt
Input/
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
After reset, the default state is SCLK0.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.
MOSI0
132
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
SPI 0 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
(GPIOE5)
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is MOSI0.
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
MISO0
131
Input/
Output
Input,
pull-up
enabled
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected. The slave device places data on the MISO
line a half-cycle before the clock edge the master device uses to
latch the data.
(GPIOE6)
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
31
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
SS0
Pin No.
Type
During
Reset
Signal Description
129
Input
Input,
pull-up
enabled
SPI 0 Slave Select — SS0 is used in slave mode to indicate to the
SPI module that the current transfer is to be received.
(GPIOE7)
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
input or output pin.
After reset, the default state is SS0.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOE_PUR register.
PHASEA1
(TB0)
6
Schmitt
Input
Input,
pull-up
enabled
Phase A1 — Quadrature Decoder, PHASEA input for decoder 1.
Schmitt
Input/
TB0 — Timer B, Channel 0
Output
(SCLK1)
Schmitt
Input/
Output
SPI 1 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. To activate the SPI function, set the
PHSA_ALT bit in the SIM_GPS register. For details, see Part
6.5.8.
(GPIOC0)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8346, the default state after reset is PHASEA1.
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOC_PUR register.
56F8346 Technical Data, Rev. 15
32
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
PHASEB1
(TB1)
Pin No.
Type
During
Reset
Signal Description
7
Schmitt
Input
Input,
pull-up
enabled
Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1.
TB1 — Timer B, Channel 1
Schmitt
Input/
Output
(MOSI1)
Schmitt
Input/
Output
SPI 1 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data. To activate the SPI function,
set the PHSB_ALT bit in the SIM_GPS register. For details, see
Part 6.5.8.
(GPIOC1)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8346, the default state after reset is PHASEB1.
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
33
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
INDEX1
Pin No.
Type
During
Reset
Signal Description
Index1 — Quadrature Decoder 1, INDEX input
TB2 — Timer B, Channel 2
8
Schmitt
Input
Input,
pull-up
enabled
(TB2)
Schmitt
Input/
Output
(MISO1)
Schmitt
Input/
Output
SPI 1 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected. The slave device places data on the MISO
line a half-cycle before the clock edge the master device uses to
latch the data. To activate the SPI function, set the INDEX_ALT bit
in the SIM_GPS register. For details, see Part 6.5.8.
(GPIOC2)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8346, the default state after reset is INDEX1.
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 2 in the
GPIOC_PUR register.
HOME1
(TB3)
9
Schmitt
Input
Input,
pull-up
enabled
Home — Quadrature Decoder 1, HOME input
Schmitt
Input/
TB3 — Timer B, Channel 3
Output
(SS1)
Schmitt
Input
SPI 1 Slave Select — In the master mode, this pin is used to
arbitrate multiple masters. In slave mode, this pin is used to select
the slave. To activate the SPI function, set the HOME_ALT bit in
the SIM_GPS register. For details, see Part 6.5.8.
(GPIOC3)
Schmitt
Input/
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
In the 56F8346, the default state after reset is HOME1.
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 3 in the
GPIOC_PUR register.
56F8346 Technical Data, Rev. 15
34
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
Pin No.
Type
During
Reset
Signal Description
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
ISA0
62
64
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA0 - 5 — These are six PWMA outputs.
65
67
68
70
113
Schmitt
Input
Input,
pull-up
enabled
ISA0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
(GPIOC8)
Schmitt
Input/
Output
Port C GPIO — These three GPIO pins can be individually
programmed as input or output pins.
ISA1
(GPIOC9)
114
115
In the 56F8346, these pins default to ISA functionality after reset.
ISA2
(GPIOC10)
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear the appropriate bit
of the GPIOC_PUR register. For details, see Part 6.5.8.
FAULTA0
FAULTA1
FAULTA2
71
73
74
Schmitt
Input
Input,
pull-up
enabled
FAULTA0 - 2 — These three fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions originate
off-chip.
To deactivate the internal pull-up resistor, set the PWMA0 bit in the
SIM_PUDR register. For details, see Part 6.5.8.
PWMB0
PWMB1
PWMB2
PWMB3
PWMB4
PWMB5
34
35
36
39
40
41
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMB0 - 5 — Six PWMB output pins.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
35
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
ISB0
Pin No.
Type
During
Reset
Signal Description
50
Schmitt
Input
Input,
pull-up
enabled
ISB0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.
(GPIOD10)
Schmitt
Input/
Output
Port D GPIO — These three GPIO pins can be individually
programmed as input or output pins.
ISB1
(GPIOD11)
52
53
At reset, these pins default to ISB functionality.
ISB2
(GPIOD12)
To deactivate the internal pull-up resistor, clear the appropriate bit
of the GPIOD_PUR register. For details, see Part 6.5.8.
FAULTB0
FAULTB1
FAULTB2
FAULTB3
ANA0
56
57
58
61
88
89
90
91
92
93
94
95
101
Schmitt
Input
Input,
pull-up
enabled
FAULTB0 - 3 — These four fault input pins are used for disabling
selected PWMB outputs in cases where fault conditions originate
off-chip.
To deactivate the internal pull-up resistor, set the PWMB bit in the
SIM_PUDR register. For details, see Part 6.5.8.
Input
Input
Input
Analog
Input
ANA0 - 3 — Analog inputs to ADC A, channel 0
ANA1
ANA2
ANA3
ANA4
Analog
Input
ANA4 - 7 — Analog inputs to ADC A, channel 1
ANA5
ANA6
ANA7
VREFH
Analog
Input
VREFH — Analog Reference Voltage High. VREFH must be less
than or equal to VDDA_ADC.
VREFP
VREFMID
VREFN
100
99
Input/
Output
Analog
Input/
Output
VREFP, VREFMID & VREFN — Internal pins for voltage reference
which are brought off-chip so they can be bypassed. Connect to a
0.1μF low ESR capacitor.
98
VREFLO
97
Input
Analog
Input
VREFLO — Analog Reference Voltage Low. This should normally
be connected to a low-noise VSSA
.
56F8346 Technical Data, Rev. 15
36
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
Pin No.
Type
During
Reset
Signal Description
ANB0
ANB1
104
105
106
107
108
109
110
111
96
Input
Analog
Input
ANB0 - 3 — Analog inputs to ADC B, channel 0
ANB2
ANB3
ANB4
Input
Analog
Input
ANB4 - 7 — Analog inputs to ADC B, channel 1
ANB5
ANB6
ANB7
TEMP_SENSE
Output
Analog
Output
Temperature Sensor Diode — This signal connects to an on-chip
diode that can be connected to one of the ADC inputs and used to
monitor the temperature of the die. Must be bypassed with a
0.01μF capacitor.
CAN_RX
CAN_TX
127
126
Schmitt
Input
Input,
pull-up
enabled
FlexCAN Receive Data — This is the CAN input. This pin has an
internal pull-up resistor.
To deactivate the internal pull-up resistor, set the CAN bit in the
SIM_PUDR register.
Open
Drain
Open
Drain
FlexCAN Transmit Data — CAN output with internal pull-up
enable at reset.*
Output
Output
* Note: If a pin is configured as open drain output mode, internal
pull-up will automatically be disabled when it outputs low. Internal
pull-up will be enabled unless it has been manually disabled by
clearing the corresponding bit in the PUREN register of the GPIO
module, when it outputs high.
If a pin is configured as push-pull output mode, internal pull-up will
automatically be disabled, whether it outputs low or high.
TC0
118
Schmitt
Input/
Output
Input,
pull-up
enabled
TC0 — Timer C Channel 0
(GPIOE8)
Schmitt
Input/
Port E GPIO — This GPIO pin can be programmed as an input or
output pin.
Output
At reset, this pin defaults to timer functionality.
To deactivate the internal pull-up resistor, clear bit 8 of the
GPIOE_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
37
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
TD0
Pin No.
Type
During
Reset
Signal Description
116
Schmitt
Input/
Output
Input,
pull-up
enabled
TD0 -1 — Timer D, Channels 0 and 1
(GPIOE10)
Schmitt
Input/
Output
Port E GPIO — These GPIO pins can be individually programmed
as input or output pins.
TD1
(GPIOE11)
117
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the appropriate bit
of the GPIOE_PUR register. See Part 6.5.6 for details.
IRQA
IRQB
54
55
Schmitt
Input
Input,
pull-up
enabled
External Interrupt Request A and B — The IRQA and IRQB
inputs are asynchronous external interrupt requests during Stop
and Wait mode operation. During other operating modes, they are
synchronized external interrupt requests, which indicate an
external device is requesting service. They can be programmed to
be level-sensitive or negative-edge triggered.
To deactivate the internal pull-up resistor, set the IRQ bit in the
SIM_PUDR register. See Part 6.5.6 for details.
RESET
86
Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed
in the reset state. A Schmitt trigger input is used for noise
immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the EXTBOOT pin. The internal
reset signal will be deasserted synchronous with the internal clocks
after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert
RESET but do not assert TRST.
Note: The internal Power-On Reset will assert on initial power-up.
To deactivate the internal pull-up resistor, set the RESET bit in the
SIM_PUDR register. See Part 6.5.6 for details.
RSTO
85
Output
Output
Reset Output — This output reflects the internal reset state of the
chip.
56F8346 Technical Data, Rev. 15
38
Freescale Semiconductor
Preliminary
Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
State
Signal Name
EXTBOOT
Pin No.
Type
During
Reset
Signal Description
112
Schmitt
Input
Input,
pull-up
enabled
External Boot — This input is tied to VDD to force the device to
boot from off-chip memory (assuming that the on-chip Flash
memory is not in a secure state). Otherwise, it is tied to ground. For
details, see Table 4-4.
Note: When this pin is tied low, the customer boot software should
disable the internal pull-up resistor by setting the XBOOT bit of the
SIM_PUDR; see Part 6.5.6.
EMI_MODE
143
Schmitt
Input
Input,
pull-up
enabled
External Memory Mode — The EMI_MODE input is internally tied
low (to VSS). This device will boot from internal flash memory
under normal operation. This function is also affected by
EXTBOOT and the Flash security mode. For details, see
Table 4-4.
If a 20-bit address bus is not desired, then this pin is tied to ground.
Note: When this pin is tied low, the customer boot software should
disable the internal pull-up resistor by setting the EMI_MODE bit of
the SIM_PUDR; see Part 6.5.6.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
39
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the
specific OCCS block diagram to reference in the OCCS chapter in the 56F8300 Peripheral User Manual.
CLKMODE
XTAL
ZSRC
Crystal
OSC
Prescaler CLK
PLLCOD
SYS_CLK2
Source to SIM
EXTAL
PLLCID
PLLDB
PLL
FOUT
FOUT/2
Postscaler
Prescaler
÷ (1,2,4,8)
Postscaler CLK
÷2
x (1 to 128)
÷ (1,2,4,8)
Bus
Interface
Bus Interface & Control
LCK
Lock
Detector
Loss of Reference
Clock Interrupt
Loss of
Reference
Clock
Detector
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator, or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator, must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown
in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
56F8346 Technical Data, Rev. 15
40
Freescale Semiconductor
Preliminary
External Clock Operation
The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
EXTAL XTAL
Rz
Sample External Crystal Parameters:
Rz = 750 KΩ
Note: If the operating temperature range is limited to
CLKMODE = 0
below 85oC (105oC junction), then Rz = 10 Meg Ω
CL1
CL2
Figure 3-2 Connecting to a Crystal Oscillator
Note:
The OCCS_COHL bit must be set to 1 when a crystal oscillator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.2
Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-3.
Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components.
The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
41
Resonator Frequency = 4 - 8MHz (optimized for 8MHz)
3 Terminal
2 Terminal
Sample External Ceramic Resonator Parameters:
Rz = 750 KΩ
EXTAL XTAL
Rz
EXTAL XTAL
Rz
CLKMODE = 0
CL1
CL2
C1
C2
Figure 3-3 Connecting a Ceramic Resonator
Note:
The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the
OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed
in the 56F8300 Peripheral User Manual.
3.2.3
External Clock Source
The recommended method of connecting an external clock is illustrated in Figure 3-4. The external clock
source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an
external clock source as well.
Note: When using an external clocking source
XTAL
EXTAL
with this configuration, the input “CLKMODE”
should be high and the COHL bit in the OSCTL
register should be set to 1.
V
External
Clock
SS
Figure 3-4 Connecting an External Clock Register
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions without the internal Relaxation Oscillator, since the 56F8346/56F8146 devices do
NOT contain this oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8346 and 56F8146 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
56F8346 Technical Data, Rev. 15
42
Freescale Semiconductor
Preliminary
Introduction
This section provides memory maps for:
•
•
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Note: Data Flash and Program RAM are NOT available on the 56F8146 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8346
56F8146
Use Restrictions
Program Flash
128KB
128KB
Erase / Program via Flash interface unit and word writes to
CDBW
Data Flash
8KB
4KB
—
—
Erase / Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via either CDBR or XDB2, but
not by both simultaneously
Program RAM
None
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
43
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8346
56F8146
Use Restrictions
Data RAM
8KB
8KB
8KB
8KB
None
Program Boot Flash
Erase / Program via Flash Interface unit and word to CDBW
4.2 Program Map
The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the
Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory
map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have
an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no
effect.
Table 4-2 OMR MB/MA Value at Reset
OMR MB =
OMR MA =
Flash Secured
State1, 2
Chip Operating Mode
EXTBOOT Pin
0
0
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled
1
Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state
1
1
0
1
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin
1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.
2. Changing MB in software will not affect Flash memory security.
Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA
Chip Operating Mode
Use internal P-space memory map configuration
0
1
Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no
effect.
The device’s external memory interface (EMI) can operate much like the 56F80x family’s EMI, or it can
be operated in a mode similar to that used on other products in the 56800E family. Initially, CS0 and CS1
are configured as PS and DS, in a mode compatible with earlier 56800 devices.
Eighteen address lines are required to shadow the first 192K of internal program space when booting
externally for development purposes. Therefore, the entire complement of on-chip memory cannot be
accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can
be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable
56F8346 Technical Data, Rev. 15
44
Freescale Semiconductor
Preliminary
Interrupt Vector Table
in the 56F8346/56F8146).
The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must
be configured as address or chip select signals to access addresses at P:$10 0000 and above.
Note: Program RAM is NOT available on the 56F8146 device.
Table 4-4 Program Memory Map at Reset
Mode 11 (MA = 1)
Mode 0 (MA = 0)
Begin/End
Address
Internal Boot
External Boot
EMI_MODE = 02,3
EMI_MODE = 14
Internal Boot
16-Bit External Address Bus
16-Bit External Address Bus
20-Bit External Address Bus
External Program Memory5
External Program Memory5
External Program Memory5
P:$1F FFFF
P:$10 0000
P:$0F FFFF
P:$03 0000
P:$02 FFFF
P:$02 F800
On-Chip Program RAM
4KB
P:$02 F7FF
P:$02 1000
Reserved
116KB
P:$02 0FFF
P:$02 0000
Boot Flash
8KB
COP Reset Address = 02 0002
Boot Location = 02 0000
Boot Flash
8KB
(Not Used for Boot in this Mode)
External Program RAM
COP Reset Address = 02 00026
Boot Location = 02 00006
External Program RAM5
Internal Program Flash7
128KB
P:$01 FFFF
P:$01 0000
P:$00 FFFF
P:$00 0000
Internal Program Flash
128KB
External Program RAM
COP Reset Address = 00 0002
Boot Location = 00 0000
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7.
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE =0” when EMI_MODE pin is tied to ground at boot up.
4. “EMI_MODE =1” when EMI_MODE pin is tied to V at boot up.
DD
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip se-
lects) pins must be reconfigured before this external memory is accessible.
6. Booting from this external address allows prototyping of the internal Boot Flash.
7. The internal Program Flash is relocated in this mode making it accessible.
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
45
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part
5.6.12 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the
56F8146 device.
1
Table 4-5 Interrupt Vector Table Contents
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Reserved for Reset Overlay2
Reserved for COP Reset Overlay2
Illegal Instruction
SW Interrupt 3
core
core
core
core
core
core
2
3
4
5
6
7
3
3
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
3
HW Stack Overflow
Misaligned Long Word Access
OnCE Step Counter
OnCE Breakpoint Unit 0
Reserved
3
1-3
1-3
core
core
core
9
1-3
1-3
1-3
P:$12
P:$14
P:$16
OnCE Trace Buffer
OnCE Transmit Register Empty
OnCE Receive Register Full
Reserved
10
11
core
core
core
core
core
14
15
16
17
18
2
1
P:$1C
P:$1E
P:$20
P:$22
P:$24
SW Interrupt 2
SW Interrupt 1
0
SW Interrupt 0
0-2
0-2
IRQA
IRQB
Reserved
LVI
20
21
0-2
0-2
P:$28
P:$2A
Low Voltage Detector (power sense)
PLL
PLL
56F8346 Technical Data, Rev. 15
46
Freescale Semiconductor
Preliminary
Interrupt Vector Table
1
Table 4-5 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
FM
FM
FM
22
23
24
0-2
0-2
0-2
P:$2C
P:$2E
P:$30
FM Access Error Interrupt
FM Command Complete
FM Command, data and address Buffers Empty
Reserved
FLEXCAN
FLEXCAN
FLEXCAN
FLEXCAN
GPIOF
26
27
28
29
30
31
32
33
34
35
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
P:$34
P:$36
P:$38
P:$3A
P:$3C
P:$3E
P:$40
P:$42
P:$44
P:$46
FLEXCAN Bus Off
FLEXCAN Error
FLEXCAN Wake Up
FLEXCAN Message Buffer Interrupt
GPIOF
GPIOE
GPIOE
GPIOD
GPIOD
GPIOC
GPIOC
GPIOB
GPIOB
GPIOA
GPIOA
Reserved
SPI1
SPI1
SPI0
SPI0
SCI1
SCI1
38
39
40
41
42
43
0-2
0-2
0-2
0-2
0-2
0-2
P:$4C
P:$4E
P:$50
P:$52
P:$54
P:$56
SPI 1 Receiver Full
SPI 1 Transmitter Empty
SPI 0 Receiver Full
SPI 0 Transmitter Empty
SCI 1 Transmitter Empty
SCI 1 Transmitter Idle
Reserved
SCI1
45
46
47
48
49
0-2
0-2
0-2
0-2
0-2
P:$5A
P:$5C
P:$5E
P:$60
P:$62
SCI 1 Receiver Error
SCI 1 Receiver Full
SCI1
DEC1
DEC1
DEC0
Quadrature Decoder #1 Home Switch or Watchdog
Quadrature Decoder #1 INDEX Pulse
Quadrature Decoder #0 Home Switch or Watchdog
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
47
1
Table 4-5 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
DEC0
50
0-2
P:$64
Quadrature Decoder #0 INDEX Pulse
Reserved
TMRD
TMRD
TMRD
TMRD
TMRC
TMRC
TMRC
TMRC
TMRB
TMRB
TMRB
TMRB
TMRA
TMRA
TMRA
TMRA
SCI0
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
P:$68
P:$6A
P:$6C
P:$6E
P:$70
P:$72
P:$74
P:$76
P:$78
P:$7A
P:$7C
P:$7E
P:$80
P:$82
P:$84
P:$86
P:$88
P:$8A
Timer D, Channel 0
Timer D, Channel 1
Timer D, Channel 2
Timer D, Channel 3
Timer C, Channel 0
Timer C, Channel 1
Timer C, Channel 2
Timer C, Channel 3
Timer B, Channel 0
Timer B, Channel 1
Timer B, Channel 2
Timer B, Channel 3
Timer A, Channel 0
Timer A, Channel 1
Timer A, Channel 2
Timer A, Channel 3
SCI 0 Transmitter Empty
SCI 0 Transmitter Idle
Reserved
SCI0
SCI0
71
72
73
74
75
76
77
78
79
80
81
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
- 1
P:$8E
P:$90
P:$92
P:$94
P:$96
P:$98
P:$9A
P:$9C
P:$9E
P:$A0
P:$A2
SCI 0 Receiver Error
SCI 0 Receiver Full
SCI0
ADCB
ADCA
ADCB
ADCA
PWMB
PWMA
PWMB
PWMA
core
ADC B Conversion Compete / End of Scan
ADC A Conversion Complete / End of Scan
ADC B Zero Crossing or Limit Error
ADC A Zero Crossing or Limit Error
Reload PWM B
Reload PWM A
PWM B Fault
PWM A Fault
SW Interrupt LP
56F8346 Technical Data, Rev. 15
48
Freescale Semiconductor
Preliminary
Data Map
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to 0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the
chip reset addresses; therefore, these locations are not interrupt vectors.
2.
4.4 Data Map
Note: Data Flash is NOT available on the 56F8146 device.
1
Table 4-6 Data Memory Map
Begin/End
Address
EX = 02
EX = 1
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 2000
External Memory
External Memory
X:$00 1FFF
X:$00 1000
On-Chip Data Flash
8KB
X:$00 0FFF
X:$00 0000
On-Chip Data RAM
8KB3
1. All addresses are 16-bit Word addresses, not byte addresses.
2. In the Operating Mode Register (OMR).
3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations.
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.
The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
49
Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides
on the Data Memory buses and is controlled separately by own set of banked registers.
The top nine words of the Program Memory Flash are treated as special memory locations. The content of
these words is used to control the operation of the Flash Controller. Because these words are part of the
Flash Memory content, their state is maintained during power-down and reset. During chip initialization,
the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash
Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located
between $00_FFF7 and $00_FFFF.
Data Memory
Program Memory
BOOT_FLASH_START + $1FFF
FM_BASE + $14
FM_BASE + $00
Banked Registers
8KB
Boot
Unbanked Registers
BOOT_FLASH_START = $02_0000
Reserved
DATA_FLASH_START + $0FFF
DATA_FLASH_START + $0000
8KB
Note: Data Flash is
NOT available in the
56F8146 device.
FM_PROG_MEM_TOP = $00_FFFF
PROG_FLASH_START + $00_FFFF
PROG_FLASH_START + $00_FFF7
PROG_FLASH_START + $00_FFF6
Configure Field
Block 0 Odd
Block 0 Even
128K Bytes
BLOCK 0 Odd (2 Bytes) $00_0003
BLOCK 0 Even (2 Bytes) $00_0002
BLOCK 0 Odd (2 Bytes) $00_0001
BLOCK 0 Even (2 Bytes) $00_0000
PROG_FLASH_START = $00_0000
Figure 4-1 Flash Array Memory Maps
Table 4-7 shows the page and sector sizes used within each Flash memory block on the chip.
Note: Data Flash is NOT available on the 56F8146 device.
Table 4-7. Flash Memory Partitions
Flash Size
Sectors
Sector Size
Page Size
Program Flash
Data Flash
128KB
8KB
16
16
4
4K x 16 bits
256 x 16 bits
1K x 16 bits
512 x 16 bits
256 x 16 bits
256 x 16 bits
Boot Flash
8KB
Please see 56F8300 Peripheral User Manual for additional Flash information.
56F8346 Technical Data, Rev. 15
50
Freescale Semiconductor
Preliminary
EOnCE Memory Map
4.6 EOnCE Memory Map
Table 4-8 EOnCE Memory Map
Address
Register Acronym
Register Name
Reserved
X:$FF FF8A
X:$FF FF8E
OESCR
External Signal Control Register
Reserved
OBCNTR
Breakpoint Unit [0] Counter
Reserved
X:$FF FF90
X:$FF FF91
X:$FF FF92
X:$FF FF93
X:$FF FF94
X:$FF FF95
X:$FF FF96
X:$FF FF97
X:$FF FF98
X:$FF FF99
X:$FF FF9A
X:$FF FF9B
X:$FF FF9C
X:$FF FF9D
X:$FF FF9E
X:$FF FF9F
X:$FF FFA0
OBMSK (32 bits)
Breakpoint 1 Unit [0] Mask Register
Breakpoint 1 Unit [0] Mask Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 2 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint 1 Unit [0] Address Register
Breakpoint Unit [0] Control Register
Breakpoint Unit [0] Control Register
Trace Buffer Register Stages
Trace Buffer Register Stages
Trace Buffer Pointer Register
Trace Buffer Control Register
Peripheral Base Address Register
Status Register
—
OBAR2 (32 bits)
—
OBAR1 (24 bits)
—
OBCR (24 bits)
—
OTB (21-24 bits/stage)
—
OTBPR (8 bits)
OTBCR
OBASE (8 bits)
OSR
OSCNTR (24 bits)
—
Instruction Step Counter
Instruction Step Counter
OCR (bits)
Control Register
Reserved
X:$FF FFFC
X:$FF FFFD
X:$FF FFFE
X:$FF FFFF
OCLSR (8 bits)
Core Lock / Unlock Status Register
OTXRXSR (8 bits)
OTX / ORX (32 bits)
OTX1 / ORX1
Transmit and Receive Status and Control Register
Transmit Register / Receive Register
Transmit Register Upper Word
Receive Register Upper Word
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
51
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-9 summarizes base addresses for the set of peripherals on the 56F8346 and 56F8146 devices.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Note: Features in italics are NOT available on the 56F8146 device.
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
External Memory Interface
Timer A
EMI
X:$00 F020
X:$00 F040
X:$00 F080
X:$00 F0C0
X:$00 F100
X:$00 F140
X:$00 F160
X:$00 F180
X:$00 F190
X:$00 F1A0
X:$00 F200
X:$00 F240
X:$00 F270
X:$00 F280
X:$00 F290
X:$00 F2A0
X:$00 F2B0
X:$00 F2C0
X:$00 F2D0
X:$00 F2E0
X:$00 F300
X:$00 F310
X:$00 F320
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
TMRA
TMRB
TMRC
TMRD
PWMA
PWMB
DEC0
DEC1
ITCN
Timer B
Timer C
Timer D
PWM A
PWM B
Quadrature Decoder 0
Quadrature Decoder 1
ITCN
ADC A
ADCA
ADCB
ADC B
Temperature Sensor
SCI #0
TSENSOR
SCI0
SCI #1
SCI1
SPI #0
SPI0
SPI #1
SPI1
COP
COP
PLL, OSC
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
CLKGEN
GPIOA
GPIOB
GPIOC
GPIOD
56F8346 Technical Data, Rev. 15
52
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)
Peripheral
GPIO Port E
Prefix
Base Address
Table Number
GPIOE
GPIOF
SIM
X:$00 F330
X:$00 F340
X:$00 F350
X:$00 F360
X:$00 F400
X:$00 F800
4-33
4-34
4-35
4-36
4-37
4-38
GPIO Port F
SIM
Power Supervisor
FM
LVI
FM
FlexCAN
FC
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register Acronym Address Offset
CSBAR 0 $0
Register Description
Reset Value
Chip Select Base Address Register 0
0x0004 = 64K when
EXT_BOOT = 0 or
EMI_MODE = 0
0x0008 = 1M when
EMI_MODE = 1
(Selects entire program
space for CS0)
Note that A17-A19 are not
available in the package
CSBAR 1
$1
Chip Select Base Address Register 1
0x0004 = 64K when
EMI_MODE = 0
0x0008 = 1M when
EMI_MODE = 1
(Selects A0-A19
addressable data space for
CS1)
Note that A17-A19 are not
available in the package
CSBAR 2
CSBAR 3
CSBAR 4
CSBAR 5
CSBAR 6
CSBAR 7
$2
$3
$4
$5
$6
$7
Chip Select Base Address Register 2
Chip Select Base Address Register 3
Chip Select Base Address Register 4
Chip Select Base Address Register 5
Chip Select Base Address Register 6
Chip Select Base Address Register 7
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
53
Table 4-10 External Memory Integration Registers Address Map (Continued)
(EMI_BASE = $00 F020)
Register Acronym Address Offset
Register Description
Reset Value
CSOR 0
$8
Chip Select Option Register 0
0x5FCB programmed for
chip select for program
space, word wide, read and
write, 11 waits
CSOR 1
$9
Chip Select Option Register 1
0x5FAB programmed for
chip select for data space,
word wide, read and write,
11 waits
CSOR 2
CSOR 3
CSOR 4
CSOR 5
CSOR 6
CSOR 7
CSTC 0
CSTC 1
CSTC 2
CSTC 3
CSTC 4
CSTC 5
CSTC 6
CSTC 7
BCR
$A
$B
Chip Select Option Register 2
Chip Select Option Register 3
$C
Chip Select Option Register 4
$D
Chip Select Option Register 5
$E
Chip Select Option Register 6
$F
Chip Select Option Register 7
$10
$11
$12
$13
$14
$15
$16
$17
$18
Chip Select Timing Control Register 0
Chip Select Timing Control Register 1
Chip Select Timing Control Register 2
Chip Select Timing Control Register 3
Chip Select Timing Control Register 4
Chip Select Timing Control Register 5
Chip Select Timing Control Register 6
Chip Select Timing Control Register 7
Bus Control Register
0x016B sets the default
number of wait states to 11
for both read and write
accesses
Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRA0_CMP1
TMRA0_CMP2
TMRA0_CAP
TMRA0_LOAD
TMRA0_HOLD
$0
$1
$2
$3
$4
Compare Register 2
Capture Register
Load Register
Hold Register
56F8346 Technical Data, Rev. 15
54
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
$5
Register Description
TMRA0_CNTR
TMRA0_CTRL
Counter Register
Control Register
$6
$7
$8
$9
$A
TMRA0_SCR
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserve
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_COMSCR
TMRA1_CMP1
TMRA1_CMP2
TMRA1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_COMSCR
TMRA2_CMP1
TMRA2_CMP2
TMRA2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRA2_CMPLD1
TMRA2_CMPLD2
TMRA2_COMSCR
TMRA3_CMP1
$30
Compare Register 1
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
55
Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 2
TMRA3_CMP2
TMRA3_CAP
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Capture Register
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_COMSC
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRB0_CMP1
TMRB0_CMP2
TMRB0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRB0_LOAD
TMRB0_HOLD
TMRB0_CNTR
TMRB0_CTRL
TMRB0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB0_CMPLD1
TMRB0_CMPLD2
TMRB0_COMSCR
TMRB1_CMP1
TMRB1_CMP2
TMRB1_CAP
TMRB1_LOAD
TMRB1_HOLD
$10
$11
$12
$13
$14
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
56F8346 Technical Data, Rev. 15
56
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-12 Quad Timer B Registers Address Map (Continued)
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
TMRB1_CNTR
TMRB1_CTRL
$15
$16
$17
$18
$19
$1A
Counter Register
Control Register
TMRB1_SCR
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB1_CMPLD1
TMRB1_CMPLD2
TMRB1_COMSCR
TMRB2_CMP1
TMRB2_CMP2
TMRB2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRB2_LOAD
TMRB2_HOLD
TMRB2_CNTR
TMRB2_CTRL
TMRB2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB2_CMPLD1
TMRB2_CMPLD2
TMRB2_COMSCR
TMRB3_CMP1
TMRB3_CMP2
TMRB3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRB3_LOAD
TMRB3_HOLD
TMRB3_CNTR
TMRB3_CTRL
TMRB3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRB3_CMPLD1
TMRB3_CMPLD2
TMRB3_COMSCR
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
57
Table 4-13 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRC0_CMP1
TMRC0_CMP2
TMRC0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRC0_LOAD
TMRC0_HOLD
TMRC0_CNTR
TMRC0_CTRL
TMRC0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC0_CMPLD1
TMRC0_CMPLD2
TMRC0_COMSCR
TMRC1_CMP1
TMRC1_CMP2
TMRC1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRC1_LOAD
TMRC1_HOLD
TMRC1_CNTR
TMRC1_CTRL
TMRC1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC1_CMPLD1
TMRC1_CMPLD2
TMRC1_COMSCR
TMRC2_CMP1
TMRC2_CMP2
TMRC2_CAP
TMRC2_LOAD
TMRC2_HOLD
TMRC2_CNTR
TMRC2_CTRL
$20
$21
$22
$23
$24
$25
$26
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
56F8346 Technical Data, Rev. 15
58
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-13 Quad Timer C Registers Address Map (Continued)
(TMRC_BASE = $00 F0C0)
Register Acronym
Address Offset
$27
Register Description
Status and Control Register
TMRC2_SCR
TMRC2_CMPLD1
TMRC2_CMPLD2
TMRC2_COMSCR
$28
$29
$2A
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRC3_CMP1
TMRC3_CMP2
TMRC3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRC3_LOAD
TMRC3_HOLD
TMRC3_CNTR
TMRC3_CTRL
TMRC3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRC3_CMPLD1
TMRC3_CMPLD2
TMRC3_COMSCR
Table 4-14 Quad Timer D Registers Address Map
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRD0_CMP1
TMRD0_CMP2
TMRD0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRD0_LOAD
TMRD0_HOLD
TMRD0_CNTR
TMRD0_CTRL
TMRD0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRD0_CMPLD1
TMRD0_CMPLD2
TMRD0_COMSCR
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
59
Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
Reserved
TMRD1_CMP1
TMRD1_CMP2
TMRD1_CAP
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
Compare Register 1
Compare Register 2
Capture Register
TMRD1_LOAD
TMRD1_HOLD
TMRD1_CNTR
TMRD1_CTRL
TMRD1_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD1_CMPLD1
TMRD1_CMPLD2
TMRD1_COMSCR
TMRD2_CMP1
TMRD2_CMP2
TMRD2_CAP
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Compare Register 1
Compare Register 2
Capture Register
TMRD2_LOAD
TMRD2_HOLD
TMRD2_CNTR
TMRD2_CTRL
TMRD2_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRD2_CMPLD1
TMRD2_CMPLD2
TMRD2_COMSCR
TMRD3_CMP1
TMRD3_CMP2
TMRD3_CAP
TMRD3_LOAD
TMRD3_HOLD
TMRD3_CNTR
$30
$31
$32
$33
$34
$35
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
56F8346 Technical Data, Rev. 15
60
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
TMRD3_CTRL
$36
$37
$38
$39
$3A
Control Register
TMRD3_SCR
Status and Control Register
TMRD3_CMPLD1
TMRD3_CMPLD2
TMRD3_COMSCR
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Table 4-15 Pulse Width Modulator A Registers Address Map
(PWMA_BASE = $00 F140)
PWMA is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
PWMA_PMCTL
$0
$1
Control Register
PWMA_PMFCTL
PWMA_PMFSA
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
$2
PWMA_PMOUT
$3
PWMA_PMCNT
$4
PWMA_PWMCM
PWMA_PWMVAL0
PWMA_PWMVAL1
PWMA_PWMVAL2
PWMA_PWMVAL3
PWMA_PWMVAL4
PWMA_PWMVAL5
PWMA_PMDEADTM
PWMA_PMDISMAP1
PWMA_PMDISMAP2
PWMA_PMCFG
$5
Counter Modulo Register
Value Register 0
$6
$7
Value Register 1
$8
Value Register 2
$9
Value Register 3
$A
$B
$C
$D
$E
$F
$10
$11
$12
Value Register 4
Value Register 5
Dead Time Register
Disable Mapping Register 1
Disable Mapping Register 2
Configure Register
PWMA_PMCCR
Channel Control Register
Port Register
PWMA_PMPORT
PWMA_PMICCR
PWM Internal Correction Control Register
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
61
Table 4-16 Pulse Width Modulator B Registers Address Map
(PWMB_BASE = $00 F160)
Register Acronym
Address Offset
Register Description
PWMB_PMCTL
$0
$1
Control Register
PWMB_PMFCTL
PWMB_PMFSA
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
$2
PWMB_PMOUT
$3
PWMB_PMCNT
$4
PWMB_PWMCM
PWMB_PWMVAL0
PWMB_PWMVAL1
PWMB_PWMVAL2
PWMB_PWMVAL3
PWMB_PWMVAL4
PWMB_PWMVAL5
PWMB_PMDEADTM
PWMB_PMDISMAP1
PWMB_PMDISMAP2
PWMB_PMCFG
$5
Counter Modulo Register
Value Register 0
$6
$7
Value Register 1
$8
Value Register 2
$9
Value Register 3
$A
$B
$C
$D
$E
$F
$10
$11
$12
Value Register 4
Value Register 5
Dead Time Register
Disable Mapping Register 1
Disable Mapping Register 2
Configure Register
PWMB_PMCCR
Channel Control Register
Port Register
PWMB_PMPORT
PWMB_PMICCR
PWM Internal Correction Control Register
Table 4-17 Quadrature Decoder 0 Registers Address Map
(DEC0_BASE = $00 F180)
Register Acronym
Address Offset
Register Description
Decoder Control Register
DEC0_DECCR
DEC0_FIR
$0
$1
$2
$3
$4
Filter Interval Register
DEC0_WTR
DEC0_POSD
DEC0_POSDH
Watchdog Time-out Register
Position Difference Counter Register
Position Difference Counter Hold Register
56F8346 Technical Data, Rev. 15
62
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued)
(DEC0_BASE = $00 F180)
Register Acronym
Address Offset
$5
Register Description
Revolution Counter Register
DEC0_REV
DEC0_REVH
DEC0_UPOS
DEC0_LPOS
DEC0_UPOSH
DEC0_LPOSH
DEC0_UIR
$6
$7
$8
$9
$A
$B
$C
$D
Revolution Hold Register
Upper Position Counter Register
Lower Position Counter Register
Upper Position Hold Register
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC0_LIR
DEC0_IMR
Table 4-18 Quadrature Decoder 1 Registers Address Map
(DEC1_BASE = $00 F190)
Quadrature Decoder 1 is NOT available on the 56F8146 device
Register Acronym
Address Offset
Register Description
Decoder Control Register
DEC1_DECCR
DEC1_FIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
Filter Interval Register
DEC1_WTR
DEC1_POSD
DEC1_POSDH
DEC1_REV
Watchdog Time-out Register
Position Difference Counter Register
Position Difference Counter Hold Register
Revolution Counter Register
Revolution Hold Register
DEC1_REVH
DEC1_UPOS
DEC1_LPOS
DEC1_UPOSH
DEC1_LPOSH
DEC1_UIR
Upper Position Counter Register
Lower Position Counter Register
Upper Position Hold Register
Lower Position Hold Register
Upper Initialization Register
Lower Initialization Register
Input Monitor Register
DEC1_LIR
DEC1_IMR
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
63
Table 4-19 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0)
Register Acronym
IPR 0
Address Offset
Register Description
Interrupt Priority Register 0
$0
$1
IPR 1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt Match Register 0
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match Register 1
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
IPR 2
$2
IPR 3
$3
IPR 4
$4
IPR 5
$5
IPR 6
$6
IPR 7
$7
IPR 8
$8
IPR 9
$9
VBA
$A
FIM0
$B
FIVAL0
FIVAH0
FIM1
$C
$D
$E
FIVAL1
FIVAH1
IRQP 0
IRQP 1
IRQP 2
IRQP 3
IRQP 4
IRQP 5
$F
$10
$11
$12
$13
$14
$15
$16
$17
$1D
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
ICTL
Interrupt Control Register
Table 4-20 Analog-to-Digital Converter Registers Address Map
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
Control Register 1
ADCA_CR 1
$0
56F8346 Technical Data, Rev. 15
64
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
$1
Register Description
Control Register 2
ADCA_CR 2
ADCA_ZCC
$2
$3
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADCA_LST 1
ADCA_LST 2
ADCA_SDIS
$4
$5
ADCA_STAT
$6
ADCA_LSTAT
ADCA_ZCSTAT
ADCA_RSLT 0
ADCA_RSLT 1
ADCA_RSLT 2
ADCA_RSLT 3
ADCA_RSLT 4
ADCA_RSLT 5
ADCA_RSLT 6
ADCA_RSLT 7
ADCA_LLMT 0
ADCA_LLMT 1
ADCA_LLMT 2
ADCA_LLMT 3
ADCA_LLMT 4
ADCA_LLMT 5
ADCA_LLMT 6
ADCA_LLMT 7
ADCA_HLMT 0
ADCA_HLMT 1
ADCA_HLMT 2
ADCA_HLMT 3
ADCA_HLMT 4
ADCA_HLMT 5
ADCA_HLMT 6
ADCA_HLMT 7
ADCA_OFS 0
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
Result Register 1
$B
Result Register 2
$C
Result Register 3
$D
Result Register 4
$E
Result Register 5
$F
Result Register 6
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
Result Register 7
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
Offset Register 0
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
65
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
ADCA_OFS 1
ADCA_OFS 2
ADCA_OFS 3
ADCA_OFS 4
ADCA_OFS 5
ADCA_OFS 6
ADCA_OFS 7
ADCA_POWER
ADCA_CAL
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Power Control Register
ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240)
Register Acronym
Address Offset
Register Description
Control Register 1
ADCB_CR 1
$0
$1
ADCB_CR 2
Control Register 2
ADCB_ZCC
$2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADCB_LST 1
ADCB_LST 2
ADCB_SDIS
$3
$4
$5
ADCB_STAT
ADCB_LSTAT
ADCB_ZCSTAT
ADCB_RSLT 0
ADCB_RSLT 1
ADCB_RSLT 2
ADCB_RSLT 3
ADCB_RSLT 4
ADCB_RSLT 5
ADCB_RSLT 6
ADCB_RSLT 7
ADCB_LLMT 0
ADCB_LLMT 1
ADCB_LLMT 2
$6
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
$12
$13
Result Register 1
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
56F8346 Technical Data, Rev. 15
66
Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCB_BASE = $00 F240)
Register Acronym
Address Offset
$14
Register Description
Low Limit Register 3
ADCB_LLMT 3
ADCB_LLMT 4
ADCB_LLMT 5
ADCB_LLMT 6
ADCB_LLMT 7
ADCB_HLMT 0
ADCB_HLMT 1
ADCB_HLMT 2
ADCB_HLMT 3
ADCB_HLMT 4
ADCB_HLMT 5
ADCB_HLMT 6
ADCB_HLMT 7
ADCB_OFS 0
ADCB_OFS 1
ADCB_OFS 2
ADCB_OFS 3
ADCB_OFS 4
ADCB_OFS 5
ADCB_OFS 6
ADCB_OFS 7
ADCB_POWER
ADCB_CAL
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
Power Control Register
ADC Calibration Register
Table 4-22 Temperature Sensor Register Address Map
(TSENSOR_BASE = $00 F270)
Temperature Sensor is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
TSENSOR_CNTL
$0
Control Register
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
67
Table 4-23 Serial Communication Interface 0 Registers Address Map
(SCI0_BASE = $00 F280)
Register Acronym
Address Offset
Register Description
Baud Rate Register
SCI0_SCIBR
SCI0_SCICR
$0
$1
Control Register
Reserved
SCI0_SCISR
SCI0_SCIDR
$3
$4
Status Register
Data Register
Table 4-24 Serial Communication Interface 1 Registers Address Map
(SCI1_BASE = $00 F290)
Register Acronym
Address Offset
Register Description
Baud Rate Register
SCI1_SCIBR
SCI1_SCICR
$0
$1
Control Register
Reserved
SCI1_SCISR
SCI1_SCIDR
$3
$4
Status Register
Data Register
Table 4-25 Serial Peripheral Interface 0 Registers Address Map
(SPI0_BASE = $00 F2A0)
Register Acronym
Address Offset
Register Description
Status and Control Register
SPI0_SPSCR
SPI0_SPDSR
SPI0_SPDRR
SPI0_SPDTR
$0
$1
$2
$3
Data Size Register
Data Receive Register
Data Transmitter Register
Table 4-26 Serial Peripheral Interface 1 Registers Address Map
(SPI1_BASE = $00 F2B0)
Register Acronym
Address Offset
Register Description
Status and Control Register
SPI1_SPSCR
SPI1_SPDSR
SPI1_SPDRR
$0
$1
$2
Data Size Register
Data Receive Register
56F8346 Technical Data, Rev. 15
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Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-26 Serial Peripheral Interface 1 Registers Address Map (Continued)
(SPI1_BASE = $00 F2B0)
Register Acronym
Address Offset
$3
Register Description
Data Transmitter Register
SPI1_SPDTR
Table 4-27 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym
Address Offset
Register Description
COPCTL
COPTO
$0
$1
$2
Control Register
Time Out Register
Counter Register
COPCTR
Table 4-28 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym
PLLCR
Address Offset
Register Description
$0
$1
$2
Control Register
PLLDB
PLLSR
Divide-By Register
Status Register
Reserved
SHUTDOWN
OSCTL
$4
$5
Shutdown Register
Oscillator Control Register
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Address Offset
Register Description
Pull-up Enable Register
Reset Value
0 x 3FFF
0 x 0000
0 x 0000
0 x 3FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
Register Acronym
GPIOA_PUR
GPIOA_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
GPIOA_DDR
GPIOA_PER
GPIOA_IAR
GPIOA_IENR
GPIOA_IPOLR
GPIOA_IPR
GPIOA_IESR
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
69
Table 4-29 GPIOA Registers Address Map (Continued)
(GPIOA_BASE = $00 F2E0)
Address Offset
Register Description
Push-Pull Mode Register
Raw Data Input Register
Reset Value
0 x 3FFF
—
Register Acronym
GPIOA_PPMODE
$9
$A
GPIOA_RAWDATA
Table 4-30 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOB_PUR
GPIOB_DR
GPIOB_DDR
GPIOB_PER
$0
$1
$2
$3
0 x 00FF
0 x 0000
0 x 0000
Data Register
Data Direction Register
Peripheral Enable Register
0 x 000F for 20-bit EMI
address at reset.
0 x 0000 for all other cases.
See Table 4-4 for details.
0 x 0000
GPIOB_IAR
$4
$5
$6
$7
$8
$9
$A
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
0 x 0000
0 x 0000
0 x 0000
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
0 x 0000
0 x 00FF
—
Table 4-31 GPIOC Registers Address Map
(GPIOC_BASE = $00 F310)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOC_PUR
GPIOC_DR
$0
$1
$2
$3
$4
$5
$6
$7
0 x 07FF
0 x 0000
0 x 0000
0 x 07FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
Data Register
GPIOC_DDR
GPIOC_PER
GPIOC_IAR
GPIOC_IENR
GPIOC_IPOLR
GPIOC_IPR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
56F8346 Technical Data, Rev. 15
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Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-31 GPIOC Registers Address Map (Continued)
(GPIOC_BASE = $00 F310)
Register Acronym
Address Offset
Register Description
Reset Value
GPIOC_IESR
$8
$9
$A
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
0 x 0000
0 x 07FF
—
GPIOC_PPMODE
GPIOC_RAWDATA
Raw Data Input Register
Table 4-32 GPIOD Registers Address Map
(GPIOD_BASE = $00 F320)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOD_PUR
GPIOD_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x 1FFF
0 x 0000
0 x 0000
0 x 1FC0
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 1FFF
—
Data Register
GPIOD_DDR
GPIOD_PER
GPIOD_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOD_IENR
GPIOD_IPOLR
GPIOD_IPR
GPIOD_IESR
GPIOD_PPMODE
GPIOD_RAWDATA
Table 4-33 GPIOE Registers Address Map
(GPIOE_BASE = $00 F330)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOE_PUR
GPIOE_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
0 x 3FFF
0 x 0000
0 x 0000
0 x 3FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
Data Register
GPIOE_DDR
GPIOE_PER
GPIOE_IAR
GPIOE_IENR
GPIOE_IPOLR
GPIOE_IPR
GPIOE_IESR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
71
Table 4-33 GPIOE Registers Address Map (Continued)
(GPIOE_BASE = $00 F330)
Register Acronym
GPIOE_PPMODE
GPIOE_RAWDATA
Address Offset
Register Description
Push-Pull Mode Register
Raw Data Input Register
Reset Value
0 x 3FFF
—
$9
$A
Table 4-34 GPIOF Registers Address Map
(GPIOF_BASE = $00 F340)
Register Acronym
Address Offset
Register Description
Reset Value
GPIOF_PUR
GPIOF_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Pull-up Enable Register
Data Register
0 x FFFF
0 x 0000
0 x 0000
0 x FFFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x FFFF
—
GPIOF_DDR
GPIOF_PER
GPIOF_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOF_IENR
GPIOF_IPOLR
GPIOF_IPR
GPIOF_IESR
GPIOF_PPMODE
GPIOF_RAWDATA
Table 4-35 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym
Address Offset
Register Description
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Pull-up Disable Register
Reserved
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
56F8346 Technical Data, Rev. 15
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Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-35 System Integration Module Registers Address Map (Continued)
(SIM_BASE = $00 F350)
Register Acronym
Address Offset
Register Description
SIM_CLKOSR
SIM_GPS
$A
$B
$C
$D
$E
Clock Out Select Register
Quad Decoder 1 / Timer B / SPI 1 Select Register
Peripheral Clock Enable Register
SIM_PCE
SIM_ISALH
SIM_ISALL
I/O Short Address Location High Register
I/O Short Address Location Low Register
Table 4-36 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym
Address Offset
Register Description
LVI_CONTROL
LVI_STATUS
$0
$1
Control Register
Status Register
Table 4-37 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
Clock Divider Register
FMCLKD
FMMCR
$0
$1
Module Control Register
Reserved
FMSECH
FMSECL
$3
$4
Security High Half Register
Security Low Half Register
Reserved
Reserved
FMPROT
$10
$11
Protection Register (Banked)
Protection Boot Register (Banked)
Reserved
FMPROTB
FMUSTAT
FMCMD
$13
$14
User Status Register (Banked)
Command Register (Banked)
Reserved
Reserved
FMOPT 0
$1A
16-Bit Information Option Register 0
Hot temperature ADC reading of Temperature Sensor;
value set during factory test
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
73
Table 4-37 Flash Module Registers Address Map (Continued)
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
FMOPT 1
$1B
16-Bit Information Option Register 1
Not used
FMOPT 2
$1C
16-Bit Information Option Register 2
Room temperature ADC reading of Temperature Sensor;
value set during factory test
Table 4-38 FlexCAN Registers Address Map
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8146 device
Register Acronym
FCMCR
Address Offset
Register Description
Module Configuration Register
$0
Reserved
FCCTL0
FCCTL1
FCTMR
$3
$4
$5
$6
Control Register 0 Register
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Reserved
FCMAXMB
FCRXGMASK_H
FCRXGMASK_L
FCRX14MASK_H
FCRX14MASK_L
FCRX15MASK_H
FCRX15MASK_L
$8
$9
$A
$B
$C
$D
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Receive Buffer 15 Mask High Register
Receive Buffer 15 Mask Low Register
Reserved
FCSTATUS
$10
$11
$12
$13
Error and Status Register
Interrupt Masks 1 Register
Interrupt Flags 1 Register
Receive and Transmit Error Counters Register
Reserved
FCIMASK1
FCIFLAG1
FCR/T_ERROR_CNTRS
Reserved
Reserved
FCMB0_CONTROL
FCMB0_ID_HIGH
$40
$41
Message Buffer 0 Control / Status Register
Message Buffer 0 ID High Register
56F8346 Technical Data, Rev. 15
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Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
FCMB0_ID_LOW
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
$42
$43
$44
$45
$46
Message Buffer 0 ID Low Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Reserved
FCMSB1_CONTROL
FCMSB1_ID_HIGH
FCMSB1_ID_LOW
FCMB1_DATA
$48
$49
$4A
$4B
$4C
$4D
$4E
Message Buffer 1 Control / Status Register
Message Buffer 1 ID High Register
Message Buffer 1 ID Low Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
Reserved
FCMB1_DATA
FCMB1_DATA
FCMB1_DATA
FCMB2_CONTROL
FCMB2_ID_HIGH
FCMB2_ID_LOW
FCMB2_DATA
$50
$51
$52
$53
$54
$55
$56
Message Buffer 2 Control / Status Register
Message Buffer 2 ID High Register
Message Buffer 2 ID Low Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Message Buffer 2 Data Register
Reserved
FCMB2_DATA
FCMB2_DATA
FCMB2_DATA
FCMB3_CONTROL
FCMB3_ID_HIGH
FCMB3_ID_LOW
FCMB3_DATA
$58
$59
$5A
$5B
$5C
$5D
$5E
Message Buffer 3 Control / Status Register
Message Buffer 3 ID High Register
Message Buffer 3 ID Low Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Message Buffer 3 Data Register
Reserved
FCMB3_DATA
FCMB3_DATA
FCMB3_DATA
FCMB4_CONTROL
$60
Message Buffer 4 Control / Status Register
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
75
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
FCMB4_ID_HIGH
FCMB4_ID_LOW
FCMB4_DATA
FCMB4_DATA
FCMB4_DATA
FCMB4_DATA
$61
$62
$63
$64
$65
$66
Message Buffer 4 ID High Register
Message Buffer 4 ID Low Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Message Buffer 4 Data Register
Reserved
FCMB5_CONTROL
FCMB5_ID_HIGH
FCMB5_ID_LOW
FCMB5_DATA
$68
$69
$6A
$6B
$6C
$6D
$6E
Message Buffer 5 Control / Status Register
Message Buffer 5 ID High Register
Message Buffer 5 ID Low Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Message Buffer 5 Data Register
Reserved
FCMB5_DATA
FCMB5_DATA
FCMB5_DATA
FCMB6_CONTROL
FCMB6_ID_HIGH
FCMB6_ID_LOW
FCMB6_DATA
$70
$71
$72
$73
$74
$75
$76
Message Buffer 6 Control / Status Register
Message Buffer 6 ID High Register
Message Buffer 6 ID Low Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Message Buffer 6 Data Register
Reserved
FCMB6_DATA
FCMB6_DATA
FCMB6_DATA
FCMB7_CONTROL
FCMB7_ID_HIGH
FCMB7_ID_LOW
FCMB7_DATA
$78
$79
$7A
$7B
$7C
$7D
$7E
Message Buffer 7 Control / Status Register
Message Buffer 7 ID High Register
Message Buffer 7 ID Low Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Message Buffer 7 Data Register
Reserved
FCMB7_DATA
FCMB7_DATA
FCMB7_DATA
56F8346 Technical Data, Rev. 15
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Freescale Semiconductor
Preliminary
Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8146 device
Register Acronym
Address Offset
Register Description
FCMB8_CONTROL
FCMB8_ID_HIGH
FCMB8_ID_LOW
FCMB8_DATA
$80
$81
$82
$83
$84
$85
$86
Message Buffer 8 Control / Status Register
Message Buffer 8 ID High Register
Message Buffer 8 ID Low Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Message Buffer 8 Data Register
Reserved
FCMB8_DATA
FCMB8_DATA
FCMB8_DATA
FCMB9_CONTROL
FCMB9_ID_HIGH
FCMB9_ID_LOW
FCMB9_DATA
$88
$89
$8A
$8B
$8C
$8D
$8E
Message Buffer 9 Control / Status Register
Message Buffer 9 ID High Register
Message Buffer 9 ID Low Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Message Buffer 9 Data Register
Reserved
FCMB9_DATA
FCMB9_DATA
FCMB9_DATA
FCMB10_CONTROL
FCMB10_ID_HIGH
FCMB10_ID_LOW
FCMB10_DATA
FCMB10_DATA
FCMB10_DATA
FCMB10_DATA
$90
$91
$92
$93
$94
$95
$96
Message Buffer 10 Control / Status Register
Message Buffer 10 ID High Register
Message Buffer 10 ID Low Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Message Buffer 10 Data Register
Reserved
FCMB11_CONTROL
FCMB11_ID_HIGH
FCMB11_ID_LOW
$98
$99
$9A
Message Buffer 11 Control / Status Register
Message Buffer 11 ID High Register
Message Buffer 11 ID Low Register
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
77
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8146 device
Register Acronym
FCMB11_DATA
Address Offset
Register Description
Message Buffer 11 Data Register
$9B
$9C
$9D
$9E
FCMB11_DATA
FCMB11_DATA
FCMB11_DATA
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Message Buffer 11 Data Register
Reserved
FCMB12_CONTROL
FCMB12_ID_HIGH
FCMB12_ID_LOW
FCMB12_DATA
FCMB12_DATA
FCMB12_DATA
FCMB12_DATA
$A0
$A1
$A2
$A3
$A4
$A5
$A6
Message Buffer 12 Control / Status Register
Message Buffer 12 ID High Register
Message Buffer 12 ID Low Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Message Buffer 12 Data Register
Reserved
FCMB13_CONTROL
FCMB13_ID_HIGH
FCMB13_ID_LOW
FCMB13_DATA
FCMB13_DATA
FCMB13_DATA
FCMB13_DATA
$A8
$A9
$AA
$AB
$AC
$AD
$AE
Message Buffer 13 Control / Status Register
Message Buffer 13 ID High Register
Message Buffer 13 ID Low Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Message Buffer 13 Data Register
Reserved
FCMB14_CONTROL
FCMB14_ID_HIGH
FCMB14_ID_LOW
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
$B0
$B1
$B2
$B3
$B4
$B5
$B6
Message Buffer 14 Control / Status Register
Message Buffer 14 ID High Register
Message Buffer 14 ID Low Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Reserved
FCMB15_CONTROL
FCMB15_ID_HIGH
FCMB15_ID_LOW
$B8
$B9
$BA
Message Buffer 15 Control / Status Register
Message Buffer 15 ID High Register
Message Buffer 15 ID Low Register
56F8346 Technical Data, Rev. 15
78
Freescale Semiconductor
Preliminary
Factory Programmed Memory
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8146 device
Register Acronym
FCMB15_DATA
Address Offset
Register Description
Message Buffer 15 Data Register
$BB
$BC
$BD
$BE
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Reserved
4.8 Factory Programmed Memory
The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader
program. The Serial Bootloader application can be used to load a user application into the Program and
Data Flash (NOT available in the 56F8146 device) memories of the device. The 56F83xx SCI/CAN
Bootloader User Manual (MC56F83xxBLUM) provides detailed information on this firmware. An
application note, Production Flash Programming (AN1973), details how the Serial Bootloader program
can be used to perform production Flash programming of the on-board Flash memories as well as other
potential methods.
Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial
Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained
in the Boot Flash memory.
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-5, Interrupt Vector Table Contents.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
79
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, zero is the highest priority, while
number 81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1
SR[8]1
Permitted Exceptions
Masked Exceptions
None
0
0
1
1
0
1
0
1
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
1. Core status register bits indicating current interrupt mask within the core.
Table 5-2 Interrupt Priority Encoding
Current Interrupt
Priority Level
Required Nested
Exception Priority
IPIC_LEVEL[1:0]1
00
01
10
11
No Interrupt or SWILP
Priority 0
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 1
Priorities 2 or 3
1. See IPIC field definition in Part 5.6.30.2.
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
56F8346 Technical Data, Rev. 15
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Freescale Semiconductor
Preliminary
Block Diagram
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
5.4 Block Diagram
any0
Priority
Level
Level 0
82 -> 7
Priority
Encoder
7
2 -> 4
Decode
INT1
INT
VAB
CONTROL
IPIC
any3
Level 3
Priority
Level
IACK
SR[9:8]
PIC_EN
82 -> 7
Priority
Encoder
7
2 -> 4
INT82
Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
Functional Mode
The ITCN is in this mode by default.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
81
•
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA
and IRQB signals automatically become low-level sensitive in these modes even if the control register bits
are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling
edge.
A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop
mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA
and IRQB can wake it up.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00F1A0)
Register
Acronym
Base Address +
Register Name
Section Location
IPR0
$0
$1
Interrupt Priority Register 0
5.6.1
5.6.2
IPR1
Interrupt Priority Register 1
IPR2
$2
Interrupt Priority Register 2
5.6.3
IPR3
$3
Interrupt Priority Register 3
5.6.4
IPR4
$4
Interrupt Priority Register 4
5.6.5
IPR5
$5
Interrupt Priority Register 5
5.6.6
IPR6
$6
Interrupt Priority Register 6
5.6.7
IPR7
$7
Interrupt Priority Register 7
5.6.8
IPR8
$8
Interrupt Priority Register 8
5.6.9
IPR9
$9
Interrupt Priority Register 9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
VBA
$A
$B
$C
$D
$E
$F
$10
$11
$12
Vector Base Address Register
Fast Interrupt 0 Match Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High Register
Fast Interrupt 1 Match Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQ Pending Register 1
56F8346 Technical Data, Rev. 15
82
Freescale Semiconductor
Preliminary
Register Descriptions
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00F1A0) (Continued)
Register
Acronym
Base Address +
Register Name
Section Location
IRQP2
$13
$14
$15
$16
$17
$1D
IRQ Pending Register 2
5.6.20
5.6.21
5.6.22
5.6.23
IRQP3
IRQP4
IRQP5
Reserved
ICTL
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Interrupt Control Register
5.6.30
Add. Register
Offset Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
$10
IPR0
IPR1
IPR2
IPR3
IPR4
IPR5
IPR6
BKPT_U0 IPL
STPCNT IPL
0
0
0
0
0
0
0
0
0
0
RX_REG IPL
TX_REG IPL
IRQB IPL
TRBUF IPL
IRQA IPL
W
R
0
0
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
W
R
0
0
GPIOD
IPL
GPIOE
IPL
GPIOF
IPL
FCMSGBUF IPL FCWKUP IPL
FCERR IPL
FCBOFF IPL
W
R
0
0
0
0
0
0
SPI1_RCV
IPL
GPIOA
IPL
GPIOB
IPL
GPIOC
IPL
SPI0_RCV IPL SPI1_XMIT IPL
DEC1_XIRQ IPL DEC1_HIRQ IPL
W
R
SCI1_RCV
IPL
SCI1_RERR IPL
TMRD1 IPL
SCI1_TIDL IPL SCI1_XMIT IPL SPI0_XMIT IPL
W
R
0
0
TMRC0 IPL
TMRA0 IPL
TMRD3 IPL
TMRB3 IPL
TMRD2 IPL
TMRB2 IPL
TMRD0 IPL
TMRB0 IPL
DEC0_XIRQ IPL DEC0_HIRQ IPL
W
R
TMRB1 IPL
TMRC3 IPL
TMRA3 IPL
TMRC2 IPL
TMRA2 IPL
TMRC1 IPL
TMRA1 IPL
IPR7
IPR8
W
R
0
0
0
0
SCI0_RCV IPL SCI0_RERR IPL
SCI0_TIDL IPL SCI0_XMIT IPL
PWMB_RL IPL ADCA_ZC IPL
W
R
PWMA_RL
IPL
IPR9
PWMA F IPL
PWMB F IPL
0
ABCB_ZC IPL
ADCA_CC IPL
ADCB_CC IPL
W
R
0
0
0
0
VECTOR BASE ADDRESS
VBA
W
R
0
0
0
0
0
0
0
VBA0
FIVAL0
FIVAH0
FIM1
FAST INTERRUPT 0
W
R
FAST INTERRUPT 0 VECTOR ADDRESS LOW
W
R
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 1
W
R
FAST INTERRUPT 1
VECTOR ADDRESS LOW
FIVAL1
FIVAH1
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
W
Figure 5-2 ITCN Register Map Summary
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
83
Add. Register
Offset Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
PENDING [16:2]
1
$11
$12
$13
$14
$15
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
PENDING [32:17]
W
R
PENDING [48:33]
PENDING [64:49]
PENDING [80:65]
W
R
W
R
W
PEND-
ING
[81]
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
$16
IRQP5
W
Reserved
ICTL
IRQB
STATE STATE
IRQA
INT
IPIC
VAB
R
IRQB
EDG
IRQA
EDG
INT_DIS
$1D
W
= Reserved
Figure 5-2 ITCN Register Map Summary
5.6.1
Interrupt Priority Register 0 (IPR0)
Base + $0
Read
15
0
14
0
13
12
11
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_U0 IPL
STPCNT IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
56F8346 Technical Data, Rev. 15
84
Freescale Semiconductor
Preliminary
Register Descriptions
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.4
Reserved—Bits 9–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Interrupt Priority Register 1 (IPR1)
Base + $1
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
RX_REG IPL TX_REG IPL
TRBUF IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
85
•
•
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.3
Interrupt Priority Register 2 (IPR2)
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
0
5
0
4
0
3
2
1
0
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
IRQB IPL
IRQA IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
Flash Memory Command, Data, Address Buffers Empty Interrupt
Priority Level (FMCBE IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.2
Flash Memory Command Complete Priority Level
(FMCC IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
00 = IRQ disabled (default)
56F8346 Technical Data, Rev. 15
86
Freescale Semiconductor
Preliminary
Register Descriptions
•
•
•
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.3
Flash Memory Error Interrupt Priority Level
(FMERR IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.4
PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.5
Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.3.7
External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
00 = IRQ disabled (default)
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
87
•
•
•
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.8
External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4
Interrupt Priority Register 3 (IPR3)
Base + $3
Read
15 14 13 12 11 10
GPIODIPL GPIOE IPL GPIOFIPL
9
8
7
6
5
4
3
2
1
0
0
0
FCMSGBUF IPL
FCWKUP IPL
FCERR IPL
FCBOFF IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-6 Interrupt Priority Register 3 (IPR3)
GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14
5.6.4.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.2
GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8346 Technical Data, Rev. 15
88
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.4.3
GPIOF Interrupt Priority Level (GPIOF IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through
2two. They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.4
FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.5
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.6
FlexCAN Error Interrupt Priority Level (FCERR IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.7
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
00 = IRQ disabled (default)
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
89
•
•
•
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.8
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Interrupt Priority Register 4 (IPR4)
Base + $4
Read
15
14
13
12
11
10
9
0
8
0
7
0
6
0
5
4
3
2
1
0
SPI0_RCV
IPL
SPI1_XMIT
IPL
SPI1_RCV
IPL
GPIOA IPL
GPIOB IPL
GPIOC IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-7 Interrupt Priority Register 4 (IPR4)
5.6.5.1
SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.2
SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8346 Technical Data, Rev. 15
90
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.5.3
SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.4
Reserved—Bits 9–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5.5
GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.6
GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.7
GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
91
5.6.6
Interrupt Priority Register 5 (IPR5)
Base + $5
Read
15
14
13
12
11
10
9
8
7
0
6
0
5
4
3
2
1
0
DEC1_XIRQ DEC1_HIRQ
IPL IPL
SCI1_RCV
IPL
SCI1_RERR
IPL
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1
Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ
IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.2
Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.3
SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8346 Technical Data, Rev. 15
92
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.6.4
SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.5
Reserved—Bits 7–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.6
SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.7
SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)—
Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.8
SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
93
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7
Interrupt Priority Register 6 (IPR6)
Base + $6
Read
15
14
13
12
11
10
9
8
7
6
5
0
4
0
3
2
1
0
DEC0_XIRQ
IPL
DEC0_HIRQ
IPL
TMRC0 IPL
TMRD3 IPL
TMRD2 IPL
TMRD1 IPL
TMRD0 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)—Bits 15–14
5.6.7.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.2
Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.3
Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
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Freescale Semiconductor
Preliminary
Register Descriptions
•
11 = IRQ is priority level 2
5.6.7.4
Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.5
Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.7
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ
IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.8
Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Freescale Semiconductor
Preliminary
95
5.6.8
Interrupt Priority Register 7 (IPR7)
Base + $7
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMRA0 IPL
TMRB3 IPL
TMRB2 IPL
TMRB1 IPL
TMRB0 IPL
TMRC3 IPL
TMRC2 IPL
TMRC1 IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-10 Interrupt Priority Register (IPR7)
Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—Bits 15–14
5.6.8.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.2
Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.3
Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.4
Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Freescale Semiconductor
Preliminary
Register Descriptions
5.6.8.5
Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.6
Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.7
Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8.8
Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Freescale Semiconductor
Preliminary
97
5.6.9
Interrupt Priority Register 8 (IPR8)
Base + $8
Read
15
14
13
12
11
0
10
0
9
8
7
6
5
4
3
2
1
0
SCI0_RCV
IPL
SCI0_RERR
IPL
SCI0_TIDL
IPL
SCI0_XMIT
IPL
TMRA3 IPL
TMRA2 IPL
TMRA1 IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-11 Interrupt Priority Register 8 (IPR8)
SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—Bits 15–14
5.6.9.1
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.9.4
SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)—
Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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Freescale Semiconductor
Preliminary
Register Descriptions
5.6.9.5
SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.6
Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.7
Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.8
Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
99
5.6.10 Interrupt Priority Register 9 (IPR9)
Base + $9
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWMA_RL
IPL
ADCA_CC
IPL
ADCB_CC
IPL
PWMA_F IPL PWMB_F IPL
PWM_RL IPL ADCA_ZC IPL ABCB_ZC IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-12 Interrupt Priority Register 9 (IPR9)
5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)—Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)—Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
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100
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level
(ADCA_ZC IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.6 ADC B Zero Crossing or Limit Error Interrupt Priority Level
(ADCB_ZC IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.7 ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC
IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
101
5.6.11 Vector Base Address Register (VBA)
Base + $A
Read
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
VECTOR BASE ADDRESS
Write
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-13 Vector Base Address Register (VBA)
5.6.11.1 Reserved—Bits 15–13
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—Bits 12–0
The contents of this register determine the location of the Vector Address Table. The value in this register
is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are
determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting
the full VAB to the 56800E core; see Part 5.3.1 for details.
5.6.12 Fast Interrupt 0 Match Register (FIM0)
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 0
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to Table 4-5.
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102
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS LOW
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Base + $D
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15 Fast Interrupt 1 Match Register (FIM1)
Base + $E
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 1
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
103
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to Table 4-5.
5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Base + $F
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
FAST INTERRUPT 1
VECTOR ADDRESS LOW
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)
Base + $10
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18 IRQ Pending 0 Register (IRQP0)
Base + $11
Read
15
1
14
1
13
12
11
10
9
8
7
6
5
4
3
1
2
1
1
1
0
1
PENDING [16:2]
Write
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-20 IRQ Pending 0 Register (IRQP0)
56F8346 Technical Data, Rev. 15
104
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.18.1 IRQ Pending (PENDING)—Bits 16–2
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.18.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19 IRQ Pending 1 Register (IRQP1)
$Base + $12
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
1
1
1
0
1
PENDING [32:17]
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1 IRQ Pending (PENDING)—Bits 32–17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.20 IRQ Pending 2 Register (IRQP2)
Base + $13
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [48:33]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1 IRQ Pending (PENDING)—Bits 48–33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
105
5.6.21 IRQ Pending 3 Register (IRQP3)
Base + $14
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [64:49]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1 IRQ Pending (PENDING)—Bits 64–49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.22 IRQ Pending 4 Register (IRQP4)
Base + $15
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [80:65]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1 IRQ Pending (PENDING)—Bits 80–65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.23 IRQ Pending 5 Register (IRQP5)
Base + $16
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
PEND-
ING
[81]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-25 IRQ Pending Register 5 (IRQP5)
56F8346 Technical Data, Rev. 15
106
Freescale Semiconductor
Preliminary
Register Descriptions
5.6.23.1 Reserved—Bits 96–82
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.
5.6.23.2 IRQ Pending (PENDING)—Bit 81
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.24 Reserved—Base + 17
5.6.25 Reserved—Base + 18
5.6.26 Reserved—Base + 19
5.6.27 Reserved—Base + 1A
5.6.28 Reserved—Base + 1B
5.6.29 Reserved—Base + 1C
5.6.30 ITCN Control Register (ICTL)
Base + $1D
Read
15
14
13
12 11 10
9
8
7
6
0
5
INT_DIS
0
4
1
3
2
1
0
INT
IPIC
VAB
IRQB STATE IRQA STATE
IRQB IRQA
EDG
EDG
Write
0
0
0
1
0
0
0
0
0
1
1
1
0
0
RESET
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
•
0 = No interrupt is being sent to the 56800E core
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
107
•
1 = An interrupt is being sent to the 56800E core
5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
•
•
•
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3
This read-only bit reflects the state of the external IRQB pin.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1
This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQB interrupt is a low-level sensitive (default)
1 = IRQB interrupt is falling-edge sensitive.
56F8346 Technical Data, Rev. 15
108
Freescale Semiconductor
Preliminary
Resets
5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive.
5.7 Resets
5.7.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
•
•
•
•
•
•
•
•
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Part 6 System Integration Module (SIM)
6.1 Overview
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
•
•
•
•
•
•
Reset sequencing
Clock generation & distribution
Stop/Wait control
Pull-up enables for selected peripherals
System status registers
Registers for software access to the JTAG ID of the chip
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
109
•
Enforcing Flash security
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
•
•
•
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be
explicitly done
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
•
•
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be either
3 x 32 clocks (phased release of reset) for reset, except for POR, which is 221 clock cycles.
Controls reset sequencing after reset
•
•
•
•
•
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
56F8346 Technical Data, Rev. 15
110
Freescale Semiconductor
Preliminary
Operating Modes
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
•
Reset Mode, which has two submodes:
— POR and RESET operation
The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the
RESET pin is asserted.
— COP reset and software reset operation
The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This allows
the software to determine the boot mode (internal or external boot) to be used on the next reset.
•
•
Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation.
Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and
PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor
from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
•
•
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
Stop Mode
When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down. Optionally, the
COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down.
This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The
CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully
functional in Stop mode.
6.4 Operating Mode Register
Bit
15
NL
R/W
0
14
0
13
0
12
0
11
0
10
9
0
8
CM
R/W
0
7
XP
R/W
0
6
SD
R/W
0
5
R
4
SA
R/W
0
3
EX
R/W
0
2
0
1
MB
R/W
X
0
MA
R/W
X
R/W
0
Type
0
0
RESET
Figure 6-1 OMR
The reset state for MB and MA will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For all
other bits, see the DSP56800E Reference Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
111
6.5 Register Descriptions
Table 6-1 SIM Registers (SIM_BASE = $00F350)
Address Offset
Address Acronym
Register Name
Control Register
Section Location
Base + $0
Base + $1
Base + $2
Base + $3
Base + $4
Base + $5
Base + $6
Base + $7
Base + $8
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
6.5.1
6.5.2
6.5.3
6.5.3
6.5.3
6.5.3
6.5.4
6.5.5
6.5.6
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half of JTAG ID
Least Significant Half of JTAG ID
Pull-up Disable Register
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
Reserved
Base + $A
Base + $B
Base + $C
Base + $D
Base + $E
SIM_CLKOSR
SIM_GPS
CLKO Select Register
6.5.7
6.5.7
6.5.8
6.5.9
6.5.10
GPIO Peripheral Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
SIM_PCE
SIM_ISALH
SIM_ISALL
Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
SIM_
CONTROL
EMI_ ONCE
MODE EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
$0
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
RSTSTS
$1
$2
$3
$4
$5
$6
$7
$8
SWR COPR EXTR POR
W
R
SIM_SCR0
SIM_SCR1
SIM_SCR2
SIM_SCR3
FIELD
W
R
FIELD
FIELD
FIELD
W
R
W
R
W
R
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
1
1
0
0
0
0
0
1
0
SIM_MSH_
ID
W
R
SIM_LSH_ID
W
R
PWMA
1
EMI_
MODE
PWMA
0
SIM_PUDR
Reserved
CAN
RESET IRQ XBOOT PWMB
CTRL
JTAG
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
CLKOSR
$A
$B
A23
0
A22
0
A21
0
A20 CLKDIS
CLKOSEL
C2
0
0
0
SIM_GPS
C3
C1
C0
W
Figure 6-2 SIM Register Map Summary
56F8346 Technical Data, Rev. 15
112
Freescale Semiconductor
Preliminary
Register Descriptions
R
W
R
PWM PWM
SPI0
$C
$D
$E
SIM_PCE
SIM_ISALH
SIM_ISALL
EMI
1
ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1
SCI0 SPI1
B
A
1
1
1
1
1
1
1
1
1
1
1
1
1
ISAL[23:22]
W
R
ISAL[21:6]
W
= Reserved
Figure 6-2 SIM Register Map Summary (Continued)
6.5.1
SIM Control Register (SIM_CONTROL)
Base + $0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
Read
Write
EMI_ ONCE SW
MODE EBL
STOP_
DISABLE
WAIT_
DISABLE
RST
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1
Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2
EMI_MODE (EMI_MODE)—Bit 6
This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with
the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings
can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset.
In addition, this pin can be used as a general purpose input pin after reset.
•
•
0 = External address bits [19:16] are initially programmed as GPIO
1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
6.5.1.3
OnCE Enable (OnCE EBL)—Bit 5
•
•
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.4
Software Reset (SWRST)—Bit 4
This bit is always read as 0. Writing a 1 to this field will cause the part to reset.
6.5.1.5
Stop Disable (STOP_DISABLE)—Bits 3–2
•
•
00 - STOP mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
113
•
•
10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
11 - Same operation as 10
6.5.1.6
Wait Disable (WAIT_DISABLE)—Bits 1–0
•
•
00 - WAIT mode will be entered when the 56800E core executes a WAIT instruction
01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
•
10 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only be
changed by resetting the device
•
11 - Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
Base + $1
Read
15
0
14
0
13
O
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
0
0
SWR COPR
EXTR POR
Write
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.2.2
Software Reset (SWR)—Bit 5
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST
bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing
a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3
COP Reset (COPR)—Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will
set the bit, while writing a 1 to the bit will clear it.
6.5.2.4
External Reset (EXTR)—Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On
Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position
will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external
RESET pin being asserted low.
56F8346 Technical Data, Rev. 15
114
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.2.5
Power-On Reset (POR)—Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared
only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the
bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On
Reset.
6.5.2.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,
and SIM_SCR3)
Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FIELD
0
Write
0
0
0
0
0
0
0
0
0
0
0
0
POR
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
Software Control Data 1 (FIELD)—Bits 15–0
6.5.3.1
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$11F4.
Base + $6
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
1
4
1
3
0
2
1
1
0
0
0
Write
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
RESET
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$401D.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
115
Base + $7
Read
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
Write
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
RESET
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Base + $8
Read
15
0
14
13
12
11
10
9
8
7
6
0
5
CTRL
0
4
0
3
JTAG
0
2
0
1
0
0
0
EMI_
MODE
PWMA1 CAN
RESET IRQ XBOOT PWMB PWMA0
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
PWMA1—Bit 14
This bit controls the pull-up resistors on the FAULTA3 pin.
6.5.6.3
CAN—Bit 13
This bit controls the pull-up resistors on the CAN_RX pin.
6.5.6.4
EMI_MODE—Bit 12
This bit controls the pull-up resistors on the EMI_MODE pin.
6.5.6.5
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
6.5.6.6
IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA and IRQB pins.
6.5.6.7
XBOOT—Bit 9
This bit controls the pull-up resistors on the EXTBOOT pin.
56F8346 Technical Data, Rev. 15
116
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.6.8
PWMB—Bit 8
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins.
6.5.6.9
PWMA0—Bit 7
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
6.5.6.10 Reserved—Bit 6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.11 CTRL—Bit 5
This bit controls the pull-up resistors on the WR and RD pins.
6.5.6.12 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.13 JTAG—Bit 3
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.6.14 Reserved—Bits 2 - 0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are
for test purposes only, and are subject to significant unspecified latencies at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, A[23:20], or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed
to operate as peripheral outputs, then the choice between A[23:20] and additional clock outputs is done
here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as
A[23:20]. This can be changed by altering A[23:20], as shown in Figure 6-9.
Base + $A
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
A23
0
8
A22
0
7
A21
0
6
A20
0
5
4
3
0
2
CLKOSEL
0
1
0
0
0
CLK
DIS
Write
0
0
0
0
0
0
1
0
RESET
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
Reserved—Bits 15–10
6.5.7.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
117
6.5.7.2
Alternate GPIOB Peripheral Function Select for A23 (A23)—Bit 9
•
•
0 = Peripheral output function of GPIOB7 is defined to be A23
1 = Peripheral output function of GPIOB7 is defined to be the oscillator clock (MSTR_OSC, see
Figure 3-4)
6.5.7.3
Alternate GPIOB Peripheral Function Select for A22 (A22)—Bit 8
•
•
0 = Peripheral output function of GPIOB6 is defined to be A22
1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2
6.5.7.4
Alternate GPIOB Peripheral Function Select for A21 (A21)—Bit 7
•
•
0 = Peripheral output function of GPIOB5 is defined to be A21
1 = Peripheral output function of GPIOB5 is defined to be SYS_CLK
6.5.7.5
Alternate GPIOB Peripheral Function Select for A20 (A20)—Bit 6
•
•
0 = Peripheral output function of GPIOB4 is defined to be A20
1 = Peripheral output function of GPIOB4 is defined to be the prescaler clock (FREF, see Figure 3-4)
6.5.7.6
Clockout Disable (CLKDIS)—Bit 5
•
•
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
6.5.7.7
CLockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
•
•
•
•
•
•
•
•
•
00000 = SYS_CLK (from OCCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = Oscillator output
01000 = Fout (from OCCS)
•
•
•
•
•
•
•
•
•
01001 = Reserved for factory test—IPB clock
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
10001 = ADCB clock
56F8346 Technical Data, Rev. 15
118
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.8
GPIO Peripheral Select Register (SIM_GPS)
The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals
for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8146
device); these peripherals work together.
The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as
SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in
Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the
choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction
with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function
of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate
controls in the indicated registers.
GPIOC_PER Register
GPIO Controlled
0
1
I/O Pad Control
SIM_ GPS Register
0
1
Quad Timer Controlled
SPI Controlled
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
119
1
Table 6-2 Control of Pads Using SIM_GPS Control
Control Registers
Pin Function
Comments
GPIO Input
0
0
1
0
1
—
—
0
—
—
0
GPIO Output
Quad Timer Input / Quad
Decoder Input 2
—
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of the timer inputs based on
the Quad Decoder Mode configuration.
Quad Timer Output / Quad
Decoder Input 3
1
—
0
1
SPI input
1
1
—
—
1
1
—
—
See SPI controls for determining the direction
of each of the SPI pins.
SPI output
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is
used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1
Reserved—Bits 15–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
GPIOC3 (C3)—Bit 3
This bit selects the alternate function for GPIOC3.
•
•
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User Manual)
1 = SS1
56F8346 Technical Data, Rev. 15
120
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.8.3
GPIOC2 (C2)—Bit 2
This bit selects the alternate function for GPIOC2.
•
•
0 = INDEX1/TB2 (default)
1 = MISO1
6.5.8.4
GPIOC1 (C1)—Bit 1
This bit selects the alternate function for GPIOC1.
•
•
0 = PHASEB1/TB1 (default)
1 = MOSI1
6.5.8.5
GPIOC0 (C0)—Bit 0
This bit selects the alternate function for GPIOC0.
•
•
0 = PHASEA1/TB0 (default)
1 = SCLK1
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0 SPI 1 SPI 0 PWMB PWMA
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1
External Memory Interface Enable (EMI)—Bit 15
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2
Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
•
1 = Clocks are enabled
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
121
•
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4
FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.5
Decoder 1 Enable (DEC1)—Bit 11
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6
Decoder 0 Enable (DEC0)—Bit 10
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.7
Quad Timer D Enable (TMRD)—Bit 9
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8
Quad Timer C Enable (TMRC)—Bit 8
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.9
Quad Timer B Enable (TMRB)—Bit 7
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
56F8346 Technical Data, Rev. 15
122
Freescale Semiconductor
Preliminary
Register Descriptions
6.5.9.11 Serial Communications Interface 1 Enable (SCI1)—Bit 5
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.15 Pulse Width Modulator B Enable (PWMB)—1
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.16 Pulse Width Modulator A Enable (PWMA)—0
Each bit controls clocks to the indicated peripheral.
•
•
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-13.
Note:
If this register is set to something other than the top of memory (EOnCE register space) and the EX bit
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
123
Instruction Portion
“Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
Note:
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is three cycles.
Base + $D
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
0
ISAL[23:22]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Base + $E
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
0
1
ISAL[21:6]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
56F8346 Technical Data, Rev. 15
124
Freescale Semiconductor
Preliminary
Clock Generation Overview
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and
system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and
system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The
SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)
to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible
means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut
down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and
master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.
Clock enables provide the means to disable individual clocks. Some peripherals provide further controls
to disable unused subfunctions. Refer to the Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300
Peripheral User Manual for further details.
6.7 Power-Down Modes Overview
The 56F8346/56F8146 devices operate in one of three power-down modes, as shown in Table 6-3.
Table 6-3 Clock Operation in Power-Down Modes
Mode
Run
Core Clocks
Active
Peripheral Clocks
Description
Device is fully functional
Active
Active
Wait
Core and memory
clocks disabled
Peripherals are active and can product interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in The only possible recoveries from Stop mode are:
the SIM, but most are gated prior to
reaching memory, core and peripherals.
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
125
6.8 Stop and Wait Mode Disable Function
Permanent
Disable
D
Q
D-FLOP
C
56800E
Reprogrammable
Disable
STOP_DIS
D
Q
D-FLOP
Clock
Select
C
R
Reset
Note: Wait disable circuit is similar
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the prescaler output.
Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL), described in Part 6.5.1. This procedure
can be on either a permanent or temporary basis. Permanently assigned applications last only until their
next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and
the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within
the SIM itself by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced
21
to permit proper operation of the device. A POR reset is first extended for 2 clock cycles to permit
stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated. It is
then followed by a 32 clock window in which peripherals are released to implement Flash security, and,
finally, followed by a 32 clock window in which the core is initialized. After completion of the described
reset sequence, application code will begin execution.
Resets may be asserted asynchronously, but they are always released internally on a rising edge of the
system clock.
56F8346 Technical Data, Rev. 15
126
Freescale Semiconductor
Preliminary
Operation with Security Enabled
Part 7 Security Features
The 56F8346/56F8146 offer security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The Flash security consists of several hardware interlocks that
block the means by which an unauthorized user could gain access to the Flash array.
However, part of the security must lie with the user’s code. An extreme example would be user’s code that
dumps the contents of the internal program, as this code would defeat the purpose of security. At the same
time, the user may also wish to put a “backdoor” in his program. As an example, the user downloads a
security key through the SCI, allowing access to a programming routine that updates parameters stored in
another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the device can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of the FM
array. These non-volatile bytes will keep the part secured through reset and through power-down of the
device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory
section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state
of security. When Flash security mode is enabled in accordance with the method described in the Flash
Memory module specification, the device will disable external P-space accesses restricting code execution
to internal memory, disable EXTBOOT = 1 mode, and disable the core EOnCE debug capabilities. Normal
program execution is otherwise unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8346/56F8146 have several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be compromised
and read without explicit user permission. Methods to block these are outlined in the next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the device will operate. These are:
•
•
•
Internal Boot Mode
External Boot Mode
Secure Mode
When Flash security is enabled as described in the Flash Memory module specification, the device will
boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot
Flash at address 0x02_0000.
This security affords protection only to applications in which the device operates in internal Flash security
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
127
mode. Therefore, the security feature cannot be used unless all executing code resides on-chip.
When security is enabled, any attempt to override the default internal operating mode by asserting the
EXTBOOT pin in conjunction with reset will be ignored.
7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the
EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port)
is active and provides the chip’s boundary scan capability and access to the ID register.
Proper implementation of Flash security requires that no access to the EOnCE port is provided when
security is enabled. The 56800E core has an input which disables reading of internal memory via the
JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the FM security
bytes.
7.2.3
Flash Lockout Recovery
If a user inadvertently enables Flash security on the device, a built-in lockout recovery mechanism can be
used to reenable access to the device. This mechanism completely reases all on-chip Flash, thus disabling
Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory
configuration (.cfg) files. Add, or uncomment the following configuration command:
unlock_flash_on_connect 1
For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual.
The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to
control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control
the period of the clock used for timed events in the FM erase algorithm. This register must be set with
appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300
Peripheral User Manual for more details on setting this register value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides
down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the
PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV
must divide the FM input clock down to a frequency of 150kHz-200kHz. The “Writing the FMCLKD
Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific
equations for calculating the correct values.
56F8346 Technical Data, Rev. 15
128
Freescale Semiconductor
Preliminary
Flash Access Blocking Mechanisms
Flash Memory
SYS_CLK
2
input
clock
DIVIDER
7
FMCLKD
7
7
FM_CLKDIV
FM_ERASE
JTAG
Figure 7-1 JTAG to FM Connection for Lockout Recovery
Two examples of FM_CLKDIV calculations follow.
EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up,
the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation
yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This
translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.
SYS_CLK
( )
(2)
150[kHz]
200[kHz]
<
<
(DIV + 1)
EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM
input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the
following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of
181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.
SYS_CLK
( )
(2)
150[kHz]
200[kHz]
<
<
(DIV + 1)
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock
divider value must be shifted into the corresponding 7-bit data register. After the data register has been
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout
sequence to commence. The controller must remain in this state until the erase sequence has completed.
For details, see the JTAG Section in the 56F8300 Peripheral User Manual.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
129
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
(by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured
operation.
7.2.4
Product Analysis
The recommended method of unsecuring a programmed device for product analysis of field failures is via
the backdoor key access. The customer would need to supply Technical Support with the backdoor key
and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows
backdoor key access must be set.
An alternative method for performing analysis on a secured hybrid controller would be to mass-erase and
reprogram the Flash with the original code, but modify the security bytes.
To insure that a customer does not inadvertently lock himself out of the device during programming, it is
recommended that he program the backdoor access key first, his application code second, and the security
bytes within the FM configuration field last.
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F8300 Peripheral User Manual.
8.2 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and
GPIOx_PER registers change from port to port. Tables 4-29 through 4-34 define the actual reset values of
these registers.
8.3 Configuration
There are six GPIO ports defined on the 56F8346/56F8146. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
56F8346 Technical Data, Rev. 15
130
Freescale Semiconductor
Preliminary
Configuration
Table 8-1 56F8346 GPIO Ports Configuration
Available
Pins in
56F8346
GPIO
Port
Port
Width
Peripheral Function
Reset Function
14 pins - EMI Address pins
A
B
14
8
14
1
EMI Address
1 pin - EMI Address pin
7 pins - EMI Address pins - Not available in this package
EMI Address
N/A
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
3 pins -PWMA current sense
C
D
11
13
11
9
DEC1 / TMRB
DEC0 / TMRA
PWMA current sense
2 pins - EMI CSn
4 pins - EMI CSn - Not available in this package
2 pins - SCI1
EMI Chip Selects
N/A
SCI1
2 pins - EMI CSn
3 pins -PWMB current sense
EMI Chip Selects
PWMB current sense
SCI0
EMI Address
SPI0
TMRC
N/A
TMRD
N/A
E
14
16
11
16
2 pins - SCI0
2 pins - EMI Address pins
4 pins - SPI0
1 pin - TMRC
1 pin - TMRC - Not available in this package
2 pins - TMRD
2 pins - TMRD - Not available in this package
16 pins - EMI Data
F
EMI Data
Table 8-2 56F8146 GPIO Ports Configuration
Available
Pins in
56F8146
GPIO
Port
Port
Width
Peripheral Function
Reset Function
14 pins - EMI Address pins
A
B
14
8
14
1
EMI Address
1 pin - EMI Address pin
7 pins - EMI Address pins - Not available in this package
EMI Address
N/A
4 pins - SPI1
4 pins - DEC0 / TMRA
3 pins - Dedicated GPIO
C
D
11
13
11
9
SPI1
DEC0 / TMRA
GPIO
2 pins - EMI CSn
4 pins - EMI CSn - Not available in this package
2 pins - SCI1
EMI Chip Selects
N/A
SCI1
2 pins - EMI CSn
3 pins - PWMB current sense
EMI Chip Selects
PWMB current sense
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
131
Table 8-2 56F8146 GPIO Ports Configuration
Available
Pins in
56F8146
GPIO
Port
Port
Width
Peripheral Function
Reset Function
SCI0
E
14
11
2 pins - SCI0
EMI Address
SPI0
2 pins - EMI Address pins
4 pins - SPI0
TMRC
N/A
GPIO
1 pin - TMRC
1 pin - TMRC - Not available in this package
2 pins - Dedicated GPIO
N/A
2 pins - TMRD - Not available in this package
16 pins - EMI Data
F
16
16
EMI Data
Table 8-3 GPIO External Signals Map
Pins in shaded rows are not available in 56F8346/56F8146
Pins in italics are NOT available in the 56F8146 device
Reset
Function
Functional Signal
Package Pin
GPIO Port
GPIO Bit
0
1
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
A8
A9
19
20
21
22
23
24
25
26
138
10
11
12
13
14
2
A10
A11
A12
A13
A14
A15
A0
3
4
5
6
GPIOA
7
8
9
A1
10
11
12
13
A2
A3
A4
A5
56F8346 Technical Data, Rev. 15
132
Freescale Semiconductor
Preliminary
Configuration
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8346/56F8146
Pins in italics are NOT available in the 56F8146 device
Reset
Function
Functional Signal
Package Pin
GPIO Port
GPIO Bit
GPIO1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
A16
33
1
2
3
4
5
6
7
GPIOB
1This is a function of the EMI_MODE, EXTBOOT, and Flash security settings at reset.
PhaseA1 / TB0 / SCLK11
PhaseB1 / TB1 / MOSI11
Index1 / TB2 / MISO11
0
1
2
3
Peripheral
Peripheral
Peripheral
Peripheral
6
7
8
9
Home1 / TB3 / SS11
PHASEA0 / TA0
PHASEB0 / TA1
INDEX0 / TA2
HOME0 / TA3
ISA0
4
5
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
139
140
141
142
113
114
115
GPIOC
6
7
8
9
ISA1
10
ISA2
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
133
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8346/56F8146
Pins in italics are NOT available in the 56F8146 device
Reset
Function
Functional Signal
Package Pin
GPIO Port
GPIO Bit
0
1
GPIO
GPIO
CS2
CS3
48
49
2
N/A
3
N/A
4
N/A
5
N/A
GPIOD
6
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
TXD1
RXD1
42
43
46
47
50
52
53
7
8
PS / CS0
DS / CS1
ISB0
9
10
11
12
ISB1
ISB2
56F8346 Technical Data, Rev. 15
134
Freescale Semiconductor
Preliminary
Configuration
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8346/56F8146
Pins in italics are NOT available in the 56F8146 device
Reset
Function
Functional Signal
Package Pin
GPIO Port
GPIO Bit
0
1
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
N/A
TXD0
RXD0
A6
4
5
2
17
3
A7
18
4
SCLK0
MOSI0
MISO0
SS0
130
132
131
129
118
5
6
GPIOE
7
8
TC0
9
10
11
12
13
Peripheral
Peripheral
N/A
TD0
TD1
116
117
N/A
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
135
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8346/56F8146
Pins in italics are NOT available in the 56F8146 device
Reset
Function
Functional Signal
Package Pin
GPIO Port
GPIO Bit
0
1
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
D7
D8
28
29
2
D9
30
3
D10
D11
D12
D13
D14
D15
D0
32
4
133
134
135
136
137
59
5
6
7
GPIOF
8
9
10
11
12
13
14
15
D1
60
D2
72
D3
75
D4
76
D5
77
D6
78
1. See Part 6.5.8 to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset .
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please contact your Freescale marketing representative or authorized distributor for
device/package-specific BSDL information.
Part 10 Specifications
10.1 General Characteristics
The 56F8346/56F8146 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital
inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and
56F8346 Technical Data, Rev. 15
136
Freescale Semiconductor
Preliminary
General Characteristics
5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the
power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Note: All specifications meet both Automotive and Industrial requirements unless individual
specifications are listed.
Note: The 56F8146 device is guaranteed to 40MHz and specified to meet Industrial requirements only;
CAN is NOT available on the 56F8146 device.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Note: The 56F8146 device is specified to meet Industrial requirements only; CAN is NOT available on the
56F8146 device.
Table 10-1 Absolute Maximum Ratings
(VSS = VSSA_ADC = 0)
Characteristic
Supply voltage
Symbol
VDD_IO
Notes
Min
- 0.3
- 0.3
Max
4.0
Unit
V
ADC Supply Voltage
VDDA_ADC, VREFH
VREFH must be less than or
equal to VDDA_ADC
4.0
V
Oscillator / PLL Supply Voltage
Internal Logic Core Supply Voltage
Input Voltage (digital)
VDDA_OSC_PLL
VDD_CORE
VIN
- 0.3
- 0.3
-0.3
-0.3
-0.3
4.0
3.0
6.0
4.0
V
V
V
V
V
OCR_DIS is High
Pin Groups 1, 2, 5, 6, 9, 10
Pin Groups 11, 12, 13
Input Voltage (analog)
VINA
Pin Groups 1, 2, 3, 4, 5, 6, 7, 8
Output Voltage
VOUT
4.0
6.01
Pin Group 4
Output Voltage (open drain)
VOD
-0.3
6.0
V
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
137
Table 10-1 Absolute Maximum Ratings (Continued)
(VSS = VSSA_ADC = 0)
Characteristic
Symbol
TA
Notes
Min
-40
-40
-40
-40
-55
-55
Max
125
105
150
125
150
150
Unit
°C
Ambient Temperature (Automotive)
Ambient Temperature (Industrial)
Junction Temperature (Automotive)
Junction Temperature (Industrial)
Storage Temperature (Automotive)
Storage Temperature (Industrial)
TA
°C
TJ
°C
TJ
°C
TSTG
TSTG
°C
°C
1. If corresponding GPIO pin is configured as open drain.
Note: Pins in italics are NOT available in the 56F8146 device.
Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0
Pin Group 2: PHASEA0, PHASEA1, PHASEB0, PHASEB1, INDEX0, INDEX1, HOME0, HOME1, ISB0-2, ISA0-2, TC0, SCLK0
Pin Group 3: RSTO, TDO
Pin Group 4: CAN_TX
Pin Group 5: A0-5, D0-15, GPIOD0-1, PS, DS
Pin Group 6: A6-15, GPIOB0, TD0-1
Pin Group 7: CLKO, WR, RD
Pin Group 8: PWMA0-5, PWMB0-5
Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3
Pin Group 10: TCK
Pin Group 11: XTAL, EXTAL
Pin Group 12: ANA0-7, ANB0-7
Pin Group 13: OCR_DIS, CLKMODE
Table 10-2 56F8346/56F8146 ElectroStatic Discharge (ESD) Protection
Characteristic
Min
Typ
Max
Unit
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
ESD for Charge Device Model (CDM)
2000
200
—
—
—
—
—
—
V
V
V
500
6
Table 10-3 Thermal Characteristics
Value
Characteristic
Comments
Symbol
Unit
Notes
144-pin LQFP
R
Junction to ambient
Natural convection
47.1
°C/W
2
θJA
56F8346 Technical Data, Rev. 15
138
Freescale Semiconductor
Preliminary
General Characteristics
6
Table 10-3 Thermal Characteristics
Value
Characteristic
Symbol
Unit
Notes
Comments
144-pin LQFP
43.8
R
Junction to ambient (@1m/sec)
°C/W
°C/W
2
θJMA
R
Junction to ambient
Natural convection
Four layer board (2s2p)
Four layer board (2s2p)
40.8
1,2
θJMA
(2s2p)
R
Junction to ambient (@1m/sec)
Junction to case
39.2
°C/W
°C/W
°C/W
W
1,2
3
θJMA
R
11.8
1
θJC
Ψ
Junction to center of case
I/O pin power dissipation
Power dissipation
4, 5
JT
P
User-determined
P D = (IDD x VDD + P I/O
I/O
P
)
W
D
(TJ - TA) / RθJA7
P
Maximum allowed PD
W
DMAX
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p ther-
mal test board.
2. Junction to ambient thermal resistance, Theta-JA (R ) was simulated to be equivalent to the JEDEC specification JESD51-2
θJA
in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes
(2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name
for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (R
), was simulated to be equivalent to the measured values using the cold
θJC
plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is
described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when
the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (Ψ ), is the "resistance" from junction to reference point thermocouple on top cen-
JT
ter of case as defined in JESD51-2. Ψ is a useful value to use to estimate junction temperature in steady-state customer en-
JT
vironments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
6. See Part 12.1 for more details on thermal design considerations.
7. TJ = Junction temperature
TA = Ambient temperature
Note: The 56F8146 device is guaranteed to 40MHz and specified to meet Industrial requirements only;
CAN is NOT available on the 56F8146 device.
Table 10-4 Recommended Operating Conditions
(VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL
)
Characteristic
Supply voltage
Symbol
Notes
Min
3
Typ
3.3
3.3
Max
3.6
Unit
V
V
DD_IO
ADC Supply Voltage
V
V
V
must be less than
REFH
3
3.6
DDA_ADC,
or equal to VDDA_ADC
V
REFH
Oscillator / PLL Supply Voltage
V
V
3
3.3
3.6
DDA_OSC_PLL
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
139
Table 10-4 Recommended Operating Conditions
(VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL
)
Characteristic
Symbol
Notes
Min
Typ
Max
Unit
Internal Logic Core Supply Voltage
Device Clock Frequency
OCR_DIS is High
V
MHz
V
V
2.25
0
2.5
—
2.75
60
DD_CORE
FSYSCLK
Input High Voltage (digital)
Pin Groups
1, 2, 5, 6, 9, 10
V
2
—
5.5
IN
Input High Voltage (analog)
Pin Group 13
Pin Group 11
V
V
V
2
—
—
VDDA+0.3
VDDA+0.3
IHA
Input High Voltage (XTAL/EXTAL,
XTAL is not driven by an external clock)
V
VDDA-0.8
IHC
Input high voltage (XTAL/EXTAL,
XTAL is driven by an external clock)
Pin Group 11
V
V
V
2
—
—
VDDA+0.3
0.8
IHC
Input Low Voltage
Pin Groups
1, 2, 5, 6, 9, 10,
11, 13
V
-0.3
IL
Output High Source Current
VOH = 2.4V (VOH min.)
Pin Groups 1, 2, 3
Pin Groups 5, 6, 7
Pin Group 8
mA
mA
I
—
—
—
—
—
—
—
—
-4
-8
OH
-12
4
Output Low Sink Current
VOL = 0.4V (VOL max)
Pin Groups
1, 2, 3, 4
I
OL
Pin Groups 5, 6, 7
Pin Group 8
—
—
—
—
—
8
12
125
Ambient Operating Temperature
(Automotive)
°C
T
-40
A
Ambient Operating Temperature
(Industrial)
105
—
°C
T
-40
10,000
10,000
15
—
—
—
—
A
Flash Endurance (Automotive)
(Program Erase Cycles)
TA = -40°C to 125°C
TA = -40°C to 105°C
TJ <= 85°C avg
Cycles
Cycles
Years
N
F
Flash Endurance (Industrial)
(Program Erase Cycles)
N
—
F
Flash Data Retention
T
—
R
Total chip source or sink current cannot exceed 200mA
See Pin Groups in Table 10-1
56F8346 Technical Data, Rev. 15
140
Freescale Semiconductor
Preliminary
DC Electrical Characteristics
10.2 DC Electrical Characteristics
Note: The 56F8146 device is specified to meet Industrial requirements only; CAN is NOT
available on the 56F8146 device.
Table 10-5 DC Electrical Characteristics
At Recommended Operating Conditions; see Table 10-4
Characteristic
Output High Voltage
Output Low Voltage
Symbol
Notes
Min
2.4
—
Typ
—
—
0
Max
—
Unit
V
Test Conditions
IOH =IOHmax
V
OH
V
IOL =IOLmax
V
0.4
OL
Digital Input Current High
pull-up enabled or disabled
Pin Groups 1, 2, 5, 6, 9
Pin Group 10
μA
VIN = 3.0V to 5.5V
I
—
+/- 2.5
IH
Digital Input Current High
with pull-down
μA
VIN = 3.0V to 5.5V
I
40
80
160
IH
Analog Input Current High
ADC Input Current High
Pin Group 13
Pin Group 12
μA
μA
μA
VIN = VDDA
VIN = VDDA
VIN = 0V
I
—
—
0
0
+/- 2.5
+/- 3.5
-50
IHA
I
IHADC
Digital Input Current Low
pull-up enabled
Pin Groups 1, 2, 5, 6, 9
I
-200
-100
IL
Digital Input Current Low
pull-up disabled
Pin Groups 1, 2, 5, 6, 9
Pin Group 10
μA
μA
VIN = 0V
VIN = 0V
I
—
—
0
0
+/- 2.5
+/- 2.5
IL
Digital Input Current Low
with pull-down
I
IL
Analog Input Current Low
ADC Input Current Low
Pin Group 13
Pin Group 12
μA
μA
μA
VIN = 0V
VIN = 0V
I
—
—
—
0
0
0
+/- 2.5
+/- 3.5
+/- 2.5
ILA
I
ILADC
EXTAL Input Current Low
clock input
VIN = VDDA or 0V
I
EXTAL
XTAL Input Current Low
clock input
CLKMODE = High
CLKMODE = Low
μA
μA
μA
VIN = VDDA or 0V
VIN = VDDA or 0V
I
—
—
—
0
—
0
+/- 2.5
200
XTAL
Output Current
High Impedance State
Pin Groups
1, 2, 3, 4, 5, 6, 7, 8
VOUT = 3.0V to 5.5V or 0V
I
+/- 2.5
OZ
Schmitt Trigger Input
Hysteresis
Pin Groups 2, 6, 9,10
V
V
—
—
—
0.3
4.5
5.5
—
—
—
—
—
—
HYS
Input Capacitance
(EXTAL/XTAL)
pF
pF
C
INC
Output Capacitance
(EXTAL/XTAL)
C
OUTC
Input Capacitance
Output Capacitance
pF
pF
C
—
—
6
6
—
—
—
—
IN
C
OUT
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
141
See Pin Groups in Table 10-1
Table 10-6 Power on Reset Low Voltage Parameters
Characteristic
Symbol
Min
Typ
Max
Units
POR Trip Point
POR
VEI2.5
VEI3.3
1.75
—
1.8
1.9
—
V
V
LVI, 2.5 volt Supply, trip point1
2.14
LVI, 3.3 volt supply, trip point2
Bias Current
—
—
2.7
—
V
I bias
110
130
μA
1. When V
2. When V
drops below V
drops below V
, an interrupt is generated.
, an interrupt is generated.
DD_CORE
DD_CORE
EI2.5
EI3.3
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
1
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
• 60MHz Device Clock
IDD_IO
RUN1_MAC
155mA
50mA
2.5mA
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with fetches from
Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
Wait3
Stop1
91mA
65μA
0μA
2.5mA
• All peripheral clocks are enabled
• ADC powered off
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
5.8mA
155μA
• PLL powered off
• External Clock is off
• All peripheral clocks are off
• ADC powered off
Stop2
5.1mA
0μA
145μA
• PLL powered off
1. No Output Switching
2. Includes Processor Core current supplied by internal voltage regulator
(VREFH - VREFLO) X 1
=
RES
212
m
56F8346 Technical Data, Rev. 15
142
Freescale Semiconductor
Preliminary
DC Electrical Characteristics
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
1
IDD_Core
IDD_ADC
IDD_OSC_PLL
Mode
Test Conditions
• 60MHz Device Clock
IDD_IO
RUN1_MAC
150mA
13μA
50mA
2.5mA
• All peripheral clocks are enabled
• All peripherals running
• Continuous MAC instructions with
fetches from Data RAM
• ADC powered on and clocked
• 60MHz Device Clock
• All peripheral clocks are enabled
• All peripherals running
• ADC powered off
Wait3
Stop1
Stop2
86mA
800μA
100μA
13μA
13μA
13μA
65μA
0μA
2.5mA
155μA
145μA
• 8MHz Device Clock
• All peripheral clocks are off
• ADC powered off
• PLL powered off
• External Clock is off
• All peripheral clocks are off
• ADC powered off
0μA
• PLL powered off
1. No Output Switching
Table 10-9. Regulator Parameters
Characteristic
Symbol
Min
Typical
Max
Unit
Unloaded Output Voltage
(0mA Load)
VRNL
2.25
—
2.75
V
Loaded Output Voltage
(200mA load)
VRL
VR
2.25
2.25
—
—
2.75
2.75
V
V
Line Regulation @ 250mA load
(VDD33 ranges from 3.0V to 3.6V)
Short Circuit Current
Iss
—
—
700
mA
(output shorted to ground)
Bias Current
I bias
Ipd
—
—
—
5.8
0
7
2
mA
μA
Power-down Current
Short-Circuit Tolerance
TRSC
—
30
minutes
(output shorted to ground)
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
143
Table 10-10. PLL Parameters
Characteristics
PLL Start-up time
Symbol
TPS
Min
0.3
0.1
120
—
Typical
0.5
Max
10
Unit
ms
ms
ps
Resonator Start-up time
Min-Max Period Variation
Peak-to-Peak Jitter
TRS
0.18
—
1
TPV
200
175
2
TPJ
—
ps
Bias Current
IBIAS
IPD
—
1.5
mA
μA
Quiescent Current, power-down mode
—
100
150
10.2.1 Temperature Sense
Note: Temperature Sensor is NOT available in the 56F8146 device.
Table 10-11 Temperature Sense Parametrics
Characteristics
Slope (Gain)1
Symbol
m
Min
—
Typical
7.762
26
Max
—
Unit
mV/°C
°C
Room Trim Temp. 1, 2
TRT
24
28
Hot Trim Temp. (Industrial)1,2
Hot Trim Temp. (Automotive)1,2
THT
122
147
—
125
128
153
—
°C
THT
150
°C
Output Voltage @
VDDA_ADC = 3.3V, TJ =0°C1
VTS0
1.370
V
Supply Voltage
VDDA_ADC
IDD-OFF
IDD-ON
3.0
—
3.3
—
—
0
3.6
10
V
Supply Current - OFF
Supply Current - ON
μA
μA
°C
—
250
6.7
Accuracy3,1 from -40°C to 150°C
Using VTS = mT + VTS0
TACC
-6.7
Resolution4, 5,1
RES
—
0.104
—
°C / bit
1. Includes the ADC conversion of the analog Temperature Sense voltage.
2. The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at
FMOPT0 and FMOPT1.
3. See Application Note, AN1980, for methods to increase accuracy.
4. Assuming a 12-bit range from 0V to 3.3V.
5. Typical resolution calculated using equation,
56F8346 Technical Data, Rev. 15
144
Freescale Semiconductor
Preliminary
AC Electrical Characteristics
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,
propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
between the 10% and 90% points, as shown in Figure 10-1.
Low
High
VIH
90%
50%
10%
Input Signal
Midpoint1
VIL
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 10-1 Input Signal Measurement References
Figure 10-2 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 10-2 Signal States
10.4 Flash Memory Characteristics
Table 10-12 Flash Timing Parameters
Characteristic
Symbol
Tprog
Terase
Tme
Min
20
Typ
—
Max
—
Unit
μs
Program time1
Erase time2
20
—
—
ms
ms
Mass erase time
100
—
—
1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual
for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro-
gram Flash module, as it contains two interleaved memories.
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
145
10.5 External Clock Operation Timing
1
Table 10-13 External Clock Operation Timing Requirements
Characteristic
Symbol
fosc
Min
0
Typ
—
Max
120
—
Unit
MHz
ns
Frequency of operation (external clock driver)2
Clock Pulse Width3
tPW
3.0
—
—
External clock input rise time4
trise
—
10
ns
External clock input fall time5
tfall
—
—
10
ns
1. Parameters listed are guaranteed by design.
2. See Figure 10-3 for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tfall
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-14 PLL Timing
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
8.4
Unit
MHz
MHz
External reference crystal frequency for the PLL1
PLL output frequency2 (fOUT
)
fop
160
—
260
PLL stabilization time3 -40° to +125°C
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
/2), please refer to the OCCS chapter in
OUT
the 56F8300 Peripheral User Manual.
56F8346 Technical Data, Rev. 15
146
Freescale Semiconductor
Preliminary
Crystal Oscillator Timing
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
10.7 Crystal Oscillator Timing
Table 10-15 Crystal Oscillator Parameters
Characteristic
Crystal Start-up time
Symbol
TCS
Min
4
Typ
5
Max
10
Unit
ms
ms
ohms
ps
Resonator Start-up time
TRS
0.1
—
0.18
—
1
Crystal ESR
RESR
TD
120
250
1.5
300
300
290
110
1
Crystal Peak-to-Peak Jitter
Crystal Min-Max Period Variation
Resonator Peak-to-Peak Jitter
Resonator Min-Max Period Variation
Bias Current, high-drive mode
Bias Current, low-drive mode
Quiescent Current, power-down mode
70
0.12
—
—
TPV
—
ns
TRJ
—
ps
TRP
—
—
ps
IBIASH
IBIASL
IPD
—
250
80
0
μA
—
μA
—
μA
10.8 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-4
shows sample timing and parameters that are detailed in Table 10-16.
The timing of each parameter consists of both a fixed delay portion and a clock related portion, as well as
user controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in this equation are defined as:
t
= Parameter delay time
D
P
= Fixed portion of the delay, due to on-chip path delays
= Period of the system clock, which determines the execution rate of the part
(i.e., when the device is operating at 60MHz, P = 16.67 ns)
M
W
= Fixed portion of a clock period inherent in the design; this number is adjusted to account
for possible derating of clock duty cycle
= Sum of the applicable wait state controls. The “Wait State Controls” column of
Table 10-16 shows the applicable controls for each parameter and the EMI chapter of the
56F8300 Peripheral User Manual details what each wait state field controls.
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler is set to 1), the EMI quadrature clock is generated using both edges of the EXTAL
÷
clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
147
and DCAEO are used to make this duty cycle adjustment where needed.
DCAOE and DCAEO are calculated as follows:
DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to
= 0.0 all other cases
÷
÷
1
1
DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to
= 0.0 all other cases
Example of DCAOE and DCAEO calculation
Assuming prescaler is set for
÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high:
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column of
Table 10-16 to make the appropriate selection.
A0-Axx,CS
tARDD
tRDA
tRDRD
tARDA
tRD
RD
tWR
tAWR
tWRWR
tWAC
tWRRD
tRDWR
WR
tRDD
tDWR
tDOH
tDOS
tAD
tDRD
Data In
Data Out
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 10-4 External Memory Interface Timing
Note:
When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
56F8346 Technical Data, Rev. 15
148
Freescale Semiconductor
Preliminary
External Memory Interface Timing
Table 10-16 External Memory Interface Timing
Wait States
Configuration
Wait States
Unit
Characteristic
Symbol
tAWR
D
M
Controls
WWS=0
WWS>0
WWS=0
WWS>0
WWS=0
WWS=0
WWS>0
WWS>0
-2.121
-1.805
-0.063
-0.253
-10.252
-2.868
-9.505
-2.552
0.50
0.75 + DCAOE
0.25 + DCAOE
0
Address Valid to WR Asserted
WWSS
WWS
ns
ns
WR Width Asserted to WR Deasserted
Data Out Valid to WR Asserted
tWR
0.25 + DCAEO
0.00
tDWR
WWSS
ns
0.50
0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
tDOH
-1.512
0.25 + DCAEO
WWSH
ns
ns
-2.047
-9.000
-3.888
0.25 + DCAOE
0.50
Valid Data Out Set-Up Time to WR
Deasserted
tDOS
WWS, WWSS
tWAC
tRDA
tARDD
tDRD
tRD
0.25 + DCAEO
WWSH
RWSH
ns
ns
ns
ns
ns
Valid Address after WR Deasserted
RD Deasserted to Address Invalid
Address Valid to RD Deasserted
Valid Input Data Hold after RD Deasserted
RD Assertion Width
-2.922
-1.645
0.00
0.00
1.00
RWSS, RWS
—
N/A1
1.00
0.257
-14.414
-19.299
-2.002
RWS
1.00
Address Valid to Input Data Valid
tAD
RWSS, RWS
RWSS
ns
ns
ns
1.25 + DCAOE
0.00
tARDA
tRDD
tWRRD
tRDRD
Address Valid to RD Asserted
-12.411
-17.297
-1.323
1.00
RD Asserted to Input Data Valid
RWSS, RWS
1.25 + DCAOE
0.25 + DCAEO
WWSH, RWSS
ns
ns
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
RWSS, RWSH
MDAR3, 4
-0.3572
0.00
WWS=0
WWS>0
WWS=0
-1.442
-0.695
-0.476
0.75 + DCAEO
1.00
WR Deasserted to WR Asserted
WWSS,
WWSH
tWRWR
ns
ns
0.50
RWSH,
WWSS,
MDAR3
RD Deasserted to WR Asserted
tRDWR
1. N/A, since device captures data before it deasserts RD
WWS>0
-0.160
0.75 + DCAOE
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
149
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
Characteristic
Symbol
Unit
See Figure
10-5
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration
tRA
tRDA
16T
63T
1.5T
18T
14T
18T
14T
22T
18T
22T
18T
1.5T
—
64T
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10-5
10-5
10-6
10-7
RESET Deassertion to First External Address Output3
Edge-sensitive Interrupt Request Width
tIRW
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
tIDM
tIDM - FAST
tIG
tIG - FAST
tIRI
tIRI - FAST
tIF
tIF - FAST
tIW
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
ns
ns
ns
ns
10-7
10-8
10-9
10-9
Delay from IRQA Assertion (exiting Wait) to External Data
Memory access4
Delay from IRQA Assertion to External Data Memory
Access (exiting Stop)
IRQA Width Assertion to Recover from Stop State5
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
21
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2 T.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
56F8346 Technical Data, Rev. 15
150
Freescale Semiconductor
Preliminary
Reset, Stop, Wait, Mode Select, and Interrupt Timing
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
Figure 10-5 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)
A0–A15
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 10-7 External Level-Sensitive Interrupt Timing
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
151
IRQA,
IRQB
tIRI
A0–A15
First Interrupt Vector
Instruction Fetch
Figure 10-8 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0–A15
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing
10.10 Serial Peripheral Interface (SPI) Timing
1
Table 10-18 SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
10-10, 10-11,
10-12, 10-13
50
50
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
10-13
10-13
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCK) high time
Master
Slave
10-10, 10-11,
10-12, 10-13
17.6
25
—
—
ns
ns
Clock (SCK) low time
Master
Slave
tCL
10-13
24.1
25
—
—
ns
ns
56F8346 Technical Data, Rev. 15
152
Freescale Semiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
1
Table 10-18 SPI Timing (Continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Data set-up time required for inputs
Master
Slave
tDS
10-10, 10-11,
10-12, 10-13
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
tDH
10-10, 10-11,
10-12, 10-13
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
tA
10-13
10-13
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
10-10, 10-11,
10-12, 10-13
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
10-10, 10-11,
0
0
—
—
ns
ns
10-12
Rise time
Master
Slave
10-10, 10-11,
10-12, 10-13
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
10-10, 10-11,
10-12, 10-13
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
153
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
tDV
MOSI
(Output)
Master MSB out
tF
Bits 14 –1
Master LSB out
tR
Figure 10-10 SPI Master Timing (CPHA = 0)
56F8346 Technical Data, Rev. 15
154
Freescale Semiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
tDH
MISO
(Input)
MSB in
Bits 14 –1
LSB in
tDI (ref)
tDI
tDV (ref)
tDV
Bits 14 – 1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-11 SPI Master Timing (CPHA = 1)
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
155
SS
(Input)
tC
tF
tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tF
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14 –1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14 –1
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
Slave LSB out
tDI
LSB in
tA
tF
MISO
(Output)
Slave MSB out
Bits 14 –1
tDV
tDS
tDH
MOSI
(Input)
MSB in
Bits 14 –1
Figure 10-13 SPI Slave Timing (CPHA = 1)
56F8346 Technical Data, Rev. 15
156
Freescale Semiconductor
Preliminary
Quad Timer Timing
10.11 Quad Timer Timing
1, 2
Table 10-19 Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min
Max
—
Unit
ns
See Figure
10-14
2T + 6
1T + 3
1T - 3
0.5T - 3
Timer input high / low period
Timer output period
PINHL
POUT
—
ns
10-14
—
ns
10-14
Timer output high / low period
POUTHL
—
ns
10-14
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PINHL
PINHL
PIN
Timer Outputs
POUTHL
POUTHL
POUT
Figure 10-14 Timer Timing
10.12 Quadrature Decoder Timing
1, 2
Table 10-20 Quadrature Decoder Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Quadrature input period
PIN
4T + 12
—
ns
ns
ns
10-15
10-15
10-15
Quadrature input high / low period
Quadrature phase period
PHL
PPH
2T + 6
1T + 3
—
—
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
157
PPH PPH PPH PPH
Phase A
(Input)
PHL
PIN
PHL
Phase B
(Input)
PHL
PIN
PHL
Figure 10-15 Quadrature Decoder Timing
10.13 Serial Communication Interface (SCI) Timing
1
Table 10-21 SCI Timing
Characteristic
Baud Rate2
Symbol
Min
—
Max
Unit
See Figure
—
BR
(fMAX/16)
Mbps
RXD3 Pulse Width
TXD4 Pulse Width
RXDPW
TXDPW
0.965/BR
0.965/BR
1.04/BR
1.04/BR
ns
ns
10-16
10-17
1. Parameters listed are guaranteed by design.
2. f is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8346 device and
MAX
40MHz for the 56F8146 device.
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 10-16 RXD Pulse Width
56F8346 Technical Data, Rev. 15
158
Freescale Semiconductor
Preliminary
Controller Area Network (CAN) Timing
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 10-17 TXD Pulse Width
10.14 Controller Area Network (CAN) Timing
Note: CAN is NOT available in the 56F8146 device.
1
Table 10-22 CAN Timing
Characteristic
Baud Rate
Bus Wake Up detection
Symbol
Min
—
5
Max
Unit
See Figure
—
BRCAN
1
Mbps
T WAKEUP
μs
10-18
—
1. Parameters listed are guaranteed by design
CAN_RX
CAN receive
data pin
T WAKEUP
(Input)
Figure 10-18 Bus Wake Up Detection
10.15 JTAG Timing
Table 10-23 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
10-19
TCK frequency of operation
using EOnCE1
fOP
DC
SYS_CLK/8
MHz
TCK frequency of operation not
using EOnCE1
fOP
DC
SYS_CLK/4
MHz
10-19
TCK clock pulse width
tPW
tDS
50
5
—
—
ns
ns
10-19
10-20
TMS, TDI data set-up time
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
159
Table 10-23 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
10-20
TMS, TDI data hold time
tDH
5
—
ns
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
tDV
tTS
—
—
30
30
—
ns
ns
ns
10-20
10-20
10-21
2T2
tTRST
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-19 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-20 Test Access Port Timing Diagram
56F8346 Technical Data, Rev. 15
160
Freescale Semiconductor
Preliminary
Analog-to-Digital Converter (ADC) Parameters
TRST
(Input)
tTRST
Figure 10-21 TRST Timing Diagram
10.16 Analog-to-Digital Converter (ADC) Parameters
Table 10-24 ADC Parameters
Characteristic
Input voltages
Symbol
VADIN
RES
Min
VREFL
12
Typ
—
Max
VREFH
12
Unit
V
Resolution
—
Bits
Integral Non-Linearity1
Differential Non-Linearity
LSB2
LSB2
INL
—
+/- 2.4
+/- 0.7
+/- 3.2
< +1
DNL
—
Monotonicity
GUARANTEED
—
ADC internal clock
fADIC
RAD
0.5
VREFL
5
5
MHz
V
Conversion range
—
6
VREFH
16
tAIC cycles3
ms
ADC channel power-up time
tADPU
ADC reference circuit power-up time4
Conversion time
tVREF
tADC
—
—
—
6
25
—
tAIC cycles3
tAIC cycles3
Sample time
tADS
—
1
—
Input capacitance
CADI
IADI
—
—
—
—
—
—
—
—
—
—
5
—
3
pF
Input injection current5, per pin
Input injection current, total
—
mA
mA
mA
mA
IADIT
—
20
VREFH current
IVREFH
IADCA
IADCB
IADCQ
EGAIN
VOFFSET
AECAL
1.2
3
ADC A current
25
—
ADC B current
25
0
—
mA
μA
Quiescent current
10
Uncalibrated Gain Error (ideal = 1)
Uncalibrated Offset Voltage
+/- .004
+/- .015
+/- 46
—
—
+/- 18
mV
Calibrated Absolute Error6
See Figure 10-22
LSBs
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
161
Table 10-24 ADC Parameters (Continued)
Characteristic
Calibration Factor 17
Symbol
CF1
Min
—
Typ
-0.003141
-17.6
Max
—
Unit
—
Calibration Factor 27
CF2
—
—
—
Crosstalk between channels
Common Mode Voltage
—
—
—
-60
—
—
dB
V
Vcommon
(VREFH - VREFLO) / 2
Signal-to-noise ratio
SNR
SINAD
THD
—
—
—
—
—
64.6
59.1
60.6
61.1
9.6
—
—
—
—
—
db
db
Signal-to-noise plus distortion ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
db
SFDR
ENOB
db
Effective Number Of Bits8
Bits
1. INL measured from V = .1V
to V = .9V
in REFH
in
REFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1μF ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration.
8. ENOB = (SINAD - 1.76)/6.02
56F8346 Technical Data, Rev. 15
162
Freescale Semiconductor
Preliminary
Equivalent Circuit for ADC Inputs
Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before
and After Calibration for VDC = 0.60V and 2.70V
in
Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset
error. The data was taken on 15 parts: three each from four processing corner lots as well as three from one
nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 45 data points
shown above), for two input DC voltages: 0.60V and 2.70V. The data indicates that for the given
population of parts, calibration significantly reduced (by as much as 39%) the collective variation (spread)
of the absolute error of the population. It also significantly reduced (by as much as 80%) the mean
(average) of the absolute error and thereby brought it significantly closer to the ideal value of zero.
Although not guaranteed, it is believed that calibration will produce results similar to those shown above
for any population of parts including those which represent processing and temperature extremes.
10.17 Equivalent Circuit for ADC Inputs
Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
163
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to V - V / 2, while the other charges to the analog input voltage. When the
REFH
REFH
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about V - V / 2. The switches switch
REFH
REFH
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
and the ADC clock frequency.
REF
Analog Input
3
4
S1
C1
C2
S/H
S3
(VREFH - VREFLO) / 2
S2
2
1
C1 = C2 = 1pF
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
3. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf
Figure 10-23 Equivalent Circuit for A/D Loading
56F8346 Technical Data, Rev. 15
164
Freescale Semiconductor
Preliminary
Power Consumption
10.18 Power Consumption
This section provides additional detail which can be used to optimize power consumption for a given
application.
Power consumption is given by the following equation:
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage current,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
2
C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
2
on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two
of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Table 10-25 IO Loading Coefficients at 10MHz
Intercept
Slope
PDU08DGZ_ME
PDU04DGZ_ME
1.3
0.11mW / pF
0.11mW / pF
1.15mW
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-25 provides coefficients for calculating power dissipated
in the IO cells as a function of capacitive load. In these cases:
TotalPower = Σ((Intercept +Slope*Cload)*frequency/10MHz)
where:
•
•
Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
165
•
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time. The one possible exception to this is if the chip is
using the external address and data buses at a rate approaching the maximum system rate. In this case,
power from these buses can be significant.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
2
device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V =
0.5 for the purposes of these rough calculations. For instance, if there is a total of 8 PWM outputs driving
10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.
56F8346 Technical Data, Rev. 15
166
Freescale Semiconductor
Preliminary
56F8346 Package and Pin-Out Information
Part 11 Packaging
11.1 56F8346 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8346. This device comes in a 144-pin
Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the LQFP; Figure 11-3
shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the 144-pin LQFP.
Orientation Mark
V
DD_IO
ANB4
ANB3
ANB2
ANB1
ANB0
V
2
PP
CLKO
TXD0
RXD0
109
Pin 1
PHASEA1
PHASEB1
INDEX1
HOME1
A1
V
V
SSA_ADC
DDA_ADC
V
V
V
V
V
REFH
REFP
REFMID
REFN
A2
A3
A4
A5
REFLO
Temp_Sense
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
CLKMODE
RESET
RSTO
V
V
V
4
CAP
V
DD_IO
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
DD_IO
3
CAP
V
SS
EXTAL
XTAL
D7
D8
D9
V
DDA_OSC_PLL
OCR_DIS
D6
D5
V
DD_IO
D10
GPIOB0
PWMB0
PWMB1
PWMB2
D4
D3
FAULTA2
FAULTA1
73
37
Figure 11-1 Top View, 56F8346 144-Pin LQFP Package
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
167
Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
2
VDD_IO
37
38
VSS
73
74
FAULTA1
FAULTA2
109
110
ANB5
ANB6
VPP2
VDD_IO
3
4
5
6
7
8
CLKO
TXD0
39
40
41
42
43
44
PWMB3
PWMB4
PWMB5
TXD1
75
76
77
78
79
80
D3
D4
111
112
113
114
115
116
ANB7
EXTBOOT
ISA0
RXD0
D5
PHASEA1
PHASEB1
INDEX1
D6
ISA1
RXD1
OCR_DIS
VDDA_OSC_PLL
ISA2
WR
TD0
9
HOME1
A1
45
46
47
RD
PS
DS
81
82
83
XTAL
117
118
119
TD1
TC0
10
11
EXTAL
A2
VCAP
3
VDD_IO
12
A3
48
GPIOD0
84
VDD_IO
120
TRST
13
14
15
A4
A5
49
50
51
GPIOD1
ISB0
85
86
87
RSTO
RESET
121
122
123
TCK
TMS
TDI
V
CAP4
VDD_IO
A6
VCAP
1
CLKMODE
16
17
52
53
ISB1
ISB2
88
89
ANA0
ANA1
124
125
TDO
V
PP1
18
19
20
A7
A8
A9
54
55
56
IRQA
IRQB
90
91
92
ANA2
ANA3
ANA4
126
127
128
CAN_TX
CAN_RX
FAULTB0
VCAP2
21
22
23
24
25
A10
A11
A12
A13
A14
57
58
59
60
61
FAULTB1
FAULTB2
D0
93
94
95
96
97
ANA5
ANA6
129
130
131
132
133
SS0
SCLK0
MISO0
MOSI0
D11
ANA7
D1
TEMP_SENSE
VREFLO
FAULTB3
26
A15
62
PWMA0
98
VREFN
134
D12
56F8346 Technical Data, Rev. 15
168
Freescale Semiconductor
Preliminary
56F8146 Package and Pin-Out Information
Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number (Continued)
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
27
28
29
30
31
VSS
63
64
65
66
67
VSS
99
VREFMID
VREFP
135
136
137
138
139
D13
D14
D7
PWMA1
PWMA2
VDD_IO
PWMA3
100
101
102
103
D8
VREFH
D15
D9
VDDA_ADC
VSSA_ADC
A0
VDD_IO
PHASEA0
32
33
D10
68
69
PWMA4
VSS
104
105
ANB0
ANB1
140
141
PHASEB0
INDEX0
GPIOB0
34
35
36
PWMB0
PWMB1
PWMB2
70
71
72
PWMA5
FAULTA0
D2
106
107
108
ANB2
ANB3
ANB4
142
143
144
HOME0
EMI_MODE
VSS
11.2 56F8146 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8146. This device comes in a 144-pin
Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the LQFP; Figure 11-3
shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the 144-pin LQFP.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
169
Orientation Mark
V
DD_IO
ANB4
ANB3
ANB2
ANB1
ANB0
V
2
PP
CLKO
TXD0
RXD0
SCLK1
MOSI1
MISO1
109
Pin 1
V
V
SSA_ADC
DDA_ADC
V
V
V
V
V
REFH
SS1
A1
A2
A3
A4
A5
REFP
REFMID
REFN
REFLO
NC
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
CLKMODE
V
4
CAP
V
DD_IO
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
RESET
RSTO
V
V
DD_IO
3
CAP
V
SS
EXTAL
XTAL
D7
D8
D9
V
DDA_OSC_PLL
OCR_DIS
D6
D5
V
DD_IO
D10
GPIOB0
PWMB0
PWMB1
PWMB2
D4
D3
NC
NC
73
37
Figure 11-2 Top View, 56F8146 144-Pin LQFP Package
Table 11-2 56F8146 144-Pin LQFP Package Identification by Pin Number
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
VDD_IO
37
VSS
73
NC
109
ANB5
56F8346 Technical Data, Rev. 15
170
Freescale Semiconductor
Preliminary
56F8146 Package and Pin-Out Information
Table 11-2 56F8146 144-Pin LQFP Package Identification by Pin Number (Continued)
Signal
Name
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
2
VPP2
38
VDD_IO
74
NC
110
ANB6
3
4
5
6
7
8
CLKO
TXD0
39
40
41
42
43
44
PWMB3
PWMB4
PWMB5
TXD1
75
76
77
78
79
80
D3
D4
111
112
113
114
115
116
ANB7
EXTBOOT
GPIOC8
GPIOC9
GPIOC10
GPIOE10
RXD0
SCLK1
MOSI1
MISO1
D5
D6
RXD1
OCR_DIS
VDDA_OSC_PLL
WR
9
SS1
A1
45
46
47
RD
PS
DS
81
82
83
XTAL
117
118
119
GPIOE11
TC0
10
11
EXTAL
A2
VCAP
3
VDD_IO
12
A3
48
GPIOD0
84
VDD_IO
120
TRST
13
14
15
A4
A5
49
50
51
GPIOD1
ISB0
85
86
87
RSTO
RESET
121
122
123
TCK
TMS
TDI
V
CAP4
VDD_IO
A6
VCAP
1
CLKMODE
16
17
52
53
ISB1
ISB2
88
89
ANA0
ANA1
124
125
TDO
V
PP1
18
19
20
A7
A8
A9
54
55
56
IRQA
IRQB
90
91
92
ANA2
ANA3
ANA4
126
127
128
NC
NC
FAULTB0
V
CAP2
21
22
23
24
25
A10
A11
A12
A13
A14
57
58
59
60
61
FAULTB1
FAULTB2
D0
93
94
95
96
97
ANA5
ANA6
ANA7
NC
129
130
131
132
133
SS0
SCLK0
MISO0
MOSI0
D11
D1
FAULTB3
VREFLO
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
171
Table 11-2 56F8146 144-Pin LQFP Package Identification by Pin Number (Continued)
Signal
Pin No.
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Name
A15
VSS
26
27
28
29
30
31
62
63
64
65
66
67
NC
VSS
NC
98
99
VREFN
VREFMID
VREFP
134
135
136
137
138
139
D12
D13
D7
100
101
102
103
D14
D8
NC
VREFH
D15
D9
VDD_IO
NC
VDDA_ADC
VSSA_ADC
A0
VDD_IO
PHASEA0
32
33
D10
68
69
NC
104
105
ANB0
ANB1
140
141
PHASEB0
INDEX0
GPIOB0
VSS
34
35
36
PWMB0
PWMB1
PWMB2
70
71
72
NC
NC
D2
106
107
108
ANB2
ANB3
ANB4
142
143
144
HOME0
EMI_MODE
VSS
56F8346 Technical Data, Rev. 15
172
Freescale Semiconductor
Preliminary
56F8146 Package and Pin-Out Information
0.20 H B-C D
0.20 A B-C D
4X
4X 36 TIPS
PIN 1
INDEX
144
109
1
108
4X e/2
A
A
E1
C
B
C
L
4
5
3
X
7
E
X=B, C or D
140X
e
E1/2
E/2
VIEW A
VIEW A
36
73
37
72
D
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS B, C AND D TO BE DETERMINED AT DATUM
H.
D1/2
D/2
4
5
D1
4. THE TOP PACKAGE BODY SIZE MAY BE SMALLER
THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM
OF 0.1 mm.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSIONS. THE MAXIMUM ALLOWABLE
PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE
MAXIMUMBODYSIZEDIMENSIONSINCLUDINGMOLD
MISMATCH.
6. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. PROTRUSIONS SHALL NOT CAUSE
THE LEAD WIDTH TO EXCEED 0.35. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD
SHALL BE 0.07 mm.
7
D
TOP VIEW
VIEW B
H
144X
A
0.1
A
8X θ2
SEATING
PLANE
7. DIMENSIONS D AND E TO BE DETERMINED AT THE
SEATING PLANE, DATUM A.
SIDE VIEW
A
MILLIMETERS
DIM MIN
MAX
1.60
0.15
1.45
0.27
0.23
0.20
0.16
PLATING
A
A1
A2
b
b1
c
c1
D
D1
e
---
c
0.05
1.35
0.17
0.17
0.09
0.09
22.00 BSC
20.00 BSC
0.50 BSC
c1
b1
A2
0.05
R2
R1
θ 1
BASE
METAL
6
E
E1
L
L1
L2
R1
R2
S
22.00 BSC
20.00 BSC
0.45
1.00 REF
0.50 REF
0.13
0.13
0.25 REF
b
0.25
GAGE PLANE
M
0.08
A
B-C
D
0.75
SECTION A-A
0.20
---
(ROTATED 90
)
°
L2
144 PLACES
A1
L
θ
θ1
θ2
0
0
7
---
°
°
θ
S
°
12 REF
°
L1
VIEW B
Figure 11-3 144-pin LQFP Mechanical Information
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
173
Please see www.freescale.com for the most current case outline.
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
θJΑ x P )
D
J
A
where:
o
T
R
= Ambient temperature for the package ( C)
A
o
= Junction-to-ambient thermal resistance ( C/W)
θJΑ
P
= Power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single-layer board and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is closer to the application
depends on the power dissipated by other components on the board. The value obtained on a single-layer
board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the
internal planes is usually appropriate if the board has low-power dissipation and the components are well
separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
R
R
θJΑ = θJC + θCΑ
where:
R
R
R
= Package junction-to-ambient thermal resistance °C/W
= Package junction-to-case thermal resistance °C/W
= Package case-to-ambient thermal resistance °C/W
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For instance, the user can change the size of the heat
θCA
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ x P )
J
T
JT
D
56F8346 Technical Data, Rev. 15
174
Freescale Semiconductor
Preliminary
Electrical Design Considerations
where:
o
T
Ψ
= Thermocouple temperature on top of package ( C)
= Thermal characterization parameter ( C)/W
T
o
JT
P
= Power dissipation in package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct device operation:
•
Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the
board ground to each VSS (GND) pin
•
The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
performance tolerances.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
175
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead
•
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS
Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor
•
•
Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
•
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins
Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. Designs that do not require debugging functionality, such as
consumer products, should tie these pins together.
•
Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an
interface to this port to allow in-circuit Flash programming
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8346/56F8146. This chip
contains two internal power regulators. One of them is powered from the V
pin and cannot
DDA_OSC_PLL
be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator
is powered from the V pins and provides power to all of the internal digital logic of the core, all
DD_IO
peripherals and the internal memories. This regulator can be turned off, if an external V
voltage
DD_CORE
is externally applied to the V
pins.
CAP
In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is
enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.
Notes:
•
•
Flash, RAM and internal logic are powered from the core regulator output
VPP1 and VPP2 are not connected in the customer system
•
All circuitry, analog and digital, shares a common VSS bus
56F8346 Technical Data, Rev. 15
176
Freescale Semiconductor
Preliminary
Power Distribution and I/O Ring Implementation
V
DDA_OSC_PLL
V
V
DDA_ADC
DD
V
V
V
V
V
REFH
V
CAP
REG
REFP
REG
I/O
ADC
REFMID
CORE
REFN
OSC
REFLO
V
V
SS
SSA_ADC
Figure 12-1 Power Management
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 13-1 Ordering Information
Ambient
Temperature
Range
Supply
Voltage
Pin
Count
Frequency
(MHz)
Part
Package Type
Order Number
MC56F8346
MC56F8346
MC56F8146
3.0–3.6V
3.0–3.6V
3.0–3.6V
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
144
144
144
60
60
40
-40° to + 105° C
-40° to + 125° C
-40° to + 105° C
MC56F8346VFV60
MC56F8346MFV60
MC56F8146VFV
MC56F8346
MC56F8346
MC56F8146
3.0–3.6V
3.0–3.6V
3.0–3.6V
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
Low-Profile Quad Flat Pack (LQFP)
144
144
144
60
60
40
-40° to + 105° C
-40° to + 125° C
-40° to + 105° C
MC56F8346VFVE*
MC56F8346MFVE*
MC56F8146VFVE*
*This package is RoHS compliant.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
Preliminary
177
How to Reach Us:
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RoHS-compliant and/or Pb-free versions of Freescale products have the
functionality and electrical characteristics of their non-RoHS-compliant
and/or non-Pb-free counterparts. For further information, see
http://www.freescale.com or contact your Freescale sales representative.
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Information in this document is provided solely to enable system and
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no express or implied copyright licenses granted hereunder to design or
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notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
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Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
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not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
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support.asia@freescale.com
For Literature Requests Only:
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LDCForFreescaleSemiconductor@hibbertgroup.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,
Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005, 2006. All rights reserved.
MC56F8346
Rev. 15
01/2007
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