935321128557_技术文档

Document Number: MPC8347EAEC

Rev. 12, 09/2011

Freescale Semiconductor

Technical Data

MPC8347EA PowerQUICC II Pro

Integrated Host Processor Hardware

Specifications

Contents

The MPC8347EA PowerQUICC II Pro is a next generation

PowerQUICC II integrated host processor. The

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

MPC8347EA contains a processor core built on Power

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Architecture® technology with system logic for networking,

storage, and general-purpose embedded applications. For

functional characteristics of the processor, refer to the

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 16

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MPC8349EA PowerQUICC II Pro Integrated Host

Processor Family Reference Manual.

8. Ethernet: Three-Speed Ethernet, MII Management . 23

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

To locate published errata or updates for this document, refer

to the MPC8347EA product summary page on our website,

as listed on the back cover of this document, or contact your

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

local Freescale sales office.

15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54

19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

21. System Design Information . . . . . . . . . . . . . . . . . . . 91

22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 94

23. Document Revision History . . . . . . . . . . . . . . . . . . . 96

Overview

NOTE

The information in this document is accurate for revision 3.x silicon and

later (in other words, for orderable part numbers ending in A or B). For

information on revision 1.1 silicon and earlier versions, see the MPC8347E

PowerQUICC II Pro Integrated Host Processor Hardware Specifications.

See Section 22.1, “Part Numbers Fully Addressed by This Document,” for

silicon revision level determination.

1 Overview

This section provides a high-level overview of the device features. Figure 1 shows the major functional

units within the MPC8347EA.

e300 Core

DUART

Dual I²C

DDR

Timers

GPIO

Interrupt

Controller

32KB

I-Cache

SDRAM

Security

Local Bus

D-Cache

Controller

High-Speed

USB 2.0

10/100/1000

Ethernet

10/100/1000

Ethernet

SEQ

PCI

DMA

Dual

Role

Host

Figure 1. MPC8347EA Block Diagram

Major features of the device are as follows:

• Embedded PowerPC e300 processor core; operates at up to 667 MHz

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the other Freescale processor families that implement Power

Architecture technology

•

Double data rate, DDR1/DDR2 SDRAM memory controller

— Programmable timing supporting DDR1 and DDR2 SDRAM

— 32- or 64-bit data interface, up to 400 MHz data rate for TBGA, 266 MHz for PBGA

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Freescale Semiconductor

Overview

— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable

— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports

— Full error checking and correction (ECC) support

— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep-mode support for SDRAM self refresh

— Auto refresh

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2

Dual three-speed (10/100/1000) Ethernet controllers (TSECs)

•

— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™,

802.3ac™ standards

— Ethernet physical interfaces:

– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex

– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex

— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100

programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module

— MII management interface for control and status

— Programmable CRC generation and checking

PCI interface

•

— Designed to comply with PCI Specification Revision 2.3

— Data bus width:

– 32-bit data PCI interface operating at up to 66 MHz

— PCI 3.3-V compatible

— PCI host bridge capabilities

— PCI agent mode on PCI interface

— PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration supporting five masters on PCI

— Accesses to all PCI address spaces

— Parity supported

— Selectable hardware-enforced coherency

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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3

Overview

— Address translation units for address mapping between host and peripheral

— Dual address cycle for target

— Internal configuration registers accessible from PCI

•

Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four

crypto-channels, a controller, and a set of crypto execution units (EUs):

— Public key execution unit (PKEU) :

– RSA and Diffie-Hellman algorithms

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard (DES) execution unit (DEU)

– DES and 3DES algorithms

– Two key (K1, K2) or three key (K1, K2, K3) for 3DES

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric-key cipher

– Key lengths of 128, 192, and 256 bits

– ECB, CBC, CCM, and counter (CTR) modes

— XOR parity generation accelerator for RAID applications

— ARC four execution unit (AFEU)

– Stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units through an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

Universal serial bus (USB) dual role controller

— USB on-the-go mode with both device and host functionality

— Complies with USB specification Rev. 2.0

— Can operate as a stand-alone USB device

– One upstream facing port

•

– Six programmable USB endpoints

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Freescale Semiconductor

Overview

— Can operate as a stand-alone USB host controller

– USB root hub with one downstream-facing port

– Enhanced host controller interface (EHCI) compatible

– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

Universal serial bus (USB) multi-port host controller

•

— Can operate as a stand-alone USB host controller

– USB root hub with one or two downstream-facing ports

– Enhanced host controller interface (EHCI) compatible

– Complies with USB Specification Rev. 2.0

— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— Direct connection to a high-speed device without an external hub

— External PHY with serial and low-pin count (ULPI) interfaces

Local bus controller (LBC)

•

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Eight chip selects for eight external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller

— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

Programmable interrupt controller (PIC)

•

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Redirects interrupts to external INTA pin in core disable mode.

— Unique vector number for each interrupt source

2

•

Dual industry-standard I C interfaces

— Two-wire interface

— Multiple master support

2

— Master or slave I C mode support

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Electrical Characteristics

— On-chip digital filtering rejects spikes on the bus

2

— System initialization data optionally loaded from I C-1 EPROM by boot sequencer embedded

hardware

•

DMA controller

— Four independent virtual channels

— Concurrent execution across multiple channels with programmable bandwidth control

— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],

DMA_DACK[0:3], DMA_DDONE[0:3]

— All channels accessible to local core and remote PCI masters

— Misaligned transfer capability

— Data chaining and direct mode

— Interrupt on completed segment and chain

DUART

•

— Two 4-wire interfaces (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

Serial peripheral interface (SPI) for master or slave

General-purpose parallel I/O (GPIO)

•

— 52 parallel I/O pins multiplexed on various chip interfaces

System timers

•

— Periodic interrupt timer

— Real-time clock

— Software watchdog timer

— Eight general-purpose timers

•

Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan

Integrated PCI bus and SDRAM clock generation

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8347EA. The device is currently targeted to these specifications. Some of these specifications are

independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer

design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Freescale Semiconductor

Electrical Characteristics

2.1.1

Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

1

Table 1. Absolute Maximum Ratings

Parameter

Symbol

Max Value

Unit

Notes

Core supply voltage

PLL supply voltage

V_DD

–0.3 to 1.32 (1.36 max

for 667-MHz core

frequency)

V

—

AV_DD

GV_DD

–0.3 to 1.32 (1.36 max

for 667-MHz core

frequency)

V

—

DDR and DDR2 DRAM I/O voltage

–0.3 to 2.75

–0.3 to 1.98

Three-speed Ethernet I/O, MII management voltage

LV_DD

–0.3 to 3.63

V

—

PCI, local bus, DUART, system control and power management, I²C,

and JTAG I/O voltage

OV_DD

Input voltage

DDR DRAM signals

MV_IN

MV_REF

LV_IN

–0.3 to (GV_DD+ 0.3)

–0.3 to (LV_DD+ 0.3)

–0.3 to (OV_DD+ 0.3)

V

2, 5

4, 5

3, 5

DDR DRAM reference

Three-speed Ethernet signals

Local bus, DUART, CLKIN, system control and

power management, I²C, and JTAG signals

OV_IN

PCI

OV_IN

T_STG

–0.3 to (OV_DD+ 0.3)

–55 to 150

V

6

Storage temperature range

°C

—

Notes:

1

Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2

3

4

5

Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

Caution: LV_INmust not exceed LV_DDby more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

(M,L,O)V_INand MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

shown in Figure 3.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

7

Electrical Characteristics

2.1.2

Power Supply Voltage Specification

Table 2 provides the recommended operating conditions for the MPC8347EA. Note that the values in

Table 2 are the recommended and tested operating conditions. Proper device operation outside these

conditions is not guaranteed.

Table 2. Recommended Operating Conditions

Recommended

Parameter

Symbol

Unit

Notes

Value

Core supply voltage for 667-MHz core frequency

Core supply voltage

V_DD

1.3 V 60 mV

1.2 V 60 mV

1.3 V 60 mV

1.2 V 60 mV

V

1

PLL supply voltage for 667-MHz core frequency

PLL supply voltage

AV_DD

GV_DD

1

DDR and DDR2 DRAM I/O voltage

2.5 V 125 mV

1.8 V 90 mV

—

Three-speed Ethernet I/O supply voltage

LV_DD1

LV_DD2

OV_DD

3.3 V 330 mV

2.5 V 125 mV

V

—

3.3 V 330 mV

2.5 V 125 mV

PCI, local bus, DUART, system control and power

management, I²C, and JTAG I/O voltage

3.3 V 330 mV

Note:

1

GV_DD, LV_DD, OV_DD, AV_DD, and V_DDmust track each other and must vary in the same direction—either in the positive or

negative direction.

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8347EA.

G/L/OV_DD+ 20%

G/L/OV_DD+ 5%

G/L/OV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

1

of t_interface

Note:

1. t_interfacerefers to the clock period associated with the bus clock interface.

Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV

DD

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

8

Electrical Characteristics

Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8347EA for the

3.3-V signals, respectively.

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

0 V

4 ns

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 3. Output Drive Capability

Output Impedance

Supply

Voltage

Driver Type

(Ω)

Local bus interface utilities signals

PCI signals (not including PCI output clocks)

PCI output clocks (including PCI_SYNC_OUT)

DDR signal

40

25

40

18

OV_DD= 3.3 V

GV_DD= 2.5 V

GV_DD= 1.8 V

DDR2 signal

18

36 (half-strength mode)

TSEC/10/100 signals

DUART, system control, I²C, JTAG, USB

40

LV_DD= 2.5/3.3 V

OV_DD= 3.3 V

GPIO signals

OV_DD= 3.3 V,

LV_DD= 2.5/3.3 V

2.2

Power Sequencing

This section details the power sequencing considerations for the MPC8347EA.

2.2.1

Power-Up Sequencing

MPC8347EAdoes not require the core supply voltage (V and AV ) and I/O supply voltages (GV ,

DD

LV , and OV ) to be applied in any particular order. During the power ramp up, before the power

DD

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

9

Power Characteristics

supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of

time that all input and output pins will actively be driven and cause contention and excessive current from

3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the

core voltage (V ) before the I/O voltage (GV , LV , and OV ) and assert PORESET before the

DD

power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply

must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.

Voltage

I/O Voltage (GV_DD, LV_DD, OV_DD

)

Core Voltage (V_DD, AV_DD

)

0.7 V

90%

Time

Figure 4. Power Sequencing Example

I/O voltage supplies (GV , LV , and OV ) do not have any ordering requirements with respect to one

DD

another.

3 Power Characteristics

The estimated typical power dissipation for the MPC8347EA device is shown in Table 4.

1

Table 4. MPC8347EA Power Dissipation

Core

Frequency

(MHz)

CSB

Frequency

(MHz)

,

Typical at T_J= 65

Typical^{2 3}

Maximum⁴

Unit

PBGA

266

400

266

133

266

133

200

100

1.3

1.1

1.5

1.4

1.5

1.3

1.6

1.4

1.9

1.7

1.8

1.7

1.8

1.6

2.1

1.9

2.0

1.9

W

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

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Power Characteristics

1

Table 4. MPC8347EA Power Dissipation (continued)

Core

Frequency

(MHz)

CSB

Frequency

(MHz)

,

Typical at T_J= 65

Typical^{2 3}

Maximum⁴

Unit

TBGA

333

166

266

133

300

150

333

166

266

133

333

2.0

1.8

2.1

1.9

2.3

2.1

2.4

2.2

2.4

2.2

3.5

3.0

2.8

3.0

2.9

3.2

3.0

3.3

3.1

3.3

3.1

4.6

3.2

2.9

3.3

3.1

3.5

3.2

3.6

3.4

3.6

3.4

5

W

400

450

500

533

667^5,6

1

2

The values do not include I/O supply power (OV_DD, LV_DD, GV_DD) or AV_DD. For I/O power values, see Table 5.

Typical power is based on a voltage of V_DD= 1.2 V, a junction temperature of T_J= 105°C, and a Dhrystone benchmark

application.

3

4

5

6

Thermal solutions may need to design to a value higher than typical power based on the end application, T_Atarget, and I/O

power.

Maximum power is based on a voltage of V_DD= 1.2 V, worst case process, a junction temperature of T_J= 105°C, and an

artificial smoke test.

Typical power is based on a voltage of V_DD= 1.3 V, a junction temperature of T_J= 105°C, and a Dhrystone benchmark

application.

Maximum power is based on a voltage of V_DD= 1.3 V, worst case process, a junction temperature of T_J= 105°C, and an

artificial smoke test.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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11

Power Characteristics

Table 5 shows the estimated typical I/O power dissipation for MPC8347EA.

Table 5. MPC8347EA Typical I/O Power Dissipation

DDR2

GV_DD

(1.8 V)

DDR1

GV_DD

(2.5 V)

OV_DD

LV_DD

Interface

Parameter

Unit

Comments

(3.3 V) (3.3 V) (2.5 V)

DDR I/O

65% utilization

2.5 V

Rs = 20 Ω

Rt = 50 Ω

2 pair of clocks

200 MHz, 32 bits

200 MHz, 64 bits

266 MHz, 32 bits

266 MHz, 64 bits

300 MHz,¹32 bits

300 MHz,¹64 bits

333 MHz,¹32 bits

333 MHz,¹64 bits

400 MHz,¹32 bits

400 MHz,¹64 bits

33 MHz, 32 bits

66 MHz, 32 bits

167 MHz, 32 bits

133 MHz, 32 bits

83 MHz, 32 bits

66 MHz, 32 bits

50 MHz, 32 bits

MII

0.31

0.42

0.35

0.47

0.37

0.50

0.39

0.53

0.44

0.59

—

0.42

0.55

0.5

0.66

0.54

0.7

0.58

0.76

—

0.04

—

W

—

PCI I/O

load = 30 pF

—

0.04

0.07

0.34

0.27

0.17

0.14

0.11

—

W

—

Local bus I/O

load = 25 pF

—

TSEC I/O

load = 25 pF

—

0.01

0.06

—

Multiply by number of

interfaces used.

GMII or TBI

—

RGMII or RTBI

12 MHz

—

USB

—

0.01

0.2

0.01

—

Multiply by 2 if using

2 ports.

480 MHz

—

Other I/O

—

1

TBGA package only.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

12

Clock Input Timing

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the device.

4.1

DC Electrical Characteristics

Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347EA.

Table 6. CLKIN DC Timing Specifications

Parameter

Input high voltage

Condition

Symbol

Min

Max

Unit

—

V_IH

V_IL

I_IN

2.7

–0.3

—

OV_DD+ 0.3

V

Input low voltage

0.4

10

CLKIN input current

PCI_SYNC_IN input current

0 V ≤ V_IN≤ OV_DD

μA

0 V ≤ V_IN≤ 0.5 V or

I_IN

—

OV_DD– 0.5 V ≤ V_IN≤ OV_DD

PCI_SYNC_IN input current

0.5 V ≤V_IN≤ OV_DD– 0.5 V

I_IN

—

50

μA

4.2

AC Electrical Characteristics

The primary clock source for the MPC8347EA can be one of two inputs, CLKIN or PCI_CLK, depending

on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the device.

Table 7. CLKIN AC Timing Specifications

Parameter/Condition

CLKIN/PCI_CLK frequency

Symbol

Min

Typical

Max

Unit

Notes

f_CLKIN

t_CLKIN

—

15

0.6

40

—

66

—

MHz

ns

1, 6

—

2

CLKIN/PCI_CLK cycle time

CLKIN/PCI_CLK rise and fall time

CLKIN/PCI_CLK duty cycle

CLKIN/PCI_CLK jitter

Notes:

t_KH, t_KL

1.0

—

2.3

60

ns

t_{KHK CLKIN}

/t

%

3

—

150

ps

4, 5

1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless

of input frequency.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

13

RESET Initialization

4.3

TSEC Gigabit Reference Clock Timing

Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.

Table 8. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LV_DD= 2.5 0.125 mV/ 3.3 V 165 mV

Parameter

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time

EC_GTX_CLK125 rise and fall time

t_G125

—

125

8

—

MHz

ns

—

1

t

_G125R/t_G125F

—

ns

LV_DD= 2.5 V

LV_DD= 3.3 V

0.75

1.0

EC_GTX_CLK125 duty cycle

t_{G125H G125}

/t

—

%

2

GMII, TBI

45

47

55

53

1000Base-T for RGMII, RTBI

EC_GTX_CLK125 jitter

Notes:

—

150

ps

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LV_DD= 2.5 V and from 0.6 and 2.7 V for

LV_DD= 3.3 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125

duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 8.2.4, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T

reference clock.

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the MPC8347EA.

5.1

RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8347EA.

1

Table 9. RESET Pins DC Electrical Characteristics

Parameter

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

—

2.0

–0.3

—

OV_DD+ 0.3

V

0.8

5

I_IN

—

μA

V

Output high voltage²

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

0.5

V

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

14

RESET Initialization

1

Table 9. RESET Pins DC Electrical Characteristics (continued)

Parameter

Symbol

Condition

Min

Max

0.4

Unit

Output low voltage

V

I_OL= 3.2 mA

—

V

OL

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus V_OHis not relevant for those pins.

5.2

RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications of the MPC8347EA.

Table 10. RESET Initialization Timing Specifications

Parameter

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

32

—

t_{PCI_SYNC_IN}

t_CLKIN

1

2

Required assertion time of PORESET with stable clock applied to CLKIN when the

MPC8347EA is in PCI host mode

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN

when the MPC8347EA is in PCI agent mode

32

—

t_{PCI_SYNC_IN}

1

HRESET/SRESET assertion (output)

512

16

4

—

t_{PCI_SYNC_IN}

t_CLKIN

1

2

HRESET negation to SRESET negation (output)

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is

in PCI host mode

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is

in PCI agent mode

4

—

t_{PCI_SYNC_IN}

1

Input hold time for POR configuration signals with respect to negation of HRESET

0

—

4

ns

—

3

Time for the MPC8347EA to turn off POR configuration signals with respect to the

assertion of HRESET

—

Time for the MPC8347EA to turn on POR configuration signals with respect to the

negation of HRESET

1

—

t_{PCI_SYNC_IN}1, 3

Notes:

1. t_{PCI_SYNC_IN}is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied

to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

2. t_CLKINis the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

15

DDR and DDR2 SDRAM

Table 11 lists the PLL and DLL lock times.

Table 11. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

DLL lock times

Notes:

—

100

μs

—

7680

122,880

csb_clk cycles

1, 2

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio

results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8347EA. Note that DDR SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.

DD

The AC electrical specifications are the same for DDR and DRR2 SDRAM.

NOTE

The information in this document is accurate for revision 3.0 silicon and

later. For information on revision 1.1 silicon and earlier versions see the

MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware

Specifications. See Section 22.1, “Part Numbers Fully Addressed by This

Document,” for silicon revision level determination.

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8347EA when GV (typ) = 1.8 V.

DD

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Notes

GV_DD

MV_REF

V_TT

1.71

0.49 × GV_DD

MV_REF– 0.04

MV_REF+ 0.125

–0.3

1.89

0.51 × GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.125

9.9

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.420 V)

I_OZ

–9.9

μA

mA

I_OH

–13.4

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

16

DDR and DDR2 SDRAM

Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V (continued)

DD

Output low current (V_OUT= 0.280 V)

I_OL

13.4

—

mA

—

Notes:

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to equal 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak noise

on MV_REFcannot exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal

MV_REF. This rail should track variations in the DC level of MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

.

Table 13 provides the DDR2 capacitance when GV_DD(typ) = 1.8 V.

Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V 0.090 V, f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when

GV (typ) = 2.5 V.

DD

Table 14. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V

DD

Parameter/Condition

I/O supply voltage

Symbol

Min

Max

Unit

Notes

GV_DD

MV_REF

V_TT

2.375

0.49 × GV_DD

MV_REF– 0.04

MV_REF+ 0.18

–0.3

2.625

0.51 × GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.18

–9.9

V

1

2

I/O reference voltage

I/O termination voltage

Input high voltage

V

3

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.95 V)

Output low current (V_OUT= 0.35 V)

Notes:

I_OZ

–9.9

μA

mA

I_OH

–15.2

—

I_OL

15.2

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

17

DDR and DDR2 SDRAM

Table 15 provides the DDR capacitance when GV_DD(typ) = 2.5 V.

Table 15. DDR SDRAM Capacitance for GV (typ) = 2.5 V

DD

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 2.5 V 0.125 V, f = 1 MHz, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

Table 16 provides the current draw characteristics for MV

.

REF

Table 16. Current Draw Characteristics for MV

REF

Parameter/Condition

Symbol

Min

Max

Unit

Note

Current draw for MV_REF

Note:

1. The voltage regulator for MV_REFmust supply up to 500 μA current.

I_MVREF

—

500

μA

1

6.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

6.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GV (typ) = 1.8 V.

DD

Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GV_DDof 1.8 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.25

—

V

—

V_IH

MV_REF+ 0.25

Table 18 provides the input AC timing specifications for the DDR SDRAM when GV (typ) = 2.5 V.

DD

Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions with GV_DDof 2.5 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.31

—

V

—

V_IH

MV_REF+ 0.31

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

18

DDR and DDR2 SDRAM

Table 19 provides the input AC timing specifications for the DDR SDRAM interface.

Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GV_DDof (1.8 or 2.5 V) 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ/MECC/MDM

t_CISKEW

ps

1, 2

3

400 MHz

–600

–750

600

750

333 MHz

266 MHz

200 MHz

—

Notes:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW. This can be

determined by the equation: t_DISKEW

value of t_CISKEW

=

(T/4 – abs (t_CISKEW)); where T is the clock period and abs (t_CISKEW) is the absolute

.

3. This specification applies only to the DDR interface.

Figure 5 illustrates the DDR input timing diagram showing the t

timing parameter.

DISKEW

MCK[n]

t_MCK

MDQS[n]

MDQ[x]

D0

D1

t_DISKEW

Figure 5. DDR Input Timing Diagram

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

19

DDR and DDR2 SDRAM

6.2.2

DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20 shows the DDR and DDR2 output AC timing specifications.

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GV_DDof (1.8 or 2.5 V) 5%.

Parameter

Symbol ¹

Min

Max

Unit

Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (PBGA

package)

t_MCK

5

—

ns

2

MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (TBGA

package)

t_MCK

7.5

—

ns

2

3

ADDR/CMD/MODT output setup with respect to MCK

t_DDKHAS

400 MHz

1.95

2.40

3.15

4.20

—

333 MHz

266 MHz

200 MHz

ADDR/CMD/MODT output hold with respect to MCK

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3

400 MHz

1.95

2.40

3.15

4.20

—

333 MHz

266 MHz

200 MHz

MCS(n) output setup with respect to MCK

400 MHz

1.95

2.40

3.15

4.20

—

333 MHz

266 MHz

200 MHz

MCS(n) output hold with respect to MCK

400 MHz

1.95

2.40

3.15

4.20

–0.6

—

333 MHz

266 MHz

—

200 MHz

—

MCK to MDQS Skew

0.6

ns

ps

4

5

MDQ/MECC/MDM output setup with respect to

MDQS

t_DDKHDS,

t_DDKLDS

400 MHz

700

775

—

333 MHz

266 MHz

1100

1200

200 MHz

MDQ/MECC/MDM output hold with respect to MDQS

t_DDKHDX,

t_DDKLDX

ps

5

400 MHz

333 MHz

700

900

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

20

DDR and DDR2 SDRAM

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions with GV_DDof (1.8 or 2.5 V) 5%.

Parameter

Symbol ¹

Min

Max

Unit

Notes

266 MHz

1100

1200

—

200 MHz

MDQS preamble start

MDQS epilogue end

Notes:

t_DDKHMP

t_DDKHME

–0.5 × t_MCK– 0.6 –0.5 × t_MCK+ 0.6

–0.6 0.6

ns

6

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing (DD) from

the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, t_DDKHAS

symbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs (A) are

set up (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes

low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by

1/2 applied cycle.

4. t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing (DD) from the

rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through control of the

DQSS override bits in the TIMING_CFG_2 register and is typically set to the same delay as the clock adjust in the CLK_CNTL

register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value.

See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications

enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t_DDKHMPfollows the

symbol conventions described in note 1.

Figure 6 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t

).

DDKHMH

MCK[n]

t_MCK

t_{DDKHMHmax) = 0.6 ns}

MDQS

t_{DDKHMH(min) = –0.6 ns}

MDQS

Figure 6. Timing Diagram for t

DDKHMH

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

21

DUART

Figure 7 shows the DDR SDRAM output timing diagram.

MCK[n]

t_MCK

t_DDKHAS,t_DDKHCS

t_DDKHAX,t_DDKHCX

ADDR/CMD/MODT

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 7. DDR SDRAM Output Timing Diagram

Figure 8 provides the AC test load for the DDR bus.

GV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 8. DDR AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the

MPC8347EA.

7.1

DUART DC Electrical Characteristics

Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8347EA.

Table 21. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

V_IH

V_IL

I_IN

2

OV_DD+ 0.3

V

–0.3

—

0.8

5

Input current (0.8 V ≤ V_IN≤ 2 V)

μA

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

22

Ethernet: Three-Speed Ethernet, MII Management

Table 21. DUART DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

V_OH

V_OL

OV_DD– 0.2

—

V

0.2

7.2

DUART AC Electrical Specifications

Table 22 provides the AC timing parameters for the DUART interface of the MPC8347EA.

Table 22. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

Maximum baud rate

Oversample rate

Notes:

256

> 1,000,000

16

baud

—

1

2

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16^thsample.

8 Ethernet: Three-Speed Ethernet, MII Management

This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and

MII management.

8.1

Three-Speed Ethernet Controller

(TSEC)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics

The electrical characteristics specified here apply to gigabit media independent interface (GMII), the

media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent

interface (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output

(MDIO) and management data clock (MDC). The MII, GMII, and TBI interfaces are defined for 3.3 V,

and the RGMII and RTBI interfaces are defined for 2.5 V. The RGMII and RTBI interfaces follow the

Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification,

Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3,

“Ethernet Management Interface Electrical Characteristics.”

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

23

Ethernet: Three-Speed Ethernet, MII Management

8.1.1

TSEC DC Electrical Characteristics

GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes

specified in Table 23 and Table 24. The RGMII and RTBI signals in Table 24 are based on a 2.5-V CMOS

interface voltage as defined by JEDEC EIA/JESD8-5.

Table 23. GMII/TBI and MII DC Electrical Characteristics

Parameter

Symbol

Conditions

Min

Max

Unit

2

Supply voltage 3.3 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Notes:

LV_DD

—

2.97

2.40

GND

2.0

3.63

LV_DD+ 0.3

0.50

V

V_OH

V_OL

V_IH

V_IL

I_IH

I_OH= –4.0 mA

LV_DD= Min

I_OL= 4.0 mA

LV_DD= Min

V

—

LV_DD+ 0.3

0.90

V

–0.3

—

V

V_IN¹= LV_DD

V_IN¹= GND

40

μA

I_IL

–600

—

1. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OV_DDsupply.

Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics

Parameters

Supply voltage 2.5 V

Symbol

Conditions

Min

Max

Unit

LV_DD

V_OH

V_OL

V_IH

V_IL

—

2.37

2.00

2.63

LV_DD+ 0.3

0.40

V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Note:

I_OH= –1.0 mA

LV_DD= Min

I_OL= 1.0 mA

GND – 0.3

1.7

V

—

LV_DD+ 0.3

0.70

V

–0.3

V

I_IH

V_IN¹= LV_DD

V_IN¹= GND

—

10

μA

I_IL

–15

—

1. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

8.2

GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.

8.2.1

GMII Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

24

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.2.1.1

GMII Transmit AC Timing Specifications

Table 25 provides the GMII transmit AC timing specifications.

Table 25. GMII Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

GTX_CLK clock period

t_GTX

_GTXH/t_GTX

t_GTKHDX

t_GTXR

—

43.75

0.5

8.0

—

56.25

5.0

ns

%

GTX_CLK duty cycle

t

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK clock rise time (20%–80%)

GTX_CLK clock fall time (80%–20%)

Notes:

ns

—

1.0

t_GTXF

—

1.0

1. The symbols for timing specifications follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs and

_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GTKHDVsymbolizes GMII transmit timing (GT)

t

with respect to the t_GTXclock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the

valid state (V) to state or setup time. Also, t_GTKHDXsymbolizes GMII transmit timing (GT) with respect to the t_GTXclock

reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general,

the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript

of t_GTXrepresents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

Figure 9 shows the GMII transmit AC timing diagram.

t

GTXR

GTX

GTX_CLK

t

GTXF

GTXH

TXD[7:0]

TX_EN

TX_ER

t

GTKHDX

Figure 9. GMII Transmit AC Timing Diagram

8.2.1.2

GMII Receive AC Timing Specifications

Table 26 provides the GMII receive AC timing specifications.

Table 26. GMII Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RX_CLK clock period

t_GRX

—

40

8.0

—

60

—

ns

%

RX_CLK duty cycle

t_{GRXH GRX}

t_GRDVKH

t_GRDXKH

/t

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

2.0

0.5

ns

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Ethernet: Three-Speed Ethernet, MII Management

Table 26. GMII Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RX_CLK clock rise (20%–80%)

RX_CLK clock fall time (80%–20%)

Note:

t_GRXR

t_GRXF

—

1.0

ns

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_GRDVKHsymbolizes GMII receive timing

(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_RXclock reference (K) going

to the high state (H) or setup time. Also, t_GRDXKLsymbolizes GMII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the t_GRXclock reference (K) going to the low (L) state or hold time. In general, the clock

reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t_GRX

represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

Figure 10 shows the GMII receive AC timing diagram.

G

t_GRX

t_GRXR

RX_CLK

t_GRXF

t_GRXH

RXD[7:0]

RX_DV

RX_ER

t_GRDXKH

t_GRDVKH

Figure 10. GMII Receive AC Timing Diagram

8.2.2

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.2.1

MII Transmit AC Timing Specifications

Table 27 provides the MII transmit AC timing specifications.

Table 27. MII Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t_MTX

t_{MTXH/ MTX}

t_MTKHDX

—

35

1

400

40

—

5

—

65

15

ns

%

t

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

ns

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Ethernet: Three-Speed Ethernet, MII Management

Table 27. MII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

TX_CLK data clock rise (20%–80%)

TX_CLK data clock fall (80%–20%)

Note:

t_MTXR

t_MTXF

1.0

—

4.0

ns

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII transmit timing

(MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference

symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of t_MTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

Figure 11 shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 11. MII Transmit AC Timing Diagram

8.2.2.2

MII Receive AC Timing Specifications

Table 28 provides the MII receive AC timing specifications.

Table 28. MII Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

t_MRX

—

400

40

—

65

—

ns

%

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t

_MRXH/t_MRX

t_MRDVKH

t_MRDXKH

35

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

10.0

—

ns

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Ethernet: Three-Speed Ethernet, MII Management

Table 28. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RX_CLK clock rise (20%–80%)

RX_CLK clock fall time (80%–20%)

Note:

t_MRXR

t_MRXF

1.0

—

4.0

ns

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKHsymbolizes MII receive timing

(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_MRXclock reference (K) going to

the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state or hold time. In general, the clock

reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t_MRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

Figure 12 provides the AC test load for TSEC.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 12. TSEC AC Test Load

Figure 13 shows the MII receive AC timing diagram.

t_MRXR

t_MRX

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKH

Figure 13. MII Receive AC Timing Diagram

8.2.3

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Ethernet: Three-Speed Ethernet, MII Management

8.2.3.1

TBI Transmit AC Timing Specifications

Table 29 provides the TBI transmit AC timing specifications.

Table 29. TBI Transmit AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

GTX_CLK clock period

t_TTX

—

40

1.0

—

8.0

—

60

ns

%

GTX_CLK duty cycle

t_{TTXH TTX}

t_TTKHDX

t_TTXR

/t

GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK clock rise (20%–80%)

GTX_CLK clock fall time (80%–20%)

Notes:

5.0

1.0

ns

t_TTXF

—

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TTKHDVsymbolizes the TBI transmit

timing (TT) with respect to the time from t_TTX(K) going high (H) until the referenced data signals (D) reach the valid state (V)

or setup time. Also, t_TTKHDXsymbolizes the TBI transmit timing (TT) with respect to the time from t_TTX(K) going high (H) until

the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on

three letters representing the clock of a particular function. For example, the subscript of t_TTXrepresents the TBI (T) transmit

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

Figure 14 shows the TBI transmit AC timing diagram.

t_TTXR

t_TTX

GTX_CLK

t_TTXH

t_TTXF

TXD[7:0]

TX_EN

TX_ER

t_TTKHDX

Figure 14. TBI Transmit AC Timing Diagram

8.2.3.2

TBI Receive AC Timing Specifications

Table 30 provides the TBI receive AC timing specifications.

Table 30. TBI Receive AC Timing Specifications

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

PMA_RX_CLK clock period

PMA_RX_CLK skew

RX_CLK duty cycle

t_TRX

16.0

—

ns

%

t_SKTRX

7.5

40

8.5

60

t_{TRXH TRX}

/t

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Ethernet: Three-Speed Ethernet, MII Management

Table 30. TBI Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DD/OV_DDof 3.3 V 10%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising

PMA_RX_CLK

2.5

—

ns

2

t_TRDVKH

2

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising

PMA_RX_CLK

t_TRDXKH

1.5

—

ns

RX_CLK clock rise time (20%–80%)

RX_CLK clock fall time (80%–20%)

Notes:

t_TRXR

t_TRXF

0.7

—

2.4

ns

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_TRDVKHsymbolizes TBI receive timing

(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t_TRXclock reference (K) going to

the high (H) state or setup time. Also, t_TRDXKHsymbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the t_TRXclock reference (K) going to the high (H) state. In general, the clock reference symbol

is based on three letters representing the clock of a particular function. For example, the subscript of t_TRXrepresents the TBI

(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For

symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).

2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times

of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.

Figure 15 shows the TBI receive AC timing diagram.

t_TRXR

t_TRX

PMA_RX_CLK1

RCG[9:0]

t_TRXH

t_TRXF

Even RCG

Odd RCG

t_TRDVKH

t_SKTRX

t_TRDXKH

PMA_RX_CLK0

t_TRXH

t_TRDXKH

t_TRDVKH

Figure 15. TBI Receive AC Timing Diagram

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Ethernet: Three-Speed Ethernet, MII Management

8.2.4

RGMII and RTBI AC Timing Specifications

Table 31 presents the RGMII and RTBI AC timing specifications.

Table 31. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LV_DDof 2.5 V 5%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)²

Clock cycle duration³

Duty cycle for 1000Base-T^{4, 5}

Duty cycle for 10BASE-T and 100BASE-TX^{3, 5}

Rise time (20%–80%)

t_SKRGT

t_RGT

–0.5

1.0

7.2

45

—

0.5

2.8

8.8

55

ns

%

8.0

50

—

t_{RGTH RGT}

t_RGTH/t_RGT

t_RGTR

t_RGTF

/t

40

60

%

—

0.75

ns

Fall time (80%–20%)

—

Notes:

1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For

example, the subscript of t_RGTrepresents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times

follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).

2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added

to the associated clock signal.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed transitioned.

5. Duty cycle reference is LV_DD/2.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Ethernet: Three-Speed Ethernet, MII Management

Figure 16 shows the RBMII and RTBI AC timing and multiplexing diagrams.

t_RGT

t_RGTH

GTX_CLK

(At Transmitter)

t_SKRGT

TXD[8:5][3:0]

TXD[8:5]

TXD[7:4][3:0]

TXD[3:0]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t_SKRGT

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t_SKRGT

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t_SKRGT

RX_CLK

(At PHY)

Figure 16. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.3

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to the MII management interface signals management

data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII,

RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller

(TSEC)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”

8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 2.5 or 3.3 V. The DC electrical

characteristics for MDIO and MDC are provided in Table 32 and Table 33.

Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage (2.5 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

LV_DD

V_OH

V_OL

V_IH

—

2.37

2.00

2.63

LV_DD+ 0.3

0.40

V

I_OH= –1.0 mA

LV_DD= Min

I_OL= 1.0 mA

GND – 0.3

1.7

—

V_IL

–0.3

0.70

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Ethernet: Three-Speed Ethernet, MII Management

Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V (continued)

Parameter

Input high current

Symbol

Conditions

Min

Max

Unit

I_IH

I_IL

V_IN¹= LV_DD

V_IN= LV_DD

—

10

—

μA

Input low current

–15

Note:

1. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

Table 33. MII Management DC Electrical Characteristics Powered at 3.3 V

Parameter

Symbol

Conditions

Min

Max

Unit

Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Note:

LV_DD

V_OH

V_OL

V_IH

V_IL

—

2.97

2.10

GND

2.00

—

3.63

LV_DD+ 0.3

0.50

V

I_OH= –1.0 mA

LV_DD= Min

I_OL= 1.0 mA

V

—

V

0.80

V

I_IH

LV_DD= Max

V_IN¹= 2.1 V

V_IN= 0.5 V

—

40

μA

I_IL

–600

—

1. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Table 1 and Table 2.

8.3.2

MII Management AC Electrical Specifications

Table 34 provides the MII management AC timing specifications.

Table 34. MII Management AC Timing Specifications

At recommended operating conditions with LV_DDis 3.3 V 10% or 2.5 V 5%.

Parameter/Condition

MDC frequency

Symbol¹

Min

Typ

Max

Unit

Notes

f_MDC

t_MDC

—

32

10

5

2.5

400

—

70

—

10

MHz

ns

2

MDC period

—

3

MDC clock pulse width high

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

t_MDCH

ns

t_MDKHDX

t_MDDVKH

t_MDDXKH

t_MDCR

—

ns

—

ns

—

0

—

ns

—

ns

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Ethernet: Three-Speed Ethernet, MII Management

Table 34. MII Management AC Timing Specifications (continued)

At recommended operating conditions with LV_DDis 3.3 V 10% or 2.5 V 5%.

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

MDC fall time

Notes:

t_MDHF

—

10

ns

—

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes management data

timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,

t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)

relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention

is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz

and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum

frequency is 1.7 MHz).

3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of

333 MHz, the delay is 58 ns).

Figure 17 shows the MII management AC timing diagram.

t_MDCR

t_MDC

MDC

t_MDCF

t_MDCH

MDIO

(Input)

t_MDDVKH

t_MDDXKH

MDIO

(Output)

t_MDKHDX

Figure 17. MII Management Interface Timing Diagram

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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34

USB

9 USB

This section provides the AC and DC electrical specifications for the USB interface of the MPC8347EA.

9.1

USB DC Electrical Characteristics

Table 35 provides the DC electrical characteristics for the USB interface.

Table 35. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

0.8

5

I_IN

—

μA

V

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

V_OH

V_OL

OV_DD– 0.2

—

0.2

V

9.2

USB AC Electrical Specifications

Table 36 describes the general timing parameters of the USB interface of the MPC8347EA.

Table 36. USB General Timing Parameters (ULPI Mode Only)

Parameter

Symbol¹

Min

Max

Unit

Notes

USB clock cycle time

t_USCK

t_USIVKH

t_USIXKH

t_USKHOV

t_USKHOX

15

4

—

7

ns

2–5

Input setup to USB clock—all inputs

Input hold to USB clock—all inputs

USB clock to output valid—all outputs

Output hold from USB clock—all outputs

Notes:

1

—

2

—

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_USIXKHsymbolizes USB timing (US) for

the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t_USKHOXsymbolizes

USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold

time.

2. All timings are in reference to USB clock.

3. All signals are measured from OV_DD/2 of the rising edge of the USB clock to 0.4 × OV_DDof the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to that of the leakage current specification.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

35

Local Bus

Figure 18 and Figure 19 provide the AC test load and signals for the USB, respectively.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 18. USB AC Test Load

USB0_CLK/USB1_CLK/DR_CLK

Input Signals

t_USIXKH

t_USIVKH

t_USKHOX

t_USKHOV

Output Signals:

Figure 19. USB Signals

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the

MPC8347EA.

10.1 Local Bus DC Electrical Characteristics

Table 37 provides the DC electrical characteristics for the local bus interface.

Table 37. Local Bus DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

0.8

5

I_IN

—

μA

V

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

V_OH

V_OL

OV_DD– 0.2

—

0.2

V

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

36

Local Bus

10.2 Local Bus AC Electrical Specification

Table 38 and Table 39 describe the general timing parameters of the local bus interface of the

MPC8347EA.

Table 38. Local Bus General Timing Parameters—DLL On

Parameter

Symbol¹

Min

Max

Unit

Notes

Local bus cycle time

t_LBK

7.5

1.5

2.2

1.0

1.5

3

—

ns

2

3, 4

5

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

t_LBIVKH1

t_LBIVKH2

t_LBIXKH1

t_LBIXKH2

t_LBOTOT1

t_LBOTOT2

t_LBOTOT3

t_LBKHLR

t_LBKHOV1

t_LBKHOV2

t_LBKHOV3

t_LBKHOX1

t_LBKHOX2

t_LBKHOZ

—

Input hold from local bus clock (except LUPWAIT)

LUPWAIT Input hold from local bus clock

—

LALE output fall to LAD output transition (LATCH hold time)

Local bus clock to LALE rise

—

6

2.5

—

1

—

7

4.5

—

3

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

Local bus clock to address valid for LAD

3

Output hold from local bus clock (except LAD/LDP and LALE)

Output hold from local bus clock for LAD/LDP

Local bus clock to output high impedance for LAD/LDP

Notes:

3

1

—

3

—

3.8

8

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for clock one

(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the rising edge of LSYNC_IN.

3. All signals are measured from OV_DD/2 of the rising edge of LSYNC_IN to 0.4 × OV_DDof the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. t_LBOTOT1should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than

the load on the LAD output pins.

6. t_LBOTOT2should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the

load on the LAD output pins.

7. t_LBOTOT3should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD

output pins.

8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to that of the leakage current specification.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

37

Local Bus

9

Table 39. Local Bus General Timing Parameters—DLL Bypass

Parameter

Symbol¹

Min

Max

Unit

Notes

Local bus cycle time

t_LBK

15

7

—

3

ns

2

3, 4

5

Input setup to local bus clock

t_LBIVKH

t_LBIXKH

Input hold from local bus clock

1.0

1.5

3

LALE output fall to LAD output transition (LATCH hold time)

Local bus clock to output valid

t_LBOTOT1

t_LBOTOT2

t_LBOTOT3

t_LBKLOV

t_LBKHOZ

6

2.5

—

7

3

Local bus clock to output high impedance for LAD/LDP

4

8

Notes:

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes high (H), in this case for clock one

(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge

of LCLK0 (for all other inputs).

3. All signals are measured from OV_DD/2 of the rising/falling edge of LCLK0 to 0.4 × OV_DDof the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. t_LBOTOT1should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the

load on the LAD output pins.

6. t_LBOTOT2should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than

the load on the LAD output pins.the

7. t_LBOTOT3should be used when RCWH[LALE] is not set and when the load on the LALE output pin equals to the load on the

LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.

Figure 20 provides the AC test load for the local bus.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 20. Local Bus C Test Load

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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38

Local Bus

Figure 21 through Figure 26 show the local bus signals.

LSYNC_IN

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH

Output Signals:

t_LBKHOV

t_LBKHLR

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE

t_LBKHOZ

t_LBKHOX

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOX

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

LALE

Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)

LCLK[n]

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH

t_LBIVKH

Input Signal:

LGTA

t_LBKLOV

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE

Output Signals:

t_LBKHOZ

t_LBKLOV

LAD[0:31]/LDP[0:3]

t_LBKLOV

t_LBOTOT

LALE

Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

39

Local Bus

LSYNC_IN

T1

T3

t_LBKHOZ1

t_LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE

t_LBIXKH2

t_LBIVKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ1

t_LBKHOV1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)

LCLK

T1

T3

t_LBKHOZ

t_LBKLOV

GPCM Mode Output Signals:

LCS[0:7]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode)

t_LBKHOZ

t_LBKLOV

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

40

Freescale Semiconductor

Local Bus

LCLK

T1

T2

T3

T4

t_LBKHOZ

t_LBKLOV

GPCM Mode Output Signals:

LCS[0:7]/LWE

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode)

t_LBKHOZ

t_LBKLOV

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

41

JTAG

LSYNC_IN

T1

T2

T3

T4

t_LBKHOZ1

t_LBKHOV1

GPCM Mode Output Signals:

LCS[0:3]/LWE

t_LBIXKH2

t_LBIVKH2

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH1

t_LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ1

t_LBKHOV1

UPM Mode Output Signals:

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)

11 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface

of the MPC8347EA.

11.1 JTAG DC Electrical Characteristics

Table 40 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the

MPC8347EA.

Table 40. JTAG Interface DC Electrical Characteristics

Parameter

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

—

OV_DD– 0.3 OV_DD+ 0.3

V

—

–0.3

—

0.8

5

I_IN

μA

V

Output high voltage

V_OH

I_OH= –8.0 mA

2.4

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

42

JTAG

Table 40. JTAG Interface DC Electrical Characteristics (continued)

Parameter

Symbol

Condition

Min

Max

Unit

Output low voltage

V_OL

I_OL= 8.0 mA

I_OL= 3.2 mA

—

0.5

0.4

V

OL

11.2 JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the

MPC8347EA. Table 41 provides the JTAG AC timing specifications as defined in Figure 28 through

Figure 31.

1

Table 41. JTAG AC Timing Specifications (Independent of CLKIN)

At recommended operating conditions (see Table 2).

Parameter

Symbol²

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f_JTG

t _JTG

0

33.3

—

2

MHz

ns

—

3

30

15

0

t_JTKHKL

t_JTGR, t_JTGF

t_TRST

ns

25

—

ns

Input setup times:

ns

Boundary-scan data

t_JTDVKH

t_JTIVKH

4

—

4

5

TMS, TDI

Input hold times:

Valid times:

ns

Boundary-scan data

TMS, TDI

t_JTDXKH

t_JTIXKH

10

—

Boundary-scan data

TDO

t_JTKLDV

t_JTKLOV

2

11

Output hold times:

Boundary-scan data

TDO

t_JTKLDX

t_JTKLOX

2

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

43

JTAG

1

Table 41. JTAG AC Timing Specifications (Independent of CLKIN) (continued)

At recommended operating conditions (see Table 2).

Parameter

Symbol²

Min

Max

Unit

Notes

JTAG external clock to output high impedance:

ns

Boundary-scan data

TDO

t_JTKLDZ

t_JTKLOZ

2

19

9

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see Figure 18).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference (K) going

to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input signals (D)

went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. In general, the clock reference symbol is

based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with

the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t_TCLK

.

5. Non-JTAG signal output timing with respect to t_TCLK

.

6. Guaranteed by design and characterization.

Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the MPC8347EA.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 27. AC Test Load for the JTAG Interface

Figure 28 provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

t_JTGR

t_JTG

VM = Midpoint Voltage (OV /2)

t_JTGF

DD

Figure 28. JTAG Clock Input Timing Diagram

Figure 29 provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 29. TRST Timing Diagram

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

44

JTAG

Figure 30 provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Boundary

Output Data Valid

Data Outputs

VM = Midpoint Voltage (OV /2)

DD

Figure 30. Boundary-Scan Timing Diagram

Figure 31 provides the test access port timing diagram.

JTAG

External Clock

VM

t_JTIVKH

t_JTIXKH

Input

TDI, TMS

TDO

Data Valid

t_JTKLOV

t_JTKLOX

Output Data Valid

t_JTKLOZ

Output Data Valid

TDO

VM = Midpoint Voltage (OV /2)

DD

Figure 31. Test Access Port Timing Diagram

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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45

I²C

12 I²C

2

This section describes the DC and AC electrical characteristics for the I C interface of the MPC8347EA.

2

12.1 I C DC Electrical Characteristics

2

Table 42 provides the DC electrical characteristics for the I C interface of the MPC8347EA.

2

Table 42. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V 10%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

Input low voltage level

Low level output voltage

V_IH

V_IL

0.7 × OV_DD

OV_DD+ 0.3

0.3 × OV_DD

0.2 × OV_DD

250

V

—

1

–0.3

0

V_OL

V

Output fall time from V_IH(min) to V_IL(max) with a bus

capacitance from 10 to 400 pF

t_I2KLKV

20 + 0.1 × C_B

ns

2

Pulse width of spikes which must be suppressed by the

input filter

t_I2KHKL

0

50

10

ns

μA

pF

3

4

Input current each I/O pin (input voltage is between

0.1 × OV_DDand 0.9 × OV_DD(max)

I_I

–10

—

Capacitance for each I/O pin

C_I

—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C_B= capacitance of one bus line in pF.

3. Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OV_DDis switched off.

2

12.2 I C AC Electrical Specifications

2

Table 43 provides the AC timing parameters for the I C interface of the MPC8347EA. Note that all values

refer to V (min) and V (max) levels (see Table 42).

IH

IL

2

Table 43. I C AC Electrical Specifications

Parameter

Symbol¹

Min

Max

Unit

SCL clock frequency

f_I2C

t_I2CL

0

400

—

kHz

μs

Low period of the SCL clock

1.3

0.6

High period of the SCL clock

t_I2CH

—

μs

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

—

μs

Hold time (repeated) START condition (after this period, the first clock

pulse is generated)

—

μs

Data setup time

t_I2DVKH

t_I2DXKL

100

—

ns

Data hold time:CBUS compatible masters

I²C bus devices

—

0²

—

μs

0.9³

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

46

I²C

2

Table 43. I C AC Electrical Specifications (continued)

Parameter

Symbol¹

Min

Max

Unit

__

Fall time of both SDA and SCL signals⁵

Setup time for STOP condition

t_I2CF

t_I2PVKH

t_I2KHDX

V_NL

300

—

ns

μs

V

0.6

1.3

Bus free time between a STOP and START condition

—

Noise margin at the LOW level for each connected device (including

hysteresis)

0.1 × OV_DD

—

Noise margin at the HIGH level for each connected device (including

hysteresis)

V_NH

0.2 × OV_DD

—

V

Notes:

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing (I2) with

respect to the time data input signals (D) reach the valid state (V) relative to the t_I2Cclock reference (K) going to the high (H)

state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the start condition (S)

goes invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C

timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V_IH(min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

3. The maximum t_I2DVKHmust be met only if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

4. C_B= capacitance of one bus line in pF.

5.)The device does not follow the “I2C-BUS Specifications” version 2.1 regarding the tI2CF AC parameter.

2

Figure 32 provides the AC test load for the I C.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

2

Figure 32. I C AC Test Load

2

Figure 33 shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2DXKL

S

Sr

Figure 33. I C Bus AC Timing Diagram

P

S

2

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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47

PCI

13 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8347EA.

13.1 PCI DC Electrical Characteristics

Table 44 provides the DC electrical characteristics for the PCI interface of the MPC8347EA.

Table 44. PCI DC Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Max

Unit

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

V_OUT≥ V_OH(min) or

V_OUT≤ V_OL(max)

2

–0.3

OV_DD+ 0.3

V

0.8

5

I_IN

V_IN¹= 0 V or V_IN= OV_DD

—

μA

V

High-level output voltage

V_OH

OV_DD= min,

OV_DD– 0.2

—

I_OH= –100 μA

Low-level output voltage

V_OL

OV_DD= min,

—

0.2

V

I_OL= 100 μA

Note:

1. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 1.

13.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the MPC8347EA. Note that the

PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is

configured as a host or agent device. Table 45 provides the PCI AC timing specifications at 66 MHz.

1

Table 45. PCI AC Timing Specifications at 66 MHz

Parameter

Symbol²

Min

Max

Unit

Notes

Clock to output valid

t

—

1

6.0

—

ns

3

PCKHOV

Output hold from clock

Clock to output high impedance

Input setup to clock

t_PCKHOX

t_PCKHOZ

t_PCIVKH

3

—

3.0

14

—

3, 4

3, 5

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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48

PCI

1

Table 45. PCI AC Timing Specifications at 66 MHz (continued)

Parameter

Symbol²

Min

Max

Unit

Notes

3, 5

Input hold from clock

t_PCIXKH

0

—

ns

Notes:

1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a

description of M66EN.

2. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_PCIVKHsymbolizes PCI timing (PC) with

respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t_SYS, reference (K) going

to the high (H) state or setup time. Also, t_PCRHFVsymbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

Table 46 provides the PCI AC timing specifications at 33 MHz.

Table 46. PCI AC Timing Specifications at 33 MHz

Parameter

Symbol¹

Min

Max

Unit

Notes

Clock to output valid

t

—

2

11

—

14

—

ns

2

PCKHOV

Output hold from clock

Clock to output high impedance

Input setup to clock

Input hold from clock

Notes:

t_PCKHOX

t_PCKHOZ

t_PCIVKH

t_PCIXKH

2

—

3.0

0

2, 3

2, 4

1. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_PCIVKHsymbolizes PCI timing (PC) with

respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t_SYS, reference (K) going

to the high (H) state or setup time. Also, t_PCRHFVsymbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the

component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

Figure 34 provides the AC test load for PCI.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 34. PCI AC Test Load

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

49

Timers

Figure 35 shows the PCI input AC timing diagram.

CLK

t_PCIVKH

t_PCIXKH

Input

Figure 35. PCI Input AC Timing Diagram

Figure 36 shows the PCI output AC timing diagram.

CLK

t_PCKHOV

t_PCKHOX

Output Delay

t_PCKHOZ

High-Impedance

Output

Figure 36. PCI Output AC Timing Diagram

14 Timers

This section describes the DC and AC electrical specifications for the timers.

14.1 Timer DC Electrical Characteristics

Table 47 provides the DC electrical characteristics for the MPC8347EA timer pins, including TIN, TOUT,

TGATE, and RTC_CLK.

Table 47. Timer DC Electrical Characteristics

Parameter

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

2.0

–0.3

—

OV_DD+ 0.3

V

Input low voltage

Input current

0.8

5

I_IN

—

μA

V

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

I_OL= 3.2 mA

2.4

—

0.5

0.4

V

—

V

OL

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

50

GPIO

14.2 Timer AC Timing Specifications

Table 48 provides the timer input and output AC timing specifications.

1

Table 48. Timers Input AC Timing Specifications

Parameter

Symbol²

Min

Unit

ns

Timers inputs—minimum pulse width

Notes:

t_TIWID

20

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external

synchronous logic. Timer inputs are required to be valid for at least t_TIWIDns to ensure proper operation.

15 GPIO

This section describes the DC and AC electrical specifications for the GPIO.

15.1 GPIO DC Electrical Characteristics

Table 49 provides the DC electrical characteristics for the MPC8347EA GPIO.

Table 49. GPIO DC Electrical Characteristics

PArameter

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

Input current

V_IH

V_IL

—

2.0

–0.3

—

OV_DD+ 0.3

V

0.8

5

I_IN

—

μA

V

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

I_OL= 3.2 mA

2.4

—

0.5

0.4

V

—

V

OL

15.2 GPIO AC Timing Specifications

Table 50 provides the GPIO input and output AC timing specifications.

1

Table 50. GPIO Input AC Timing Specifications

Parameter

Symbol²

Min

Unit

GPIO inputs—minimum pulse width

t_PIWID

20

ns

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external

synchronous logic. GPIO inputs must be valid for at least t_PIWIDns to ensure proper operation.

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IPIC

16 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

16.1 IPIC DC Electrical Characteristics

Table 51 provides the DC electrical characteristics for the external interrupt pins.

1

Table 51. IPIC DC Electrical Characteristics

Parameter

Input high voltage

Symbol

Condition

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

—

2.0

–0.3

—

OV_DD+ 0.3

V

—

2

Input low voltage

Input current

0.8

5

—

μA

V

Output low voltage

Notes:

V_OL

I_OL= 8.0 mA

I_OL= 3.2 mA

—

0.5

0.4

V

—

V

2

OL

1. This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT.

2. IRQ_OUT and MCP_OUT are open-drain pins; thus V_OHis not relevant for those pins.

16.2 IPIC AC Timing Specifications

Table 52 provides the IPIC input and output AC timing specifications.

1

Table 52. IPIC Input AC Timing Specifications

Parameter

Symbol²

Min

20

Unit

IPIC inputs—minimum pulse width

t_PICWID

ns

Notes:

1. Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external

synchronous logic. IPIC inputs must be valid for at least t_PICWIDns to ensure proper operation in edge triggered mode.

17 SPI

This section describes the SPI DC and AC electrical specifications.

17.1 SPI DC Electrical Characteristics

Table 53 provides the SPI DC electrical characteristics.

Table 53. SPI DC Electrical Characteristics

Parameter

Symbol

Condition

Min

Max

Unit

Input high voltage

Input low voltage

V_IH

V_IL

—

2.0

OV_DD+ 0.3

0.8

V

–0.3

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SPI

Table 53. SPI DC Electrical Characteristics (continued)

Parameter

Symbol

Condition

Min

Max

Unit

Input current

I_IN

—

2.4

—

5

—

μA

V

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

I_OL= 3.2 mA

0.5

0.4

V

—

V

OL

17.2 SPI AC Timing Specifications

Table 54 provides the SPI input and output AC timing specifications.

1

Table 54. SPI AC Timing Specifications

Parameter

Symbol²

Min

Max

Unit

SPI outputs valid—Master mode (internal clock) delay

SPI outputs hold—Master mode (internal clock) delay

SPI outputs valid—Slave mode (external clock) delay

SPI outputs hold—Slave mode (external clock) delay

SPI inputs—Master mode (internal clock input setup time

SPI inputs—Master mode (internal clock input hold time

SPI inputs—Slave mode (external clock) input setup time

SPI inputs—Slave mode (external clock) input hold time

Notes:

t_NIKHOV

t_NIKHOX

t_NEKHOV

t_NEKHOX

t_NIIVKH

—

0.5

—

2

6

ns

—

8

—

4

t_NIIXKH

0

t_NEIVKH

t_NEIXKH

4

2

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.

Timings are measured at the pin.

2. The symbols for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOXsymbolizes the internal timing

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Figure 37 provides the AC test load for the SPI.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 37. SPI AC Test Load

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Package and Pin Listings

Figure 38 and Figure 39 represent the AC timings from Table 54. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 38 shows the SPI timings in slave mode (external clock).

SPICLK (Input)

t_NEIXKH

t_NEIVKH

Input Signals:

SPIMOSI

(See Note)

t_NEKHOX

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 39 shows the SPI timings in master mode (internal clock).

SPICLK (Output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO

(See Note)

t_NIKHOX

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram

18 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8347EA is available

in two packages—a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See Section 18.1,

“Package Parameters for the MPC8347EA TBGA,” Section 18.2, “Mechanical Dimensions for the

MPC8347EA TBGA,” Section 18.3, “Package Parameters for the MPC8347EA PBGA,” and

Section 18.4, “Mechanical Dimensions for the MPC8347EA PBGA.”

18.1 Package Parameters for the MPC8347EA TBGA

The package parameters are provided in the following list. The package type is 35 mm × 35 mm, 672 tape

ball grid array (TBGA).

Package outline

Interconnects

35 mm × 35 mm

672

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Package and Pin Listings

Pitch

1.00 mm

1.46 mm

Module height (typical)

Solder balls

62 Sn/36 Pb/2 Ag (ZU package)

96.5 Sn/3.5Ag (VV package)

Ball diameter (typical)

0.64 mm

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Package and Pin Listings

18.2 Mechanical Dimensions for the MPC8347EA TBGA

Figure 40 shows the mechanical dimensions and bottom surface nomenclature for the MPC8347EA,

672-TBGA package.

Notes:

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement must exclude any effect of mark on top surface of package.

Figure 40. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347EA TBGA

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Package and Pin Listings

18.3 Package Parameters for the MPC8347EA PBGA

The package parameters are as provided in the following list. The package type is 29 mm × 29 mm,

620 plastic ball grid array (PBGA).

Package outline

29 mm × 29 mm

620

Interconnects

Pitch

1.00 mm

2.46 mm

2.23 mm

2.00 mm

Module height (maximum)

Module height (typical)

Module height (minimum)

Solder balls

62 Sn/36 Pb/2 Ag (ZQ package)

96.5 Sn/3.5Ag (VR package)

Ball diameter (typical)

0.60 mm

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Package and Pin Listings

18.4 Mechanical Dimensions for the MPC8347EA PBGA

Figure 41 shows the mechanical dimensions and bottom surface nomenclature for the MPC8347EA,

620-PBGA package.

Notes:

1. All dimensions are in millimeters.

2. Dimensioning and tolerancing per ASME Y14. 5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

Figure 41. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347EA PBGA

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Package and Pin Listings

18.5 Pinout Listings

Table 55 provides the pinout listing for the MPC8347EA, 672 TBGA package.

Table 55. MPC8347EA (TBGA) Pinout Listing

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

PCI

B34

C33

PCI_INTA/IRQ_OUT

O

OV_DD

2

PCI_RESET_OUT

PCI_AD[31:0]

—

G30, G32, G34, H31, H32, H33, H34,

J29, J32, J33, L30, K31, K33, K34,

L33, L34, P34, R29, R30, R33, R34,

T31, T32, T33, U31, U34, V31, V32,

V33, V34, W33, W34

I/O

PCI_C/BE[3:0]

PCI_PAR

J30, M31, P33, T34

I/O

I

OV_DD

—

5

P32

PCI_FRAME

M32

PCI_TRDY

N29

5

PCI_IRDY

M34

5

PCI_STOP

N31

5

PCI_DEVSEL

PCI_IDSEL

N30

5

J31

—

5

PCI_SERR

N34

I/O

I

PCI_PERR

N33

5

PCI_REQ[0]

D32

—

PCI_REQ[1]/CPCI1_HS_ES

PCI_REQ[2:4]

PCI_GNT0

D34

E34, F32, G29

I

C34

I/O

O

PCI_GNT1/CPCI1_HS_LED

PCI_GNT2/CPCI1_HS_ENUM

PCI_GNT[3:4]

M66EN

D33

E33

O

F31, F33

A19

O

I

DDR SDRAM Memory Interface

MDQ[0:63]

D5, A3, C3, D3, C4, B3, C2, D4, D2,

E5, G2, H6, E4, F3, G4, G3, H1, J2,

L6, M6, H2, K6, L2, M4, N2, P4, R2,

T4, P6, P3, R1, T2, AB5, AA3, AD6,

AE4, AB4, AC2, AD3, AE6, AE3, AG4,

AK5, AK4, AE2, AG6, AK3, AK2, AL2,

AL1, AM5, AP5, AM2, AN1, AP4, AN5,

AJ7, AN7, AM8, AJ9, AP6, AL7, AL9,

AN8

I/O

GV_DD

—

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Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

MECC[0:4]/MSRCID[0:4]

MECC[5]/MDVAL

MECC[6:7]

W4, W3, Y3, AA6, T1

I/O

O

GV_DD

—

U1

Y1, Y6

MDM[0:8]

B1, F1, K1, R4, AD4, AJ1, AP3, AP7,

Y4

MDQS[0:8]

B2, F5, J1, P2, AC1, AJ2, AN4, AL8,

W2

I/O

GV_DD

—

MBA[0:1]

MA[0:14]

AD1, AA5

O

GV_DD

—

W1, U4, T3, R3, P1, M1, N1, L3, L1,

K2, Y2, K3, J3, AP2, AN6

MWE

AF1

O

GV_DD

—

3

MRAS

AF4

MCAS

AG3

AG2, AG1, AK1, AL4

H3, G1

O

MCS[0:3]

MCKE[0:1]

MCK[0:5]

MODT[0:3]

MBA[2]

O

U2, F4, AM3, V3, F2, AN3

U3, E3, AN2, V4, E1, AM4

AH3, AJ5, AH1, AJ4

H4

O

—

10

O

MDIC0

AB1

I/O

MDIC1

AA1

—

Local Bus Controller Interface

LAD[0:31]

AM13, AP13, AL14, AM14, AN14,

AP14, AK15, AJ15, AM15, AN15,

AP15, AM16, AL16, AN16, AP16,

AL17, AM17, AP17, AK17, AP18,

AL18, AM18, AN18, AP19, AN19,

AM19, AP20, AK19, AN20, AL20,

AP21, AN21

I/O

OV_DD

—

LDP[0]/CKSTOP_OUT

LDP[1]/CKSTOP_IN

LDP[2]/LCS[4]

AM21

I/O

O

OV_DD

—

AP22

AN22

LDP[3]/LCS[5]

AM22

LA[27:31]

AK21, AP23, AN23, AP24, AK22

AN24, AL23, AP25, AN25

AK23, AP26, AL24, AM25

AN26

LCS[0:3]

O

LWE[0:3]/LSDDQM[0:3]/LBS[0:3]

LBCTL

O

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Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

LALE

AK24

O

I/O

O

OV_DD

—

13

—

LGPL0/LSDA10/cfg_reset_source0

LGPL1/LSDWE/cfg_reset_source1

LGPL2/LSDRAS/LOE

LGPL3/LSDCAS/cfg_reset_source2

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5/cfg_clkin_div

LCKE

AP27

AL25

AJ24

AN27

I/O

O

AP28

AL26

AM27

LCLK[0:2]

AN28, AK26, AP29

O

LSYNC_OUT

AM12

O

LSYNC_IN

AJ10

General Purpose I/O Timers

F24

I

GPIO1[0]/DMA_DREQ0/GTM1_TIN1/

GTM2_TIN2

I/O

OV_DD

—

GPIO1[1]/DMA_DACK0/GTM1_TGATE1/

GTM2_TGATE2

E24

GPIO1[2]/DMA_DDONE0/GTM1_TOUT1

B25

D24

I/O

OV_DD

—

GPIO1[3]/DMA_DREQ1/GTM1_TIN2/

GTM2_TIN1

GPIO1[4]/DMA_DACK1/GTM1_TGATE2/

GTM2_TGATE1

A25

B24

A24

D23

I/O

OV_DD

—

GPIO1[5]/DMA_DDONE1/GTM1_TOUT2/

GTM2_TOUT1

GPIO1[6]/DMA_DREQ2/GTM1_TIN3/

GTM2_TIN4

GPIO1[7]/DMA_DACK2/GTM1_TGATE3/

GTM2_TGATE4

GPIO1[8]/DMA_DDONE2/GTM1_TOUT3

B23

A23

I/O

OV_DD

—

GPIO1[9]/DMA_DREQ3/GTM1_TIN4/

GTM2_TIN3

GPIO1[10]/DMA_DACK3/GTM1_TGATE4/

GTM2_TGATE3

F22

E22

I/O

OV_DD

—

GPIO1[11]/DMA_DDONE3/GTM1_TOUT4/

GTM2_TOUT3

USB Port 1

A26

MPH1_D0_ENABLEN/DR_D0_ENABLEN

MPH1_D1_SER_TXD/DR_D1_SER_TXD

MPH1_D2_VMO_SE0/DR_D2_VMO_SE0

I/O

OV_DD

—

B26

D25

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Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

MPH1_D3_SPEED/DR_D3_SPEED

MPH1_D4_DP/DR_D4_DP

A27

B27

C27

D26

E26

D27

A28

I/O

I

OV_DD

—

MPH1_D5_DM/DR_D5_DM

MPH1_D6_SER_RCV/DR_D6_SER_RCV

MPH1_D7_DRVVBUS/DR_D7_DRVVBUS

MPH1_NXT/DR_SESS_VLD_NXT

MPH1_DIR_DPPULLUP/

I/O

DR_XCVR_SEL_DPPULLUP

MPH1_STP_SUSPEND/

DR_STP_SUSPEND

F26

E27

O

I

OV_DD

—

MPH1_PWRFAULT/

DR_RX_ERROR_PWRFAULT

MPH1_PCTL0/DR_TX_VALID_PCTL0

MPH1_PCTL1/DR_TX_VALIDH_PCTL1

MPH1_CLK/DR_CLK

A29

O

I

OV_DD

—

D28

B29

USB Port 0

MPH0_D0_ENABLEN/DR_D8_CHGVBUS

MPH0_D1_SER_TXD/DR_D9_DCHGVBUS

MPH0_D2_VMO_SE0/DR_D10_DPPD

MPH0_D3_SPEED/DR_D11_DMMD

MPH0_D4_DP/DR_D12_VBUS_VLD

MPH0_D5_DM/DR_D13_SESS_END

MPH0_D6_SER_RCV/DR_D14

C29

I/O

I

OV_DD

—

A30

E28

B30

C30

A31

B31

MPH0_D7_DRVVBUS/DR_D15_IDPULLUP

MPH0_NXT/DR_RX_ACTIVE_ID

C31

B32

MPH0_DIR_DPPULLUP/DR_RESET

MPH0_STP_SUSPEND/DR_TX_READY

MPH0_PWRFAULT/DR_RX_VALIDH

MPH0_PCTL0/DR_LINE_STATE0

MPH0_PCTL1/DR_LINE_STATE1

MPH0_CLK/DR_RX_VALID

A32

I/O

I

A33

C32

D31

I/O

I

E30

B33

Programmable Interrupt Controller

MCP_OUT

AN33

C19

O

OV_DD

2

IRQ0/MCP_IN/GPIO2[12]

IRQ[1:5]/GPIO2[13:17]

I/O

—

C22, A22, D21, C21, B21

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Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

IRQ[6]/GPIO2[18]/CKSTOP_OUT

IRQ[7]/GPIO2[19]/CKSTOP_IN

A21

I/O

OV_DD

—

C20

Ethernet Management Interface

EC_MDC

EC_MDIO

A7

O

LV_DD1

—

E9

I/O

12

Gigabit Reference Clock

EC_GTX_CLK125

C8

I

LV_DD1

—

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_COL/GPIO2[20]

TSEC1_CRS/GPIO2[21]

TSEC1_GTX_CLK

A17

I/O

O

OV_DD

LV_DD1

OV_DD

LV_DD1

OV_DD

LV_DD1

OV_DD

—

3

F12

D10

TSEC1_RX_CLK

A11

I

—

11

—

TSEC1_RX_DV

B11

I

TSEC1_RX_ER/GPIO2[26]

TSEC1_RXD[7:4]/GPIO2[22:25]

TSEC1_RXD[3:0]

B17

I/O

I

B16, D16, E16, F16

E10, A8, F10, B8

TSEC1_TX_CLK

D17

I

TSEC1_TXD[7:4]/GPIO2[27:30]

TSEC1_TXD[3:0]

A15, B15, A14, B14

I/O

O

A10, E11, B10, A9

TSEC1_TX_EN

B9

O

TSEC1_TX_ER/GPIO2[31]

A16

I/O

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_COL/GPIO1[21]

TSEC2_CRS/GPIO1[22]

TSEC2_GTX_CLK

C14

I/O

O

OV_DD

LV_DD2

OV_DD

LV_DD2

OV_DD

—

D6

A4

TSEC2_RX_CLK

B4

I

TSEC2_RX_DV/GPIO1[23]

TSEC2_RXD[7:4]/GPIO1[26:29]

TSEC2_RXD[3:0]/GPIO1[13:16]

TSEC2_RX_ER/GPIO1[25]

TSEC2_TXD[7]/GPIO1[31]

E6

A13, B13, C13, A12

D7, A6, E8, B7

D14

I/O

O

B12

TSEC2_TXD[6]/DR_XCVR_TERM_SEL

TSEC2_TXD[5]/DR_UTMI_OPMODE1

TSEC2_TXD[4]/DR_UTMI_OPMODE0

C12

D12

E12

O

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Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

TSEC2_TXD[3:0]/GPIO1[17:20]

TSEC2_TX_ER/GPIO1[24]

TSEC2_TX_EN/GPIO1[12]

TSEC2_TX_CLK/GPIO1[30]

B5, A5, F8, B6

F14

I/O

LV_DD2

OV_DD

LV_DD2

OV_DD

—

3

C5

E14

—

DUART

AK27, AN29

AL28, AM29

AP30

UART_SOUT[1:2]/MSRCID[0:1]/LSRCID[0:1]

UART_SIN[1:2]/MSRCID[2:3]/LSRCID[2:3]

UART_CTS[1]/MSRCID4/LSRCID4

UART_CTS[2]/MDVAL/ LDVAL

O

OV_DD

—

I/O

O

AN30

UART_RTS[1:2]

AP31, AM30

I²C interface

AK29

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

I/O

OV_DD

2

AP32

AN31

AM31

SPI

SPIMOSI/LCS[6]

SPIMISO/LCS[7]

SPICLK

AN32

I/O

I

OV_DD

—

AP33

AK30

SPISEL

AL31

Clocks

AN9, AP9, AM10

AN10

PCI_CLK_OUT[0:2]

PCI_CLK_OUT[3]/LCS[6]

PCI_CLK_OUT[4]/LCS[7]

PCI_SYNC_IN/PCI_CLOCK

PCI_SYNC_OUT

O

I

OV_DD

—

3

AJ11

AK12

AP11

O

I

RTC/PIT_CLOCK

AM32

—

CLKIN

AM9

I

JTAG

TCK

TDI

E20

I

OV_DD

—

4

F20

TDO

TMS

TRST

B20

O

I

3

A20

4

B19

I

4

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Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

Test

TEST

D22

I

OV_DD

6

7

TEST_SEL

AL13

PMC

QUIESCE

A18

O

OV_DD

—

System Control

PORESET

HRESET

SRESET

C18

I

OV_DD

—

1

B18

I/O

D18

Thermal Management

K32

2

THERM0

I

—

9

Power and Ground Signals

L31

AV_DD

1

Powerfore300

PLL (1.2 V)

AV_DD

1

—

nominal, 1.3 V

for 667 MHz)

AV_DD2

AP12

Power for

system PLL

(1.2 V)

AV_DD

2

—

nominal, 1.3 V

for 667 MHz)

AV_DD3

AV_DD4

GND

AE1

PowerforDDR

DLL (1.2 V)

nominal, 1.3 V

for 667 MHz)

—

AV_DD

—

AJ13

PowerforLBIU

DLL (1.2 V)

nominal, 1.3 V

for 667 MHz)

4

A1, A34, C1, C7, C10, C11, C15, C23,

C25, C28, D1, D8, D20, D30, E7, E13,

E15, E17, E18, E21, E23, E25, E32,

F6, F19, F27, F30, F34, G31, H5, J4,

J34, K30, L5, M2, M5, M30, M33, N3,

N5, P30, R5, R32, T5, T30, U6, U29,

U33, V2, V5, V30, W6, W30, Y30,

AA2, AA30, AB2, AB6, AB30, AC3,

AC6, AD31, AE5, AF2, AF5, AF31,

AG30, AG31, AH4, AJ3, AJ19, AJ22,

AK7, AK13, AK14, AK16, AK18, AK20,

AK25, AK28, AL3, AL5, AL10, AL12,

AL22, AL27, AM1, AM6, AM7, AN12,

AN17, AN34, AP1, AP8, AP34

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

65

Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

GV_DD

A2, E2, G5, G6, J5, K4, K5, L4, N4, P5, PowerforDDR

GV_DD

—

R6, T6, U5, V1, W5, Y5, AA4, AB3,

AC4, AD5, AF3, AG5, AH2, AH5, AH6,

AJ6, AK6, AK8, AK9, AL6

DRAM I/O

voltage

(2.5 V)

LV_DD1

C9, D11

Power for

three-speed

Ethernet #1

and for

LV_DD

1

—

Ethernet

management

interface I/O

(2.5 V, 3.3 V)

LV_DD

2

C6, D9

Power for

three-speed

Ethernet #2

I/O (2.5 V,

3.3 V)

LV_DD

2

—

V_DD

E19, E29, F7, F9, F11,F13, F15, F17, Power for core

V_DD

F18, F21, F23, F25, F29, H29, J6,

K29, M29, N6, P29, T29, U30, V6,

V29, W29, AB29, AC5, AD29, AF6,

AF29, AH29, AJ8, AJ12, AJ14, AJ16,

AJ18, AJ20, AJ21, AJ23, AJ25, AJ26,

AJ27, AJ28, AJ29, AK10

(1.2 V

nominal, 1.3 V

for 667 MHz)

OV_DD

B22, B28, C16, C17, C24, C26, D13,

PCI, 10/100

OV_DD

—

D15, D19, D29, E31, F28, G33, H30, Ethernet, and

L29, L32, N32, P31, R31, U32, W31, other standard

Y29, AA29, AC30, AE31, AF30, AG29,

AJ17, AJ30, AK11, AL15, AL19, AL21,

AL29, AL30, AM20, AM23, AM24,

AM26, AM28, AN11, AN13

(3.3 V)

MVREF1

MVREF2

M3

I

DDR

reference

voltage

—

AD2

DDR

reference

voltage

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

66

Package and Pin Listings

Table 55. MPC8347EA (TBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

No Connection

Pin Type

Supply

NC

W32, AA31, AA32, AA33, AA34,

AB31, AB32, AB33, AB34, AC29,

AC31, AC33, AC34, AD30, AD32,

AD33, AD34, AE29, AE30, AH32,

AH33, AH34, AM33, AJ31, AJ32,

AJ33, AJ34, AK32, AK33, AK34,

AM34, AL33, AL34, AK31, AH30,

AC32, AE32, AH31, AL32, AG34,

AE33, AF32, AE34, AF34, AF33,

AG33, AG32, AL11, AM11, AP10, Y32,

Y34, Y31, Y33

—

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV_DD

.

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV_DD

.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. This pin must always be tied to GND.

7. This pin must always be pulled up to OV_DD

.

8. This pin must always be left not connected.

9. Thermal sensitive resistor.

10.It is recommended that MDIC0 be tied to GRD using an 18 Ω resistor and MDIC1 be tied to DDR power using an 18 Ω

resistor.

11.TSEC1_TXD[3] is required an external pull-up resistor. For proper functionality of the device, this pin must be pulled up or

actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net.

12. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LV_DD1

.

13. For systems that boot from local bus (GPCM)-controlled NOR flash, a pullup on LGPL4 is required.

Table 56 provides the pinout listing for the MPC8347EA, 620 PBGA package.

Table 56. MPC8347EA (PBGA) Pinout Listing

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI

D20

B21

PCI1_INTA/IRQ_OUT

O

OV_DD

2

PCI1_RESET_OUT

PCI1_AD[31:0]

—

E19, D17, A16, A18, B17, B16, D16,

B18, E17, E16, A15, C16, D15, D14,

C14, A12, D12, B11, C11, E12, A10,

C10, A9, E11, E10, B9, B8, D9, A8,

C9, D8, C8

I/O

PCI1_C/BE[3:0]

PCI1_PAR

A17, A14, A11, B10

I/O

OV_DD

—

5

D13

B14

PCI1_FRAME

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

67

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

PCI1_TRDY

A13

I/O

I

OV_DD

5

PCI1_IRDY

E13

PCI1_STOP

C13

5

PCI1_DEVSEL

PCI1_IDSEL

B13

5

C17

—

5

PCI1_SERR

C12

I/O

I

PCI1_PERR

B12

5

PCI1_REQ[0]

A21

PCI1_REQ[1]/CPCI1_HS_ES

PCI1_REQ[2:4]

PCI1_GNT0

C19

—

C18, A19, E20

I

B20

I/O

O

PCI1_GNT1/CPCI1_HS_LED

PCI1_GNT2/CPCI1_HS_ENUM

PCI1_GNT[3:4]

M66EN

C20

B19

O

A20, E18

L26

O

I

DDR SDRAM Memory Interface

MDQ[0:63]

AC25, AD27, AD25, AH27, AE28,

AD26, AD24, AF27, AF25, AF28,

AH24, AG26, AE25, AG25, AH26,

AH25, AG22, AH22, AE21, AD19,

AE22, AF23, AE19, AG20, AG19,

AD17, AE16, AF16, AF18, AG18,

AH17, AH16, AG9, AD12, AG7, AE8,

AD11, AH9, AH8, AF6, AF8, AE6,

AF1, AE4, AG8, AH3, AG3, AG4, AH2,

AD7, AB4, AB3, AG1, AD5, AC2, AC1,

AC4, AA3, Y4, AA4, AB1, AB2, Y5, Y3

I/O

GV_DD

—

MECC[0:4]/MSRCID[0:4]

MECC[5]/MDVAL

MECC[6:7]

AG13, AE14, AH12, AH10, AE15

I/O

O

GV_DD

—

AH14

AE13, AH11

MDM[0:8]

AG28, AG24, AF20, AG17, AE9, AH5,

AD1, AA2, AG12

MDQS[0:8]

AE27, AE26, AE20, AH18, AG10, AF5,

AC3, AA1, AH13

I/O

GV_DD

—

MBA[0:1]

MA[0:14]

AF10, AF11

O

GV_DD

—

AF13, AF15, AG16, AD16, AF17,

AH20, AH19, AH21, AD18, AG21,

AD13, AF21, AF22, AE1, AA5

MWE

AD10

O

GV_DD

—

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

68

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

MRAS

AF7

O

GV_DD

—

3

MCAS

AG6

AE7, AH7, AH4, AF2

AG23, AH23

MCS[0:3]

MCKE[0:1]

MCK[0:5]

MODT[0:3]

MBA[2]

O

AH15, AE24, AE2, AF14, AE23, AD3

AG15, AD23, AE3, AG14, AF24, AD2

AG5, AD4, AH6, AF4

AD22

O

—

9

O

MDIC0

AG11

I/O

MDIC1

AF12

—

9

Local Bus Controller Interface

LAD[0:31]

T4, T5, T1, R2, R3, T2, R1, R4, P1, P2,

P3, P4, N1, N4, N2, N3, M1, M2, M3,

N5, M4, L1, L2, L3, K1, M5, K2, K3, J1,

J2, L5, J3

I/O

OV_DD

—

LDP[0]/CKSTOP_OUT

LDP[1]/CKSTOP_IN

LDP[2]/LCS[4]

H1

I/O

O

OV_DD

—

12

—

K5

H2

LDP[3]/LCS[5]

G1

LA[27:31]

J4, H3, G2, F1, G3

LCS[0:3]

J5, H4, F2, E1

O

LWE[0:3]/LSDDQM[0:3]/LBS[0:3]

LBCTL

F3, G4, D1, E2

O

H5

E3

O

LALE

O

LGPL0/LSDA10/cfg_reset_source0

LGPL1/LSDWE/cfg_reset_source1

LGPL2/LSDRAS/LOE

LGPL3/LSDCAS/cfg_reset_source2

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5/cfg_clkin_div

LCKE

F4

I/O

O

D2

C1

C2

I/O

O

C3

B3

E4

LCLK[0:2]

D4, A3, C4

U3

O

LSYNC_OUT

O

LSYNC_IN

Y2

I

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

69

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

General Purpose I/O Timers

GPIO1[0]/DMA_DREQ0/GTM1_TIN1/

GTM2_TIN2

D27

I/O

OV_DD

—

GPIO1[1]/DMA_DACK0/GTM1_TGATE1/

GTM2_TGATE2

E26

GPIO1[2]/DMA_DDONE0/GTM1_TOUT1

D28

G25

I/O

OV_DD

—

GPIO1[3]/DMA_DREQ1/GTM1_TIN2/

GTM2_TIN1

GPIO1[4]/DMA_DACK1/GTM1_TGATE2/

GTM2_TGATE1

J24

F26

E27

E28

I/O

OV_DD

—

GPIO1[5]/DMA_DDONE1/GTM1_TOUT2/

GTM2_TOUT1

GPIO1[6]/DMA_DREQ2/GTM1_TIN3/

GTM2_TIN4

GPIO1[7]/DMA_DACK2/GTM1_TGATE3/

GTM2_TGATE4

GPIO1[8]/DMA_DDONE2/GTM1_TOUT3

H25

F27

I/O

OV_DD

—

GPIO1[9]/DMA_DREQ3/GTM1_TIN4/

GTM2_TIN3

GPIO1[10]/DMA_DACK3/

GTM1_TGATE4/GTM2_TGATE3

K24

G26

I/O

OV_DD

—

GPIO1[11]/DMA_DDONE3/

GTM1_TOUT4/GTM2_TOUT3

USB Port 1

C28

MPH1_D0_ENABLEN/DR_D0_ENABLEN

MPH1_D1_SER_TXD/DR_D1_SER_TXD

MPH1_D2_VMO_SE0/DR_D2_VMO_SE0

MPH1_D3_SPEED/DR_D3_SPEED

MPH1_D4_DP/DR_D4_DP

I/O

I

OV_DD

—

F25

B28

C27

D26

MPH1_D5_DM/DR_D5_DM

E25

MPH1_D6_SER_RCV/DR_D6_SER_RCV

MPH1_D7_DRVVBUS/DR_D7_DRVVBUS

MPH1_NXT/DR_SESS_VLD_NXT

C26

D25

B26

MPH1_DIR_DPPULLUP/

E24

I/O

DR_XCVR_SEL_DPPULLUP

MPH1_STP_SUSPEND/

DR_STP_SUSPEND

A27

C25

O

I

OV_DD

—

MPH1_PWRFAULT/

DR_RX_ERROR_PWRFAULT

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

70

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

MPH1_PCTL0/DR_TX_VALID_PCTL0

MPH1_PCTL1/DR_TX_VALIDH_PCTL1

MPH1_CLK/DR_CLK

A26

O

I

OV_DD

—

B25

A25

USB Port 0

MPH0_D0_ENABLEN/DR_D8_CHGVBUS

MPH0_D1_SER_TXD/DR_D9_DCHGVBUS

MPH0_D2_VMO_SE0/DR_D10_DPPD

MPH0_D3_SPEED/DR_D11_DMMD

MPH0_D4_DP/DR_D12_VBUS_VLD

MPH0_D5_DM/DR_D13_SESS_END

MPH0_D6_SER_RCV/DR_D14

D24

I/O

I

OV_DD

—

C24

B24

A24

D23

C23

B23

MPH0_D7_DRVVBUS/DR_D15_IDPULLUP

MPH0_NXT/DR_RX_ACTIVE_ID

A23

D22

MPH0_DIR_DPPULLUP/DR_RESET

MPH0_STP_SUSPEND/DR_TX_READY

MPH0_PWRFAULT/DR_RX_VALIDH

MPH0_PCTL0/DR_LINE_STATE0

MPH0_PCTL1/DR_LINE_STATE1

MPH0_CLK/DR_RX_VALID

C22

I/O

I

B22

A22

E21

I/O

I

D21

C21

Programmable Interrupt Controller

MCP_OUT

E8

O

OV_DD

2

IRQ0/MCP_IN/GPIO2[12]

IRQ[1:5]/GPIO2[13:17]

IRQ[6]/GPIO2[18]/CKSTOP_OUT

IRQ[7]/GPIO2[19]/CKSTOP_IN

J28

I/O

—

K25, J25, H26, L24, G27

G28

J26

Ethernet Management Interface

EC_MDC

EC_MDIO

Y24

O

LV_DD1

—

Y25

Gigabit Reference Clock

Y26

I/O

11

EC_GTX_CLK125

I

LV_DD1

—

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_COL/GPIO2[20]

TSEC1_CRS/GPIO2[21]

TSEC1_GTX_CLK

M26

U25

V24

I/O

O

OV_DD

LV_DD1

—

3

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

71

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

TSEC1_RX_CLK

U26

I

LV_DD1

OV_DD

LV_DD1

OV_DD

LV_DD1

OV_DD

—

10

—

TSEC1_RX_DV

U24

TSEC1_RX_ER/GPIO2[26]

TSEC1_RXD[7:4]/GPIO2[22:25]

TSEC1_RXD[3:0]

L28

I/O

I

M27, M28, N26, N27

W26, W24, Y28, Y27

TSEC1_TX_CLK

N25

I

TSEC1_TXD[7:4]/GPIO2[27:30]

TSEC1_TXD[3:0]

N28, P25, P26, P27

I/O

O

I/O

V28, V27, V26, W28

TSEC1_TX_EN

W27

TSEC1_TX_ER/GPIO2[31]

N24

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_COL/GPIO1[21]

TSEC2_CRS/GPIO1[22]

TSEC2_GTX_CLK

P28

I/O

O

OV_DD

LV_DD2

OV_DD

LV_DD2

OV_DD

LV_DD2

OV_DD

LV_DD2

OV_DD

—

3

AC28

AC27

TSEC2_RX_CLK

AB25

I

TSEC2_RX_DV/GPIO1[23]

TSEC2_RXD[7:4]/GPIO1[26:29]

TSEC2_RXD[3:0]/GPIO1[13:16]

TSEC2_RX_ER/GPIO1[25]

TSEC2_TXD[7]/GPIO1[31]

AC26

R28, T24, T25, T26

AA25, AA26, AA27, AA28

R25

I/O

O

T27

TSEC2_TXD[6]/DR_XCVR_TERM_SEL

TSEC2_TXD[5]/DR_UTMI_OPMODE1

TSEC2_TXD[4]/DR_UTMI_OPMODE0

TSEC2_TXD[3:0]/GPIO1[17:20]

TSEC2_TX_ER/GPIO1[24]

T28

U28

O

U27

O

AB26, AB27, AA24, AB28

I/O

R27

AD28

R26

TSEC2_TX_EN/GPIO1[12]

TSEC2_TX_CLK/GPIO1[30]

—

DUART

B4, A4

D5, C5

B5

UART_SOUT[1:2]/MSRCID[0:1]/LSRCID[0:1]

UART_SIN[1:2]/MSRCID[2:3]/LSRCID[2:3]

UART_CTS[1]/MSRCID4/LSRCID4

UART_CTS[2]/MDVAL/LDVAL

O

OV_DD

—

I/O

O

A5

UART_RTS[1:2]

D6, C6

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

72

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

I²C interface

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

E5

I/O

OV_DD

2

A6

B6

E7

SPI

SPIMOSI/LCS[6]

SPIMISO/LCS[7]

SPICLK

D7

I/O

I

OV_DD

—

C7

B7

SPISEL

A7

Clocks

PCI_CLK_OUT[0:2]

PCI_CLK_OUT[3]/LCS[6]

PCI_CLK_OUT[4]/LCS[7]

PCI_SYNC_IN/PCI_CLOCK

PCI_SYNC_OUT

Y1, W3, W2

O

I

OV_DD

—

3

W1

V3

U4

U5

O

I

RTC/PIT_CLOCK

E9

—

CLKIN

W5

I

JTAG

TCK

TDI

H27

I

OV_DD

—

4

H28

TDO

TMS

TRST

M24

O

I

3

J27

4

K26

I

4

Test

TEST

F28

I

OV_DD

6

TEST_SEL

T3

PMC

QUIESCE

K27

O

OV_DD

—

System Control

PORESET

HRESET

SRESET

K28

M25

L27

I

OV_DD

—

1

I/O

2

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

73

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Supply

Signal

Package Pin Number

Pin Type

Notes

Thermal Management

THERM0

B15

Power and Ground Signals

C15

I

—

8

AV_DD

1

Powerfore300

PLL (1.2 V)

AV_DD1

—

nominal, 1.3 V

for 667 MHz)

AV_DD2

U1

Power for

system PLL

(1.2 V)

AV_DD

2

—

nominal, 1.3 V

for 667 MHz)

AV_DD

3

AF9

U2

PowerforDDR

DLL (1.2 V

nominal, 1.3 V

for 667 MHz)

—

AV_DD4

GND

PowerforLBIU

DLL (1.2 V

nominal, 1.3 V

for 667 MHz)

AV_DD4

A2, B1, B2, D10, D18, E6, E14, E22,

F9, F12, F15, F18, F21, F24, G5, H6,

J23, L4, L6, L12, L13, L14, L15, L16,

L17, M11, M12, M13, M14, M15, M16,

M17, M18, M23, N11, N12, N13, N14,

N15, N16, N17, N18, P6, P11, P12,

P13, P14, P15, P16, P17, P18, P24,

R5, R11, R12, R13, R14, R15, R16,

R17, R18, R23, T11, T12, T13, T14,

T15, T16, T17, T18, U6, U11, U12,

U13, U14, U15, U16, U17, U18, V12,

V13, V14, V15, V16, V17, V23, V25,

W4, Y6, AA23, AB24, AC5, AC8,

—

AC11, AC14, AC17, AC20, AD9,

AD15, AD21, AE12, AE18, AF3, AF26

GV_DD

U9, V9, W10, W19, Y11, Y12, Y14, PowerforDDR

GV_DD

—

Y15, Y17, Y18, AA6, AB5, AC9, AC12,

AC15, AC18, AC21, AC24, AD6, AD8,

AD14, AD20, AE5, AE11, AE17, AG2,

AG27

DRAM I/O

voltage

(2.5 V)

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

74

Package and Pin Listings

Table 56. MPC8347EA (PBGA) Pinout Listing (continued)

Power

Notes

Signal

Package Pin Number

Pin Type

Supply

LV_DD

1

U20, W25

Power for

three-speed

Ethernet #1

and for

LV_DD

1

—

Ethernet

management

interface I/O

(2.5 V, 3.3 V)

LV_DD

2

V20, Y23

Power for

three-speed

Ethernet #2

I/O (2.5 V,

3.3 V)

LV_DD2

—

V_DD

J11, J12, J15, K10, K11, K12, K13, Power for core

V_DD

K14, K15, K16, K17, K18, K19, L10,

L11, L18, L19, M10, M19, N10, N19,

P9, P10, P19, R10, R19, R20, T10,

T19, U10, U19, V10, V11, V18, V19,

W11, W12, W13, W14, W15, W16,

W17, W18

(1.2 V)

OV_DD

B27, D3, D11, D19, E15, E23, F5, F8,

PCI, 10/100

OV_DD

—

F11, F14, F17, F20, G24, H23, H24, Ethernet, and

J6, J14, J17, J18, K4, L9, L20, L23, other standard

L25, M6, M9, M20, P5, P20, P23, R6,

R9, R24, U23, V4, V6

(3.3 V)

MVREF1

MVREF2

AF19

AE10

I

DDR

reference

voltage

—

I

DDR

reference

voltage

No Connection

NC

V1, V2, V5

—

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV_DD

.

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV_DD

.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. This pin must always be tied to GND.

7. This pin must always be left not connected.

8. Thermal sensitive resistor.

9. It is recommended that MDIC0 be tied to GRD using an 18 Ω resistor and MDIC1 be tied to DDR power using an 18 Ω resistor.

10.TSEC1_TXD[3] is required an external pull-up resistor. For proper functionality of the device, this pin must be pulled up or

actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net.

11. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LV_DD1

.

12. For systems that boot from local bus (GPCM)-controlled NOR flash, a pullup on LGPL4 is required.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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75

Clocking

19 Clocking

Figure 42 shows the internal distribution of the clocks.

e300 Core

Core PLL

core_clk

csb_clk

To DDR

Memory

6

DDR

Controller

DDR

Memory

Device

MCK[0:5]

Clock

Div

/2

ddr_clk

Clock

Unit

System PLL

lbiu_clk

/n

LCLK[0:2]

To Local Bus

Memory

Local Bus

Memory

Device

LBIU

DLL

LSYNC_OUT

LSYNC_IN

Controller

csb_clk to Rest

of the Device

PCI_CLK/

PCI_SYNC_IN

CFG_CLKIN_DIV

CLKIN

PCI_SYNC_OUT

PCI Clock

Divider

5

PCI_CLK_OUT[0:4]

Figure 42. MPC8347EA Clock Subsystem

The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device

is configured in PCI host or PCI agent mode. When the MPC8347EA is configured as a PCI host device,

CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for

PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether

CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select

whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to

synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,

with equal delay to all PCI agent devices in the system, to allow the MPC8347EA to function. When the

device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal

should be tied to GND.

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76

Freescale Semiconductor

Clocking

As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the

DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following

equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the

csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL

multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL),

which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset,

clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock

subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWL[DDRCM])

ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (÷2) to

create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the

same frequency as ddr_clk.

The internal lbiu_clk frequency is determined by the following equation:

lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])

lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create

the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is

controlled by LCCR[CLKDIV].

In addition, some of the internal units may have to be shut off or operate at lower frequency than the

csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped

register after the device exits reset. Table 57 specifies which units have a configurable clock frequency.

Table 57. Configurable Clock Units

Unit

Default Frequency

Options

TSEC1

csb_clk/3

csb_clk

Off, csb_clk, csb_clk/2, csb_clk/3

Off, csb_clk

TSEC2, I²C1

Security core

USB DR, USB MPH

PCI and DMA complex

Table 58 provides the operating frequencies for the MPC8347EA TBGA under recommended operating

conditions (see Table 2). All frequency combinations shown in the table below may not be available.

Maximum operating frequencies depend on the part ordered, see Section 22.1, “Part Numbers Fully

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

77

Clocking

Addressed by This Document,” for part ordering details and contact your Freescale Sales Representative

or authorized distributor for more information.

Table 58. Operating Frequencies for TBGA

Characteristic¹

e300 core frequency (core_clk)

400 MHz

266–400

533 MHz

266–533

667 MHz

266–667

Unit

MHz

Coherent system bus frequency (csb_clk)

DDR1 memory bus frequency (MCK)²

DDR2 memory bus frequency (MCK)³

Local bus frequency (LCLKn)⁴

100–266

100–133

16.67–133

25–66

100–333

100–133

100–200

16.67–133

25–66

100–333

100–166.67

100–200

16.67–133

25–66

MHz

PCI input frequency (CLKIN or PCI_CLK)

Security core maximum internal operating frequency

133

166

USB_DR, USB_MPH maximum internal operating

frequency

133

166

1

The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,

LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value

of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal

operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.

The DDR data rate is 2x the DDR memory bus frequency.

The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x

the csb_clk frequency (depending on RCWL[LBIUCM]).

2

3

4

Table 59 provides the operating frequencies for the MPC8347EA PBGA under recommended operating

conditions.

Table 59. Operating Frequencies for PBGA

Parameter¹

266 MHz

333 MHz

400 MHz

Unit

MHz

e300 core frequency (core_clk)

200–266

200–333

100–266

100–133

16.67–133

25–66

200–400

Coherent system bus frequency (csb_clk)

DDR1 memory bus frequency (MCK)²

DDR2 memory bus frequency (MCK)³

Local bus frequency (LCLKn)⁴

MHz

PCI input frequency (CLKIN or PCI_CLK)

Security core maximum internal operating frequency

133

USB_DR, USB_MPH maximum internal operating

frequency

133

1

The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,

LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value

of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal

operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.

The DDR data rate is 2× the DDR memory bus frequency.

2

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Freescale Semiconductor

Clocking

3

4

The DDR data rate is 2× the DDR memory bus frequency.

The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the

csb_clk frequency (depending on RCWL[LBIUCM]).

19.1 System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 60 shows the multiplication factor

encodings for the system PLL.

Table 60. System PLL Multiplication Factors

RCWL[SPMF]

System PLL Multiplication Factor

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

× 16

Reserved

× 2

× 3

× 4

× 5

× 6

× 7

× 8

× 9

× 10

× 11

× 12

× 13

× 14

× 15

As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 61

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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79

Clocking

and Table 62 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

Table 61. CSB Frequency Options for Host Mode

Input Clock Frequency (MHz)²

CFG_CLKIN_DIV

at Reset¹

csb_clk :

SPMF

16.67

25

33.33

66.67

Input Clock Ratio²

csb_clk Frequency (MHz)

Low

High

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0010

0011

0100

0101

0110

0111

1000

2 : 1

3 : 1

4 : 1

5 : 1

6 : 1

7 : 1

8 : 1

9 : 1

10 : 1

11 : 1

12 : 1

13 : 1

14 : 1

15 : 1

16 : 1

2 : 1

3 : 1

4 : 1

5 : 1

6 : 1

7 : 1

8 : 1

133

200

266

333

100

125

150

175

200

225

250

275

300

325

133

166

200

233

266

300

333

100

116

133

150

166

183

200

216

233

250

266

133

200

266

333

100

133

166

200

233

1

2

CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.

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Clocking

Table 62. CSB Frequency Options for Agent Mode

Input Clock Frequency (MHz)²

CFG_CLKIN_DIV

at Reset¹

csb_clk :

SPMF

16.67

25

33.33

66.67

Input Clock Ratio²

csb_clk Frequency (MHz)

Low

High

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0010

0011

0100

0101

0110

0111

1000

2 : 1

3 : 1

133

200

266

333

100

4 : 1

100

125

150

175

200

225

250

275

300

325

133

166

200

233

266

300

333

5 : 1

6 : 1

100

7 : 1

116

133

150

166

183

200

216

8 : 1

9 : 1

10 : 1

11 : 1

12 : 1

13 : 1

14 : 1

15 : 1

16 : 1

4 : 1

233

250

266

100

150

200

250

300

133

200

266

333

266

6 : 1

100

133

166

200

233

266

8 : 1

10 : 1

12 : 1

14 : 1

16 : 1

1

2

CFG_CLKIN_DIV doubles csb_clk if set high.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.

19.2 Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 63 shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 63 should be considered as reserved.

NOTE

Core VCO frequency = core frequency × VCO divider

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

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Clocking

VCO divider must be set properly so that the core VCO frequency is in the

range of 800–1800 MHz.

Table 63. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider¹

0–1

2–5

6

nn

0000

n

PLL bypassed

(PLL off, csb_clk clocks core directly) (PLL off, csb_clk clocks core directly)

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0001

0010

0011

0

1

0

1

0

1:1

2

4

8

2

4

8

2

4

8

2

4

8

2

4

8

1:1

1.5:1

2:1

2.5:1

3:1

1

Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency

is in the range of 800–1800 MHz.

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Clocking

19.3 Suggested PLL Configurations

Table 64 shows suggested PLL configurations for 33 and 66 MHz input clocks.

Table 64. Suggested PLL Configurations

RCWL

400 MHz Device

533 MHz Device

667 MHz Device

Input

Clock

Freq

Ref

CSB

Freq

(MHz)

Core

Freq

(MHz)

CSB

Freq

(MHz)

Core

Freq

(MHz)

CSB

Freq

(MHz)

Core

Freq

(MHz)

No.¹

CORE

PLL

Clock

Freq

Clock

Freq

SPMF

(MHz)²

33 MHz CLKIN/PCI_CLK Options

922

723

604

624

803

823

903

923

704

724

A03

804

705

606

904

805

A04

1001

0111

0110

1000

1001

0111

1010

1000

0111

0110

1001

1000

1010

0100010

0100011

0000100

0100100

0000011

0100011

0000011

0100011

0000011

0100011

0000011

0000100

0000101

0000110

0000100

0000101

0000100

—

33

—

233

200

266

—

33

—

233

200

266

300

233

333

266

—

f300

350

400

450

466

500

533

33

300

233

200

266

300

233

333

266

233

200

300

266

333

300

350

400

450

466

500

533

583

600

667

350

400

—

66 MHz CLKIN/PCI_CLK Options

304

324

403

423

305

503

404

0011

0100

0011

0101

0100

0000100

0100100

0000011

0100011

0000101

0000011

0000100

66

200

266

—

400

66

200

266

200

333

266

400

500

533

66

200

266

200

333

266

400

500

533

—

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Thermal

Table 64. Suggested PLL Configurations (continued)

400 MHz Device 533 MHz Device

RCWL

667 MHz Device

Input

Ref

CSB

Freq

(MHz)

Core

Freq

(MHz)

CSB

Freq

(MHz)

Core

Freq

(MHz)

CSB

Freq

(MHz)

Core

Freq

(MHz)

No.¹

CORE

PLL

Clock

Freq

Clock

Freq

Clock

Freq

SPMF

(MHz)²

306

405

0011

0100

0101

0000110

0000101

0000100

—

66

200

266

333

600

667

504

1

The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and

COREPLL settings given in the table.

The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode.

2

20 Thermal

This section describes the thermal specifications of the MPC8347EA.

20.1 Thermal Characteristics

Table 65 provides the package thermal characteristics for the 672 35 × 35 mm TBGA of the MPC8347EA.

Table 65. Package Thermal Characteristics for TBGA

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection on single-layer board (1s)

Junction-to-ambient natural convection on four-layer board (2s2p)

Junction-to-ambient (at 200 ft/min) on single-layer board (1s)

Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p)

Junction-to-ambient (at 2 m/s) on single-layer board (1s)

Junction-to-ambient (at 2 m/s) on four-layer board (2s2p)

Junction-to-board thermal

R_θJA

R_θJMA

R_θJB

14

11

8

°C/W

1, 2

1, 3

4

9

7

3.8

1.7

Junction-to-case thermal

R_θJC

5

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Thermal

Table 65. Package Thermal Characteristics for TBGA (continued)

Characteristic

Symbol

Value

Unit

Notes

Junction-to-package natural convection on top

ψ_JT

1

°C/W

6

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM).

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 66 provides the package thermal characteristics for the 620 29 × 29 mm PBGA of the MPC8347EA.

Table 66. Package Thermal Characteristics for PBGA

Parameter

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection on single-layer board (1s)

Junction-to-ambient natural convection on four-layer board (2s2p)

Junction-to-ambient (at 200 ft/min) on single-layer board (1s)

Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p)

Junction-to-board thermal

R_θJA

R_θJMA

R_θJB

21

15

17

12

6

°C/W

1, 2

1, 3

4

Junction-to-case thermal

R_θJC

5

Junction-to-package natural convection on top

Notes

ψ_JT

5

6

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

20.2 Thermal Management Information

For the following sections, P = (V × I ) + P where P is the power dissipation of the I/O drivers.

D

DD

I/O

See Table 5 for I/O power dissipation values.

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Thermal

20.2.1 Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R

× P )

D

J

A

θJA

where:

T = junction temperature (°C)

J

T = ambient temperature for the package (°C)

A

R

= junction-to-ambient thermal resistance (°C/W)

θJA

P = power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy

estimation of thermal performance. Generally, the value obtained on a single-layer board is appropriate for

a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually

appropriate if the board has low power dissipation and the components are well separated. Test cases have

demonstrated that errors of a factor of two (in the quantity T – T ) are possible.

J

A

20.2.2 Estimation of Junction Temperature with Junction-to-Board

Thermal Resistance

The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal

resistance. The thermal performance of any component is strongly dependent on the power dissipation of

surrounding components. In addition, the ambient temperature varies widely within the application. For

many natural convection and especially closed box applications, the board temperature at the perimeter

(edge) of the package is approximately the same as the local air temperature near the device. Specifying

the local ambient conditions explicitly as the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R

× P )

D

J

A

θJA

where:

T = junction temperature (°C)

J

T = ambient temperature for the package (°C)

A

R

= junction-to-ambient thermal resistance (°C/W)

θJA

P = power dissipation in the package (W)

D

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction

temperature can be made. The application board should be similar to the thermal test condition: the

component is soldered to a board with internal planes.

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Thermal

20.2.3 Experimental Determination of Junction Temperature

To determine the junction temperature of the device in the application after prototypes are available, use

the thermal characterization parameter (Ψ ) to determine the junction temperature and a measure of the

JT

temperature at the top center of the package case using the following equation:

T = T + (Ψ × P )

J

T

JT

D

where:

T = junction temperature (°C)

J

T = thermocouple temperature on top of package (°C)

T

Ψ

= junction-to-ambient thermal resistance (°C/W)

JT

P = power dissipation in the package (W)

D

The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type

T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

20.2.4 Heat Sinks and Junction-to-Case Thermal Resistance

Some application environments require a heat sink to provide the necessary thermal management of the

device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case

thermal resistance and a case-to-ambient thermal resistance:

R

= R

+ R

θJA

θJC θCA

where:

R

= junction-to-ambient thermal resistance (°C/W)

= junction-to-case thermal resistance (°C/W)

= case-to-ambient thermal resistance (°C/W)

θJA

θJC

θCA

R_θJCis device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R_θCA. For instance, the user can change the size of the heat

sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit

board, or change the thermal dissipation on the printed-circuit board surrounding the device.

The thermal performance of devices with heat sinks has been simulated with a few commercially available

heat sinks. The heat sink choice is determined by the application environment (temperature, air flow,

adjacent component power dissipation) and the physical space available. Because there is not a standard

application environment, a standard heat sink is not required.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Thermal

Table 67 and Table 68 show heat sink thermal resistance for TBGA and PBGA of the MPC8347EA.

Table 67. Heat Sink and Thermal Resistance of MPC8347EA (TBGA)

35 × 35 mm TBGA

Heat Sink Assuming Thermal Grease

Air Flow

Thermal Resistance

AAVID 30 × 30 × 9.4 mm pin fin

Natural convection

1 m/s

10

6.5

5.6

8.4

4.7

4

AAVID 30 × 30 × 9.4 mm pin fin

2 m/s

AAVID 31 × 35 × 23 mm pin fin

Natural convection

1 m/s

AAVID 31 × 35 × 23 mm pin fin

2 m/s

Wakefield, 53 × 53 × 25 mm pin fin

MEI, 75 × 85 × 12 no adjacent board, extrusion

MEI, 75 × 85 × 12 mm, adjacent board, 40 mm side bypass

f

Natural convection

1 m/s

5.7

3.5

2.7

6.7

4.1

2.8

3.1

2 m/s

Natural convection

1 m/s

2 m/s

1 m/s

Table 68. Heat Sink and Thermal Resistance of MPC8347EA (PBGA)

29 × 29 mm PBGA

Heat Sink Assuming Thermal Grease

Air Flow

Thermal Resistance

AAVID 30 × 30 × 9.4 mm pin fin

Natural convection

1 m/s

13.5

9.6

8.8

11.3

8.1

7.5

9.1

7.1

6.5

10.1

7.7

6.6

6.9

AAVID 30 × 30 × 9.4 mm pin fin

2 m/s

AAVID 31 × 35 × 23 mm pin fin

Natural convection

1 m/s

AAVID 31 × 35 × 23 mm pin fin

2 m/s

Wakefield, 53 × 53 × 25 mm pin fin

Natural convection

1 m/s

Wakefield, 53 × 53 × 25 mm pin fin

2 m/s

MEI, 75 × 85 × 12 no adjacent board, extrusion

MEI, 75 × 85 × 12 mm, adjacent board, 40 mm side bypass

Natural convection

1 m/s

2 m/s

1 m/s

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Thermal

Accurate thermal design requires thermal modeling of the application environment using computational

fluid dynamics software which can model both the conduction cooling and the convection cooling of the

air moving through the application. Simplified thermal models of the packages can be assembled using the

junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More

detailed thermal models can be made available on request.

Heat sink vendors include the following list:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

408-567-8082

Alpha Novatech

473 Sapena Ct. #12

Santa Clara, CA 95054

Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Millennium Electronics (MEI)

Loroco Sites

671 East Brokaw Road

San Jose, CA 95112

408-436-8770

800-522-2800

603-635-5102

Internet: www.mei-thermal.com

Tyco Electronics

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Interface material vendors include the following:

Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01801

Internet: www.chomerics.com

781-935-4850

800-248-2481

Dow-Corning Corporation

Dow-Corning Electronic Materials

P.O. Box 994

Midland, MI 48686-0997

Internet: www.dowcorning.com

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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89

Thermal

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

800-347-4572

Internet: www.microsi.com

The Bergquist Company

18930 West 78th St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

20.3 Heat Sink Attachment

When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip.

The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to

the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the

package from the board. Such peeling forces reduce the solder joint lifetime of the package. The

recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive

attachment should attach to painted or plastic surfaces, and its performance should be verified under the

application requirements.

20.3.1 Experimental Determination of the Junction Temperature with a

Heat Sink

When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimize the size of the clearance to minimize the change in thermal

performance caused by removing part of the thermal interface to the heat sink. Because of the experimental

difficulties with this technique, many engineers measure the heat sink temperature and then back calculate

the case temperature using a separate measurement of the thermal resistance of the interface. From this

case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

T = T + (R

× P )

D

J

C

θJC

where:

T = junction temperature (°C)

J

T = case temperature of the package (°C)

C

R

= junction-to-case thermal resistance (°C/W)

θJC

P = power dissipation (W)

D

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System Design Information

21 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8347EA.

21.1 System Clocking

The MPC8347EA includes two PLLs:

1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The

frequency ratio between the platform and CLKIN is selected using the platform PLL ratio

configuration bits as described in Section 19.1, “System PLL Configuration.”

2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e300 core clock and the platform clock is selected using the e300 PLL ratio

configuration bits as described in Section 19.2, “Core PLL Configuration.”

21.2 PLL Power Supply Filtering

Each PLL gets power through independent power supply pins (AV 1, AV 2, respectively). The AV

DD

level should always equal to V , and preferably these voltages are derived directly from V through a

DD

low frequency filter scheme.

There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to

provide four independent filter circuits as illustrated in Figure 43, one to each of the four AV pins.

DD

Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.

The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built

with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic

(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value

capacitor.

To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the

specific AV pin being supplied. It should be possible to route directly from the capacitors to the AV

DD

pin, which is on the periphery of package, without the inductance of vias.

Figure 43 shows the PLL power supply filter circuit.

10 Ω

V_DD

AV_DD(or L2AV_DD)

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 43. PLL Power Supply Filter Circuit

21.3 Decoupling Recommendations

Due to large address and data buses and high operating frequencies, the MPC8347EA can generate

transient power surges and high frequency noise in its power supply, especially while driving large

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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System Design Information

capacitive loads. This noise must be prevented from reaching other components in the MPC8347EA

system, and the device itself requires a clean, tightly regulated source of power. Therefore, the system

designer should place at least one decoupling capacitor at each V , OV , GV , and LV pin of the

DD

device. These capacitors should receive their power from separate V , OV , GV , LV , and GND

DD

power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under

the device using a standard escape pattern. Others can surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, distribute several bulk storage capacitors around the PCB, feeding the V , OV , GV ,

DD

and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should

DD

have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also

be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk

capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

21.4 Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low

inputs should be tied to OV , GV , or LV as required. Unused active high inputs should be

DD

connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of

DD

the MPC8347EA.

21.5 Output Buffer DC Impedance

The MPC8347EA drivers are characterized over process, voltage, and temperature. For all buses, the

2

driver is a push-pull single-ended driver type (open drain for I C).

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV

0

DD

or GND. Then the value of each resistor is varied until the pad voltage is OV /2 (see Figure 44). The

DD

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals

P

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System Design Information

OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each

DD

P

N

other in value. Then, Z = (R + R ) ÷ 2.

0

P

N

OV_DD

R_N

SW2

SW1

Pad

R_P

Data

OGND

Figure 44. Driver Impedance Measurement

Two measurements give the value of this resistance and the strength of the driver current source. First, the

output voltage is measured while driving logic 1 without an external differential termination resistor. The

measured voltage is V = R

× I

. Second, the output voltage is measured while driving logic 1

1

source

with an external precision differential termination resistor of value R . The measured voltage is

term

V = (1 ÷ (1/R + 1/R )) × I

. Solving for the output impedance gives R

= R

× (V ÷ V – 1).

2

1

2

source

term 1 2

The drive current is then I

= V ÷ R

.

source

1

source

Table 69 summarizes the signal impedance targets. The driver impedance are targeted at minimum V

,

DD

nominal OV , 105°C.

DD

Table 69. Impedance Characteristics

Local Bus, Ethernet,

PCI Signals

(Not Including PCI

Output Clocks)

PCI Output Clocks

(Including

PCI_SYNC_OUT)

DUART, Control,

Configuration, Power

Management

Impedance

DDR DRAM Symbol

Unit

R

42 Target

NA

25 Target

NA

42 Target

NA

20 Target

NA

Z₀

W

N

P

Differential

Z_DIFF

Note: Nominal supply voltages. See Table 1, T_j= 105°C.

21.6 Configuration Pin Multiplexing

The MPC8347EA power-on configuration options can be set through external pull-up or pull-down

resistors of 4.7 kΩ on certain output pins (see the customer-visible configuration pins). These pins are used

as output only pins in normal operation.

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Ordering Information

However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched

when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal

function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with

the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed

for the output pins.

21.7 Pull-Up Resistor Requirements

The MPC8347EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins,

2

including I C pins, and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface,

refer to application note AN2931, “PowerQUICC Design Checklist.”

22 Ordering Information

This section presents ordering information for the device discussed in this document, and it shows an

example of how the parts are marked.

NOTE

The information in this document is accurate for revision 3.x silicon and

later (in other words, for orderable part numbers ending in A or B). For

information on revision 1.1 silicon and earlier versions, see the MPC8347E

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

(Document Order No. MPC8347EEC).

22.1 Part Numbers Fully Addressed by This Document

Table 70 shows an analysis of the Freescale part numbering nomenclature for the MPC8347EA. The

individual part numbers correspond to a maximum processor core frequency. Each part number also

contains a revision code that refers to the die mask revision number. For available frequency configuration

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Freescale Semiconductor

Ordering Information

parts including extended temperatures, refer to the device product summary page on our website listed on

the back cover of this document or, contact your local Freescale sales office.

Table 70. Part Numbering Nomenclature

MPC

nnnn

Part

e

t

pp

aa

a

r

Product

Encryption

Temperature¹

Range

Processor

Platform

Frequency

Revision

Level

Package²

Code Identifier Acceleration

Frequency³

MPC

8347

Blank = Not Blank = 0 to 105°C ZU =TBGA

e300 core

speed

D = 266

F = 333⁴

B = 3.1

included

C = –40 to 105°C VV = PB free TBGA

E = included

ZQ = PBGA

VR = PB Free PBGA

AD = 266

AG = 400

AJ = 533

AL = 667

Notes:

1. For temperature range = C, processor frequency is limited to 400 (PBGA) with a platform frequency of 266 and up to 533

(TBGA) with a platform frequency of 333

2. See Section 18, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other

maximum core frequencies.

4. ALF marked parts support DDR1 data rate up to 333 MHz (at 333 MHz CSB as the 'F' marking implies) and DDR2 data rate

up to 400 MHz (at 200 MHz CSB). AJF marked parts support DDR1 and DDR2 data rate up to 333 MHz (at a CSB of 333

MHz).

Table 71 shows the SVR settings by device and package type.

Table 71. SVR Settings

Device

Package

SVR (Rev. 3.0)

MPC8347EA

MPC8347A

MPC8347EA

MPC8347A

TBGA

PBGA

8052_0030

8053_0030

8054_0030

8055_0030

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Document Revision History

22.2 Part Marking

Parts are marked as in the example shown in Figure 45.

MPCnnnnetppaaar

core/platform MHZ

ATWLYYWW

CCCCC

*MMMMM

YWWLAZ

TBGA/

PBGA

Notes:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

Figure 45. Freescale Part Marking for TBGA or PBGA Devices

23 Document Revision History

This table provides a revision history of this document.

Table 72. Document Revision History

Rev.

Number

Date

Substantive Change(s)

12

09/2011

• In Section 2.2, “Power Sequencing,” added Section 2.2.1, “Power-Up Sequencing” and Figure 4.

• In Table 25, Table 29 and Table 31, removed the GTX_CLK125.

• In Table 34, updated t_MDKHDXMax value from 170ns to 70ns.

11

11/2010

• In Table 56, added overbar to LCS[4] and LCS[5] signals. In Table 55 and Table 56, added note

for pin LGPL4.

• In Section 21.7, “Pull-Up Resistor Requirements, updated the list of open drain type pins.

10

9

05/2010

5/2009

• In Table 25 through Table 30, changed V_IL(min) to V_IH(max) to (20%–80%).

• Added Table 8, “EC_GTX_CLK125 AC Timing Specifications.”

• In Section 18.3, “Package Parameters for the MPC8347EA PBGA, changed solder ball for TBGA

and PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag.

• In Table 58, updated frequency for DDR2, from 100-200 to 100-133 at core frequency = 533MHz.

• In Table 59, added two columns for the DDR1 and DDR2 memory bus frequency.

• In Table 70, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1

and DDR2.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Document Revision History

Table 72. Document Revision History (continued)

Rev.

Number

Date

Substantive Change(s)

8

2/2009

• Added footnote 6 to Table 7.

• In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.

• In Table 39, corrected t_LBKHOVparameter to t_LBKLOV(output data is driven on falling edge of clock

in DLL bypass mode). Similarly, made the same correction to Figure 22, Figure 24, and Figure 25

for output signals.

• Added footnote 10 and 11 to Table 55 and Table 56.

• In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.

• In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five

independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and

“the four AVDD pins.”

• In Table 58, corrected the max csb_clk to 266 MHz.

• In Table 64, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz

• Added footnote 4 to Table 70.

• In Table 70, updated note 1 to say the following: “For temperature range = C, processor frequency

is limited to 533 (TBGA) and 400 (PBGA) with a platform frequency of 266.”

7

6

4/2007

3/2007

• In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and

added USB to the seventh row.

• In Table 4, “Operating Frequencies for TBGA,” added column for 400 MHz.

• In Section 21.7, “Pull-Up Resistor Requirements,“deleted last two paragraphs and after first

paragraph, added a new paragraph.

• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”

• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.

• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to t_CISKEW

and deleted original note 3; renumbered the remaining notes.

• In Figure 43, “JTAG Interface Connection,” updated with new figure.

• In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (csb_clk)’

row, changed the value in the 533 MHz column to 100-333.

• In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK

Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz

CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306,

changed the CORE PLL value to 0000110.

• In Section 23, “Ordering Information,” replaced first paragraph and added a note.

• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.

5

1/2007

• In Table 1, “Absolute Maximum Ratings,” added (1.36 max for 667-MHz core frequency).

• In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply

voltage of 1.3 V for 667-MHz parts.

• In Table 4, “MPC8347EA Power Dissipation,” added two footnotes to 667-MHz row showing

nominal core supply voltage of 1.3 V for 667-MHz parts.

• In Table 54, “MPC8347EA (TBGA) Pinout Listing,” updated V_DDrow to show nominal core supply

voltage of 1.3 V for 667-MHz parts.

4

3

12/2006

11/2006

Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T_ddkhdsfor 333 MHz

from 900 ps to 775 ps.

• Updated note in introduction.

• In the features list in Section 1, “Overview,” updated DDR data rate to show 266 MHz for PBGA

parts for all silicon revisions, and 400 MHz for DDR2 for TBGA parts for silicon Rev. 2 and 3.

• In Table 5, “MPC8347EA Typical I/O Power Dissipation,” added GV_DD1.8-V values for DDR2;

added table footnote to designate rates that apply only to the TBGA package.

• In Section 23, “Ordering Information,” replicated note from document introduction.

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

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Document Revision History

Table 72. Document Revision History (continued)

Substantive Change(s)

Rev.

Date

Number

2

8/2006

• Changed all references to revision 2.0 silicon to revision 3.0 silicon.

• Changed VIH minimum value in Table 39, “JTAG Interface DC Electrical Characteristics,” to

OV_DD– 0.3.

• In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min

= 2 and max = OV_DD+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min

= 2 and max = OV_DD+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”

• In Table 63, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.

1

4/2006

• Removed Table 20, “Timing Parameters for DDR2-400.”

• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC

Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.

• Changed Min and Max values for V_IHand VIL in Table 40,“PCI DC Electrical Characteristics.”

• In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout

Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that

MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω

resistor.’

• In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout

Listing,” in row AVDD3 changed power supply from “AVDD3” to ‘—.’

0

3/2006

Initial public release

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98

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Document Number: MPC8347EAEC

Rev. 12

09/2011


型号：	935321128557
厂家：	NXP
描述：	RISC Microprocessor
文件：	总99页 (文件大小：1086K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935321128557 [NXP]

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