935323801557 [NXP]
RISC Microcontroller;
| 型号： | 935323801557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 |
| 文件： | 总77页 (文件大小：1485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Data Sheet: Technical Data
K22P144M120SF5V2
Rev 5, 03/2015
Kinetis K22F Sub-Family Data
MK22FX512AVLQ12
MK22FN1M0AVLQ12
MK22FX512AVMD12
MK22FN1M0AVMD12
Sheet
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K22 product family members are optimized for cost-sensitive
applications requiring low-power, USB connectivity, processing
efficiency with floating point unit. It shares the comprehensive
enablement and scalability of the Kinetis family. This product
offers:
• Up to 1 MB of flash memory with up to 128 KB of SRAM
• Small package with high memory density
• Run power consumption down to 279 μA/MHz. Static
power consumption down to 5.1 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 268 nA
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator
144 LQFP
20 x 20 x 1.6 mm Pitch 13 x 13 x 1.7 mm Pitch
0.5 mm 1 mm
144 BGA
Performance
• Up to 120 MHz ARM Cortex-M4-based core with DSP
Communication interfaces
• USB full-/low-speed On-the-Go controller
• USB Device Charger detect
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules
• Six UART modules
instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 1 MB program flash memory and 128 KB RAM
• 4 KB FlexRAM and 128 KB FlexNVM on FlexMemory
devices
• Secure Digital host controller (SDHC)
• I2S module
• FlexBus external bus interface
System peripherals
Timers
• Multiple low-power modes; low leakage wakeup unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• Two 8-channel Flex-Timers (PWM/Motor Control)
• Two 2-channel Flex-Timers (PWM/Quad Decoder)
• Periodic interrupt timers and 16-bit low-power timer
• Carrier modulator transmitter
• External watchdog monitor and software watchdog
• Real-time clock
• Programmable delay block
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
Operating Characteristics
• Three analog comparators (CMP)
• Voltage reference
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Memory
Part Number
Maximum number of I\O's
Flash (KB)
SRAM (KB)
128
MK22FX512AVLQ12
MK22FN1M0AVLQ12
MK22FX512AVMD12
MK22FN1M0AVMD12
512 KB
1 MB
100
100
100
100
128
512 KB
1 MB
128
128
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Selector
Guide
Description
Resource
Solution Advisor
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K20PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P144M50SF5V2RM1
K22P144M50SF5V21
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 144-pin:
98ASS23177W1
• MAPBGA-144 pin:
98ASA00222D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Kinetis K21/22F Family
ARM® Cortex™-M4
Core
System
Clocks
Internal
and external
watchdogs
Phase-
locked loop
Debug
Memory
protection
Frequency-
locked loop
DSP
interfaces
Floating-
point unit
Low/high
frequency
oscillators
Interrupt
DMA
controller
Internal
reference
clocks
Low-leakage
wakeup
Communication Interfaces
Analog
I2S
x1
Timers
x4 (20ch)
I2C
x2
16-bit ADC
x2
Random
Number
Generator
Secure
Digital
Analog
comparator
x3
UART
x6
Hardware
Encryption
USB OTG
LS/FS/HS
SPI
x3
6-bit DAC
x3
CAN
x1
USB LS/FS
transceiver
Tamper
detect
12-bit DAC
USB charger
detect
Voltage
reference
USB voltage
regulator
Available only in K21
LEGEND
Figure 1. K20 block diagram
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings....................................................................................5
3.4.1
3.4.2
3.4.3
Flash (FTFE) electrical specifications............... 27
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
EzPort switching specifications.........................32
Flexbus switching specifications....................... 33
3.5 Security and integrity modules........................................ 36
3.6 Analog............................................................................. 36
3.6.1
3.6.2
3.6.3
3.6.4
ADC electrical specifications.............................37
CMP and 6-bit DAC electrical specifications.....41
12-bit DAC electrical characteristics................. 43
Voltage reference electrical specifications........46
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
Voltage and current operating requirements.....7
LVD and POR operating requirements............. 8
Voltage and current operating behaviors.......... 8
Power mode transition operating behaviors......10
Power consumption operating behaviors..........10
EMC radiated emissions operating behaviors...14
Designing with radiated emissions in mind....... 15
Capacitance attributes...................................... 15
3.7 Timers..............................................................................47
3.8 Communication interfaces............................................... 47
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
USB electrical specifications.............................47
USB DCD electrical specifications.................... 48
USB VREG electrical specifications..................48
CAN switching specifications............................ 49
DSPI switching specifications (limited voltage
range)................................................................49
DSPI switching specifications (full voltage
2.3 Switching specifications...................................................15
2.3.1
2.3.2
Device clock specifications............................... 15
General switching specifications.......................16
3.8.6
range)................................................................51
I2C switching specifications.............................. 52
UART switching specifications..........................53
SDHC specifications......................................... 53
2.4 Thermal specifications.....................................................17
3.8.7
3.8.8
3.8.9
2.4.1
2.4.2
Thermal operating requirements.......................17
Thermal attributes............................................. 17
3 Peripheral operating requirements and behaviors.................. 19
3.1 Core modules.................................................................. 19
3.8.10 I2S switching specifications.............................. 54
4 Dimensions............................................................................. 66
4.1 Obtaining package dimensions....................................... 66
5 Pinout......................................................................................67
5.1 K22 Signal Multiplexing and Pin Assignments.................67
5.2 K22 Pinouts..................................................................... 73
6 Revision History...................................................................... 75
7 Copyright................................................................................. 0
8 Legal....................................................................................... 0
3.1.1
3.1.2
Debug trace timing specifications..................... 19
JTAG electricals................................................19
3.2 System modules.............................................................. 22
3.3 Clock modules................................................................. 22
3.3.1
3.3.2
3.3.3
MCG specifications........................................... 22
Oscillator electrical specifications..................... 25
32 kHz oscillator electrical characteristics.........27
3.4 Memories and memory interfaces................................... 27
4
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
–0.3
Max.
3.8
Unit
V
VDD
IDD
Digital supply voltage
Digital supply current
—
185
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog1, RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–0.3
5.5
VAIO
–0.3
VDD + 0.3
25
V
ID
–25
mA
V
VDDA
VUSB0_DP
VUSB0_DM
VBAT
VDD – 0.3
–0.3
VDD + 0.3
3.63
USB0_DP input voltage
V
USB0_DM input voltage
–0.3
3.63
V
RTC battery supply voltage
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
6
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
1.71
Max.
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
0.06 × VDD
-5
—
—
V
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
3
mA
IICAIO
Analog2, EXTAL, and XTAL pin DC injection current
— single pin
mA
-5
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
V
4
VDD voltage required to retain RAM
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
—
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
7
Freescale Semiconductor, Inc.
General
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|
IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection
currents.
4. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
8
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
General
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description
Min.
Typ
Max.
Unit
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
100
mA
1
—
—
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
—
—
0.5
0.5
V
V
IOLT
IIND
Output low current total for all ports
—
—
100
mA
Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
2, 3
• All digital pins
—
0.002
0.5
μA
• VIN = VDD
• All digital pins except PTD7
• PTD7
—
—
0.002
0.004
0.5
1
μA
μA
IIND
Input leakage current, digital pins
• VIL < VIN < VDD
2
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
18
12
8
26
19
13
6
μA
μA
μA
μA
3
IIND
Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
—
20
20
1
50
0.25
50
μA
μA
kΩ
kΩ
IOZ
RPU
RPD
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
35
35
4
5
Internal pulldown resistors
50
1. Open drain outputs must be pulled to VDD
2. Measured at VDD=3.6V
.
3. Internal pull-up/pull-down resistors disabled.
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
9
Freescale Semiconductor, Inc.
General
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
—
—
—
—
—
—
—
183
183
105
105
5.0
μs
μs
μs
μs
μs
μs
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
4.4
• VLPS → RUN
• STOP → RUN
4.4
2.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
—
—
33.57
33.51
36.2
36.1
mA
mA
Table continues on the next page...
10
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
General
Notes
3, 4
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
—
46.36
50.1
mA
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
—
46.31
57.4
49.9
—
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
—
—
—
18.2
7.2
—
—
—
—
—
mA
mA
mA
mA
mA
2
5
6
7
8
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.21
1.88
0.80
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
0.528
1.6
2.25
8
mA
mA
mA
• @ 70°C
5.2
20
• @ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
78
700
2400
3600
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
498
1300
• @ 105°C
IDD_LLS Low leakage stop mode current at 3.0 V
—
—
—
5.1
28
15
80
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
124
300
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
3.1
7.5
45
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
14.5
63.5
195
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
—
—
2.0
6.9
5
μA
μA
32
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
11
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• @ 70°C
—
30
112
μA
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
1.25
6.5
37
2.1
18.5
108
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
—
—
—
0.745
6.03
37
1.65
18
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
108
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
—
—
—
0.268
3.7
1.25
15
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
22.9
95
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
• @ 105°C
IDD_VBAT Average current when CPU is not accessing
RTC registers
9
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.68
1.2
0.8
1.56
5.3
μA
μA
μA
• @ 105°C
• @ 3.0V
3.6
• @ –40 to 25°C
• @ 70°C
—
—
—
0.81
1.45
4.3
0.96
1.89
6.33
μA
μA
μA
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
12
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
General
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in PEE mode at greater than 100 MHz frequencies
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
13
Freescale Semiconductor, Inc.
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
23
27
28
14
K
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
14
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
120
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
FB_CLK
fFLASH
Bus clock
—
—
—
—
60
50
25
25
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
fLPTMR
LPTMR clock
VLPR mode1
System and core clock
Bus clock
fSYS
fBUS
—
—
4
4
MHz
MHz
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
15
Freescale Semiconductor, Inc.
General
Table 9. Device clock specifications (continued)
Symbol
Description
Min.
—
Max.
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes
FB_CLK
fFLASH
FlexBus clock
Flash clock
—
0.8
16
25
16
8
fERCLK
External reference clock
LPTMR clock
—
fLPTMR_pin
—
fLPTMR_ERCLK LPTMR external reference clock
fFlexCAN_ERCLK FlexCAN external reference clock
—
—
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
—
12.5
4
—
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
Port rise and fall time (low drive strength)
• Slew disabled
5
16
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
General
Notes
Table 10. General switching specifications
Symbol
Description
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
Min.
Max.
Unit
—
12
ns
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Die junction temperature
Ambient temperature
TA
105
°C
2.4.2 Thermal attributes
Board type
Symbol
Descriptio 144 LQFP
n
144
MAPBGA
Unit
Notes
1
Single-layer RθJA
(1s)
Thermal
45
48
59
41
°C/W
resistance,
junction to
ambient
(natural
convection)
1
Four-layer
(2s2p)
RθJA
Thermal
36
29
°C/W
resistance,
junction to
ambient
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
17
Freescale Semiconductor, Inc.
General
Board type
Symbol
Descriptio 144 LQFP
n
144
MAPBGA
Unit
Notes
(natural
convection)
1
Single-layer RθJMA
(1s)
Thermal
36
38
48
35
°C/W
resistance,
junction to
ambient (200
ft./min. air
speed)
1
Four-layer
(2s2p)
RθJMA
Thermal
30
25
°C/W
resistance,
junction to
ambient (200
ft./min. air
speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance,
junction to
board
24
9
16
9
23
11
3
°C/W
°C/W
°C/W
2
3
4
Thermal
resistance,
junction to
case
Thermal
characterizati
on
2
2
parameter,
junction to
package top
outside
center
(natural
convection)
Notes
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/
JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of
the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
18
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
(limited to 50 MHz)
MHz
Twl
Twh
Tr
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
ns
ns
ns
ns
ns
—
—
3
Tf
3
Ts
—
—
Th
Data hold
2
TRACECLK
T
r
T
f
T
T
wh
wl
T
cyc
Figure 5. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 6. Trace data specifications
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
19
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
2.6
—
—
8
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 14. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
J4
Description
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK rise and fall times
—
3
J5
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
20
0
—
—
J6
J7
—
—
8
25
J8
25
J9
—
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
22.1
22.1
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 7. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 8. Boundary scan (JTAG) timing
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 9. Test Access Port timing
TCLK
TRST
J14
J13
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
22
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
fints_t
Iints
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
0.6
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
0.5
0.3
2
1
%fdco
%fdco
1 , 2
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
fintf_ft
fintf_t
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
—
Iintf
Internal reference (fast clock) current
—
25
—
—
—
µA
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
20.97
MHz
3, 4
frequency range
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
—
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
—
95.98
—
MHz
Jcyc_fll
FLL period jitter
ps
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
120
—
MHz
µA
PLL operating current
8
8
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
9
9
—
—
120
75
—
—
ps
ps
• fvco = 120 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 120 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
24
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description
VDD Supply voltage
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
IDDOSC Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
600
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
7.5
500
650
2.5
3.25
4
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-
power mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
—
0
—
kΩ
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
—
—
—
0.6
VDD
0.6
—
—
—
—
V
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
26
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.3 32 kHz oscillator electrical characteristics
3.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.3.2 32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
vec_extal32 Externally provided input clock amplitude
700
VBAT
mV
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT
.
3.4 Memories and memory interfaces
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm8
Program Phrase high-voltage time
thversscr Erase Flash Sector high-voltage time
thversblk128k Erase Flash Block high-voltage time for 128 KB
thversblk512k Erase Flash Block high-voltage time for 512 KB
—
13
113
904
3616
ms
ms
ms
1
1
1
—
104
416
—
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk128k
trd1blk512k
• 128 KB data flash
—
—
—
—
0.5
1.8
ms
ms
• 512 KB program flash
trd1sec4k Read 1s Section execution time (4 KB flash)
—
—
—
—
—
—
—
90
100
95
μs
μs
μs
μs
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Phrase execution time
Erase Flash Block execution time
• 128 KB data flash
40
tpgm8
150
2
tersblk128k
tersblk512k
—
—
110
435
925
ms
ms
• 512 KB program flash
3700
tersscr
Erase Flash Sector execution time
—
—
15
5
115
—
ms
ms
2
tpgmsec1k Program Section execution time (1KB flash)
Read 1s All Blocks execution time
trd1allx
• FlexNVM devices
—
—
2.2
ms
trdonce
Read Once execution time
—
—
—
—
—
90
30
—
μs
μs
ms
μs
1
tpgmonce Program Once execution time
tersall
Erase All Blocks execution time
870
—
7400
30
2
1
tvfykey
Verify Backdoor Access Key execution time
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol Description
Swap Control execution time
Min.
Typ.
Max.
Unit
Notes
tswapx01
tswapx02
tswapx04
tswapx08
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
—
—
—
—
200
90
90
—
—
150
150
30
μs
μs
μs
μs
Program Partition for EEPROM execution time
• 32 KB EEPROM backup
tpgmpart32k
tpgmpart128k
—
—
70
75
—
—
ms
ms
• 128 KB EEPROM backup
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram64k
tsetram128k
—
—
—
—
70
0.8
1.3
2.4
—
μs
ms
ms
ms
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
1.2
1.9
3.1
teewr8bers Byte-write to erased FlexRAM location
execution time
—
175
275
μs
3
Byte-write to FlexRAM execution time:
teewr8b32k
teewr8b64k
teewr8b128k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
—
—
—
385
475
650
1700
2000
2350
μs
μs
μs
teewr16bers 16-bit write to erased FlexRAM location
execution time
—
175
275
μs
16-bit write to FlexRAM execution time:
teewr16b32k
teewr16b64k
teewr16b128k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
—
—
—
385
475
650
1700
2000
2350
μs
μs
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
360
550
μs
32-bit write to FlexRAM execution time:
teewr32b32k
teewr32b64k
teewr32b128k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
—
—
—
630
810
2000
2250
2650
μs
μs
μs
1200
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current
adder during high
voltage flash
programming
operation
—
3.5
7.5
mA
IDD_ERS
Average current
adder during high
voltage flash erase
operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
nnvmcycee Cycling endurance for EEPROM backup
Write endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
20 K
2
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
• EEPROM backup to FlexRAM ratio = 4,096
70 K
630 K
2.5 M
10 M
20 M
175 K
1.6 M
6.4 M
25 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem.
Minimum and typical values assume all byte-writes to FlexRAM.
30
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycee
EEESPLIT × EEESIZE
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on
DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 11. EEPROM backup writes to FlexRAM
3.4.2 EzPort switching specifications
Table 24. EzPort switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
18
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
32
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 12. EzPort Timing Diagram
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
11.5
—
ns
1
1
2
2
0.5
8.5
0.5
ns
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
33
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
13.5
—
ns
1
1
2
2
0
ns
13.7
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
34
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB3
FB5
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 13. FlexBus read timing diagram
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
35
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 14. FlexBus write timing diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
36
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on
the differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
—
—
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
37
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 15. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
Table continues on the next page...
38
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
1.2
2.4
3.0
4.4
Typ.2
Max.
3.9
Unit
MHz
MHz
MHz
MHz
Notes
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
tADACK =
1/fADACK
4.0
6.1
clock source
fADACK
5.2
7.3
6.2
9.5
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total
unadjusted error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
—
0.7
0.2
1.0
0.5
–1.1 to
+1.9
–0.3 to 0.5
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN
VDDA
=
5
Quantization
error
0.5
ENOB Effective
number of bits
16-bit differential mode
• Avg = 32
6
bits
bits
12.8
11.9
14.5
13.8
• Avg = 4
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
• Avg = 4
Signal-to-noise See ENOB
plus distortion
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic 16-bit differential mode
7
7
dB
dB
distortion
—
—
-94
-85
—
—
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
39
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IIn
leakage
current
EIL
Input leakage
error
IIn × RAS
mV
=
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 16. Typical ENOB vs. ADC_CLK for 16-bit differential mode
40
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 17. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
41
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
42
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 30. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
43
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.3.2 12-bit DAC operating behaviors
Table 31. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
150
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
700
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
AC
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
3.7
—
μV/C
%FSR/C
μV/yr
Ω
6
0.000421
—
—
100
250
Rop
SR
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
—
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
44
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 20. Typical INL error vs. digital code
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
45
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 21. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
Notes
—
1.71
3.6
V
Operating temperature
range of the device
°C
—
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
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Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 33. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Bandgap only current
—
—
80
µA
µV
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
2
100
—
µs
—
1
Vvdrift
Voltage drift (Vmax -Vmin across the full
voltage range)
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 35. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
—
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
47
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
NOTE
The MCGFLLCLK does not meet the USB jitter
specifications for certification.
3.8.2 USB DCD electrical specifications
Table 36. USB0 DCD electrical specifications
Symbol
Description
Min.
0.5
Typ.
—
Max.
0.7
Unit
V
VDP_SRC USB_DP source voltage (up to 250 μA)
VLGC
Threshold voltage for logic high
USB_DP source current
0.8
—
2.0
V
IDP_SRC
7
10
13
μA
μA
kΩ
V
IDM_SINK USB_DM sink current
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.33
3.8.3 USB VREG electrical specifications
Table 37. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
—
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
Table continues on the next page...
48
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 37. USB VREG electrical specifications
(continued)
Symbol Description
• Run mode
• Standby mode
Min.
Typ.1
Max.
Unit
Notes
2.1
2.8
3.6
V
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
3.8.4 CAN switching specifications
See General switching specifications.
3.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
—
8.5
—
ns
ns
−2
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
49
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 38. Master mode DSPI timing (limited voltage range) (continued)
Num
DS7
DS8
Description
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
15
0
Max.
—
Unit
ns
Notes
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 22. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
15
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
17.4
—
ns
ns
2
—
ns
7
—
ns
—
—
16
16
ns
ns
50
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
Last data
DSPI_SOUT
Data
Data
DS13
First data
DSPI_SIN
Figure 23. DSPI classic SPI timing — slave mode
3.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
20.5
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
51
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 24. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
19
19
ns
ns
2
ns
7
ns
—
—
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 25. DSPI classic SPI timing — slave mode
52
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
3.8.7 I2C switching specifications
See General switching specifications.
3.8.8 UART switching specifications
See General switching specifications.
3.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. The
following timing specifications assume a load of 50 pF.
Table 42. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 8.3
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
53
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD7
SD8
Figure 26. SDHC timing
3.8.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame
sync (I2S_FS) shown in the figures below.
Table 43. I2S master mode timing
Num
Description
Min.
2.7
40
45%
80
45%
—
Max.
3.6
—
Unit
Operating voltage
V
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
0
—
—
15
0
—
15
0
—
—
54
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 27. I2S timing — master mode
Table 44. I2S slave mode timing
Num
Description
Operating voltage
Min.
Max.
3.6
—
Unit
2.7
V
S11
S12
S13
S14
S15
S16
S17
S18
S19
I2S_BCLK cycle time (input)
80
45%
4.5
2
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
ns
—
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
—
18
0
—
4.5
2
—
I2S_RXD hold after I2S_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
21
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
55
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S19
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 28. I2S timing — slave modes
3.8.10.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 45. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
80
55%
—
MCLK period
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
15
—
—
ns
ns
ns
0
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
56
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 29. I2S/SAI timing — master modes
Table 46. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
80
3.6
—
V
S11
S12
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
23.5
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
5.8
2
—
—
25
ns
ns
ns
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
57
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 30. I2S/SAI timing — slave modes
3.8.10.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
45%
—
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
58
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 31. I2S/SAI timing — master modes
Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
250
3.6
—
V
S11
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
3
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
63
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
30
2
—
—
72
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
59
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 32. I2S/SAI timing — slave modes
3.8.10.3 Ordering parts
3.8.10.3.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK22 and MK22
3.8.10.4 Part identification
3.8.10.4.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.8.10.4.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
3.8.10.4.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
60
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Values
Field
Description
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K22
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 16 = 168 MHz
• 18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
3.8.10.4.4 Example
This is an example part number:
MK22FN1M0VMD10
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
61
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.10.4.5 Small package marking
In an effort to save space, small package devices use special marking on the chip. These
markings have the following format:
Q ## C F T PP
This table lists the possible values for each field in the part number for small packages
(not all combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
##
C
Kinetis family
Speed
• 2# = K21/K22
• H = 120 MHz
F
Flash memory configuration
• K = 512 KB + Flex
• 1 = 1 MB
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LL = 100 LQFP
• MC = 121 MAPBGA
• LQ = 144 LQFP
• MD = 144 MAPBGA
• DC = 121 XFBGA
This tables lists some examples of small package marking along with the original part
numbers:
Original part number
MK22FX512VLQ12
Alternate part number
M22HKVLQ
M22H1VMD
MK22FN1M0VMD12
3.8.10.5 Terminology and guidelines
3.8.10.5.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.8.10.5.1.1 Example
This is an example of an operating requirement:
62
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.8.10.5.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
3.8.10.5.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.8.10.5.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
3.8.10.5.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.8.10.5.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
63
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.10.5.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.8.10.5.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.8.10.5.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.8.10.5.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
64
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8.10.5.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.10.5.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.10.5.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
65
Freescale Semiconductor, Inc.
Dimensions
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.8.10.5.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
98ASS23177W
Table continues on the next page...
144-pin LQFP
66
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Pinout
If you want the drawing for this package
144-pin MAPBGA
Then use this document number
98ASA00222D
98ASA00628D
169-pin MAPBGA
5 Pinout
5.1 K22 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• The analog input signals ADC0_DP2 and ADC0_DM2
on PTE2 and PTE3 are available only for K21 and K22
devices and are not present on K10 and K20 devices.
• The TRACE signals on PTE0, PTE1, PTE2, PTE3, and
PTE4 are available only for K11, K12, K21, and K22
devices and are not present on K10 and K20 devices.
• If the VBAT pin is not used, the VBAT pin should be
left floating. Do not connect VBAT pin to VSS.
• The FTM_CLKIN signals on PTB16 and PTB17 are
available only for K11, K12, K21, and K22 devices and
is not present on K10 and K20 devices. For K22D
devices this signal is on ALT7, and for K22F devices,
this signal is on ALT4.
• The FTM0_CH2 signal on PTC5/LLWU_P9 is
available only for K11, K12, K21, and K22 devices and
is not present on K10 and K20 devices.
• The I2C0_SCL signal on PTD2/LLWU_P13 and
I2C0_SDA signal on PTD3 are available only for K11,
K12, K21, and K22 devices and are not present on K10
and K20 devices.
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
D3
1
PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
TRACE_
CLKOUT
I2C1_SDA
RTC_
CLKOUT
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
67
Freescale Semiconductor, Inc.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
D2
D1
E4
2
3
4
PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT
SPI1_SCK
SPI1_SIN
UART1_RX
SDHC0_D0
TRACE_D3
TRACE_D2
TRACE_D1
I2C1_SCL
SPI1_SIN
PTE2/
LLWU_P1
ADC0_DP2/
ADC0_DP2/
PTE2/
UART1_
CTS_b
SDHC0_
DCLK
ADC1_SE6a ADC1_SE6a LLWU_P1
PTE3
ADC0_DM2/
ADC0_DM2/
PTE3
UART1_
RTS_b
SDHC0_
CMD
SPI1_SOUT
ADC1_SE7a ADC1_SE7a
E5
F6
E3
5
6
7
VDD
VSS
VDD
VDD
VSS
VSS
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
UART3_RX
SDHC0_D3
TRACE_D0
E2
E1
8
9
PTE5
PTE6
DISABLED
DISABLED
PTE5
PTE6
SPI1_PCS2
SPI1_PCS3
SDHC0_D2
I2S0_MCLK
FTM3_CH0
FTM3_CH1
UART3_
CTS_b
USB_SOF_
OUT
F4
10
PTE7
DISABLED
PTE7
UART3_
RTS_b
I2S0_RXD0
FTM3_CH2
F3
F2
11
12
PTE8
PTE9
DISABLED
DISABLED
PTE8
PTE9
I2S0_RXD1
I2S0_TXD1
UART5_TX
UART5_RX
I2S0_RX_FS
FTM3_CH3
FTM3_CH4
I2S0_RX_
BCLK
F1
G4
G3
13
14
15
PTE10
PTE11
PTE12
DISABLED
DISABLED
DISABLED
PTE10
PTE11
PTE12
UART5_
CTS_b
I2S0_TXD0
FTM3_CH5
FTM3_CH6
FTM3_CH7
UART5_
RTS_b
I2S0_TX_FS
I2S0_TX_
BCLK
E6
F7
H3
H1
H2
G1
G2
J1
16
17
18
19
20
21
22
23
24
25
26
27
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
J2
K1
K2
L1
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
L2
M1
M2
28
29
30
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
68
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
H5
G5
G6
H6
K3
31
32
33
34
35
VDDA
VDDA
VDDA
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22 ADC0_SE22 ADC0_SE22
J3
36
37
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
CMP1_IN2/
CMP1_IN2/
CMP1_IN2/
ADC0_SE21 ADC0_SE21 ADC0_SE21
M3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18 ADC1_SE18 ADC1_SE18
L3
L4
38
39
DAC0_OUT/
CMP1_IN3/
ADC0_SE23 ADC0_SE23 ADC0_SE23
DAC0_OUT/
CMP1_IN3/
DAC0_OUT/
CMP1_IN3/
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23 ADC1_SE23 ADC1_SE23
L5
—
RTC_
RTC_
RTC_
WAKEUP_B
WAKEUP_B
WAKEUP_B
M7
M6
L6
—
40
41
42
43
44
45
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
VDD
VDD
VDD
—
VSS
VSS
VSS
M4
PTE24
ADC0_SE17 ADC0_SE17 PTE24
UART4_TX
UART4_RX
EWM_OUT_
b
K5
K4
46
47
PTE25
PTE26
ADC0_SE18 ADC0_SE18 PTE25
EWM_IN
DISABLED
DISABLED
DISABLED
PTE26
PTE27
UART4_
CTS_b
RTC_
CLKOUT
USB_CLKIN
J4
48
PTE27
UART4_
RTS_b
H4
J5
49
50
PTE28
PTA0
PTE28
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
UART0_
CTS_b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
J6
51
52
PTA1
PTA2
JTAG_TDI/
EZP_DI
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
K6
JTAG_TDO/
TRACE_
SWO/
JTAG_TDO/
TRACE_
SWO
EZP_DO
EZP_DO
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
69
Freescale Semiconductor, Inc.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
K7
53
54
55
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
JTAG_TMS/
SWD_DIO
L7
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
NMI_b
EZP_CS_b
M8
PTA5
DISABLED
PTA5
USB_CLKIN
CMP2_OUT
CLKOUT
I2S0_TX_
BCLK
JTAG_
TRST_b
E7
G7
J7
56
57
58
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
DISABLED
PTA6
FTM0_CH3
TRACE_
CLKOUT
J8
59
60
PTA7
PTA8
ADC0_SE10 ADC0_SE10 PTA7
ADC0_SE11 ADC0_SE11 PTA8
FTM0_CH4
FTM1_CH0
TRACE_D3
TRACE_D2
K8
FTM1_QD_
PHA
L8
M9
L9
61
62
63
64
65
66
PTA9
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
DISABLED
PTA9
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
FTM1_QD_
PHB
TRACE_D1
TRACE_D0
PTA10
PTA11
PTA12
PTA10
PTA11
PTA12
FTM2_QD_
PHA
I2C2_SDA
I2C2_SCL
I2C2_SDA
I2C2_SCL
FTM2_QD_
PHB
K9
J9
CMP2_IN0
CMP2_IN1
CAN0_TX
CAN0_RX
SPI0_PCS0
I2S0_TXD0
FTM1_QD_
PHA
PTA13/
LLWU_P4
PTA13/
LLWU_P4
I2S0_TX_FS FTM1_QD_
PHB
L10
PTA14
PTA14
I2S0_RX_
BCLK
I2S0_TXD1
L11
K10
67
68
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
I2S0_RXD0
SPI0_SOUT
UART0_
CTS_b
I2S0_RX_FS I2S0_RXD1
K11
69
PTA17
ADC1_SE17 ADC1_SE17 PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_MCLK
E8
G8
70
71
72
VDD
VDD
VDD
VSS
VSS
VSS
M12
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_
CLKIN0
M11
73
PTA19
XTAL0
XTAL0
FTM_
CLKIN1
LPTMR0_
ALT1
L12
K12
J12
J11
J10
H12
H11
74
75
76
77
78
79
80
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
RESET_b
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
FB_A29
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
70
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
H10
81
82
83
84
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
H9
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
FTM1_QD_
PHB
G12
G11
PTB2
PTB3
ADC0_SE12 ADC0_SE12 PTB2
UART0_
RTS_b
FTM0_FLT3
ADC0_SE13 ADC0_SE13 PTB3
UART0_
CTS_b
FTM0_FLT0
G10
G9
85
86
87
88
89
PTB4
PTB5
PTB6
PTB7
PTB8
ADC1_SE10 ADC1_SE10 PTB4
ADC1_SE11 ADC1_SE11 PTB5
ADC1_SE12 ADC1_SE12 PTB6
ADC1_SE13 ADC1_SE13 PTB7
FTM1_FLT0
FTM2_FLT0
F12
F11
F10
FB_AD23
FB_AD22
FB_AD21
DISABLED
PTB8
UART3_
RTS_b
F9
90
PTB9
DISABLED
PTB9
SPI1_PCS1
UART3_
CTS_b
FB_AD20
E12
E11
H7
91
92
93
94
95
PTB10
PTB11
VSS
ADC1_SE14 ADC1_SE14 PTB10
ADC1_SE15 ADC1_SE15 PTB11
SPI1_PCS0
SPI1_SCK
UART3_RX
UART3_TX
FB_AD19
FB_AD18
FTM0_FLT1
FTM0_FLT2
VSS
VSS
VDD
F5
VDD
VDD
E10
PTB16
DISABLED
PTB16
PTB17
PTB18
PTB19
SPI1_SOUT
SPI1_SIN
CAN0_TX
CAN0_RX
UART0_RX
UART0_TX
FTM2_CH0
FTM2_CH1
FTM_
CLKIN0
FB_AD17
FB_AD16
FB_AD15
EWM_IN
E9
96
97
98
PTB17
PTB18
PTB19
DISABLED
DISABLED
DISABLED
FTM_
CLKIN1
EWM_OUT_
b
D12
D11
I2S0_TX_
BCLK
FTM2_QD_
PHA
I2S0_TX_FS FB_OE_b
FTM2_QD_
PHB
D10
D9
99
PTB20
PTB21
PTB22
PTB23
PTC0
DISABLED
DISABLED
DISABLED
DISABLED
PTB20
PTB21
PTB22
PTB23
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD31
FB_AD30
FB_AD29
FB_AD28
FB_AD14
CMP0_OUT
CMP1_OUT
CMP2_OUT
100
101
102
103
C12
C11
B12
SPI0_PCS5
ADC0_SE14 ADC0_SE14 PTC0
SPI0_PCS4
PDB0_
EXTRG
I2S0_TXD1
I2S0_TXD0
I2S0_TX_FS
B11
A12
A11
104
105
106
PTC1/
LLWU_P6
ADC0_SE15 ADC0_SE15 PTC1/
LLWU_P6
ADC0_SE4b/ ADC0_SE4b/ PTC2
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
UART1_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
FB_AD13
FB_AD12
CLKOUT
PTC2
UART1_
CTS_b
CMP1_IN0
CMP1_IN0
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
UART1_RX
I2S0_TX_
BCLK
H8
—
107
108
VSS
VDD
VSS
VDD
VSS
VDD
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
71
Freescale Semiconductor, Inc.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
A9
D8
C8
B8
A8
D7
109
110
111
112
113
114
PTC4/
LLWU_P8
DISABLED
DISABLED
CMP0_IN0
CMP0_IN1
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
I2S0_RXD0
FB_AD11
FB_AD10
FB_AD9
CMP1_OUT
CMP0_OUT
I2S0_MCLK
PTC5/
LLWU_P9
PTC5/
LLWU_P9
LPTMR0_
ALT2
FTM0_CH2
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_
EXTRG
I2S0_RX_
BCLK
PTC7
PTC8
PTC9
PTC10
PTC7
USB_SOF_
OUT
I2S0_RX_FS FB_AD8
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2 CMP0_IN2
FTM3_CH4
I2S0_MCLK
FB_AD7
FB_AD6
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3 CMP0_IN3
FTM3_CH5
I2S0_RX_
BCLK
FTM2_FLT0
FTM3_FLT0
C7
B7
115
116
ADC1_SE6b ADC1_SE6b PTC10
ADC1_SE7b ADC1_SE7b PTC11/
I2C1_SCL
I2C1_SDA
FTM3_CH6
FTM3_CH7
I2S0_RX_FS FB_AD5
PTC11/
LLWU_P11
I2S0_RXD1
FB_RW_b
FB_AD27
FB_AD26
LLWU_P11
A7
D6
117
118
PTC12
PTC13
DISABLED
DISABLED
PTC12
UART4_
RTS_b
PTC13
UART4_
CTS_b
C6
B6
—
119
120
121
122
123
PTC14
PTC15
VSS
DISABLED
DISABLED
VSS
PTC14
PTC15
UART4_RX
UART4_TX
FB_AD25
FB_AD24
VSS
VDD
—
VDD
VDD
A6
PTC16
DISABLED
PTC16
PTC17
UART3_RX
UART3_TX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b
D5
C5
124
125
PTC17
DISABLED
DISABLED
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_0_
b
PTC18
PTC19
PTC18
PTC19
UART3_
RTS_b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
B5
A5
D4
126
127
128
DISABLED
DISABLED
UART3_
CTS_b
FB_CS3_b/
FB_BE7_0_
BLS31_24_b
FB_TA_b
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
UART2_
RTS_b
FTM3_CH0
FTM3_CH1
FB_ALE/
FB_CS1_b/
FB_TS_b
PTD1
ADC0_SE5b ADC0_SE5b PTD1
UART2_
CTS_b
FB_CS0_b
72
Freescale Semiconductor, Inc.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Pinout
144
144
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
C4
129
PTD2/
LLWU_P13
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
UART2_TX
FTM3_CH2
FB_AD4
I2C0_SCL
I2C0_SDA
B4
A4
130
131
PTD3
DISABLED
DISABLED
PTD3
SPI0_SIN
FTM3_CH3
FTM0_CH4
FB_AD3
FB_AD2
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
EWM_IN
A3
A2
132
133
PTD5
ADC0_SE6b ADC0_SE6b PTD5
SPI0_PCS2
SPI0_PCS3
UART0_
CTS_b
FTM0_CH5
FTM0_CH6
FB_AD1
FB_AD0
EWM_OUT_
b
PTD6/
ADC0_SE7b ADC0_SE7b PTD6/
UART0_RX
FTM0_FLT0
LLWU_P15
LLWU_P15
M10
F8
134
135
136
137
138
139
VSS
VSS
VSS
VDD
VDD
VDD
A1
C9
B9
B3
PTD7
PTD8
PTD9
PTD10
DISABLED
DISABLED
DISABLED
DISABLED
PTD7
PTD8
PTD9
PTD10
CMT_IRO
I2C0_SCL
I2C0_SDA
UART0_TX
UART5_RX
UART5_TX
FTM0_CH7
FTM0_FLT1
FB_A16
FB_A17
UART5_
RTS_b
FB_A18
B2
140
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_
CTS_b
SDHC0_
CLKIN
FB_A19
B1
C3
141
142
143
144
—
PTD12
PTD13
PTD14
PTD15
NC
DISABLED
DISABLED
DISABLED
DISABLED
NC
PTD12
PTD13
PTD14
PTD15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FTM3_FLT0
SDHC0_D4
SDHC0_D5
SDHC0_D6
SDHC0_D7
FB_A20
FB_A21
FB_A22
FB_A23
C2
C1
SPI2_PCS1
M5
A10
B10
C10
NC
NC
NC
NC
—
NC
NC
—
NC
NC
—
NC
NC
5.2 K22 Pinouts
The below figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
73
Freescale Semiconductor, Inc.
Pinout
PTE0
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
1
108
107
106
105
104
103
102
101
100
99
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
4
VDD
5
PTC1/LLWU_P6
PTC0
VSS
6
PTE4/LLWU_P2
PTE5
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
8
PTE6
9
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
98
PTE9
97
PTE10
96
PTE11
95
PTE12
94
VDD
VSS
93
VSS
PTB11
PTB10
PTB9
92
VSS
91
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
90
PTB8
89
PTB7
88
PTB6
87
PTB5
86
PTB4
85
PTB3
84
PTB2
83
ADC0_DP0/ADC1_DP3
ADC0_DM0/ADC1_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM0/ADC0_DM3
VDDA
PTB1
82
PTB0/LLWU_P5
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
81
80
79
78
VREFH
77
VREFL
76
VSSA
75
_SE16/CMP2_IN2/ADC0_SE22
_SE16/CMP1_IN2/ADC0_SE21
74
73
Figure 33. K22 144 LQFP Pinout Diagram
74
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
PTC4/
LLWU_P8
PTC3/
LLWU_P7
PTD6/
LLWU_P15
PTD4/
LLWU_P14
PTD0/
LLWU_P12
A
B
C
D
E
F
PTC8
NC
PTC2
PTC0
A
B
C
D
E
F
PTD7
PTD5
PTC16
PTC12
PTC11/
LLWU_P11
PTC1/
LLWU_P6
PTD12
PTD15
PTD11
PTD14
PTD10
PTD13
PTE0
PTD3
PTC19
PTC18
PTC17
VDD
PTC15
PTC14
PTC13
VDD
PTC7
PTD9
PTD8
PTB21
PTB17
PTB9
PTB5
PTB1
NC
NC
PTD2/
PTC6/
LLWU_P10
PTC10
PTC9
VDD
VSS
PTB23
PTB19
PTB11
PTB7
PTB22
PTB18
PTB10
PTB6
LLWU_P13
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTC5/
LLWU_P9
PTD1
PTE3
PTB20
PTB16
PTB8
PTB4
PTE4/
LLWU_P2
PTE6
PTE5
PTE9
VDD
VDD
VSS
PTE10
PTE8
PTE12
VSS
PTE7
VDD
VSS
G
H
J
G
H
J
VOUT33
VREGIN
PTE11
PTE28
PTE27
PTE26
VREFH
VDDA
PTA0
VREFL
VSSA
PTA1
VSS
PTB3
PTB2
PTB0/
LLWU_P5
USB0_DP
ADC0_DP1
ADC1_DP1
USB0_DM
ADC0_DM1
ADC1_DM1
VSS
VSS
PTA29
PTA26
PTA17
PTA15
PTA28
PTA25
PTA24
RESET_b
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
PTA13/
LLWU_P4
PTA6
PTA3
PTA7
PTA8
PTA9
PTA27
PTA16
PTA14
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
K
L
K
L
PTE25
PTA2
PTA12
PTA11
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
RTC_
WAKEUP_B
ADC0_DM0/
ADC1_DM3
ADC0_DP0/
ADC1_DP3
PTA4/
LLWU_P3
VBAT
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
M
M
PTE24
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
1
2
3
4
5
6
7
8
9
10
11
12
Figure 34. K22 144 MAPBGA Pinout Diagram
6 Revision History
The following table provides a revision history for this document.
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
75
Freescale Semiconductor, Inc.
Revision History
Table 49. Revision History
Rev. No.
Date
11/2012
5/2013
Substantial Changes
1
2
Alpha customer release
• Updated supported part numbers and document number
• Updated section "Voltage and current operating behaviors"
• Added the following figures:
• Run mode supply current vs. core frequency
• VLPR mode supply current vs. core frequency
• Updated section "Device clock specifications"
• Updated section "Power consumption operating behaviors"
• Updated section "Power mode transition operating behaviors"
• Updated section "JTAG limited voltage range electricals"
• Updated section "MCG specifications"
• Updated section "Oscillator DC electrical specifications"
• Updated section "16-bit ADC operating conditions"
• Updated the pinouts
• Added section "Alternate part numbers for small packages"
3
8/2013
• Updated section "Power consumption operating behaviors"
• Updated the "Run mode supply current vs. core frequency" figure in section
"Diagram: Typical IDD_RUN operating behavior
4
5
11/2014
03/2015
• Updated the table "Voltage and current operating behavior"
• Format changes
• Updated supported part numbers
• Updated document number
• Updated the table "I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
• Updated the table "I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)"
76
Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.
Freescale Semiconductor, Inc.
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Document Number K22P144M120SF5V2
Revision 5, 03/2015
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