935323828557 [NXP]
RISC Microcontroller;型号: | 935323828557 |
厂家: | NXP |
描述: | RISC Microcontroller 微控制器 外围集成电路 |
文件: | 总100页 (文件大小:1695K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
KE1xFP100M168SF0
Rev. 4, 06/2019
Kinetis KE1xF with up to 512 KB
MKE1xF512VLL16
MKE1xF512VLH16
MKE1xF256VLL16
MKE1xF256VLH16
Flash
Up to 168 MHz ARM® Cortex®-M4 Based Microcontroller
The KE1xF microcontroller is built on the ARM® Cortex®-M4
processor with stronger performance and higher memory
densities in multiple packages. This device offers up to 168 MHz
performance with integrated single-precision floating point unit
(FPU) and digital signal processor (DSP). Embedded flash
memory sizes range from 256 KB to 512 KB.
100 LQFP (LL)
14x14x1.4 mm Pitch
0.5 mm
64 LQFP (LH)
10x10x1.4 mm Pitch
0.5 mm
Core Processor and System
Memory and memory interfaces
• ARM® Cortex®-M4 core, supports up to 168 MHz
frequency with 1.25 Dhrystone MIPS per MHz
• ARM Core based on the ARMv7 Architecture and
Thumb®-2 ISA
• Up to 512 KB program flash with ECC
• Up to 64 KB SRAM with ECC
• 64 KB FlexNVM with ECC for data flash and with
EEPROM emulation
• Integrated Digital Signal Processor (DSP)
• Configurable Nested Vectored Interrupt Controller
(NVIC)
• 4 KB FlexRAM for EEPROM emulation
• 8 KB I/D cache to minimize performance impact of
memory access latencies
• Single-precision Floating Point Unit (FPU)
• 16-channel DMA controller extended up to 64 channels
with DMAMUX
• Boot ROM with built in bootloader
Mixed-signal analog
• 3× 12-bit analog-to-digital converter (ADC) with up
to 16 channel analog inputs per module, up to 1M
sps
• 3× high-speed analog comparators (CMP) with
internal 8-bit digital to analog converter (DAC)
• 1× 12-bit digital to analog converter (DAC)
Reliability, safety and security
• Error-correcting code (ECC) on Flash and SRAM
memories
• System memory protection unit (MPU) module
• Flash Access Control (FAC)
• Cyclic Redundancy Check (CRC) generator module
• 128-bit unique identification (ID) number
• Internal watchdog (WDOG) with independent clock
source
• External watchdog monitor (EWM) module
• ADC self calibration feature
Timing and control
• 4× Flex Timers (FTM) for PWM generation, offering
up to 32 standard channels
• 1× Low-Power Timer (LPTMR) working at Stop
mode, with flexible wake up control
• 3× Programmable Delay Block (PDB) with flexible
trigger system, to provide accurate delay and trigger
generation for inter-module synchronization
• 1× Low-power Periodic Interrupt Timer (LPIT) with 4
independent channels, for general purpose
• Pulse Width Timer (PWT)
• On-chip clock loss monitoring
Human-machine interface (HMI)
• Supports up to 92 interrupt request (IRQ) sources
• Up to 89 GPIO pins with interrupt functionality
• 8 high drive pins
• Digital filters
• Real timer clock (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Clock interfaces
Connectivity and communications interfaces
• TriggerMUX: for module inter-connectivity
• 3× low-power universal asynchronous receiver/
transmitter (LPUART) modules with DMA support
and working at Stop mode
• 4 - 40 MHz fast external oscillator (OSC)
• 32 kHz slow external oscillator (OSC32)
• 48 MHz high-accuracy (up to 1ꢀ) fast internal
reference clock (FIRC) for high-speed run
• 8 MHz / 2 MHz high-accuracy (up to 3ꢀ) slow internal
reference clock (SIRC) for low-speed run
• 128 kHz low power oscillator (LPO)
• Phased lock loop (PLL)
• 2 low-power serial peripheral interface (LPSPI)
modules with DMA support and working at Stop
mode
• 2× low-power inter-integrated circuit (LPI2C)
modules with DMA support and working at Stop
mode
• Up to 50 MHz DC external square wave input clock
• System clock generator (SCG)
• Real time counter (RTC)
• Up to 2 ×FlexCAN modules, with flexible message
buffers and mailboxes
Power management
• FlexIO module for flexible and high performance
serial interfaces emulation
• Low-power ARM Cortex-M4 core with excellent energy
efficiency
• Power management controller (PMC) with multiple
power modes: HSRun, Run, Wait, Stop, VLPR, VLPW
and VLPS
• Supports clock gating for unused modules, and specific
peripherals remain working in low power modes
• POR, LVD/LVR
Debug functionality
• Serial Wire JTAG Debug Port (SWJ-DP) combines
• Debug Watchpoint and Trace (DWT)
• Instrumentation Trace Macrocell (ITM)
• Test Port Interface Unit (TPIU)
• Flash Patch and Breakpoints (FPB)
Operating Characteristics
• Voltage range: 2.7 to 5.5 V
• Ambient temperature range: –40 to 105 °C
Related Resources
Type
Description
Resource
KE1xF512PB 1
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KE1xFP100M168SF0RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document:
KE1xFP100M168SF0
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_E_0N79P 1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
100-LQFP: 98ASS23308W
64-LQFP: 98ASS23234W
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
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Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
NXP Semiconductors
Kinetis KE1xF Sub-Family
ARM® Cortex® -M4
System
Memories and Memory Interfaces
Clocks
OSC
Core
MPU
Program
flash
RAM
FIRC
SIRC
PLL
eDMA
Debug
interfaces
FlexMemory
DSP
Boot ROM
DMAMUX
Interrupt
controller
FPU
TRGMUX
WDOG
EWM
OSC32
LPO
Security
Communication Interfaces
Human-Machine
Interface (HMI)
Analog
Timers
and Integrity
LPI 2C
x2
FlexTimer
8ch x4
12-bit ADC
GPIO
CRC
ECC
FAC
upto 89
x3
LPUART
x3
PDB x3
LPIT, 4ch
LPTMR
High drive
I/O (8 pins)
CMP x3
12-bit DAC
x1
LPSPI
x2
Digital filters
(all ports)
FlexCAN
PMC
upto x2
SRTC
PWT
FlexIO
Figure 1. Functional block diagram
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Table of Contents
1 Ordering information............................................................... 5
5.1.1
5.1.2
5.1.3
5.1.4
Definitions......................................................... 42
2 Overview................................................................................. 5
2.1 System features...............................................................6
Examples.......................................................... 42
Typical-value conditions....................................43
Relationship between ratings and operating
requirements..................................................... 43
Guidelines for ratings and operating
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
ARM Cortex-M4 core........................................ 6
NVIC..................................................................7
AWIC.................................................................7
Memory............................................................. 8
Reset and boot..................................................8
Clock options.....................................................10
Security............................................................. 11
Power management..........................................12
Debug controller................................................13
5.1.5
requirements..................................................... 44
5.2 Ratings............................................................................ 44
5.2.1
5.2.2
5.2.3
5.2.4
Thermal handling ratings...................................44
Moisture handling ratings..................................45
ESD handling ratings........................................ 45
Voltage and current operating ratings...............45
2.2 Peripheral features.......................................................... 14
5.3 General............................................................................46
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
eDMA and DMAMUX........................................ 14
FTM...................................................................14
ADC...................................................................15
DAC...................................................................15
CMP.................................................................. 16
RTC...................................................................16
LPIT...................................................................17
PDB...................................................................17
LPTMR..............................................................18
5.3.1
5.3.2
5.3.3
Nonswitching electrical specifications...............46
Switching specifications.................................... 57
Thermal specifications...................................... 60
5.4 Peripheral operating requirements and behaviors...........63
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
System modules................................................63
Clock interface modules....................................64
Memories and memory interfaces.....................71
Security and integrity modules..........................74
Analog...............................................................74
Communication interfaces.................................82
Debug modules.................................................86
2.2.10 CRC.................................................................. 18
2.2.11 LPUART............................................................18
2.2.12 LPSPI................................................................19
2.2.13 FlexCAN............................................................19
2.2.14 LPI2C................................................................ 21
2.2.15 FlexIO................................................................21
2.2.16 Port control and GPIO.......................................22
3 Memory map........................................................................... 24
4 Pinouts.................................................................................... 26
4.1 KE1xF Signal Multiplexing and Pin Assignments............ 26
4.2 Port control and interrupt summary................................. 29
4.3 Module Signal Description Tables................................... 30
4.4 Pinout diagram................................................................ 35
4.5 Package dimensions....................................................... 37
5 Electrical characteristics..........................................................42
5.1 Terminology and guidelines.............................................42
6 Design considerations.............................................................90
6.1 Hardware design considerations..................................... 90
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Printed circuit board recommendations.............90
Power delivery system...................................... 91
Analog design................................................... 91
Digital design.....................................................92
Crystal oscillator................................................95
6.2 Software considerations.................................................. 96
7 Part identification.....................................................................97
7.1 Description.......................................................................97
7.2 Format............................................................................. 97
7.3 Fields............................................................................... 97
7.4 Example...........................................................................97
8 Revision history.......................................................................98
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Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
Comm
unicat
ion
Part number
Marking
(Line1/Line2)
Flash SRAM FlexNVM/
Pin
Packa GPIOs GPIOs ADC
FlexC
AN
(KB)
512
512
256
256
512
512
256
256
512
512
256
256
(KB)
64
64
32
32
64
64
32
32
64
64
32
32
FlexRAM count
(KB)
ge
(INT/H chann
D)1
els
MKE18F512VLL MKE18F512 /
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
64/4
100
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
89
58
89
58
89
58
89
58
89
58
89
58
89/8
16
2
2
2
2
1
1
1
1
0
0
0
0
16
VLL16
MKE18F512VL
H16
MKE18F512 /
VLH16
64
58/8
89/8
58/8
89/8
58/8
89/8
58/8
89/8
58/8
89/8
58/8
16
16
16
16
16
16
16
16
16
16
16
MKE18F256VLL MKE18F256 /
100
64
16
VLL16
MKE18F256VL
H16
MKE18F256 /
VLH16
MKE16F512VLL MKE16F512 /
100
64
16
VLL16
MKE16F512VL
H16
MKE16F512 /
VLH16
MKE16F256VLL MKE16F256 /
100
64
16
VLL16
MKE16F256VL
H16
MKE16F256 /
VLH16
MKE14F512VLL MKE14F512 /
100
64
16
VLL16
MKE14F512VL
H16
MKE14F512 /
VLH16
MKE14F256VLL MKE14F256 /
100
64
16
VLL16
MKE14F256VL
H16
MKE14F256 /
VLH16
1. INT: interrupt pin numbers; HD: high drive pin numbers
2 Overview
The following figure shows the system diagram of this device.
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NXP Semiconductors
Overview
Slave
Master
Cortex M4
M0
8 KB
IOPORT
Cache
code bus
Flash
upto 512 KB
FMC
Debug
(SWD/JTAG)
CM4 core
M1
S0
S1
NVIC
system bus
16 KB ROM
various
peripheral
blocks
upto 64 KB SRAM
M2
eDMA
S2
System Clock Generator (SCG)
Fast IRC
Slow IRC
SOSC
PLL
OSC32
LPO
Clock Source
Figure 2. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1 System features
The following sections describe the high-level system features.
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Overview
2.1.1 ARM Cortex-M4 core
The ARM Cortex-M4 is the member of the Cortex M Series of processors targeting
microcontroller cores focused on very cost sensitive, deterministic, interrupt driven
environments. The Cortex M4 processor is based on the ARMv7 Architecture and
Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and
Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP
(ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with
SIMD (single instruction multiple data) DSP style multiply-accumulates and
saturating arithmetic.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 16 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains 4 bits. It
also differs in number of interrupt sources and supports 240 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency . It also
can be used to wake the MCU core from Wait and VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect
asynchronous wake-up events in Stop mode and signal to clock control logic to
resume system clocking. After clock restarts, the NVIC observes the pending interrupt
and performs the normal interrupt or event processing. The AWIC can be used to
wake MCU core from Partial Stop, Stop and VLPS modes.
Wake-up sources for this SoC are listed as below:
Table 2. AWIC Stop and VLPS Wake-up Sources
Wake-up source
Available system resets
Pin interrupts
ADCx
Description
RESET pin, WDOG, JTAG , loss of clock(LOC) reset and loss of lock (LOL) reset
Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx is optional functional with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
CMPx
LPI2C
LPUART
LPSPI
Table continues on the next page...
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NXP Semiconductors
Overview
Table 2. AWIC Stop and VLPS Wake-up Sources (continued)
Wake-up source
LPIT
Description
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes
FlexIO
LPTMR
RTC
Functional in Stop/VLPS modes
SCG
Functional in Stop mode (Only SIRC)
CAN
CAN stop wakeup
NMI
Non-maskable interrupt
2.1.4 Memory
This device has the following features:
• Upto 512 KB of embedded program flash memory.
• Upto 64 KB of embedded SRAM accessible (read/write) at CPU clock speed with 0
wait states.
• The non-volatile memory is divided into several arrays:
• 64 KB of embedded data flash memory
• 4 KB of Emulated EEPROM
• 16 KB ROM (built-in bootloader to support UART, I2C, and SPI interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program flash
is 4 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents from
debug port.
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the footnote,
is reset by the corresponding Reset source. N means the
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Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
NXP Semiconductors
Overview
specific module is not reset by the corresponding Reset
source.
Table 3. Reset source
Reset
Descriptions
Modules
sources
PMC SIM SMC RCM
Reset
pin is
WDO SCG RTC LPTM Other
G
R
s
negated
POR reset
Power-on reset (POR)
Y
Y1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
System
resets
Low-voltage detect
(LVD)
External pin reset
(RESET)
Y1
Y1
Y1
Y2
Y2
Y2
Y3
Y3
Y3
Y4
Y4
Y4
Y
Y
Y
Y5
Y5
Y5
Y6
Y6
Y6
N
N
N
N
N
N
Y
Y
Y
Watchdog (WDOG)
reset
Multipurpose clock
generator loss of clock
(LOC) reset
Multipurpose clock
generator loss of lock
(LOL) reset
Stop mode acknowledge Y1
error (SACKERR)
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y
Y
Y5
Y5
Y6
Y6
N
N
N
N
Y
Y
Software reset (SW)
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y3
Y3
Y3
Y3
Y4
Y4
Y4
Y4
Y
Y
Y
Y
Y5
Y5
Y5
Y5
Y6
Y6
Y6
Y6
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Lockup reset (LOCKUP)
MDM DAP system reset
Debug reset Debug reset
1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Except SIM_SOPT1
3. Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT
4. Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS
5. Except WDOG_CS[TST]
6. Except SCG_CSR and SCG_FIRCSTAT
This device supports booting from:
• internal flash
• boot ROM
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NXP Semiconductors
Overview
POR or Reset
N
RCM[FORCEROM] =00
Y
N
N
FOPT[BOOTPIN_OPT]=0
Y
BOOTCFG0 pin=0
Y
N
FOPT[BOOTSRC
_SEL]=10/11
Y
Boot from ROM
Boot from Flash
Figure 3. Boot flow chart
The blank chip is default to boot from ROM and remaps the vector table to ROM base
address, otherwise, it remaps to flash address.
2.1.6 Clock options
The SCG module controls which clock source is used to derive the system clocks. The
clock generation logic divides the selected clock source into a variety of clock domains,
including the clocks for the system bus masters, system bus slaves, and flash memory .
The clock generation logic also implements module-specific clock gating to allow
granular shutoff of modules.
The following figure is a high level block diagram of the clock generation. For more
details on the clock operation and configuration, see the Clocking chapter in the
Reference Manual.
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Overview
00
01
10
11
PWT
TCLK0
TCLK1
TCLK2
00
01
SIM_CHIPCTL[PWT_CLKSEL]
10
11
FTMx
SIM_FTMOPT0[FTMxCLKSEL]
SCG
SCG_SPLLCFG[SOURCE]
1
Core
RAM
GPIOC
48 MHz
Fast
IRC
0110
÷2
PLL
PREDIV
(SCG_SPLLCFG)
0
DMAMUX
eDMA
PDB
0011
0010
default start up
DIVCORE
Flash
CORE_CLK/SYS_CLK
8MHz/2MHz
Slow
IRC
PCC
0001
FLASH_CLK
Other
DIVSLOW
DIVBUS
SYS_CLK
BUS_CLK
CRC
8-bit DAC
ACMPx
PCC_xxx[CGC]
SCG_xCCR[SCS]
(x=R, V, H)
BUSOUT
12-bit DAC
PLL_CLK
PLLDIV1_CLK
PLLDIV2_CLK
PLLDIV1
Peripheral
Registers
PLLDIV2
SIRC_CLK
FIRC_CLK
SIRCDIV1_CLK
SIRCDIV2_CLK
ADCx
FlexIO
LPIT
SIRCDIV1
SIRCDIV2
Async clock
FIRCDIV1_CLK
FIRCDIV2_CLK
FIRCDIV1
FIRCDIV2
SCG_SOSCCFG[EREFS]
LPI2Cx
0
LPUARTx
LPSPIx
SOSCDIV1_CLK
SOSCDIV2_CLK
SOSC_CLK
SOSCDIV1
SOSCDIV2
EXTAL
High Range
OSC
1
PCC_xxx[PCS]
Other 0000 0001 0011 0010 0110
SCG CLKOUT
SCG_CLKOUTCNFG
[CLKOUTSEL]
XTAL
OSC
OSC32_CR[ROSCEREFS]
0
00
WDOG
LPTMR
01
10
CLKOUTDIV
CLKOUT
EXTAL32
XTAL32
Low Range
OSC
11
1
SIM_CHIPCTL[CLKOUTSEL]
OSC32
LPO_CLK
OSC32_CLK
RTC
1kHz
LPO128K
1
÷128
EWM
PMC
00
01
10
11
32kHz
RTC_CLKIN
0
RTC_CLKOUT
RTC_CR[LPOS]
PORT Control
SIM_CHIPCTL[RTC_CLKSEL]
FlexCANx
Figure 4. Clocking block diagram
2.1.7 Security
Security state can be enabled via programming flash configure field (0x40e). After
enabling device security, the SWD/JTAG port cannot access the memory resources of
the MCU.
External interface
SWD/JTAG port
Security
Unsecure
Can't access memory source by SWD/ the debugger can write to the Flash
JTAG interface
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
2.1.7.1 Flash Access Control (FAC)
The FAC is a native or third-party configurable memory protection scheme optimized
to allow end users to utilize software libraries while offering programmable
restrictions to these libraries. The flash memory is divided into equal size segments
that provide protection to proprietary software libraries. The protection of these
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
11
NXP Semiconductors
Overview
segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access
rights for each transaction routed to the on-chip flash memory. Configurability allows
an increasing number of protected segments while supporting two levels of vendors
adding their proprietary software to a device.
2.1.7.2 Error-correcting code (ECC)
The ECC detection is also supported on Flash and SRAM memories. It supports auto
correction of one-bit error and reporting more than one-bit error.
2.1.8 Power management
The Power Management Controller (PMC) expands upon ARM’s operational modes of
Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can
be used to optimize current consumption for a wide range of applications. The WFI or
WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on ARM’s operational modes, See the ARM®
Cortex® User Guide.
The PMC provides High Speed Run (HSRUN), Normal Run (RUN), and Very Low
Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the
MCU core is active and can access all peripherals. The difference between the modes is
the maximum clock frequency of the system and therefore the power consumption. The
configuration that matches the power versus performance requirements of the
application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS) configurations in
ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the
peripherals are disabled. Depending on the requirements of the application, different
portions of the analog, logic, and memory can be retained or disabled to conserve
power.
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Overview
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC) are used to wake up the MCU from low power states.
The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The
AWIC is used to wake up the MCU core from STOP and VLPS modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 5. Peripherals states in different operational modes
Core mode
Device mode
Descriptions
Run mode
High Speed Run
In HSRun mode, MCU is able to operate at a faster frequency, and all device
modules are operational.
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode
Deep sleep
Wait
In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static
state. Stop mode retains all registers and SRAMs while maintaining Low
Voltage Detection protection. In Stop mode, the ADC, DAC, CMP, LPTMR,
RTC, and pin interrupts are operational. The NVIC is disabled, but the AWIC
can be used to wake up from an interrupt.
Very Low Power Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low
speed), ADC, OSC, RTC, LPTMR, LPIT, FlexIO, LPUART, LPI2C,LPSPI,
and DMA are operational, LVD and NVIC are disabled, AWIC is used to
wake up from interrupt.
NOTE
When the MCU is in HSRUN or VLP mode, user cannot
write FlexRAM (EEPROM), and cannot launch an FTFE
command including flash programming/erasing.
2.1.9 Debug controller
This device has extensive debug capabilities including run control and tracing
capabilities. The standard ARM debug port supports SWD/JTAG interface.
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Overview
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
2.2.1 eDMA and DMAMUX
The eDMA is a highly programmable data-transfer engine optimized to minimize any
required intervention from the host processor. It is intended for use in applications
where the data size to be transferred is statically known and not defined within the
transferred data itself. The DMA controller in this device implements 16 channels
which can be routed from up to 63 DMA request sources through DMA MUX module.
Main features of eDMA are listed below:
• All data movement via dual-address transfers: read from source, write to
destination
• 16-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• Channel activation via one of three methods
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
2.2.2 FTM
This device contains four FlexTimer modules.
The FlexTimer module (FTM) is a two-to-eight channel timer that supports input
capture, output compare, and the generation of PWM signals to control electric motor
and power management applications. The FTM time reference is a 16-bit counter that
can be used as an unsigned or signed counter.
Several key enhancements of this module are made:
• Signed up counter
• Deadtime insertion hardware
• Fault control inputs
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Overview
• Enhanced triggering functionality
• Initialization and polarity control
2.2.3 ADC
This device contains three 12-bit SAR ADC modules. The ADC module supports
hardware triggers from FTM, LPTMR, PIT, RTC, external trigger pin and CMP
output. It supports wakeup of MCU in low power mode when using internal clock
source or external crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 12-bit resolution
• Up to 16 single-ended external analog inputs
• Support 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Input clock selectable from up to four sources
• Operation in low-power modes for lower noise
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable Voltage reference: from external or alternate
• Self-Calibration mode
2.2.3.1 Temperature sensor
This device contains one temperature sensor internally connected to the input channel
of AD26, see ADC electrical characteristics for details of the linearity factor.
The sensor must be calibrated to gain good accuracy, so as to provide good linearity,
see also AN3031 for more detailed application information of the temperature sensor.
2.2.4 DAC
The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC.
The output of the DAC can be placed on an external pin or set as one of the inputs to
the analog comparator, or ADC.
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Overview
DAC module has the following features:
• On-chip programmable reference generator output. The voltage output range is
from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
• Vin can be selected from two reference sources
• Static operation in Normal Stop mode
• 16-word data buffer supported with multiple operation modes
• DMA support
2.2.5 CMP
There are three analog comparators on this device.
• Each CMP has its own independent 8-bit DAC.
• Each CMP supports up to 7 analog inputs from external pins.
• Each CMP is able to convert an internal reference from the bandgap.
• Each CMP supports internal reference from the on-chip 12-bit DAC out.
• Each CMP supports the round-robin sampling scheme. In summary, this allow the
CMP to operate independently in VLPS and Stop modes, whilst being triggered
periodically to sample up to 8 inputs. Only if an input changes state is a full wakeup
generated.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, windowed, or
digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: Shorter propagation delay at the
expense of higher power, and Low power with longer propagation delay
• DMA transfer support
• Functional in all power modes available on this MCU
• The window and filter functions are not available in STOP mode
• Integrated 8-bit DAC with selectable supply reference source and can be power
down to conserve power
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Overview
2.2.6 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the oscillator, or clock directly from RTC_CLKIN pin.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
2.2.7 LPIT
The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module
generating independent pre-trigger and trigger outputs. These timer channels can
operate individually or can be chained together. The LPIT can operate in low power
modes if configured to do so. The pre-trigger and trigger outputs can be used to
trigger other modules on the device.
This device contains one LPIT module with four channels. The LPIT generates
periodic trigger events to the DMAMUX.
2.2.8 PDB
The Programmable Delay Block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs and/or generates the interval triggers to DACs, so that the precise
timing between ADC conversions and/or DAC updates can be achieved. The PDB can
optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in
the CMP block.
The PDB module has the following capabilities:
• trigger input sources and one software trigger source
• 1 DAC refresh trigger output, for this device
• configurable PDB channels for ADC hardware trigger
• 1 pulse output, for this device
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Overview
2.2.9 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.10 CRC
This device contains one cyclic redundancy check (CRC) module which can generate
16/32-bit CRC code for error detection.
The CRC module provides a programmable polynomial, WAS, and other parameters
required to implement a 16-bit or 32-bit CRC standard.
The CRC module has the following features:
• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift
register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface
2.2.11 LPUART
This product contains three Low-Power UART modules, and can work in Stop and
VLPS modes. The module also supports 4× to 32× data oversampling rate to meet
different applications.
The LPUART module has the following features:
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Overview
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4× to 32×
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
2.2.12 LPSPI
This device contains two LPSPI modules. The LPSPI is a low power Serial Peripheral
Interface (SPI) module that supports an efficient interface to an SPI bus as a master
and/or a slave. The LPSPI can continue operating in stop modes provided an
appropriate clock is available and is designed for low CPU overhead with DMA
offloading of FIFO register accesses.
The LPSPI modules have the following features:
• Command/transmit FIFO of 4 words
• Receive FIFO of 4 words
• Host request input can be used to control the start time of an SPI bus transfer
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Overview
2.2.13 FlexCAN
This device contains two FlexCAN modules. The FlexCAN module is a communication
controller implementing the CAN protocol according to the ISO 11898-1 standard and
CAN 2.0 B protocol specifications.
Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes.
The FlexCAN module has the following features:
• Flexible mailboxes of zero to eight bytes data length
• Each mailbox configurable as receive or transmit, all supporting standard and
extended messages
• Individual Rx Mask registers per mailbox
• Full-featured Rx FIFO with storage capacity for up to six frames and automatic
internal pointer handling with DMA support
• Transmission abort capability
• Programmable clock source to the CAN Protocol Interface, either peripheral clock
or oscillator clock
• RAM not used by reception or transmission structures can be used as general
purpose RAM space
• Listen-Only mode capability
• Programmable Loop-Back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independence from the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low power modes, with programmable wake up on bus activity
• Remote request frames may be handled automatically or by software
• CAN bit time settings and configuration bits can only be written in Freeze mode
• Tx mailbox status (Lowest priority buffer or empty buffer)
• Identifier Acceptance Filter Hit Indicator (IDHIT) register for received frames
• SYNCH bit available in Error in Status 1 register to inform that the module is
synchronous with CAN bus
• CRC status for transmitted message
• Rx FIFO Global Mask register
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Overview
• Selectable priority between mailboxes and Rx FIFO during matching process
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either
128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual
masking capability
2.2.14 LPI2C
This device contains two LPI2C modules. The LPI2C is a low power Inter-Integrated
Circuit (I2C) module that supports an efficient interface to an I2C bus as a master
and/or a slave. The LPI2C can continue operating in stop modes provided an
appropriate clock is available and is designed for low CPU overhead with DMA
offloading of FIFO register accesses. The LPI2C implements logic support for
standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The
LPI2C module also complies with the System Management Bus (SMBus)
Specification, version 2.
The LPI2C modules have the following features:
• Standard, Fast, Fast+ and Ultra Fast modes are supported
• HS-mode supported in slave mode
• Multi-master support including synchronization and arbitration
• Clock stretching
• General call, 7-bit and 10-bit addressing
• Software reset, START byte and Device ID require software support
• For master mode:
• command/transmit FIFO of 4 words
• receive FIFO of 4 words
• For slave mode:
• separate I2C slave registers to minimize software overhead due to master/
slave switching
• support for 7-bit or 10-bit addressing, address range, SMBus alert and general
call address
• transmit/receive data register supporting interrupt or DMA requests
2.2.15 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to UART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/
Waveform generation. The module supports programmable baud rates independent of
bus clock frequency, with automatic start/stop bit generation.
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Overview
The FlexIO module has the following features:
• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using
remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match
modes, and continuous data transfer
• The timing of the shifter's shift, load and store events are controlled by the highly
flexible 16-bit timer assigned to the shifter
• Two or more shifters can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable on
a variety of internal or external trigger conditions with programmable trigger
polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional
output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation
2.2.16 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control, digital
filtering, and external interrupt functions. The GPIO data direction and output data
registers control the direction and output data of each pin when the pin is configured for
the GPIO function. The GPIO input data register displays the logic value on each pin
when the pin is configured for any digital function, provided the corresponding Port
Control and Interrupt module for that pin is enabled.
The following figure shows the basic I/O pad structure. Pseudo open-drain pins have
the p-channel output driver disabled when configured for open-drain operation. None of
the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above
VDD.
NOTE
The RESET_b pin is also a normal I/O pad with pseudo open-
drain.
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Overview
Digital input
IBE=1 whenever
MUX≠000
IFE
IBE
ESD
Bus
VDD
RPULL
PE
PS
Analog input
Digital output
DSE
Figure 5. I/O simplified block diagram
The PORT module has the following features:
• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.
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Memory map
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. For more details of the system memory and peripheral
locations, see the Memory Map chapter in the Reference Manual.
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Memory map
0x4000_0000
0x4000_1000
0x4000_8000
0x4000_9000
0x4000_A000
0x4000_D000
AIPS-Lite
Reserved
Note:
eDMA
The size of Flash and SRAM varies for
devices with different part numbers.
See "Ordering information" in DataSheet for details.
DMA TCD
Reserved
MPU
0x4000_E000
0x4000_F000
0x4001_0000
Reserved
GPIO controller (aliased to 400F_F000)
Reserved
0x0000_0000
Flash *
0x4002_0000
Flash memory unit
0x4002_1000
0x4002_2000
0x4002_5000
0x4002_6000
0x0007_FFFF
DMAMUX0
4003_4000: FlexCAN0
Reserved
0x0000_0000
0x07FF_FFFF
FlexCAN1
FTM3
ADC1
Code space
0x0800_0000
0x1000_0000
0x1001_0000
0x4002_7000
0x4002_8000
0x4002_C000
Reserved
Reserved
FlexNVM
Reserved
LPSPI0
0x4002_D000
0x4002_E000
0x4003_2000
0x1400_0000
0x1400_1000
0x1800_0000
LPSPI1
4003_1000: PDB1
CRC
4003_3000: PDB2
FlexRAM
Reserved
0x1C00_0000
Reserved
0x4003_3000
0x4003_6000
0x1C00_0000
PDB0
LPIT0
ROM
0x4003_7000
0x4003_8000
0x4003_9000
Boot ROM
FTM0
FTM1
FTM2
ADC0
ADC2
0x1C00_3FFF
0x1C00_4000
0x1FF0_0000
Reserved
Data Space
Reserved
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_D000
0x4003_E000
0x4004_0000
0x4004_1000
0x1FF0_0000
SRAM_L
0x2000_0000
0x2010_0000
0x2200_0000
SRAM_U
RTC
0x200F_FFFF
Aliased to SRAM_U
bit-band region
4003_F000: DAC0
0x2400_0000
0x4000_0000
LPTMR0
Reserved
Reserved
0x4004_8000
0x4004_9000
0x4004_A000
SIM
Public
peripheral
0x4000_0000
PORT A
PORT B
PORT C
PORT D
AIPS
peripherals
0x4004_B000
0x4004_C000
0x4010_0000
0x4200_0000
Reserved
0x4004_D000
Aliased to AIPS
and GPIO
bit-band region
PORT E
Reserved
0x4008_0000
Reserved
0x4004_E000
0x4005_2000
0x4005_3000
0x400F_F000
GPIO
WDOG
Reserved
PWT
0x4400_0000
0xE000_0000
0x400F_FFFF
Reserved
0xE000_0000
0x4005_6000
Reserved
0xE000_E000
System
0x4005_7000
0x4005_A000
Reserved
FlexIO
Reserved
control
space
0x4005_B000
0x4006_0000
0x4006_1000
Private
peripheral
OSC32
0xE000_F000
Reserved
EWM
TRGMUX0
0x4006_2000
0x4006_3000
0xE00F_F000
Core
0xE010_0000
0xFFFF_FFFF
TRGMUX1
SCG
ROM table
0x4006_4000
0x4006_5000
0x4006_6000
0x4006_7000
0xE00F_FFFF
Reserved
PCC
LPI2C0
LPI2C1
Reserved
0x4006_8000
0x4006_A000
LPUART0
LPUART1
0x4006_B000
0x4006_C000
0x4006_D000
0x4007_3000
0x4007_4000
LPUART2
Reserved
CMP0
CMP1
0x4007_5000
0x4007_6000
0x4007_D000
0x4007_E000
CMP2
Reserved
PMC
SMC
RCM
0x4007_F000
0x4007_FFFF
Figure 6. Memory map
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Pinouts
4 Pinouts
4.1 KE1xF Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
On this device, there are several special ADC channels which
support hardware interleave between multiple ADCs. Taking
ADC0_SE4 and ADC1_SE14 channels as an example, these
two channels can work independently, but they can also be
hardware interleaved. In the hardware interleaved mode, a
signal on the pin PTB0 can be sampled by both ADC0 and
ADC1. The interleaved mode is enabled by
SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. For more
information, see "ADC Hardware Interleaved Channels" in
the ADC chapter of Reference Manual.
100
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
—
1
10
—
—
1
VREFL/
VSS
VREFL/
VSS
VREFL/
VSS
PTE16
DISABLED
PTE16
FTM2_CH7
FTM2_CH6
FTM2_CH1
FTM2_CH0
FTM2_CH5
FTM2_CH4
FXIO_D3
FXIO_D2
FXIO_D1
FXIO_D0
FXIO_D5
FXIO_D4
TRGMUX_
OUT7
2
PTE15
PTD1
DISABLED
ADC2_SE1
ADC2_SE0
ADC2_SE13
ADC2_SE12
PTE15
PTD1
TRGMUX_
OUT6
3
ADC2_SE1
ADC2_SE0
ADC2_SE13
ADC2_SE12
FTM0_CH3
FTM0_CH2
PWT_IN1
CLKOUT
LPSPI1_SIN
LPSPI1_SCK
TRGMUX_
OUT2
4
2
PTD0
PTD0
TRGMUX_
OUT1
5
3
PTE11
PTE10
PTE11
PTE10
LPTMR0_
ALT1
TRGMUX_
OUT5
6
4
TRGMUX_
OUT4
7
8
—
5
PTE13
PTE5
DISABLED
DISABLED
PTE13
PTE5
FTM2_FLT0
FTM2_CH3
TCLK2
FTM2_QD_
PHA
CAN0_TX
CAN0_RX
FXIO_D7
FXIO_D6
EWM_IN
9
6
PTE4
DISABLED
PTE4
BUSOUT
FTM2_QD_
PHB
FTM2_CH2
EWM_OUT_b
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Pinouts
100
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
10
11
12
13
14
15
16
17
18
7
VDD
VDD
VDD
8
VDDA
VREFH
VREFL
VSS
VDDA
VDDA
9
VREFH
VREFL
VSS
VREFH
VREFL
VSS
—
—
11
12
—
13
PTB7
PTB6
PTE14
PTE3
EXTAL
XTAL
EXTAL
XTAL
PTB7
LPI2C0_SCL
LPI2C0_SDA
FTM0_FLT1
FTM0_FLT0
PTB6
PTE14
PTE3
ACMP2_IN3
DISABLED
ACMP2_IN3
FTM2_FLT1
FTM2_FLT0
LPUART2_
RTS
TRGMUX_IN6
ACMP2_OUT
19
20
21
22
23
—
—
14
15
16
PTE12
PTD17
PTD16
PTD15
PTE9
DISABLED
DISABLED
ACMP2_IN0
ACMP2_IN1
PTE12
PTD17
PTD16
PTD15
PTE9
FTM0_FLT3
FTM0_FLT2
FTM0_CH1
FTM0_CH0
FTM0_CH7
LPUART2_TX
LPUART2_RX
ACMP2_IN0
ACMP2_IN1
ACMP2_IN2/
DAC0_OUT
ACMP2_IN2/
DAC0_OUT
LPUART2_
CTS
24
25
26
27
28
29
—
—
17
18
19
20
PTD14
PTD13
PTE8
PTB5
PTB4
PTC3
DISABLED
DISABLED
ACMP0_IN3
DISABLED
ACMP1_IN2
PTD14
PTD13
PTE8
PTB5
PTB4
PTC3
FTM2_CH5
FTM2_CH4
FTM0_CH6
FTM0_CH5
FTM0_CH4
FTM0_CH3
CLKOUT
RTC_CLKOUT
ACMP0_IN3
ACMP1_IN2
LPSPI0_PCS1
LPSPI0_SOUT
CAN0_TX
TRGMUX_IN0
TRGMUX_IN1
ACMP1_OUT
ADC0_SE11/
ACMP0_IN4/
EXTAL32
ADC0_SE11/
ACMP0_IN4/
EXTAL32
30
21
PTC2
ADC0_SE10/
ACMP0_IN5/
XTAL32
ADC0_SE10/
ACMP0_IN5/
XTAL32
PTC2
FTM0_CH2
CAN0_RX
31
32
33
22
23
24
PTD7
PTD6
PTD5
DISABLED
DISABLED
DISABLED
PTD7
PTD6
PTD5
LPUART2_TX
LPUART2_RX
FTM2_CH3
FTM2_FLT3
FTM2_FLT2
FTM2_FLT1
LPTMR0_
ALT2
PWT_IN2
TRGMUX_IN7
34
35
36
—
—
—
PTD12
PTD11
PTD10
DISABLED
DISABLED
DISABLED
PTD12
PTD11
PTD10
FTM2_CH2
FTM2_CH1
FTM2_CH0
LPI2C1_HREQ
LPUART2_
RTS
FTM2_QD_
PHA
LPUART2_
CTS
FTM2_QD_
PHB
37
38
39
—
—
25
VSS
VSS
VDD
VSS
VDD
VDD
PTC1
ADC0_SE9/
ACMP1_IN3
ADC0_SE9/
ACMP1_IN3
PTC1
PTC0
FTM0_CH1
FTM0_CH0
FTM1_CH7
FTM1_CH6
40
26
PTC0
ADC0_SE8/
ACMP1_IN4
ADC0_SE8/
ACMP1_IN4
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27
NXP Semiconductors
Pinouts
100
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
41
42
43
44
45
—
—
27
28
29
PTD9
ACMP1_IN5
DISABLED
ACMP1_IN5
PTD9
LPI2C1_SCL
LPI2C1_SDA
FTM1_FLT3
FTM1_FLT2
FTM1_CH3
FTM2_FLT3
FTM2_FLT2
LPI2C1_SCLS
LPI2C1_SDAS
FTM1_CH5
FTM1_CH4
PTD8
PTD8
PTC17
PTC16
PTC15
ADC0_SE15
ADC0_SE14
ADC0_SE15
ADC0_SE14
PTC17
PTC16
PTC15
ADC0_SE13/
ACMP2_IN4
ADC0_SE13/
ACMP2_IN4
46
47
48
30
31
32
PTC14
PTB3
PTB2
ADC0_SE12/
ACMP2_IN5
ADC0_SE12/
ACMP2_IN5
PTC14
PTB3
PTB2
FTM1_CH2
FTM1_CH1
FTM1_CH0
ADC0_SE7
ADC0_SE7
LPSPI0_SIN
LPSPI0_SCK
FTM1_QD_
PHA
TRGMUX_IN2
TRGMUX_IN3
ADC0_SE6
ADC0_SE6
FTM1_QD_
PHB
49
50
51
52
53
54
—
—
—
—
33
34
PTC13
PTC12
PTC11
PTC10
PTB1
DISABLED
DISABLED
DISABLED
DISABLED
ADC0_SE5
ADC0_SE4
PTC13
PTC12
PTC11
PTC10
PTB1
FTM3_CH7
FTM3_CH6
FTM3_CH5
FTM3_CH4
LPUART0_TX
LPUART0_RX
FTM2_CH7
FTM2_CH6
ADC0_SE5
ADC0_SE4
LPSPI0_SOUT TCLK0
PTB0
PTB0
LPSPI0_PCS0 LPTMR0_
ALT3
PWT_IN3
55
56
57
58
59
35
36
37
38
39
PTC9
PTC8
PTA7
PTA6
PTE7
ADC2_SE15
ADC2_SE14
ADC2_SE15
ADC2_SE14
PTC9
PTC8
PTA7
PTA6
PTE7
LPUART1_TX
LPUART1_RX
FTM0_FLT2
FTM0_FLT1
FTM0_CH7
FTM1_FLT1
FTM1_FLT0
RTC_CLKIN
LPSPI1_PCS1
FTM3_FLT0
LPUART0_
RTS
LPUART0_
CTS
ADC0_SE3/
ACMP1_IN1
ADC0_SE3/
ACMP1_IN1
LPUART1_
RTS
ADC0_SE2/
ACMP1_IN0
ADC0_SE2/
ACMP1_IN0
LPUART1_
CTS
ADC2_SE2/
ACMP2_IN6
ADC2_SE2/
ACMP2_IN6
60
61
62
63
64
65
66
67
68
69
40
41
—
—
—
—
—
42
43
44
VSS
VSS
VSS
VDD
VDD
VDD
PTA17
PTB17
PTB16
PTB15
PTB14
PTB13
PTB12
PTD4
DISABLED
ADC2_SE3
ADC1_SE15
ADC1_SE14
ADC1_SE9
ADC1_SE8
ADC1_SE7
PTA17
PTB17
PTB16
PTB15
PTB14
PTB13
PTB12
PTD4
FTM0_CH6
FTM0_CH5
FTM0_CH4
FTM0_CH3
FTM0_CH2
FTM0_CH1
FTM0_CH0
FTM0_FLT3
FTM3_FLT0
LPSPI1_PCS3
LPSPI1_SOUT
LPSPI1_SIN
LPSPI1_SCK
FTM3_FLT1
FTM3_FLT2
FTM3_FLT3
EWM_OUT_b
ADC2_SE3
ADC1_SE15
ADC1_SE14
ADC1_SE9
ADC1_SE8
ADC1_SE7
ADC1_SE6/
ACMP1_IN6
ADC1_SE6/
ACMP1_IN6
70
71
72
45
46
47
PTD3
PTD2
PTA3
NMI_b
ADC1_SE3
ADC1_SE2
ADC1_SE1
PTD3
PTD2
PTA3
FTM3_CH5
FTM3_CH4
FTM3_CH1
LPSPI1_PCS0 FXIO_D5
LPSPI1_SOUT FXIO_D4
TRGMUX_IN4
TRGMUX_IN5
LPUART0_TX
NMI_b
ADC1_SE2
ADC1_SE1
LPI2C0_SCL
EWM_IN
28
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Pinouts
100
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP
73
74
75
76
77
78
48
—
—
—
—
49
PTA2
ADC1_SE0
ADC2_SE8
ADC2_SE9
ADC2_SE10
ADC2_SE11
ADC1_SE0
ADC2_SE8
ADC2_SE9
ADC2_SE10
ADC2_SE11
PTA2
FTM3_CH0
FTM3_CH3
FTM3_CH2
FTM3_CH1
FTM3_CH0
FTM1_CH1
LPI2C0_SDA
LPI2C0_HREQ
LPI2C0_SDAS
LPI2C0_SCLS
EWM_OUT_b
LPUART0_RX
PTB11
PTB10
PTB9
PTB8
PTA1
PTB11
PTB10
PTB9
PTB8
PTA1
ADC0_SE1/
ACMP0_IN1
ADC0_SE1/
ACMP0_IN1
LPI2C0_SDAS FXIO_D3
FTM1_QD_
PHA
LPUART0_
RTS
TRGMUX_
OUT0
79
50
PTA0
ADC0_SE0/
ACMP0_IN0
ADC0_SE0/
ACMP0_IN0
PTA0
FTM2_CH1
LPI2C0_SCLS
FXIO_D2
FTM2_QD_
PHA
LPUART0_
CTS
TRGMUX_
OUT3
80
81
82
83
84
51
52
—
—
53
PTC7
PTC6
PTA16
PTA15
PTE6
ADC1_SE5
ADC1_SE4
ADC1_SE13
ADC1_SE12
ADC1_SE5
ADC1_SE4
ADC1_SE13
ADC1_SE12
PTC7
PTC6
PTA16
PTA15
PTE6
LPUART1_TX
LPUART1_RX
FTM1_CH3
CAN1_TX
FTM3_CH3
FTM3_CH2
CAN1_RX
LPSPI1_PCS2
LPSPI0_PCS3
FTM1_CH2
ADC1_SE11/
ACMP0_IN6
ADC1_SE11/
ACMP0_IN6
LPSPI0_PCS2
FTM3_CH7
FTM3_CH6
LPUART1_
RTS
85
54
PTE2
ADC1_SE10
ADC1_SE10
PTE2
LPSPI0_SOUT LPTMR0_
ALT3
PWT_IN3
LPUART1_
CTS
86
87
88
89
90
91
92
—
—
—
55
56
57
58
VSS
VSS
VSS
VDD
VDD
VDD
PTA14
PTA13
PTA12
PTA11
PTA10
DISABLED
ADC2_SE4
ADC2_SE5
DISABLED
PTA14
PTA13
PTA12
PTA11
PTA10
FTM0_FLT0
FTM1_CH7
FTM1_CH6
FTM1_CH5
FTM1_CH4
FTM3_FLT1
CAN1_TX
EWM_IN
FTM1_FLT0
BUSOUT
ADC2_SE4
ADC2_SE5
LPI2C1_SCLS
LPI2C1_SDAS
FXIO_D1
CAN1_RX
LPUART0_RX
LPUART0_TX
JTAG_TDO/
noetm_Trace_
SWO
FXIO_D0
JTAG_TDO/
noetm_Trace_
SWO
93
94
95
59
60
61
PTE1
PTE0
PTC5
ADC2_SE6
ADC2_SE7
JTAG_TDI
ADC2_SE6
ADC2_SE7
PTE1
PTE0
PTC5
LPSPI0_SIN
LPSPI0_SCK
FTM2_CH0
LPI2C0_HREQ LPI2C1_SCL
TCLK1 LPI2C1_SDA
FTM1_FLT1
FTM1_FLT2
RTC_CLKOUT LPI2C1_HREQ
FTM2_QD_
PHB
JTAG_TDI
96
62
PTC4
JTAG_TCLK/
SWD_CLK
ACMP0_IN2
PTC4
FTM1_CH0
RTC_CLKOUT
EWM_IN
FTM1_QD_
PHB
JTAG_TCLK/
SWD_CLK
97
98
63
64
PTA5
PTA4
RESET_b
PTA5
PTA4
TCLK1
JTAG_TRST_b RESET_b
JTAG_TMS/
SWD_DIO
ACMP0_OUT
EWM_OUT_b
JTAG_TMS/
SWD_DIO
99
—
—
PTA9
PTA8
DISABLED
DISABLED
PTA9
PTA8
FXIO_D7
FXIO_D6
FTM3_FLT2
FTM3_FLT3
FTM1_FLT3
100
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NXP Semiconductors
Pinouts
4.2 Port control and interrupt summary
The following table provides more information regarding the Port Control and Interrupt
configurations.
Table 6. Ports summary
Feature
Port A
Port B
Yes
Port C
Port D
Port E
Yes
Pull select control Yes
Yes
Yes
Pull select at reset PTA4/PTA5=Pull
up, Others=No
No
PTC5=Pull up,
Others=No
PTD3=Pull up,
Others=No
No
Pull enable control Yes
Yes
Yes
Yes
Yes
Pull enable at reset PTA4/
PTA5=Enabled;
Disabled
PTC4/
PTC5=Enabled;
Others=Disabled
PTD3=Enabled;
Others=Disabled
Disabled
Others=Disabled
Passive filter
enable control
PTA5=Yes;
Others=No
No
No
PTD3=Yes;
Others=No
No
Passive filter
enable at reset
PTA5=Enabled;
Others=Disabled
Disabled
Disabled
Disabled
PTB4/PTB5 only
Disabled
Disabled
Disabled
Disabled
No
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTE0/PTE1 only
Disabled
Open drain enable Disabled
control
Open drain enable Disabled
at reset
Drive strength
enable control
No
PTD0/PTD1/
PTD15/PTD16 only
Drive strength
enable at reset
Disabled
Disabled
Yes
Disabled
Pin mux control Yes
Yes
Yes
Yes
Pin mux at reset PTA4/PTA5/
PTA10=ALT7;
ALT0
PTC4/PTC5=ALT7; PTD3=ALT7;
ALT0
Others=ALT0
Others=ALT0
Others=ALT0
Lock bit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt and DMA Yes
request
Digital glitch filter Yes
Yes
Yes
Yes
Yes
4.3 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used in
the module's chapter. They also briefly describe the signal function and direction.
30
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NXP Semiconductors
Pinouts
4.3.1 Core Modules
Table 7. JTAG Signal Descriptions
Chip signal name
JTAG_TMS
Module signal
name
Description
I/O
I/O
I
JTAG_TMS/
SWD_DIO
JTAG Test Mode Selection
JTAG Test Clock
JTAG_TCLK
JTAG_TCLK/
SWD_CLK
JTAG_TDI
JTAG_TDI
JTAG Test Data Input
JTAG Test Data Output
I
JTAG_TDO
JTAG_TDO/
O
TRACE_SWO
JTAG_TRST_b
JTAG_TRST_b
JTAG Reset
I
Table 8. SWD Signal Descriptions
Chip signal name
SWD_CLK
Module signal
Description
I/O
I
name
JTAG_TCLK/
SWD_CLK
Serial Wire Clock
Serial Wire Data
SWD_DIO
JTAG_TMS/
SWD_DIO
I/O
Table 9. TPIU Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TRACE_SWO
JTAG_TDO/
TRACE_SWO
Trace output data from the ARM CoreSight debug block over a
single pin
O
4.3.2 System Modules
Table 10. System Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
NMI_b
—
Non-maskable interrupt NOTE: Driving the NMI signal low forces
a non-maskable interrupt, if the NMI function is selected on the
corresponding pin.
I
RESET_b
VDD
—
—
—
Reset bidirectional signal
MCU power
I/O
I
I
VSS
MCU ground
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NXP Semiconductors
Pinouts
Table 11. EWM Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
EWM_IN
EWM_in
EWM input for safety status of external safety circuits. The polarity
of EWM_IN is programmable using the EWM_CTRL[ASSIN] bit.
The default polarity is active-low.
I
EWM_OUT_b
EWM_out
EWM reset out signal
O
4.3.3 Clock Modules
Table 12. OSC (in SCG) Signal Descriptions
Chip
signal
name
Module signal name
Description
I/O
EXTAL
XTAL
EXTAL
XTAL
External clock/Oscillator input
Oscillator output
I
O
Table 13. RTC Oscillator (OSC32) Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
EXTAL32
XTAL32
EXTAL32
XTAL32
32.768 kHz oscillator input
32.768 kHz oscillator output
I
O
4.3.4 Analog
Table 14. ADCn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
AD[15:0]
VREFSH
VREFSL
VDDA
ADCn_SE[15:0]
VREFH
Single-Ended Analog Channel Inputs
Voltage Reference Select High
Voltage Reference Select Low
Analog Power Supply
I
I
I
I
VREFL
VDDA
Table 15. DAC0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
DAC0_OUT
—
DAC output
O
32
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NXP Semiconductors
Pinouts
Table 16. ACMPn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
IN[ 6:0]
CMPO
ACMPn_IN[ 6:0]
ACMPn_OUT
Analog voltage inputs
Comparator output
I
O
4.3.5 Timer Modules
Table 17. LPTMR0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPTMR0_ALT[3:1]
LPTMR_ALTn
Pulse Counter Input pin
I
Table 18. RTC Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
RTC_CLKOUT
RTC_CLKOUT
1 Hz square-wave output or 32 kHz clock
O
Table 19. FTMn Signal Descriptions
Chip signal name Module signal name Description
I/O
FTMn_CH[7:0]
FTMn_FLT[3:0]
TCLK[2:0]
CHn
FTM channel (n), where n can be 7-0
Fault input (j), where j can be 3-0
I/O
FAULTj
EXTCLK
I
I
External clock. FTM external clock can be selected to drive the
FTM counter.
4.3.6 Communication Interfaces
Table 20. CANn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
CAN Rx
CAN Tx
CANn_RX
CANn_TX
CAN Receive Pin
CAN Transmit Pin
I
O
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33
NXP Semiconductors
Pinouts
Table 21. LPSPIn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
SOUT
SIN
LPSPIn_SOUT
LPSPIn_SIN
Serial Data Out
Serial Data In
O
I
LPSPIn_SCK
SCK
Serial Clock
I/O
I/O
LPSPIn_PCS[3:0]
PCS[3:0]
Peripheral Chip Select 0-3
Table 22. LPI2Cn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPI2Cn_SCL
LPI2Cn_SDA
LPI2Cn_HREQ
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
I
SDA
HREQ
Host request, can initiate an LPI2C master transfer if asserted and
the I2C bus is idle.
LPI2Cn_SCLS
LPI2Cn_SDAS
SCLS
SDAS
Secondary I2C clock line.
Secondary I2C data line.
I/O
I/O
Table 23. LPUARTn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPUARTn_TX
LPUARTn_RX
LPUARTn_CTS
LPUARTn_RTS
LPUART_TXD
LPUART_RXD
LPUART_CTS
LPUART_RTS
Transmit data
Receive data
Clear to send
Request to send
I/O
I
I
O
Table 24. FlexIO Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
FXIO_D[7:0]
FXIO_D[7:0]
Bidirectional FlexIO Shifter and Timer pin inputs/outputs
I/O
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NXP Semiconductors
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
Pinouts
4.3.7 Human-Machine Interfaces (HMI)
Table 25. GPIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[17:0]
PTB[17:0]
PTC[17:0]
PTD[17:0]
PTE[16:0]
PORTA17–PORTA0 General-purpose input/output
PORTB17–PORTB0 General-purpose input/output
PORTC17–PORTC0 General-purpose input/output
PORTD17–PORTD0 General-purpose input/output
PORTE16–PORTE0 General-purpose input/output
I/O
I/O
I/O
I/O
I/O
4.4 Pinout diagram
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous table of Pin Assignments.
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
35
NXP Semiconductors
Pinouts
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE16
PTE15
PTD1
PTB10
PTB11
PTA2
2
3
4
PTA3
PTD0
5
PTD2
PTD3
PTD4
PTB12
PTB13
PTB14
PTB15
PTB16
PTB17
PTA17
VDD
PTE11
PTE10
PTE13
PTE5
6
7
8
9
PTE4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
VDDA
VREFH
VREFL
VSS
PTB7
VSS
PTB6
PTE7
PTA6
PTE14
PTE3
PTA7
PTE12
PTD17
PTD16
PTD15
PTE9
PTC8
PTC9
PTB0
PTB1
PTC10
PTC11
PTD14
PTD13
Figure 7. 100 LQFP Pinout Diagram
36
NXP Semiconductors
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
Pinouts
PTD1
PTD0
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTA2
PTA3
PTD2
PTD3
PTD4
PTB12
PTB13
VDD
2
PTE11
PTE10
PTE5
3
4
5
PTE4
6
VDD
7
VDDA
8
VREFH
VREFL / VSS
PTB7
9
VSS
10
11
12
13
14
15
16
PTE7
PTA6
PTA7
PTC8
PTC9
PTB0
PTB1
PTB6
PTE3
PTD16
PTD15
PTE9
Figure 8. 64 LQFP Pinout Diagram
4.5 Package dimensions
The following figures show the dimensions of the package options for the devices
supported by this document.
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
37
NXP Semiconductors
Pinouts
Figure 9. 100-pin LQFP package dimensions 1
38
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
NXP Semiconductors
Pinouts
Figure 10. 100-pin LQFP package dimensions 2
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
39
NXP Semiconductors
Pinouts
Figure 11. 64-pin LQFP package dimensions 1
40
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
NXP Semiconductors
Pinouts
Figure 12. 64-pin LQFP package dimensions 2
Kinetis KE1xF with up to 512 KB Flash, Rev. 4, 06/2019
41
NXP Semiconductors
Electrical characteristics
5 Electrical characteristics
5.1 Terminology and guidelines
5.1.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
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5.1.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
5.1.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
5.0
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5.1.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
5.1.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
5.2 Ratings
5.2.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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5.2.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2.3 ESD handling ratings
Symbol
VHBM
Description
Min.
Max.
Unit
Notes
Electrostatic discharge voltage, human body model
− 6000
6000
V
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
All pins except the corner pins
Corner pins only
− 500
− 750
− 100
500
750
100
V
V
ILAT
Latch-up current at ambient temperature upper limit
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2.4 Voltage and current operating ratings
NOTE
Functional operating conditions appear in the "DC electrical
specifications". Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed. Stress beyond the listed maximum values may
affect device reliability or cause permanent damage to the
device.
Table 26. Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
5.8 1
80
Unit
V
Supply voltage
IDD
Digital supply current
mA
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Table 26. Voltage and current operating ratings (continued)
Symbol
VIO
Description
Min.
VSS – 0.3
–25
Max.
VDD + 0.3
25
Unit
V
IO pin input voltage
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.1
VDD + 0.1
V
1. 60s lifetime - No restrictions, i.e. the part can switch.
10 hours lifetime - Device in reset, i.e. the part cannot switch.
5.3 General
5.3.1 Nonswitching electrical specifications
5.3.1.1 Voltage and current operating requirements
Table 27. Voltage and current operating requirements
Symbol Description
Min.
2.7
Max.
5.5
Unit
V
Notes
VDD
Supply voltage
VDDA
Analog supply voltage
VDD-to-VDDA differential voltage
2.7
5.5
V
VDD
–
– 0.1
0.1
V
VDDA
VSS
–
VSS-to-VSSA differential voltage
– 0.1
0.1
V
VSSA
IICIO
DC injection current — single pin
VIN < VSS - 0.3 V (Negative current injection)
VIN > VDD + 0.3 V (Positive current injection)
− 3
—
—
mA
mA
1
2
+ 3
IICcont
Contiguous pin DC injection current —
regional limit, includes sum of negative
injection currents or sum of positive injection
currents of 16 contiguous pins
− 25
VDD
+ 25
VDD
mA
V
VODPU Open drain pullup voltage level
1. All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater
than VDD + 0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VSS – 0.3V–VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=[VIN–(VDD + 0.3V)]/|IICIO|.
The actual resistor values should be an order of magnitude higher to tolerate transient voltages.
2. Open drain outputs must be pulled to VDD
.
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5.3.1.2 DC electrical specifications at 3.3 V Range and 5.0 V Range
Table 28. DC electrical specifications
Symbol
Parameter
Value
Typ
3.3
Unit
Notes
Min
Max
VDD
I/O Supply Voltage 1
2.7
4
V
@ VDD = 3.3 V
@ VDD = 5.0 V
4
—
—
5.5
V
V
Vih
Input Buffer High Voltage
@ VDD = 3.3 V
0.7 × VDD
VDD + 0.3
@ VDD = 5.0 V
0.65 × VDD
VSS − 0.3
—
—
VDD + 0.3
0.3 × VDD
V
V
Vil
Input Buffer Low Voltage
@ VDD = 3.3 V
@ VDD = 5.0 V
VSS − 0.3
—
0.35 ×
VDD
V
Vhys
Input Buffer Hysteresis
0.06 × VDD
2.8
—
—
—
—
V
Ioh_5
Normal drive I/O current source capability
measured when pad = (VDD − 0.8 V)
mA
@ VDD = 3.3 V
@ VDD = 5.0 V
4.8
2.4
—
—
—
—
mA
mA
Iol_5
Ioh_20
Iol_20
Normal drive I/O current sink capability
measured when pad = 0.8 V
@ VDD = 3.3 V
@ VDD = 5.0 V
4.4
—
—
—
—
mA
mA
High drive I/O current source capability
measured when pad = (VDD − 0.8 V), 2
10.8
@ VDD = 3.3 V
@ VDD = 5.0 V
18.5
10.1
—
—
—
—
mA 3
mA
High drive I/O current sink capability measured
when pad = 0.8 V4
@ VDD = 3.3 V
@ VDD = 5.0 V
18.5
—
—
—
—
mA 3
nA
I_leak
VOH
Hi-Z (Off state) leakage current (per pin)
Output high voltage
300
5, 6
7
Normal drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = − VDD – 0.8
2.8 mA)
—
—
—
—
—
—
—
V
V
Normal drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = − VDD – 0.8
4.8 mA)
High drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
10.8 mA)
VDD – 0.8
VDD – 0.8
—
—
V
High drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
18.5 mA)
—
V
IOHT
Output high current total for all ports
100
mA
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Symbol
Table 28. DC electrical specifications (continued)
Parameter
Value
Typ
Unit
Notes
Min
Max
VOL
Output low voltage
7
Normal drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
2.8 mA)
—
—
—
—
—
—
—
—
—
—
0.8
0.8
0.8
0.8
100
V
V
Normal drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
4.8 mA)
High drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
10.8 mA)
V
High drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
18.5 mA)
V
IOLT
IIN
Output low current total for all ports
mA
Input leakage current (per pin) for full temperature range
@ VDD = 3.3 V
8, 7
All pins other than high drive port pins
High drive port pins
—
—
0.002
0.004
0.5
0.5
μA
μA
Input leakage current (per pin) for full temperature range
@ VDD = 5.5 V
All pins other than high drive port pins
High drive port pins
Internal pull-up resistors
@ VDD = 3.3 V
—
—
20
0.005
0.010
—
0.5
0.5
65
μA
μA
kΩ
RPU
9
@ VDD = 5.0 V
20
20
—
—
50
65
kΩ
kΩ
RPD
Internal pull-down resistors
@ VDD = 3.3 V
10
@ VDD = 5.0 V
20
—
50
kΩ
1. Max power supply ramp rate is 500 V/ms.
2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value
given above.
3. The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.
4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value given
above.
5. Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).
6. Maximum pin leakage current at the ambient temperature upper limit.
7. PTD0, PTD1, PTD15, PTD16, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability
selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
8. Refers to the pin leakage on the GPIOs when they are OFF.
9. Measured at VDD supply voltage = VDD min and input V = VSS
10. Measured at VDD supply voltage = VDD min and input V = VDD
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5.3.1.3 Voltage regulator electrical characteristics
C
DEC
VDD
VDD
VDDA
VDDA
VDD
100 LQFP
Package
64 LQFP
Package
VREFH
VREFL
VDD
VSS
VREFH
VSS
VREFL / VSS
VSS
C
DEC
Figure 13. Pinout decoupling
Table 29. Voltage regulator electrical characteristics
Symbol
Description
Min.
—
Typ.
100
100
Max.
—
Unit
nF
, 1, 2
CREF
ADC reference high decoupling capacitance
Recommended decoupling capacitance
2, 3
CDEC
—
—
nF
1. For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.
2. The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins.
3. The requirement and value of of CDEC will be decided by the device application requirement.
NOTE
For 64 LQFP, the external decoupling capacitor CDEC must
be added, and the minimum value is 100 nF.
5.3.1.4 LVR, LVD and POR operating requirements
Table 30. VDD supply LVR, LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Rising and Falling VDD POR detect
voltage
1.1
1.6
2.0
V
VLVRX
LVRX falling threshold (RUN, HSRUN,
and STOP modes)
2.53
2.58
2.64
V
LVRX hysteresis
—
45
—
mV
V
1
VLVRX_HYST
VLVRX_LP
LVRX falling threshold (VLPS/VLPR
modes)
1.97
2.12
2.44
VLVRX_LP_HYST LVRX hysteresis (VLPS/VLPR modes)
VLVD Falling low-voltage detect threshold
—
40
—
3
mV
V
2.8
2.88
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Table 30. VDD supply LVR, LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
LVD hysteresis
—
50
—
mV
1
VLVD_HYST
VLVW
VLVW_HYST
VBG
Falling low-voltage warning threshold
LVW hysteresis
4.19
0.97
4.31
68
4.5
V
mV
V
1
Bandgap voltage reference
1.00
1.03
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
5.3.1.5 Power mode transition operating behaviors
Table 31. Power mode transition operating behaviors
Description
System Clock
Core, Bus, Flash
frequency (MHz)
Min.
Typ. (μs)1 Max. (μs)2
STOP→RUN
FIRC
SPLL
FIRC
SPLL
SPLL
SPLL
48, 48, 24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.32
12.8
12.6
12.9
149
STOP→RUN
VLPS→RUN
VLPS→RUN
RUN→HSRUN
HSRUN→RUN
RUN→VLPR
VLPR→RUN
VLPR→RUN
WAIT→RUN
WAIT→RUN
VLPW→VLPR
VLPS→VLPR
VLPW→RUN
120, 60, 24
7.04
7.32
142
48, 48, 24
120, 60, 24
120, 60, 24→120, 60, 24
120, 60, 24→120, 60, 24
120, 60, 24→4, 4, 1
4, 4, 1→48, 48, 24
4, 4, 1→120, 60, 24
48, 48, 24
3.96
0.704
7.62
19.4
157
6.74
1.155
8.54
31.8
168
SPLL→SIRC
SIRC→FIRC
SIRC→SPLL
FIRC
0.476
0.260
10.3
10.8
128
0.554
0.310
16.2
15.7
143
SPLL
120, 60, 24
SIRC
4, 4, 1
SIRC
4, 4, 1
FIRC (reset value)
FIRC (reset value)
48, 48, 24 (reset value)
48, 48, 24 (reset value)
3
tPOR
112
122
1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V.
2. Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V.
3. After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first
instruction, across the operating temperature range of the chip.
5.3.1.6 Power consumption
The following table shows the power consumption targets for the device in various
modes of operations.
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NOTE
The maximum values stated in the following table represent
characterized results equivalent to the mean plus three times
the standard deviation (mean + 3 sigma).
Table 32. Power consumption operating behaviors
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
ts
HSRUN
IDD_HSRUN PLL
Running CoreMark in Flash in Compute 25 ℃
—
—
44.50
51.88
46.36
mA
Operation mode.
105 ℃
59.46
Core@168MHz, bus @84MHz,flash
@24MHz VDD=5V
PLL
PLL
PLL
PLL
Running CoreMark in Flash all
peripheral clock disabled.
25 ℃
—
—
50.49
58.31
52.35
65.89
105 ℃
Core@168MHz, bus @84MHz,flash
@24MHz VDD=5V
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
60.51
68.62
62.37
76.20
105 ℃
Core@168MHz, bus @84MHz,flash
@24MHz VDD=5V
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
52.74
60.76
54.60
68.34
105 ℃
Core@168MHz, bus @84MHz,flash
@24MHz VDD=5V
Running While(1) loop in Flash all
peripheral clock enabled.
25 ℃
—
—
62.48
70.75
64.34
78.33
105 ℃
Core@168MHz, bus @84MHz,flash
@24MHz VDD=5V
RUN
IDD_RUN
PLL
PLL
PLL
PLL
Running CoreMark in Flash in Compute 25 ℃
—
—
29.04
34.82
29.67
40.43
mA
Operation mode.
105 ℃
Core@120MHz, bus @60MHz,flash
@24MHz VDD=5V
Running CoreMark in Flash all
peripheral clock disabled.
25 ℃
—
—
33.29
39.08
33.92
44.69
105 ℃
Core@120MHz, bus @60MHz,flash
@24MHz VDD=5V
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
41.00
47.00
41.63
52.61
105 ℃
Core@120MHz, bus @60MHz,flash
@24MHz VDD=5V
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
34.59
40.68
35.22
46.29
105 ℃
Core@120MHz, bus @60MHz,flash
@24MHz VDD=5V
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Table 32. Power consumption operating behaviors (continued)
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
ts
PLL
Running While(1) loop in Flash all
peripheral clock enabled.
25 ℃
—
—
39.87
46.03
40.50
105 ℃
51.64
Core@120MHz, bus @60MHz,flash
@24MHz VDD=5V
IRC48M
IRC48M
IRC48M
IRC48M
IRC8M
IRC8M
IRC8M
IRC8M
IRC8M
IRC2M
Running CoreMark in Flash in Compute 25 ℃
—
—
14.02
19.76
14.65
25.37
Operation mode.
105 ℃
Core@48MHz, bus @48MHz, flash
@24MHz , VDD=5V
Running CoreMark in Flash all
peripheral clock disabled.
25 ℃
—
—
16.83
22.64
17.46
28.25
105 ℃
Core@48MHz, bus @48MHz, flash
@24MHz , VDD=5V
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
19.70
25.59
20.33
31.20
105 ℃
Core@48MHz, bus @48MHz, flash
@24MHz , VDD=5V
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
17.22
23.23
17.85
28.84
105 ℃
Core@48MHz, bus @48MHz, flash
@24MHz , VDD=5V
VLPR
IDD_VLPR
Very Low Power Run Core Mark in
Flash in Compute Operation mode.
25 ℃
25 ℃
25 ℃
25 ℃
25 ℃
25 ℃
—
—
—
—
—
—
1.52
1.73
1.95
1.77
1.96
1.19
1.63
1.84
2.06
1.88
2.07
1.30
mA
Core@4MHz, bus @4MHz, flash
@1MHz, VDD=5V
Very Low Power Run Core Mark in
Flash all peripheral clock disabled.
Core@4MHz, bus @4MHz, flash
@1MHz, VDD=5V
Very Low Power Run Core Mark in
Flash all peripheral clock enabled.
Core@4MHz, bus @4MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock disabled.
Core@4MHz, bus @4MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock enabled.
Core@4MHz, bus @4MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock disabled.
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Table 32. Power consumption operating behaviors (continued)
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
ts
Core@2MHz, bus @2MHz, flash
@1MHz, VDD=5V
IRC2M
Very Low Power Run While(1) loop in
Flash all peripheral clock enabled.
25 ℃
—
1.28
1.39
Core@2MHz, bus @2MHz, flash
@1MHz, VDD=5V
WAIT
IDD_WAIT
PLL
core disabled, system@120MHz, bus
@60MHz, flash disabled (flash doze
enabled), VDD=5 V, all peripheral
clocks disabled
25 ℃
25 ℃
25 ℃
25 ℃
—
—
—
—
—
14.13
8.50
1.08
0.84
175
14.78
9.15
1.18
0.94
484
mA
IRC48M
core disabled, system@48 MHz, bus
@48MHz, flash disabled (flash doze
enabled), VDD=5 V, all peripheral
clocks disabled
VLPW
IDD_VLPW IRC8M
Very Low Power Wait current, core
disabled system@4MHz, bus@4Mhz
and flash@1MHz, all peripheral clocks
disabled, VDD=5V
mA
IRC2M
Very Low Power Wait current, core
disabled system@2MHz, bus@2Mhz
and flash@1MHz, all peripheral clocks
disabled, VDD=5V
STOP
STOP
VLPS
VLPS
IDD_STOP
IDD_STOP
IDD_VLPS
IDD_VLPS
-
-
-
-
Stop mode current, VDD=5V, clock bias 25 ℃ and
μA
μA
μA
μA
enabled 2
below
50 ℃
85 ℃
105 ℃
—
—
—
—
438
1433
2860
92
1014
2864
5263
299
Stop mode current, VDD=5V, clock bias 25 ℃ and
disabled 2
below
50 ℃
85 ℃
105 ℃
—
—
—
—
211
671
1287
175
530
1397
2502
483
Very Low Power Stop current, VDD=5V, 25 ℃ and
clock bias enabled 2
below
50 ℃
85 ℃
105 ℃
—
—
—
—
424
1367
2864
91
998
2792
5258
298
Very Low Power Stop current, VDD=5V, 25 ℃ and
clock bias disabled 2
below
50 ℃
85 ℃
105 ℃
—
—
—
208
525
656
1378
2514
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1. These values are based on characterization but not covered by test limits in production.
2. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.
NOTE
CoreMark benchmark compiled using IAR 7.40 with
optimization level high, optimized for balanced.
5.3.1.6.1 Low power mode peripheral current adder — typical value
Symbol
Description
Typical
ILPTMR
LPTMR peripheral adder measured by placing the device in VLPS mode
with LPTMR enabled using LPO. Includes LPO power consumption.
366 nA
ICMP
CMP peripheral adder measured by placing the device in VLPS mode
with CMP enabled using the 8-bit DAC and a single external input for
compare. 8-bit DAC enabled with half VDDA voltage, low speed mode.
Includes 8-bit DAC power consumption.
16 μA
IRTC
RTC peripheral adder measured by placing the device in VLPS mode
with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit
and the RTC counter enabled. Includes EXTAL32 (32 kHz external
crystal) power consumption.
312 nA
ILPUART
LPUART peripheral adder measured by placing the device in VLPS
mode with selected clock source waiting for RX data at 115200 baud
rate. Includes selected clock source power consumption. (SIRC 8 MHz)
79 μA
45 μA
IFTM
FTM peripheral adder measured by placing the device in VLPW mode
with selected clock source, outputting the edge aligned PWM of 100 Hz
frequency.
IADC
ADC peripheral adder combining the measured values at VDD and
VDDA by placing the device in VLPS mode. ADC is configured for low
power mode using SIRC clock source, 8-bit resolution and continuous
conversions.
484 μA
ILPI2C
LPI2C peripheral adder measured by placing the device in VLPS mode
with selected clock source sending START and Slave address, waiting
for RX data. Includes the DMA power consumption.
179 μA
18 μA
ILPIT
LPIT peripheral adder measured by placing the device in VLPS mode
with internal SIRC 8 MHz enabled in Stop mode. Includes selected clock
source power consumption.
ILPSPI
LPSPI peripheral adder measured by placing the device in VLPS mode
with selected clock source, output data on SOUT pin with SCK 500 kbit/s.
Includes the DMA power consumption.
565 μA
5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• SCG in SOSC for both Run and VLPR modes
• No GPIOs toggled
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• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Temperature=25, VDD=5V
ClockGates
Core-Bus-Flash
CoreFreq
Figure 14. Run mode supply current vs. core frequency
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Temperature=25, VDD=5V
ClockGates
Core-Bus-Flash
CoreFreq
Figure 15. VLPR mode supply current vs. core frequency
5.3.1.7 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following applications notes, available on http://www.nxp.com for advice
and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
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• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
5.3.1.7.1 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
5.3.1.7.2 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions.
1. Go to http://www.nxp.com.
2. Perform a keyword search for “EMC design”.
3. Select the "Documents" category and find the application notes.
5.3.1.8 Capacitance attributes
Table 33. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
NOTE
Please refer to External Oscillator electrical specifications
for EXTAL/XTAL pins.
5.3.2 Switching specifications
5.3.2.1 Device clock specifications
Table 34. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed RUN mode
fSYS
fBUS
System and core clock
Bus clock
—
—
168
84
MHz
MHz
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Table 34. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
fFLASH
Flash clock
—
25
MHz
Normal RUN mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
120
60
MHz
MHz
MHz
MHz
Flash clock
25
LPTMR clock
50
VLPR / VLPW mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fERCLK
fLPTMR
fFlexCAN
Flash clock
1
External reference clock
LPTMR clock
16
13
4
FlexCAN clock
1. The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing
specification for any other module.
5.3.2.2 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 16. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Normal drive strength
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5.3.2.3 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 35. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
50
—
—
ns
3
4
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5.3.2.4 AC specifications at 3.3 V range
Table 36. Functional pad AC specifications
Characteristic
Symbol
Min
Typ
Max
Unit
I/O Supply Voltage
Vdd 1
2.7
4
V
1. Max power supply ramp rate is 500 V/ms.
Name
Prop Delay (ns) 1
Rise/Fall Edge (ns) 2
Min Max
Drive Load (pF)
Max
17.5
28
Normal drive I/O pad
High drive I/O pad
CMOS Input 3
5
9
17
32
17
33
3
25
50
25
50
0.5
19
5
26
9
4
1.2
1. Propagation delay measured from 50ꢀ of core side input to 50ꢀ of the output.
2. Edges measured using 20ꢀ and 80ꢀ of the VDD supply.
3. Input slope = 2 ns.
NOTE
All measurements were taken accounting for 150 mV drop
across VDD and VSS.
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5.3.2.5 AC specifications at 5 V range
Table 37. Functional pad AC specifications
Characteristic
Symbol
Min
Typ
Max
Unit
I/O Supply Voltage
Vdd 1
4
5.5
V
1. Max power supply ramp rate is 500 V/ms.
Name
Prop Delay (ns) 1
Rise/Fall Edge (ns) 2
Min Max
Drive Load (pF)
Max
12
18
13
19
3
Normal drive I/O pad
High drive I/O pad
CMOS Input 3
3.6
8
10
17
10
19
2.8
25
50
25
50
0.5
3.6
8
1.2
1. As measured from 50ꢀ of core side input to 50ꢀ of the output.
2. Edges measured using 20ꢀ and 80ꢀ of the VDD supply.
3. Input slope = 2 ns.
NOTE
All measurements were taken accounting for 150 mV drop
across VDD and VSS.
5.3.3 Thermal specifications
5.3.3.1 Thermal operating requirements
Table 38. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
Notes
Die junction temperature
Ambient temperature
°C
°C
TA
105
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
5.3.3.2 Thermal attributes
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5.3.3.2.1 Description
The tables in the following sections describe the thermal characteristics of the device.
NOTE
Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting side
(board) temperature, ambient temperature, air flow, power
dissipation or other components on the board, and board
thermal resistance.
5.3.3.2.2 Thermal characteristics for the 64-pin LQFP package
Table 39. Thermal characteristics for the 64-pin LQFP package
Rating
Conditions
Symbol
Value
Unit
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Single layer board (1s)
RθJA
60
°C/W
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
RθJA
RθJMA
RθJMA
42
49
36
°C/W
°C/W
°C/W
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Thermal resistance, Junction to Board4
Thermal resistance, Junction to Case 5
Thermal resistance, Junction to Package Top6
—
—
RθJB
RθJC
ψJT
24
12
2
°C/W
°C/W
°C/W
Natural Convection
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.3.3.2.3 Thermal characteristics for the 100-pin LQFP package
Table 40. Thermal characteristics for the 100-pin LQFP package
Rating
Conditions
Symbol
Value
Unit
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Single layer board (1s)
RθJA
57
°C/W
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Table 40. Thermal characteristics for the 100-pin LQFP package (continued)
Rating
Conditions
Symbol
Value
Unit
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Four layer board (2s2p)
RθJA
44
°C/W
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Single layer board (1s)
Four layer board (2s2p)
RθJMA
RθJMA
47
38
°C/W
°C/W
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Thermal resistance, Junction to Board4
Thermal resistance, Junction to Case 5
Thermal resistance, Junction to Package Top6
—
—
RθJB
RθJC
ψJT
30
14
2
°C/W
°C/W
°C/W
Natural Convection
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s
or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.3.3.2.4 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation:
TJ = TA + (RθJA × PD)
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values
in common usage: the value determined on a single layer board and the value obtained
on a board with two planes. For packages such as the PBGA, these values can be
different by a factor of two. Which value is closer to the application depends on the
power dissipated by other components on the board. The value obtained on a single
layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the board has low
power dissipation and the components are well separated.
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When a heat sink is used, the thermal resistance is expressed in the following equation
as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal
resistance:
RθJA = RθJC + RθCA
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the
thermal environment to change the case to ambient thermal resistance, RθCA. For
instance, the user can change the size of the heat sink, the air flow around the device,
the interface material, the mounting arrangement on printed circuit board, or change
the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine
the junction temperature with a measurement of the temperature at the top center of
the package case using this equation:
TJ = TT + (ΨJT × PD)
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using
a 40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
5.4 Peripheral operating requirements and behaviors
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5.4.1 System modules
There are no specifications necessary for the device's system modules.
5.4.2 Clock interface modules
5.4.2.1 Oscillator electrical specifications
5.4.2.1.1 External Oscillator electrical specifications
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Single input buffer
(EXTAL32 WAVE)
ref_clk
mux
Differential input comparator
(VLP mode)
Peak detector
LP mode
Driver
(VLP mode)
Pull down resistor (OFF)
ESD PAD
300 ohms
ESD PAD
300 ohms
XTAL32 pin
EXTAL32 pin
Series resistor for current
limitation
Crystal or resonator
C1
C2
Figure 17. Oscillator connections scheme (OSC32)
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Single input buffer
(EXTAL WAVE)
ref_clk
mux
Differential input comparator
(HG/LP mode)
Peak detector
LP mode
Driver
(HG/LP mode)
Pull down resistor (OFF)
ESD PAD
300 ohms
ESD PAD
40 ohms
XTAL pin
EXTAL pin
1
Series resistor for current
limitation
1M ohms Feedback Resistor
Crystal or resonator
C1
C2
NOTE:
1. 1M Feedback resistor is needed only for HG mode.
Figure 18. Oscillator connections scheme (OSC)
NOTE
Data values in the following "External Oscillator electrical
specifications" tables are from simulation.
Table 41. External Oscillator electrical specifications (OSC32)
Symbol Description
VDD Supply voltage
Min.
Typ.
—
Max.
5.5
Unit
V
Notes
2.7
IDDOSC32 Supply current
—
6
500
—
—
nA
1
gmXOSC32 Oscillator transconductance
9
µA/V
V
VIH
Input high voltage — EXTAL32 pin in external
clock mode
0.7 × VDD
—
VDD+0.3
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Table 41. External Oscillator electrical specifications (OSC32) (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
@VDD=3.3 V
@VDD=5.0 V
0.65 × VDD
VSS –0.3
—
—
VDD+0.3
V
V
VIL
Input low voltage — EXTAL32 pin in external
0.3 ×
VDD
clock mode
@VDD=3.3 V
@VDD=5.0 V
VSS –0.3
—
0.35 ×
VDD
V
C1
C2
RF
RS
EXTAL32 load capacitance
XTAL32 load capacitance
Feedback resistor
—
—
—
—
—
—
—
—
—
—
—
—
2
2
—
MΩ
kΩ
V
Series resistor
—
Vpp_OSC32 Peak-to-peak amplitude of oscillation (oscillator
mode)
0.6
3
1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator,
loading capacitance.
2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator
manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider
the parasitic capacitance of package and board.
3. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be
connected to any other devices.
Table 42. External Oscillator electrical specifications (OSC)
Symbol
VDD
Description
Min.
Typ.
Max.
Unit Notes
Supply voltage
2.7
—
5.5
V
IDDOSC
Supply current — low-gain mode (low-power mode) (HGO=0)
1
4 MHz
—
—
—
—
—
—
200
300
1.2
1.6
2
—
—
—
—
—
—
µA
µA
mA
mA
mA
mA
1
8 MHz
16 MHz
24 MHz
32 MHz
40 MHz
2.6
IDDOSC
Supply current — high-gain mode (HGO=1)
32 kHz
—
—
—
—
—
—
—
25
1
—
—
—
—
—
—
—
µA
mA
mA
mA
mA
mA
mA
4 MHz
8 MHz
1.2
3.5
5
16 MHz
24 MHz
32 MHz
5.5
6
40 MHz
gmXOSC
Fast external crystal oscillator transconductance
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Table 42. External Oscillator electrical specifications (OSC)
(continued)
Symbol
Description
Min.
15
Typ.
—
Max.
45
Unit Notes
µA / V
32 kHz, Low Frequency Range, High Gain (32 kHz)
Medium Frequency Range (4-8 MHz)
2.2
16
—
9.7
37
mA / V
mA / V
V
High Frequency Range (8-40 MHz)
VIH
VIL
Input high voltage — EXTAL pin in external clock
mode
1.75
—
—
VDD
Input low voltage — EXTAL pin in external clock
mode
VSS
1.20
V
C1
C2
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
2
2
Feedback resistor
3
Low-frequency, high-gain mode (32 kHz)
—
—
10
—
—
—
MΩ
Medium/high-frequency, low-gain mode (low-power
mode) (4-8 MHz, 8-40 MHz)
MΩ
Medium/high-frequency, high-gain mode (4-8 MHz,
8-40 MHz)
—
1
—
MΩ
RS
Series resistor
Low-frequency, high-gain mode (32 kHz)
—
—
200
0
—
—
kΩ
kΩ
Medium/high-frequency, low-gain mode (low-power
mode) (4-8 MHz, 8-40 MHz)
Medium/high-frequency, high-gain mode (4-8 MHz,
8-40 MHz)
—
0
—
kΩ
Vpp
Peak-to-peak amplitude of oscillation (oscillator mode)
Low-frequency, high-gain mode
4
—
—
—
3.3
1.0
3.3
—
—
—
V
V
V
Medium/high-frequency, low-gain mode
Medium/high-frequency, high-gain mode
1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator, loading
capacitance.
2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator
manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider
the parasitic capacitance of package and board.
3. When low power mode is selected, RF is integrated and must not be attached externally.
4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
5.4.2.1.2 External Oscillator frequency specifications
Table 43. External Oscillator frequency specifications (OSC32)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc32_lo Oscillator crystal or resonator frequency — low-
frequency mode
30
—
40
kHz
tdc_extal32 Input clock duty cycle (external clock mode)
40
50
60
ꢀ
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Table 43. External Oscillator frequency specifications (OSC32) (continued)
Symbol Description
Min.
—
Typ.
—
Max.
40
Unit
kHz
ms
Notes
fec_extal32 Input clock frequency (external clock mode)
tcst32
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
2000
—
1
1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve
specifications.
Table 44. External Oscillator frequency specifications (OSC)
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — Low
Frequency, High Gain Mode
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_me Oscillator crystal or resonator frequency —
Medium Frequency
4
8
—
—
8
MHz
fosc_hi
Oscillator crystal or resonator frequency —
High Frequency
40
tdc_extal Input clock duty cycle (external clock mode)
fec_extal Input clock frequency (external clock mode)
40
—
—
50
—
60
50
—
ꢀ
MHz
ms
tcst
Crystal startup time — 32 kHz Low Frequency,
High-Gain Mode
500
1
Crystal startup time — 8 MHz Medium
Frequency, Low-Power Mode
—
—
—
—
1.5
2.5
2
—
—
—
—
Crystal startup time — 8 MHz Medium
Frequency, High-Gain Mode
Crystal startup time — 40 MHz High
Frequency, Low-Power Mode
Crystal startup time — 40 MHz High
Frequency, High-Gain Mode
2.5
1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve
specifications.
5.4.2.2 System Clock Generation (SCG) specifications
5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 45. Fast internal RC Oscillator electrical specifications
Symbol
Parameter
Value
Typ.
Unit
Min.
Max.
FFIRC
IVDD
Fast internal reference frequency
Supply current
—
—
MHz
µA
48
—
400
500
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Table 45. Fast internal RC Oscillator electrical specifications
(continued)
Symbol
Parameter
Value
Typ.
—
Unit
Min.
FIRC
Max.
FIRC
FUntrimmed IRC frequency (untrimmed)
×
×
MHz
(1-0.3)
(1+0.3)
ΔFOL
Open loop total deviation of IRC frequency over voltage and
temperature1
Regulator enable
Startup time
—
—
0.5
—
1
3
ꢀFFIRC
µs2
TStartup
TJIT
Period jitter (RMS)
35
150
ps
1. The limit is respected across process, voltage and full temperature range.
2. Startup time is defined as the time between clock enablement and clock availability for system use.
NOTE
Fast internal RC Oscillator is compliant with CAN and LIN
standards.
5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 46. Slow internal RC oscillator (SIRC) electrical specifications
Symbol
Parameter
Value
Typ.
2
Unit
Min.
Max.
FSIRC
Slow internal reference frequency
—
—
MHz
8
IVDD
FUntrimmed
ΔFOL
Supply current
—
—
23
—
—
µA
IRC frequency (untrimmed)
—
MHz
Open loop total deviation of IRC frequency over
voltage and temperature1
Regulator enable
Startup time
—
—
—
6
3
ꢀFSIRC
µs2
TStartup
—
1. The limit is respected across process, voltage and full temperature range.
2. Startup time is defined as the time between clock enablement and clock availability for system use.
5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications
Table 47. Low Power Oscillator (LPO) electrical specifications
Symbol
FLPO
Parameter
Internal low power oscillator frequency
Current consumption
Min.
113
1
Typ.
128
3
Max.
139
7
Unit
kHz
µA
ILPO
Tstartup
Startup Time
—
—
20
µs
70
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Electrical characteristics
5.4.2.2.4 PLL electrical specifications
Table 48. PLL electrical specifications
Symbol
Parameter
Min.
8
Typ.
—
Max.
50
Unit
MHz
MHz
MHz
MHz
Fpll_ref
PLL Reference Frequency Range
Fvcoclk_2x VCO output frequency
Fvcoclk PLL output frequency
Fvcoclk_90 PLL output frequency
180
90
—
360
180
180
—
90
—
Ipll
PLL operating current1
VCO @ 150 MHz (Fpll_ref = 12 MHz, VDIV
multiplier = 25, PRDIV divide = 2)
—
—
2.8
3.6
—
—
mA
mA
VCO @ 300 MHz (Fpll_ref = 12 MHz, VDIV
multiplier = 50, PRDIV divide = 2)
Jcyc_pll
PLL Period Jitter (RMS)2
at Fvco 180 MHz
—
—
120
75
—
—
ps
ps
at Fvco 360 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)2
at Fvco 180 MHz
—
—
1350
600
—
—
ps
ps
ꢀ
s
at Fvco 360 MHz
—
Dunl
Lock exit frequency tolerance
Lock detector detection time3
4.47
—
5.97
100 × 10-6
1075(1/
Tpll_lock
—
+
Fpll_ref
)
1. Excludes any oscillator currents that are also consuming power while PLL is in operation.
2. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary
3. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference,
thisspecification assumes it is already running.
5.4.3 Memories and memory interfaces
5.4.3.1 Flash memory module (FTFE) electrical specifications
This section describes the electrical characteristics of the flash memory module
(FTFE).
5.4.3.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
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Table 49. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm8
Program Phrase high-voltage time
thversscr Erase Flash Sector high-voltage time
thversblk64k Erase Flash Block high-voltage time for 64 KB
thversblk512k Erase Flash Block high-voltage time for 512 KB
—
113
452
3616
ms
ms
ms
1
1
1
—
52
—
416
1. Maximum time based on expectations at cycling end-of-life.
5.4.3.1.2 Flash timing specifications — commands
Table 50. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk64k
• 64 KB data flash
—
—
—
—
0.5
1.8
ms
ms
trd1blk512k
• 512 KB program flash
trd1sec2k Read 1s Section execution time (2 KB flash)
trd1sec4k Read 1s Section execution time (4 KB flash)
—
—
—
—
—
—
—
—
—
90
75
100
95
μs
μs
μs
μs
μs
1
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Phrase execution time
Erase Flash Block execution time
• 64 KB data flash
40
tpgm8
150
2
tersblk64k
—
—
55
475
ms
ms
tersblk512k
• 512 KB program flash
435
3700
tersscr
Erase Flash Sector execution time
—
—
—
—
—
—
—
—
15
5
115
—
ms
ms
ms
μs
2
1
tpgmsec1k Program Section execution time (1 KB flash)
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
2.2
30
trdonce
—
tpgmonce Program Once execution time
90
500
—
—
μs
tersall
tvfykey
tersallu
Erase All Blocks execution time
4200
30
ms
μs
2
1
2
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
Program Partition for EEPROM execution time
• 32 KB EEPROM backup
500
4200
ms
tpgmpart32k
tpgmpart64k
—
—
70
71
—
—
ms
ms
• 64 KB EEPROM backup
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram48k
—
—
—
70
0.8
1.0
—
μs
ms
ms
• 32 KB EEPROM backup
1.2
1.5
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Electrical characteristics
Table 50. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tsetram64k
• 48 KB EEPROM backup
—
1.3
1.9
ms
• 64 KB EEPROM backup
Byte-write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr8b32k
teewr8b48k
teewr8b64k
—
—
—
385
430
475
1700
1850
2000
μs
μs
μs
• 48 KB EEPROM backup
• 64 KB EEPROM backup
16-bit write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr16b32k
teewr16b48k
teewr16b64k
—
—
—
385
430
475
1700
1850
2000
μs
μs
μs
• 48 KB EEPROM backup
• 64 KB EEPROM backup
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
360
1500
μs
32-bit write to FlexRAM execution time:
teewr32b32k
teewr32b48k
teewr32b64k
• 32 KB EEPROM backup
• 48 KB EEPROM backup
• 64 KB EEPROM backup
—
—
—
630
720
810
2000
2125
2250
μs
μs
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.4.3.1.3 Flash high voltage current behaviors
Table 51. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage flash
programming operation
—
3.5
7.5
mA
IDD_ERS
Average current adder during high voltage flash
erase operation
—
1.5
4.0
mA
5.4.3.1.4 Reliability specifications
Table 52. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
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Table 52. NVM reliability specifications (continued)
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100ꢀ of write endurance
tnvmretee10 Data retention up to 10ꢀ of write endurance
nnvmcycee Cycling endurance for EEPROM backup
Write endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
20 K
2
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
140 K
1.26 M
5 M
400 K
3.2 M
12.8 M
50 M
—
—
—
—
writes
writes
writes
writes
20 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit or
32-bit writes to FlexRAM; all 8-bit writes result in 50ꢀ less endurance.
5.4.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.4.5 Analog
5.4.5.1 ADC electrical specifications
5.4.5.1.1 12-bit ADC operating conditions
Table 53. 12-bit ADC operating conditions
Symbol Description
Conditions
Absolute
Min.
2.7
Typ.1
Max.
5.5
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD
-100
0
+100
mV
2
(VDD – VDDA
)
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Electrical characteristics
Table 53. 12-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
ΔVSSA
Ground voltage
Delta to VSS (VSS
-100
0
+100
mV
2
– VSSA
)
VREFH
ADC reference voltage high
2.5
VDDA
VDDA
100m
+
V
3
3
VREFL
VADIN
RS
ADC reference voltage low
Input voltage
− 100
VREFL
—
0
100
VREFH
5
mV
V
—
—
0.5
Source impedendance
fADCK < 4 MHz
kΩ
kΩ
RSW1
Channel Selection Switch
Impedance
—
1.2
RAD
CP1
CP2
CS
Sampling Switch Impedance
Pin Capacitance
—
—
—
—
2
2
3
5
—
5
kΩ
pF
Analog Bus Capacitance
Sampling capacitance
—
4
pF
5
pF
fADCK
ADC conversion clock
frequency
40
50
MHz
4, 5
7
Crate
ADC conversion rate
No ADC
20
—
1200
Ksps
hardware
averaging6
Continuous
conversions
enabled,
subsequent
conversion time
1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. Clock and compare cycle need to be set according the guidelines in the block guide.
5. ADC conversion will become less reliable above maximum frequency.
6. When using ADC hardware averaging, refer to the device Reference Manual to determine the most appropriate
setting for AVGS.
7. Max ADC conversion rate of 1200 Ksps is with 10-bit mode
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Electrical characteristics
Figure 19. ADC input impedance equivalency diagram
5.4.5.1.2 12-bit ADC electrical characteristics
NOTE
All the parameters in the table are given assuming system
clock as the clocking source for ADC.
NOTE
For ADC signals adjacent to VDD/VSS or the XTAL pins
some degradation in the ADC performance may be observed.
NOTE
All values guarantee the performance of the ADC for the
multiple ADC input channel pins. When using the ADC to
monitor the internal analogue parameters, please assume
minor degradation.
Table 54. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max. 3
Unit
Notes
IDDA_ADC Supply current at 2.7 to
5.5 V
621
658 μA @
5 V
696
μA
4
Sample Time
275
—
Refer to
the
ns
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Table 54. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max. 3
Unit
Notes
device's
Reference
Manual
TUE
DNL
INL
Total unadjusted error
at 2.7 to 5.5 V
—
—
—
—
—
—
—
—
4.5
0.8
1.4
–2
6.56
1.07
3.95
-3.40
-4.14
0.5
LSB5
LSB5
LSB5
LSB5
LSB5
LSB5
bits
6
Differential non-
linearity at 2.7 to 5.5 V
6
Integral non-linearity at
2.7 to 5.5 V
6
6
EFS
Full-scale error at 2.7
to 5.5 V
VADIN = VDDA
EZS
Zero-scale error at 2.7
to 5.5 V
–2.7
—
EQ
Quantization error at
2.7 to 5.5 V
ENOB
Effective number of bits
at 2.7 to 5.5 V
11.3
70
—
7
Signal-to-noise plus
See ENOB
—
SINAD = 6.02 ×
ENOB + 1.76
SINAD distortion at 2.7 to 5.5
V
dB
EIL
Input leakage error at
2.7 to 5.5 V
IIn × RAS
mV
IIn = leakage
current (refer to
the MCU's
voltage and
current operating
ratings)
VTEMP_S Temperature sensor
slope at 2.7 to 5.5 V
Across the full
temperature
range of the
device
1.492
730
1.564
740.5
1.636
751
mV/°C
mV
8, 9
VTEMP25 Temperatue sensor
voltage at 2.7 to 5.5 V
25 °C
8, 9
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated.
3. These values are based on characterization but not covered by test limits in production.
4. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
5. 1 LSB = (VREFH - VREFL)/2N
6. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = ꢀ1, AVGS = ꢀ11)
7. Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.
8. ADC conversion clock < 3 MHz
9. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more
detailed application information of the temperature sensor.
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5.4.5.2 CMP with 8-bit DAC electrical specifications
Table 55. Comparator with 8-bit DAC electrical specifications
Symbol
VDD
Description
Min.
Typ. 1
Max.
Unit
V
Supply voltage
2.7
—
5.5
IDDHS
Supply current, High-speed mode2
within ambient temperature range
Supply current, Low-speed mode2
within ambient temperature range
Analog input voltage
μA
—
145
200
IDDLS
μA
—
0
5
10
VAIN
VAIO
0 - VDDX
VDDX
V
Analog input offset voltage, High-speed mode
within ambient temperature range
Analog input offset voltage, Low-speed mode
within ambient temperature range
Propagation delay, High-speed mode3
within ambient temperature range
Propagation delay, Low-speed mode3
within ambient temperature range
Propagation delay, High-speed mode4
within ambient temperature range
Propagation delay, Low-speed mode4
within ambient temperature range
Initialization delay, High-speed mode 3
within ambient temperature range
Initialization delay, Low-speed mode3
within ambient temperature range
mV
-25
-40
—
—
—
—
—
—
—
1
4
25
40
200
2
VAIO
tDHSB
tDLSB
tDHSS
tDLSS
tIDHS
mV
ns
30
0.5
70
1
µs
ns
400
5
µs
μs
1.5
10
0
3
tIDLS
μs
30
—
VHYST0
Analog comparator hysteresis, Hyst0 (VAIO
within ambient temperature range
)
mV
mV
VHYST1
Analog comparator hysteresis, Hyst1, High-speed
mode
within ambient temperature range
—
—
—
—
16
11
32
22
53
30
90
53
Analog comparator hysteresis, Hyst1, Low-speed
mode
within ambient temperature range
VHYST2
Analog comparator hysteresis, Hyst2, High-speed
mode
mV
mV
within ambient temperature range
Analog comparator hysteresis, Hyst2, Low-speed
mode
within ambient temperature range
VHYST3
Analog comparator hysteresis, Hyst3, High-speed
mode
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Table 55. Comparator with 8-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ. 1
Max.
Unit
within ambient temperature range
—
48
133
Analog comparator hysteresis, Hyst3, Low-speed
mode
within ambient temperature range
8-bit DAC current adder (enabled)
8-bit DAC integral non-linearity
8-bit DAC differential non-linearity
—
—
33
10
—
—
80
16
IDAC8b
INL
μA
LSB5
–0.6
–0.5
0.5
0.5
DNL
LSB
1. Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.
2. Difference at input > 200mV
3. Applied (100 mV + Hyst) around switch point
4. Applied (30 mV + 2 × Hyst) around switch point
5. 1 LSB = Vreference/256
Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Electrical characteristics
Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
Figure 22. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 0)
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Figure 23. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1)
5.4.5.3 12-bit DAC electrical characteristics
5.4.5.3.1 12-bit DAC operating requirements
Table 56. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
2.7
2.7
20
Max.
5.5
5.5
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
3
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance can improve the bandwidth performance of the DAC.
3. Output range is from ground + 0.2 to VDACR - 0.2
5.4.5.3.2 12-bit DAC operating behaviors
Table 57. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
330
μA
P
IDDA_DACH Supply current — high-power mode
—
—
1200
μA
P
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Table 57. 12-bit DAC operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
—
—
—
15
—
0.7
—
—
—
—
30
5
μs
μs
1
1
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode
tCCDACHP Code-to-code settling time (0xBF8 to
0xC08) — high-power mode
—
μs
Vdacoutl DAC output voltage range low — high-
power mode, no load, DAC set to 0x000
100
VDACR
8
mV
mV
LSB
LSB
Vdacouth DAC output voltage range high — high-
power mode, no load, DAC set to 0xFFF
VDACR
100
−
INL
Integral non-linearity error — high-power
mode
—
2
3
DNL
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
—
—
0.4
0.1
0.8
0.6
ꢀFSR
ꢀFSR
4
4
PSRR Power supply rejection ratio
High-power mode, code set to 3FF or BFF
Low-power mode, code set to 3FF or BFF
68
dB
5
6
60
5
TCO
TGE
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Slew rate -80h→ F7Fh→ 80h
—
—
—
—
μV/C
ꢀFSR/C
V/μs
0.000421
1
1.5
—
—
• High power (SPHP
• Low power (SPLP
)
0.05
0.12
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
4. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
5. DAC reference to VREFH (DACREF_1)
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
5.4.6 Communication interfaces
5.4.6.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
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Electrical characteristics
5.4.6.2 LPSPI electrical specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The following tables provide timing characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI
pins.
Table 58. LPSPI master mode timing
Num.
Symbol Description
fSPSCK Frequency of SPSCK
tSPSCK
Min.
Max.
Unit
Hz
Note
1
2
fperiph/2048
2 x tperiph
fperiph/2
1
2
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
2. tperiph = 1/fperiph
NOTE
High drive pin should be used for fast bit rate.
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1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 24. LPSPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 25. LPSPI master mode timing (CPHA = 1)
Table 59. LPSPI slave mode timing
Num.
Symbol Description
Min.
Max.
fperiph/2
—
Unit
Hz
Note
1
1
2
3
fSPSCK
tSPSCK
tLead
Frequency of SPSCK
0
2 x tperiph
1
SPSCK period
ns
2
Enable lead time
—
tperiph
—
Table continues on the next page...
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Table 59. LPSPI slave mode timing (continued)
Num.
4
Symbol Description
tLag Enable lag time
tWSPSCK Clock (SPSCK) high or low time
Min.
Max.
—
Unit
tperiph
ns
Note
—
—
—
—
3
1
5
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
Figure 26. LPSPI slave mode timing (CPHA = 0)
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SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
Figure 27. LPSPI slave mode timing (CPHA = 1)
5.4.6.3 LPI2C
Table 60. LPI2C specifications
Symbol Description
Min.
Max.
100
Unit
Notes
fSCL
SCL clock frequency
Standard mode (Sm)
Fast mode (Fm)
0
0
0
0
0
kHz
1, 2, 3
400
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
1. Hs-mode is only supported in slave mode.
2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with
appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The
maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up
devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum
bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode
can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more
information on the required pull-up devices, see I2C Bus Specification.
3. See General switching specifications
5.4.7 Debug modules
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Electrical characteristics
5.4.7.1 SWD electricals
Table 61. SWD full voltage range electricals
Symbol
VDDA
S1
Description
Min.
2.7
0
Max.
5.5
25
—
Unit
V
Operating voltage
SWD_CLK frequency of operation
SWD_CLK cycle period
MHz
ns
S2
1/S1
15
—
S3
SWD_CLK clock pulse width
—
ns
S4
SWD_CLK rise and fall times
3
ns
S9
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
8
—
ns
S10
S11
S12
1.4
—
—
ns
25
—
ns
5
ns
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 28. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
S9
S10
Input data valid
S11
Output data valid
S12
S11
Output data valid
Figure 29. Serial wire data timing
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5.4.7.2 JTAG electricals
Table 62. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
Boundary Scan
MHz
0
0
10
20
—
JTAG and CJTAG
J2
J3
TCLK cycle period
1/J1
ns
ns
TCLK clock pulse width
Boundary Scan
50
25
—
20
1
—
—
3
JTAG and CJTAG
J4
J5
TCLK rise and fall times
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
—
—
25
25
—
—
19
19
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TRST assert time
TRST setup time (negation) to TCLK high
Table 63. JTAG full voltage range electricals
Symbol
VDDA
J1
Description
Min.
Max.
Unit
V
Operating voltage
2.7
5.5
TCLK frequency of operation
Boundary Scan
MHz
0
0
10
15
—
JTAG and CJTAG
J2
J3
TCLK cycle period
1/J1
ns
ns
TCLK clock pulse width
Boundary Scan
50
33
—
—
—
3
JTAG and CJTAG
J4
J5
J6
J7
J8
TCLK rise and fall times
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
20
1.4
—
—
—
27
27
—
Table continues on the next page...
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Table 63. JTAG full voltage range electricals (continued)
Symbol
J9
Description
Min.
8
Max.
—
Unit
ns
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
J10
1.4
—
—
ns
J11
26.2
26.2
—
ns
J12
—
ns
J13
TRST assert time
100
8
ns
J14
TRST setup time (negation) to TCLK high
—
ns
J2
J4
J3
J3
TCLK (input)
J4
Figure 30. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 31. Boundary scan (JTAG) timing
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Design considerations
TCLK
J9
J10
Input data valid
TDI/TMS
J11
Output data valid
TDO
TDO
TDO
J12
J11
Output data valid
Figure 32. Test Access Port timing
TCLK
TRST
J14
J13
Figure 33. TRST timing
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
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Design considerations
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital
circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground. Consider to add ferrite bead or
inductor to some sensitive lines.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground
plane directly under LQFP packages; and solder the exposed pad (EP) to ground
directly under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as
sequential segments.
• Always route the power net as star topology, and make each power trace loop as
minimum as possible.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
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Design considerations
MCU
1
2
Input signal
ADCx
R
C
Figure 34. RC circuit for ADC input
High voltage measurement circuits require voltage division, current limiting, and over-
voltage protection as shown the following figure. The voltage divider formed by R1 –
R4 must yield a voltage less than or equal to VREFH. The current must be limited to
less than the injection current limit. External clamp diodes can be added here to protect
against transient over-voltages.
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 35. High voltage measurement with an ADC input
NOTE
For more details of ADC related usage, refer to AN5250:
How to Increase the Analog-to-Digital Converter Accuracy in
an Application.
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially the
RESET_b pin.
• RESET_b pin
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Design considerations
The RESET_b pin is a pseudo open-drain I/O pin that has an internal pullup
resistor. An external RC circuit is recommended to filter noise as shown in the
following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 36. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength.
The supervisor chip must have an active high, open-drain output.
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 37. Reset signal connection to external reset chip
• NMI pin
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Design considerations
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level
on this pin will trigger non-maskable interrupt. When this pin is enabled as the NMI
function, an external pull-up resistor (10 kΩ) as shown in the following figure is
recommended for robustness.
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
VDD
MCU
10k
NMI_b
Figure 38. NMI pin biasing
• Debug interface
This MCU uses the standard ARM SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
recommendations mentioned above must also be considered.
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 39. SWD debug interface
• Unused pin
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Design considerations
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators.
An external feedback is required when using high gain (HGO=1) mode.
The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or
resonator frequency is below 2 MHz. Otherwise, the low power oscillator (HGO=0)
must not have any series resistance; and the high frequency, high gain oscillator with a
frequency above 2 MHz does not require any series resistance.
OSC32
EXTAL32
XTAL32
1
2
Cx
Cy
CRYSTAL
Figure 40. RTC Oscillator (OSC32) module connection – Diagram 1
Table 64. External crystal/resonator connections
Oscillator mode
Low frequency (32.768 kHz), high gain
High frequency (1-32 MHz), low power
High frequency (1-32 MHz), high gain
Oscillator mode
Diagram 3
Diagram 2
Diagram 3
OSCILLATOR
EXTAL
OSCILLATOR
XTAL
EXTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 41. Crystal connection – Diagram 2
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Design considerations
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 42. Crystal connection – Diagram 3
NOTE
For PCB layout, the user could consider to add the guard ring
to the crystal oscillator circuit.
6.2 Software considerations
All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and
software enablement solutions, which can reduce development costs and time to market.
Featured software and tools are listed below. Visit http://www.nxp.com/kinetis/sw for
more information and supporting collateral.
Evaluation and Prototyping Hardware
• Tower System Development Platform: http://www.nxp.com/tower
IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.nxp.com/kds
• Partner IDEs: http://www.nxp.com/kide
Run-time Software
• Kinetis SDK: http://www.nxp.com/ksdk
• Kinetis Bootloader: http://www.nxp.com/kboot
• ARM mbed Development Platform: http://www.nxp.com/mbed
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
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Part identification
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KE## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 65. Part number fields description
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KE##
A
Kinetis family
Key attribute
• KE18, KE16, KE14
• D = Cortex-M4 with DSP
• F = Cortex-M4 with DSP and FPU
FFF
R
Program flash memory size
Silicon revision
• 512 = 512 KB
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LH = 64 LQFP (10 mm x 10 mm)
• LL = 100 LQFP (14 mm x 14 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 16 = 168 MHz
• R = Tape and reel
• (Blank) = Trays
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Revision history
7.4 Example
This is an example part number:
MKE18F512VLL16
8 Revision history
The following table provides a revision history for this document.
Table 66. Revision history
Rev. No.
Date
Substantial Changes
2
09/2016
Initial public release.
(public
release)
2.1
10/2016
• Updated the max value of "Frequency of operation", in the "LPSPI slave mode timing"
table.
(internal
version)
• Minor correction: VDDE symbol should be VDD, in the "DC electrical specifications"
table.
• Minor update in the "Clocking block diagram" figure.
• Minor update in the "Analog design" section.
2.2
06/2017
08/2017
• Updated the "Voltage and current operating ratings" section.
• Minor update in the "Pinout decoupling" figure.
• Fixed the "Description" collumn of STOP and VLPS mode rows, in the "Power
consumption operating behaviors" table.
(internal
version)
2.3
• Minor update in the "Clock interfaces" section of the feature list, on the front matter
cover pages.
• Minor fix in the VLPW row of "Power consumption operating behaviors" table: the
values for IRC8M and IRC2M are swapped.
(internal
version)
• Some updates in the "External Oscillator electrical specifications (OSC32)" and
"External Oscillator electrical specifications (OSC)" tables.
• Some updates in the "External Oscillator frequency specifications (OSC32)" and
"External Oscillator frequency specifications (OSC)" tables.
3
07/2018
• Updated the figure "Memory map".
• Minor updates in the figures "Oscillator connections scheme (OSC32)" and "Oscillator
connections scheme (OSC)".
• Some updates of VIH and VIL in the "External Oscillator electrical specifications
(OSC32)" and "External Oscillator electrical specifications (OSC)" tables, and minor
editorial fix.
(public
release)
• Updated the table "Fast internal RC Oscillator electrical specifications": FIRC is
trimmed to 48 MHz only, in this device.
• Updated the figure "ADC input impedance equivalency diagram".
• Corrected the unit as uA, in the IDDA_ADC row of the table "12-bit ADC characteristics".
• Footnote updated in the tables "LPSPI master mode timing" and "LPSPI slave mode
timing".
• Corrected the minimum and the maximum values of VLVRX in the "VDD supply LVR,
LVD and POR operating requirements" table.
• Updated the "Voltage and current operating requirements" table.
Table continues on the next page...
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Revision history
Table 66. Revision history (continued)
Rev. No.
Date
Substantial Changes
4
06/2019
• Corrected the "Clock interfaces" section in the cover page: FIRC is trimmed to 48
MHz only in this device. Up to 50 MHz DC external square wave input clock.
• Minor fix in Figure 4.
(public
release)
• Note added after Table 5.
• Statement restored in the section RTC : The time counter within the RTC is clocked
by a 32.768 kHz clock sourced from an external crystal using the oscillator, or clock
directly from RTC_CLKIN pin.
• Minor fix in Table 23.
• Some major updates in Table 53.
• Some minor updates in tables "LPSPI master mode timing" and "LPSPI slave mode
timing", including the footnotes, in the section LPSPI electrical specifications.
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Information in this document is provided solely to enable system and software implementers to use
NXP products. There are no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits based on the information in this document. NXP reserves the right to
make changes without further notice to any products herein.
How to Reach Us:
Home Page:
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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any
particular purpose, nor does NXP assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets
and/or specifications can and do vary in different applications, and actual performance may vary over
time. All operating parameters, including "typicals," must be validated for each customer application
by customer's technical experts. NXP does not convey any license under its patent rights nor the
rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
While NXP has implemented advanced security features, all products may be subject to unidentified
vulnerabilities. Customers are responsible for the design and operation of their applications and
products to reduce the effect of these vulnerabilities on customer's applications and products, and
NXP accepts no liability for any vulnerability that is discovered. Customers should implement
appropriate design and operating safeguards to minimize the risks associated with their applications
and products.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,
EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE
CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,
MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,
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Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, UMEMS, eIQ,
Immersiv3D, EdgeLock, and EdgeScale are trademarks of NXP B.V. All other product or service
names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11,
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Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK,
ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology
may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved.
Oracle and Java are registered trademarks of Oracle and/or its affiliates. The Power Architecture and
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©2015–2019 NXP B.V.
Document Number KE1xFP100M168SF0
Revision 4, 06/2019
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