935346451557_技术文档

Document Number MPC5746R

Rev. 6, 06/2017

NXP Semiconductors

Data Sheet: Technical Data

MPC5746R

SPC5746R Microcontroller

Data Sheet

Features

• For functional characteristics, see the MPC5746R

Microcontroller Reference Manual.

• This document provides electrical specifications, pin

assignments, and package diagrams for the MPC5746R

series of microcontroller units (MCUs).

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1

Introduction........................................................................................3

17.2 Flash memory Array Integrity and Margin Read

1.1 Block diagram......................................................................... 3

Package pinouts and signal descriptions............................................5

Absolute maximum ratings................................................................ 6

Electromagnetic Compatibility (EMC)..............................................7

Electrostatic discharge (ESD)............................................................ 7

Operating conditions.......................................................................... 8

DC electrical specifications................................................................11

I/O pad specification.......................................................................... 12

8.1 Input pad specifications...........................................................12

8.2 Output pad specifications........................................................15

8.3 I/O pad current specifications................................................. 17

Reset pad (PORST, RESET) electrical characteristics...................... 18

specifications...........................................................................55

17.3 Flash memory module life specifications................................55

17.4 Data retention vs program/erase cycles...................................56

17.5 Flash memory AC timing specifications.................................57

17.6 Flash read wait state and address pipeline control settings.....58

18 AC specifications............................................................................... 58

18.1 Debug and calibration interface timing...................................58

2

3

4

5

6

7

8

18.1.1

18.1.2

18.1.3

JTAG interface timing............................................ 58

Nexus interface timing............................................61

Aurora LVDS interface timing............................... 63

18.2 DSPI timing with CMOS and LVDS...................................... 65

9

18.2.1

DSPI master mode full duplex timing with CMOS

and LVDS pads.......................................................66

DSPI CMOS slave mode........................................ 78

10 Oscillator and FMPLL....................................................................... 22

11 ADC modules.....................................................................................26

11.1 ADC input description............................................................ 26

11.2 SAR ADC................................................................................26

11.3 S/D ADC................................................................................. 29

12 Temperature sensor............................................................................ 39

13 LVDS fast asynchronous serial transmission (LFAST) pad

18.2.2

18.3 FEC timing.............................................................................. 80

18.3.1

18.3.2

18.3.3

18.3.4

18.3.5

MII-lite receive signal timing (RXD[3:0],

RX_DV, RX_ER, and RX_CLK)...........................80

MII-lite transmit signal timing (TXD[3:0],

TX_EN, TX_ER, TX_CLK)...................................81

MII-lite async inputs signal timing (CRS and

COL)....................................................................... 82

MII-lite serial management channel timing

electrical characteristics..................................................................... 40

13.1 LFAST interface timing diagrams...........................................40

13.2 LFAST and MSC /DSPI LVDS interface electrical

characteristics..........................................................................42

(MDIO and MDC).................................................. 82

RMII serial management channel timing (MDIO

and MDC)............................................................... 83

RMII receive signal timing (RXD[1:0], CRS_DV)84

RMII transmit signal timing (TXD[1:0], TX_EN). 85

14 LFAST PLL electrical characteristics................................................45

15 Aurora LVDS electrical characteristics............................................. 46

16 Power management PMC POR LVD sequencing..............................47

16.1 Power management electrical characteristics..........................47

18.3.6

18.3.7

16.1.1

16.1.2

16.1.3

16.1.4

16.1.5

16.1.6

Recommended power transistors............................ 47

Power management integration.............................. 48

Regulator example for the NJD2873 transistor...... 50

Regulator example for the 2SCR574d transistor.... 51

Device voltage monitoring......................................51

Power up/down sequencing.................................... 53

18.4 UART timings.........................................................................86

18.5 eMIOS timing..........................................................................86

19 Obtaining package dimensions.......................................................... 86

20 Thermal characteristics...................................................................... 87

20.1 General notes for specifications at maximum junction

temperature..............................................................................89

17 Flash memory specifications..............................................................54

17.1 Flash memory program and erase specifications.................... 54

21 Ordering information......................................................................... 90

22 Revision history................................................................................. 91

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

2

NXP Semiconductors

Introduction

1 Introduction

The MPC5746R family of 32-bit microcontrollers is the latest achievement in integrated

automotive application controllers. It belongs to an expanding range of automotive-

focused products designed for flexibility to support a variety of applications. The

advanced and cost-efficient host processor core of the MPC5746R automotive controller

family complies with the Power Architecture embedded category. It operates at speeds as

high as 200 MHz and offers high-performance processing optimized for low power

consumption. It capitalizes on the available development infrastructure of current Power

Architecture devices and is supported with software drivers, operating systems, and

configuration code to assist with users' implementations. This section contains detailed

information on power considerations, DC/AC electrical characteristics, and AC timing

specifications.

Note

Within this document, V_{DD_HV_IO}refers to supply pins V_{DD_HV_IO_MAIN}

,

V_{DD_HV_IO_JTAG}, V_{DD_HV_IO_FEC}, and V_{DD_HV_IO_MSC}

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

3

Introduction

1.1 Block diagram

Computational Shell - Fast Domain 200MHz

Double INTC

MPC5746R

Nexus

Aurora

JTAGM JTAGC

DCI

SPU

Router

Safety Lake

SWT_1

STM_1

SWT_0

STM_0

E200 z425 - 200 MHz

Main Core_0

E200 z424 - 200 MHz

Checker Core_0s

E200 z425 - 200 MHz

Main Core_1

Nexus3p

DSP

Nexus RWA

DSP

Delay

RCCU

Delayed Lock-step

with Redundnacy

Checkers

Scalar

SP-FPU

Scalar

DSP

VLE

SP-FPU

I -Mem ctrl

I-Cache ctrl

I -Mem ctrl

I-Cache ctrl

I -Mem ctrl

I-Cache ctrl

16kB

IMEM

16kB

IMEM

Delay

RCCU

8kB - 2way

D -Mem ctrl

32kB

DMEM

Concentrator

w/ E2E Ecc

50 MHz

Nexus Data

Concentrator

w/ E2E Ecc

100 MHz

32kB

DMEM

Delay

RCCU

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

Nexus Data Trace

Trace

Instruction

32 ADD

64 DATA

Instruction

32 ADD

64 DATA

32 ADD

32 DATA

32 ADD

32 DATA

Load/ 32 ADD

64 DATA

Safety Lake

Load/ 32 ADD

64 DATA

Store

Slow ^MC²ross Bar Switch (AMBA 2.0 v6 AHB) - 32 bit - 100 MHz^M3

M1

M2

Fast Cross Bar Switch^M(³AMBA 2.0 v6^MA⁰HB) - 64 ^Mb¹it - 200 MHz

M4

S7

S0

System Memory Protection Unit (SMPU_1)

System Memory Protection Unit (SMPU_0)

S3

S2

S3

S2

S1

S4

S0

32 ADD

64 DATA

32 ADD

64 DATA

32 ADD

64 DATA

Intelligent

Bridging

Bus gasket

SRAM Ctrl

w/ E2E Ecc

Decorated

access

FLASH Controller

Dual Ported

Incl. Set-Associative

Prefetch Buffers

w/ E2E Ecc

AIPS PBridge_0

E2E Ecc

Decorate Storage

50MHz

AIPS PBridge_1

E2E Ecc

Decorate Storage

50MHz

Overlay

Backdoor

for

system

RAM

32 ADD

32 DATA

32 ADD

32 DATA

256 Page Line

2 stage Pipeline

SRAM

224KB

Buddy

Device

Interface

Calibration

Bus

Overlay

Peripheral

Cluster A

Peripheral

Cluster B

RAM

16kB

Flash

4MB

Standby

SRAM

32KB

EEPROM

256k

Standby

Regulator

Standby

Supply

NVM (Single Module)

Peripherals allocation to the bridges is

based on safety and pinout

requirements

Peripheral Domain - 50 MHz

Figure 1. Core block diagram

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

4

NXP Semiconductors

Package pinouts and signal descriptions

LINFlex_M0

LINFlex_2

LINFlex_0

FlexCAN_2

FlexCAN_0

PMC

DSPI_M0

DSPI_4

DSPI_2

DSPI_0

DECFILTER_0

PIT_RTI

ATX

PCU

DECFILTER_1

BAR

MEMU

JTAGM

SSCM

STCU2

PASS

JDC

CFLASH

LFAST

TDM

ADC_SD_2

Zipwire

SIUL2

ADC_SD_0

ADC_SAR_2

ADC_SAR_0

SENT_0

DMAMUX_3

FlexCAN_3

FlexCAN_1

CRC_1

ME

CGM

BCTU

DTS

PLLs

XOSC

RCOSC

RGM

CRC_0

REACM

CMU

FCCU

eMIOS_1

DSPI_M1

DSPI_3

eTPU_0 Reg.

eTPU_0 Code.

RAM

eTPU_0 Par.

RAM

PIT

eMIOS_0

DMAMUX_0

DMAMUX_1

DMAMUX_2

WKPU

DSPI_1

IGF

EIM

SENT_1

LINFlex_M1

LINFlex_3

LINFlex_1

ADC_SD_1

ADC_SAR_3

ADC_SAR_1

FEC

eDMA

3x SWT

2x STM

INTC

PBRIDGE_1

SEMA4

PFLASH

PCM

PRAM

2 x SMPU

2x XBIC

2x XBAR

PBRIDGE_0

Figure 2. Peripherals allocation

2 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

5

Absolute maximum ratings

3 Absolute maximum ratings

Functional operating conditions are given in the DC electrical specifications. Absolute

maximum voltages are stress ratings only, and functional operation at the maxima is not

guaranteed. Stress beyond listed maxima may affect device reliability or cause permanent

damage to the device.

Table 1. Absolute maximum ratings

Value

Symbol

Parameter

Conditions¹

Unit

Min

Max

1000k

1.5

Cycle

Lifetime power cycles

—

V

V_{DD_LV}

1.2 V core supply voltage ^{2, 3, 4}

Emulation module voltage^{2, 3, 4}

I/O supply voltage⁵

—

–0.3

V_{DD_LV_BD}

—

1.5

V_{DD_HV_IO_MAIN}

V_{DD_HV_IO_JTAG}

V_{DD_HV_IO_FEC}

—

6.0

Crystal oscillator and JTAG supply

FEC supply voltage

Reference to V_SS

6.0

Not using Ethernet Reference to

V_SS

6.0

V_{DD_HV_IO_MSC}

V_{DD_HV_PMC}

MSC supply voltage

Reference to V_SS

–0.3

6.0

V

Power Management Controller supply

voltage ⁶

—

V_{DD_HV_FLA}

V_DDSTBY

Decoupling pin for flash regulator⁶

RAM standby supply voltage⁶

S/D ADC ground voltage

—

–0.3

—

V

—

6.0

0.3

6.0

0.3

6.0

1.5

V_{SS_HV_ADV_SD}

V_{SS_HV_ADV_SAR}

V_{DD_HV_ADV_SAR}

V_{DD_HV_ADV_SD}

V_{SS_HV_ADR_SD}

V_{SS_HV_ADR_SAR}

V_{DD_HV_ADR_SAR}

V_{DD_HV_ADR_SD}

V_{DD_LV_BD}- V_{DD_LV}

Reference to V_SS

Reference to V_{SS_HV_ADV_SAR}

Reference to V_{SS_HV_ADV_SD}

Reference to V_SS

Reference to V_{SS_HV_ADR_SAR}

Reference to V_{SS_HV_ADR_SD}

SAR ADC ground voltage

SAR ADC supply voltage

S/D ADC supply voltage

S/D ADC ground reference

SAR ADC ground reference

SAR ADC alternate reference

S/D ADC alternate reference

Emulation module supply differential to 1.2

V core supply

—

V_SS– V_{SS_HV_ADR_SAR}V_{SS_HV_ADR_SAR}differential voltage

V_SS– V_{SS_HV_ADR_SD}V_{SS_HV_ADR_SD}differential voltage

V_SS– V_{SS_HV_ADV_SAR}V_{SS_HV_ADV_SAR}differential voltage

V_SS– V_{SS_HV_ADV_SD}V_{SS_HV_ADV_SD}differential voltage

—

–0.3

—

0.3

6.0

—

V

V_IN

I/O input voltage range⁷

, 8, 9

Relative to V_{SS_HV_IO}

8, 9

Relative to V_{DD_HV_IO}

0.3

5

I_INJD

Maximum DC injection current for digital

pad

Per pin, applies to all digital pins

–5

mA

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

6

NXP Semiconductors

Electromagnetic Compatibility (EMC)

Table 1. Absolute maximum ratings (continued)

Value

Symbol

Parameter

Conditions¹

Unit

Min

Max

I_INJA

Maximum DC injection current for analog Per pin, applies to all analog pins

pad

–5

5

mA

10, 11

I_MAXSEG

Maximum current per I/O segment

—

–120

–55

120

175

mA

°C

T_STG

STORAGE

T_SDR

Storage temperature range and non-

operating times

—

Maximum storage time, assembled part

programmed in ECU

Maximum solder temperature¹²

No supply; storage temperature

in range –40 °C to 60 °C

—

20

yrs

°C

260

—

Pb-free package

Moisture sensitivity level¹³

MSL

—

3

—

1. Voltage is referenced to V_SSunless otherwise noted.

2. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum T_J= 150 °C, remaining time as defined in note -1 and

note -1.

3. Allowed 1.375 – 1.45 V for 10 hours cumulative time at maximum T_J= 150 °C, remaining time as defined in note -1.

4. 1.32 – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at

maximum T_J= 150 °C.

5. Allowed 5.5 – 6.0 V for 10 hours cumulative time at maximum T_J= 150 °C, remaining time at or below 5.0 V +10%.

6. Allowed 3.6 – 4.5 V for 10 hours cumulative time at maximum T_J= 150 °C, remaining time at or below 3.3 V +10%. This is

an internally regulated supply. Values given are for reference only.

7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current

condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin

to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal

calculations.

8. Relative value can be exceeded, if design measures are taken to ensure injection current limitation (parameters I_INJDand

I_INJA).

9. V_{DD_HV_IO}/V_{SS_HV_IO}refers to supply pins and corresponding grounds: V_{DD_HV_IO_MAIN}, V_{DD_HV_IO_JTAG}, V_{DD_HV_IO_FEC}

V_{DD_HV_IO_MSC}

,

.

10. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V_{DD_HV_IO}power segment is

defined as one or more GPIO pins located between two V_{DD_HV_IO}supply pins.

11. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O

segment current.

12. Solder profile per IPC/JEDEC J-STD-020D.

13. Moisture sensitivity per JEDEC test method A112.

4 Electromagnetic Compatibility (EMC)

EMC measurements to IC-level IEC standards are available from NXP on request.

5 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

7

Operating conditions

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

Device failure is defined as: "If after exposure to ESD pulses, the device does not meet

the device specification requirements, which includes the complete DC parametric and

functional testing at room temperature and hot temperature. Maximum DC parametrics

variation within 10% of maximum specification."

Table 2. ESD ratings

Parameter

Conditions

All pins

Value

2000

500

Unit

V

ESD for Human Body Model (HBM)¹

ESD for field induced Charged Device Model (CDM)²

All pins

V

1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing

2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level

6 Operating conditions

The following table describes the operating conditions for the device, and for which all

specifications in the data sheet are valid, except where explicitly noted.

The device operating conditions must not be exceeded in order to guarantee proper

operation and reliability.

NOTE

All power supplies need to be powered up to ensure normal

operation of the device.

Table 3. Device operating conditions

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Frequency

T_J-40 °C to 150 °C

Temperature

f_SYS

Device operating frequency¹

—

200

MHz

T_J

Operating temperature range -

junction

–40.0

—

150.0

125.0

°C

T_A(T_Lto T_H)

Operating temperature range -

ambient

Voltage

LVD/HVD enabled

LVD/HVD disabled^{4, 5, 6}

V_{DD_LV}

External core supply voltage^{2, 3}

I/O supply voltage ⁷

1.2

1.18

3.5

—

1.32

1.38

5.5

V

V_{DD_HV_IO_MAIN}

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

8

NXP Semiconductors

Operating conditions

Table 3. Device operating conditions (continued)

Value

Unit

Symbol

Parameter

Conditions

Min

3.5

3.0

3.5

3.0

3.5

3.0

3.5

Typ

—

Max

5.5

3.6

5.5

3.6

5.5

3.6

5.5

V_{DD_HV_IO_FEC}

FEC I/O supply voltage⁸

5 V range

V

3.3 V range

5 V range

V_{DD_HV_IO_MSC}

MSC I/O supply voltage⁹

JTAG I/O supply voltage¹¹

3.3 V range

5 V range

10

V_{DD_HV_IO_JTAG}

3.3 V range

Full functionality

12

V_{DD_HV_PMC}

Power Management Controller

(PMC) supply voltage

13

V_DDSTBY

RAM standby supply voltage¹⁴

—

1.3

—

5.9

0.9

—

V

V_{STBY_BO}

Standby RAM brownout voltage

V_{DD_LV_STBY_SW}

Standby RAM switch V_{DD_LV}voltage

threshold

S/D ADC supply voltage^{15, 16}

0.95

—

V_{DD_HV_ADV_SD}

V_{DD_HV_ADV_SAR}

4.5

3.0

—

5.5

V

SAR ADC supply voltage

—

17

V_{DD_HV_ADR_SD}

S/D ADC reference

—

3.0

—

5.5

25

V

V_{DD_HV_ADR_SD}

–

S/D ADC reference differential

voltage

mV

V_{DD_HV_ADV_SD}

V_{SS_HV_ADR_SD}

V_{SS_HV_ADV_SD}

–

V_{SS_HV_ADR_SD}differential voltage

–25

—

25

mV

—

V_{DD_HV_ADR_SAR}

SAR ADC reference

3.0

—

5.5

25

V

V_{DD_HV_ADR_SAR}

V_{DD_HV_ADV_SAR}

–

SAR ADC reference differential

voltage

mV

V_{SS_HV_ADR_SAR}

V_{SS_HV_ADV_SAR}

–

V_{SS_HV_ADR_SAR}differential voltage

–25

—

25

mV

—

V_{SS_HV_ADV_SD}– V_SSV_{SS_HV_ADV_SD}differential voltage

V_{SS_HV_ADV_SAR}– V_SSV_{SS_HV_ADV_SAR}differential voltage

—

–25

—

25

mV

—

V_{RAMP_VDD_LV}

Slew rate on power supply pins

(VDD_LV)

Ramp up

Ramp down

Ramp up

Ramp down

0.069

0.0345

0.148

0.125

100 V/ms

100

V_{RAMP_VDD_HV_IO_MAIN}, Slew rate on power supply pins

100 V/ms

100

V_{RAMP_VDD_HV_PMC}

(VDD_HV_IO_MAIN,

VDD_HV_PMC)

Injection current

I_IC

DC injection current (per pin)^{18, 19, 20}Digital pins and analog pins

–3.0

–80

—

3.0

80

mA

I_MAXSEG

Maximum current per power

—

segment^{21, 22}

1. Maximum operating frequency is applicable to the computational cores and platform for the device.

2. Core voltage as measured on device pin to guarantee published silicon performance.

3. During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct

silicon operation is guaranteed. See power management and reset management for description.

4. Maximum core voltage is not permitted for entire product life. See absolute maximum rating.

5. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor

externally supply voltage may result in erroneous operation of the device.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

9

Operating conditions

6. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the

reset sequence, and the LVD/HVD are active until that point.

7. The pad are operative till 3.0V full performance. The IRC oscillator is supplied by this pin and it is setting the min voltage

limit.

8. FEC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

9. MSC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

10. If XOSC is enabled via DCF_UTEST_Miscellaneous[XOSC_EN], V_{DD_HV_IO_JTAG}must be within the operating range

before RESET pin is released.

11. JTAG will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

12. The startup of flash regulator and memory initialization immediately after Phase0 of reset sequence could cause a drop of

the PMC supply. No LVD event will be generated as during this time the LVD monitors are not enabled.

13. V_DDSTBYsupply must be present before and after power up/down of the device supplies and the ramp rate should be less

than 33.3 kV/s.

14. RAM retention is not guaranteed below 1.3 V, but no effect on RAM operation for voltages below 1.3 V when V_{DD_LV}is

above the minimum value.

15. For supply voltages between 3.6V and 4.5V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will

recover to a fully functional state when the voltage rises above 4.5V.

16. V_{DD_HV_ADV_SD}must be higher or equal than the V_{DD_HV_ADV_SAR}supply to guarantee full performance. It is recommended

to connect the V_{DD_HV_ADV_SD}to V_{DD_HV_ADV_SAR}at board level.

17. Temperature Sensor and its associated Band-Gap reference are supplied by this pin. The temperature sensor

performance is guaranteed only between 4.5 V and 5.5 V.

18. Full device lifetime without performance degradation.

19. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the

absolute maximum ratings table for maximum input current for reliability requirements.

20. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is

above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network

calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more

information, see the device characterization report.

21. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V_{DD_HV_IO}power segment is

defined as one or more GPIO pins located between two V_{DD_HV_IO}supply pins.

22. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O

segment current.

Table 4. Emulation (buddy) device operating conditions

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Frequency

—

Standard JTAG 1149.1/1149.7 frequency

High-speed debug frequency

Data trace frequency

—

50

MHz

320 MHz

1250 MHz

Temperature

T_{J_BD}

Device junction operating temperature range

Ambient operating temperature range

Packaged devices –40.0

—

150.0 °C

125.0 °C

T_{A _BD}

Voltage

V_{DD_LV_BD}Buddy core supply voltage

—

1.18

3.0

—

1.32

5.5

V

V_{DD_HV_IO_B}Buddy I/O supply voltage

D

V_{RAMP_BD}Buddy slew rate on power supply pins

—

500 V/ms

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

10

NXP Semiconductors

DC electrical specifications

7 DC electrical specifications

The following table describes the DC electrical specifications.

Table 5. DC electrical specifications

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

I_{DD_LV}

Maximum operating

current on the V_{DD_LV}

supply ¹

MPC5746R/

MPC5745R

—

700

mA

MPC5743R/

MPC5742R

—

610

40

I_{DD_LV_PE}

Operating current on the

V_{DD_LV}supply for flash

program/erase

mA

—

I_{DD_HV_PMC}

Operating current on the Flash read

—

40

70

35

10

40

V_{DD_HV_PMC}supply²

Flash P/E

PMC only

Operating current on the Flash read

V_{DD_HV_PMC}supply

(internal core reg

bypassed)

mA

Flash P/E

I_VRCCTRL

Core regulator DC current

—

25

575

55

mA

µA

output on VRC_CTRL pin

I_{DDSTBY_ON}

32 KB RAM Standby

Leakage Current

V_{DDSTBY @}1.3 V to

5.9 V, T_J= 150 °C

(standby regulator on,

V_{DDSTBY @}1.3 V to

5.9 V, T_A= 40 °C

RAM not operational)^{3, 4, 5}

V_{DDSTBY @}1.3 V to

5.9 V, T_A= 85 °C

65

I_{DDSTBY_REG}

I_{DD_LV_BD}

32 KB RAM Standby

Regulator Current ⁶

V_{DDSTBY @}1.2 V to

5.9 V, Tj = 150 °C

50

µA

BD Debug/Emulation low T_J= 150 °C

voltage supply operating

250

mA

—

V_{DD_LV_BD}= 1.32

V

current⁷

I_{DD_HV_IO_BD}

Debug/Emulation high

voltage supply operating

current (Aurora + JTAG/

LFAST)

T_J= 150 °C

—

130

mA

I_BG

Bandgap reference

current consumption

—

600

120

µA

I_{DD_BD_STBY}

BD Debug/Emulation low T_J= 150 °C

voltage supply standby

current

mA

V_{DD_LV_BD}= 1.32

V

I_VDDA

VDDA supply current

—

16

25

mA

1. Value is derived from a typical application at 200MHz, Core 0 Data and Instruction Cache On, Core 1 in Lockstep mode,

typical usage for SARADC, SDADC, DMA, eTPU, eMIOS, CAN, MSC, SPI, SENT, PIT, and Flash reads.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

11

I/O pad specification

2. This value is considering the use of the internal core regulator with an external ballast with the minimum value of h_FEof 60.

3. Data is retained for full TB range of -40 °C to 125 °C. RAM supply switch to the standby regulator occurs when the V_{DD_LV}

supply falls below 0.95V.

4. V_DDSTBYmay be supplied with a non-regulated power supply, but the absolute maximum voltage on V_DDSTBYgiven in the

absolute maximum ratings table must be observed.

5. The maximum value for I_{DDSTBY_ON}is also valid when switching from the core supply to the standby supply, and when

powering up the device and switching the RAM supply back to V_{DD_LV}

6. When the V_DDSTBYpin is powered, the standby RAM regulator current is present on the pin, regardless if the device is in

standby mode or not. No current is present on the pin when V_DDSTBYpin is set to 0V, disabling the standby regulator.

7. Worst case usage (data trace, data overlay, full Aurora utilization).

8 I/O pad specification

The following table describes the different pad type configurations.

Table 6. I/O pad specification descriptions

Pad type

Description

General-purpose I/O pad

General-purpose I/O pads with four selectable output slew

rate settings. The GPIO pads have CMOS input threshold

levels.

LVDS pads

Low Voltage Differential Signal interface pads

Input only pads

These pads, which ensure low input leakage, are associated

with the ADC channels. The digital inputs of these pads have

CMOS, and TTL input threshold levels.

Note

Each I/O pin on the device supports specific drive

configurations. See the signal description table in the device

reference manual for the available drive configurations for each

I/O pin.

8.1 Input pad specifications

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

12

NXP Semiconductors

I/O pad specification

V

IN

V

DD

V

IH

V

HYS

V

IL

V

INTERNAL

(SIUL register)

Figure 3. I/O input DC electrical characteristics definition

Table 7. I/O input DC electrical characteristics

Symbol

Parameter¹

Conditions

Value²

Unit

Max

Min

Typ

VIHTTL

TTL input high level

TTL input low level

3.0 V < V_{DD_HV_IO}< 5.5 V

2.0

—

V_{DD_HV_IO}

0.3

+

V

VILTTL

V_SS-0.3

0.3

—

0.6

—

100³

V

VHYSTTL

TTL level input hysteresis 3.0 V < V_{DD_HV_IO}< 5.5 V

V

VDRFTTTL TTL Input VIL/VIH

temperature drift

—

mV

VIHCMOS_H CMOS input high level

(with hysteresis)

3.0 V < V_{DD_HV_IO}< 5.5 V

0.65 *

V_{DD_HV_IO}

—

V_{DD_HV_IO}

+ 0.3

V

VIHCMOS

CMOS input high level

(without hysteresis)

3.0 V < V_{DD_HV_IO}< 5.5 V

0.55 *

V_{DD_HV_IO}

—

V_{DD_HV_IO}

0.3

+

V

VILCMOS_H CMOS input low level (with 3.0 V < V_{DD_HV_IO}< 5.5 V

hysteresis)

V_SS-0.3

0.35 *

V_{DD_HV_IO}

0.4 *

VILCMOS

CMOS input low level

(without hysteresis)

3.0 V < V_{DD_HV_IO}< 5.5 V

—

V_SS-0.3

—

V

V_{DD_HV_IO}

—

VHYSCMOS CMOS input hysteresis

0.1 *

V

V_{DD_HV_IO}

—

VDRFTCMO CMOS Input VIL/VIH

100³

mV

S

temperature drift

INPUT CHARACTERISTICS⁴

I_LKGDigital input leakage

GPIO pins

-1.0

—

1.0

8

µA

pF

V_SS< V_IN< V_{DD_HV_IO}

GPIO and Input pins

C_IN

Input capacitance

1. Supported input levels vary according to pad types. Pad type "pad_sr_hv" supports only the CMOS input level, while pad

type "pad_isatww_st_hv" supports TTL and CMOS levels. Refer to the IO spreadsheet attached to the Reference Manual

for the pad type of each pin.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

13

I/O pad specification

2. TTL level input specifications apply to the digital inputs on the analog input pins, and not the GPIO pins on the device.

3. In a 1 ms period, assuming stable voltage and a temperature variation of 30 ꢀ°C, VIL/VIH shift is within 50 mV. For

SENT requirement, refer to Note in the "I/O pad current specifications" section.

4. For LFAST, microsecond bus, and LVDS input characteristics, refer to dedicated communication module chapters.

The following table provides the current specifications for the GPIO pad weak pull-up

and pull-down.

Table 8. GPIO Pull-Up/Down DC electrical characteristics

Symbol

Parameter

Conditions

Value

Typ

Unit

Min

Max

|IWPU|

Weak pull-up current

absolute value¹

Vin = VIH = 0.65 * V_{DD_HV_IO}

4.5V < V_{DD_HV_IO}< 5.5V

3.0V < V_{DD_HV_IO}< 3.6V

Vin = VIL = 0.35 * V_{DD_HV_IO}

4.5V < V_{DD_HV_IO}< 5.5V

3.0V < V_{DD_HV_IO}< 3.6V

Vin = VIL = 1.1V (TTL)

µA

30

18

—

120

80

4.5V < V_{DD_HV_IO}< 5.5V

Vin = VIH = 0.65 * V_{DD_HV_IO}

4.5V < V_{DD_HV_IO}< 5.5V

3.0V < V_{DD_HV_IO}< 3.6V

Vin = VIL = 0.35 * V_{DD_HV_IO}

4.5V < V_{DD_HV_IO}< 5.5V

3.0V < V_{DD_HV_IO}< 3.6V

Vin = VIL = 0.9V (TTL)

—

130

|IWPD|

Weak pull-down current

absolute value

µA

—

120

80

30

18

—

4.5V < V_{DD_HV_IO}< 5.5V

16

—

1. Weak pull-up/down is enabled within tWK_PU = 1 µs after internal/external reset has been asserted. Output voltage will

depend on the amount of capacitance connected to the pin.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

14

NXP Semiconductors

I/O pad specification

t

WK_PU

V

DD_HV_IO

V

DD_POR

RESET

(INTERNAL)

pull-up

enabled

YES

NO

(1)

PAD

(1)

POWER-UP

Application defined

RESET

Application defined

POWER-DOWN

1

Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.

Figure 4. Weak pull-up electrical characteristics definition

Analog input leakage and pull up/down information is located in the ADC input

description section.

8.2 Output pad specifications

The following figure provides the description of output DC electrical characteristics.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

15

I/O pad specification

V

INTERNAL

(SIUL2 register)

V

HYS

t

PD

t

PD

t

V

SKEW20-80

out

90%

80%

50%

20%

10%

t

R20-80

t

F20-80

t

R10-90

t

F10-90

t

(max) = MAX(t

;t

)

TR

R10-90 F10-90

t

(max) = MAX(t

;t

)

TR20-80

R20-80 F20-80

(min) = MIN(t

;t

)

TR

R10-90 F10-90

(min) = MIN(t

;t

)

TR20-80

R20-80 F20-80

t

= t

-t_F20-80

SKEW20-80

R20-80

Figure 5. I/O output DC electrical characteristics definition

Table 9. GPIO pad output buffer electrical characteristics

Symbol

Parameter

Conditions

Value ¹, ²

Unit

Min

0.8 *

VDD_H

V_IO

Typ

Max

VOH

GPIO pad output high voltage 4.5V < VDD_HV_IO < 5.0V

MSCR[OERC] = 11, IOH = 38mA

MSCR[OERC] = 10, IOH = 19mA

MSCR[OERC] = 01, IOH = 10mA

MSCR[OERC] = 00, IOH = 5mA

—

V

3.0V < VDD_HV_IO < 3.6V

0.8 *

VDD_H

V_IO

—

MSCR[OERC] = 11, IOH = 19mA

MSCR[OERC] = 10, IOH = 10mA

MSCR[OERC] = 01, IOH = 7mA

MSCR[OERC] = 00, IOH = 5mA

VOL

GPIO pad output low voltage 4.5V < VDD_HV_IO < 5.0V

MSCR[OERC] = 11, IOL = 48mA

MSCR[OERC] = 10, IOL = 24mA

MSCR[OERC] = 01, IOL = 12mA

Table continues on the next page...

—

0.2 *

VDD_H

V_IO

V

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

16

NXP Semiconductors

I/O pad specification

Table 9. GPIO pad output buffer electrical characteristics (continued)

Symbol

Parameter

Conditions

Value ¹, ²

Unit

Min

Typ

Max

MSCR[OERC] = 00, IOL = 6mA

3.0V < VDD_HV_IO < 3.6V

—

0.2 *

VDD_H

V_IO

MSCR[OERC] = 11, IOL = 24mA

MSCR[OERC] = 10, IOL = 12mA

MSCR[OERC] = 01, IOL = 9mA

MSCR[OERC] = 00, IOL = 6mA

tR_F

GPIO pad output transition

time (rise/fall)

MSCR[OERC] = 11

CL = 25pF

—

1.5

3

ns

%

CL = 50pF

CL = 25pF

CL = 50pF

MSCR[OERC] = 10

MSCR[OERC] = 01

MSCR[OERC] = 00

6.5

25

40

6

tPD

GPIO pad output propagation MSCR[OERC] = 11

delay time

7.5

11.5

45

75

10

MSCR[OERC] = 10

MSCR[OERC] = 01

MSCR[OERC] = 00

|t_{SKEW_W}

|

Difference between rise and

fall time

-

1. All GPIO pad output specifications are valid for 3.0V < VDD_HV_IO < 5.5V, except where explicitly stated.

2. All values need to be confirmed during device validation.

8.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is

associated to a VDD_HV_IO/VSS_HV_IO supply pair.

The following tables provides I/O consumption figures.

Table 10. I/O current consumption at VDD_HV_IO = 3.6 V

Cell

VDD_HV_IO

(V)

Load (pF)

Period1 (ns)

MSCR[OERC] Idde AVG (mA) Idde RMS (mA)

pad_sr_hv

3.63

25

50

12

15

39

16

23

66

90

11

10

01

13

16

20

8

37

36

44

20

21

37

4

200

25

50

9

200

50

12

1.4

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

17

Reset pad (PORST, RESET) electrical characteristics

Table 10. I/O current consumption at VDD_HV_IO = 3.6 V (continued)

Cell

VDD_HV_IO

(V)

Load (pF)

Period1 (ns)

MSCR[OERC] Idde AVG (mA) Idde RMS (mA)

200

50

130

150

200

3

1.6

4

9

4

00

200

11

Table 11. I/O current consumption at VDD_HV_IO = 5.5 V

Cell

VDD_HV_IO

(V)

Load (pF)

Period1 (ns)

MSCR[OERC] Idde AVG (mA) Idde RMS (mA)

pad_sr_hv

5.5

25

50

9

10.2

26

11

10

37

42

46

25

21

26

6

83

89

92

53

44

49

14

35

9

200

25

10.5

16

50

200

50

44

54

01

00

200

50

80

15

4

80

200

130

9

22

In order to ensure device reliability, the average current of the I/O on a single segment

should remain below the I_MAXSEGvalue given in the table "Absolute maximum ratings".

In order to ensure device functionality, the sum of the dynamic and static current of the

I/O on a single segment should remain below the I_MAXSEGvalue given in the table

"Device operating conditions".

Note

The MPC5746R I/O Signal Description and Input Multiplexing

Tables are contained in a Microsoft Excel workbook file

attached to the Reference Manual.

9 Reset pad (PORST, RESET) electrical characteristics

The device implements a dedicated bidirectional reset pin (PORST).

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

18

NXP Semiconductors

Reset pad (PORST, RESET) electrical characteristics

NOTE

PORST pin does not require active control. It is possible to

implement an external pull-up to ensure correct reset exit

sequence. Recommended value is 4.7 kohm.

PORST can optionally be connected to an external power-on

supply circuitry.

No restrictions exist on reset signal slew rate apart from

absolute maximum rating compliance.

V

DD

V

DDMIN

V

DDPOR

PORST

V

IH

V

IL

device start-up phase

PORST undriven

device reset by

internal power-on reset

device reset

forced by external circuitry

PORST driven low

by internal power-on reset

Figure 6. Start-up reset requirements

The following figure describes device behavior depending on supply signal on PORST:

1. PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis.

Device remains in current state.

2. PORST low pulse duration is too short—it is filtered by a low pass filter. Device

remains in current state.

3. PORST low pulse is generating a reset:

• a) PORST low but initially filtered during at least W_FRST. Device remains

initially in current state.

• b) PORST potentially filtered until W_NFRST. Device state is unknown. It may

either be reset or remains in current state depending on extra condition

(temperature, voltage, device).

• c) PORST asserted for longer than W_NFRST. Device is under reset.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

19

Reset pad (PORST, RESET) electrical characteristics

V_PORST

V

DD

V

IH

V

HYS

V

IL

internal

reset

filtered by

hyst er esi s

filtered by

lowp ass filter

unknown reset

state

filtered by

lowp ass filter

device under hardware reset

W

FRST

W

NFRST

3b

1

2

3a

3c

Figure 7. Noise filtering on reset signal

Table 12. Reset electrical characteristics

Symbol Parameter

Conditions

Value¹

Typ

—

Unit

Min

Max

V_IHReset Input high level TTL

V_ILReset Input low level TTL

3.5 V < VDD_HV_IO < 5.5 V

2.0

V_{DD_HV_IO}

0.3

+

V

3.5 V < VDD_HV_IO < 3.6 V

4.5 V < VDD_HV_IO < 5.5 V

3.5 V < VDD_HV_IO < 5.5 V

V_SS- 0.3

300

—

0.6

0.8

—

V_HYS

Reset

Input hysteresis TTL

Input high level CMOS

Input low level CMOS

Input hysteresis CMOS

mV

V

V_IH

PORST

3.5 V < VDD_HV_IO < 5.5 V

—

0.65 *

V_{DD_HV_IO}

—

V_{DD_HV_IO}

0.3

V_IL

PORST

V_SS- 0.3

0.35 *

V_{DD_HV_IO}

V

V_HYS

0.1 *

V_{DD_HV_IO}

—

mV

V

PORST

V_{DD_POR}Minimum supply for strong pulldown

activation

—

1.2

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

20

NXP Semiconductors

Reset pad (PORST, RESET) electrical characteristics

Table 12. Reset electrical characteristics (continued)

Symbol Parameter

Conditions

Value¹

Typ

—

Unit

Min

Max

I_{OL_R}

Strong pull-down current²

Device under power-on reset

V_OL= 0.35 * V_{DD_HV_IO}

14

—

mA

3.5 V < VDD_HV_IO < 3.6 V

Device under power-on reset

V_OL= 0.35 * V_{DD_HV_IO}

35

30

18

—

30

18

—

4.5 V < VDD_HV_IO < 5.5 V

|I_WPU

Reset

|

Weak pull-up current absolute value RESET pin

μA

V_IN= VIH = 0.65 * V_{DD_HV_IO}

4.5 V < VDD_HV_IO < 5.5 V

RESET pin

—

V_IN= VIH = 0.65 * V_{DD_HV_IO}

3.5 V < VDD_HV_IO < 3.6 V

RESET pin

120

80

120

80

—

V_IN= VIL = 0.35 * V_{DD_HV_IO}

4.5 V < VDD_HV_IO < 5.5 V

RESET pin

V_IN= VIL = 0.35 * V_{DD_HV_IO}

3.5 V < VDD_HV_IO < 3.6 V

PORST pin

|I_WPD

PORST value

|

Weak pull-down current absolute

μA

V_IN= VIH = 0.65 * V_{DD_HV_IO}

4.5 V < VDD_HV_IO < 5.5 V

PORST pin

V_IN= VIH = 0.65 * V_{DD_HV_IO}

3.5 V < VDD_HV_IO < 3.6 V

PORST pin

V_IN= VIL = 0.35 * V_{DD_HV_IO}

4.5 V < VDD_HV_IO < 5.5 V

PORST pin

—

V_IN= VIL = 0.35 * V_{DD_HV_IO}

3.5 V < VDD_HV_IO < 3.6 V

—

W_FRST

PORST and RESET input filtered

pulse

—

500

—

ns

W_NFRSTPORST and RESET input not

filtered pulse

—

2000

W_FNMI

ESR1 input filtered pulse

—

20

—

ns

W_NFNMI

ESR1 input not filtered pulse

400

1. An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and RESET pins for fast negation of

the signals.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

21

Oscillator and FMPLL

2. Strong pull-down is enabled during power up / phase0 on both pads but after that a weak pull-down is enabled on PORST

and a weak pull-up is enabled on RESET.

10 Oscillator and FMPLL

Two on-chip PLLs, the peripheral clock and reference PLL (PLL0), and the frequency

modulated system PLL (PLL1) generate the system and auxiliary clocks from the

external oscillator.

PLL0_PHI0

RCOSC

PLL0

PLL0_PHI1

XOSC

PLL1_PHI0

PLL1

Figure 8. PLL integration

Table 13. PLL0 electrical characteristics

Value

Typ

—

Symbol

Parameter

Conditions

Min

Unit

Max

40

f_PLL0IN

PLL0 input clock¹

PLL0 input clock duty cycle¹

—

8

40

MHz

%

Δ_PLL0IN

—

60

f_PLL0VCOPLL0 VCO frequency

f_PLL0PHI0PLL0 output clock PHI0

t_PLL0LOCKPLL0 lock time

600

4.762

—

1250

400

110

300²

MHz

µs

—

|

Δ

PLL0_PHI1 single period jitter

f_PLL0IN= 20 MHz (resonator)

f_PLL0PHI1= 40 MHz, 6-

sigma

—

ps

|

PLL0PHI1SPJ

Δ_PLL0LTJPLL0 output long term jitter²

10 periods accumulated

jitter (80 MHz frequency),

6-sigma pk-pk

–250

–300

–650

—

250

300

650

ps

f_PLL0IN= 20 MHz (resonator), VCO

frequency = 800 MHz

16 periods accumulated

jitter (50 MHz frequency),

6-sigma pk-pk

long term jitter

(< 1MHz frequency), 6-

sigma pk-pk

I_PLL0

PLL0 consumption

FINE LOCK state

—

5

mA

1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted

when using internal RCOSC or external oscillator is used in functional mode.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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NXP Semiconductors

Oscillator and FMPLL

2. V_{DD_LV}noise due to application in the range V_{DD_LV}= 1.25V (+/-5%) with frequency below PLL bandwidth (40 KHz) will be

filtered.

Table 14. FMPLL1 electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

38

Typ

—

Max

78

f_PLL1IN

PLL1 input clock¹

PLL1 input clock duty cycle¹

—

MHz

%

Δ_PLL1IN

35

65

f_PLL1VCOPLL1 VCO frequency

f_PLL1PHI0PLL1 output clock PHI0

t_PLL1LOCKPLL1 lock time

600

4.762

—

1250

200

100

250

2

MHz

µs

f_PLL1MODPLL1 modulation frequency

—

kHz

%

|δ _PLL1MOD| PLL1 modulation depth (when enabled) Center spread

0.25

0.5

—

Down spread

4

500²

%

|

PLL1_PHI0 single period peak to peak f_PLL1PHI0= 200 MHz, 6-

ps

Δ

jitter

sigma pk-pk

|

PLL1PHI0SPJ

I_PLL1

PLL1 consumption

FINE LOCK state

—

6

mA

1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when

using internal PLL0 or external oscillator is used in functional mode.

2. 1.25V +/-5%, application noise below 40kHz at V_{DD_LV}pin - no frequency modulation

All oscillator specifications are valid for V_{DD_HV_IO_JTAG}= 3.0 V to 5.5 V.

Table 15. XOSC External Oscillator electrical specifications

Value

Max

Unit

Symbol

Parameter

Conditions

Min

4

f_XTAL

Crystal Frequency Range¹

—

8

MHz

>8

20

40

16MHz < freq < 40MHz (at present, freq =

20M and 40M have been validated, but still

needs to be carried out for freq = 16MHz)

>20

t_cst

t_rec

Crystal start-up time^{2, 3}

Crystal recovery time⁴

EXTAL input high voltage⁵

(External Reference)

T_J= 150 °C, 20 MHz ≤ f ≤ 40 MHz

—

5

ms

V

0.5

—

V_IHEXT

V_REF= 0.28 * V_{DD_HV_IO_JTAG}

V_REF

+ 0.6

V_ILEXT

EXTAL input low voltage

(External Reference)

V_REF= 0.28 * V_{DD_HV_IO_JTAG}

—

V_REF

0.6

-

V

C_{S_EXTAL}

Total on-chip stray capacitance

on EXTAL pin⁶

BGA

QFP

BGA

QFP

4.75

5.25

4.75

5.25

3

5.25

5.75

5.25

5.75

13

pF

C_{S_XTAL}

Total on-chip stray capacitance

on XTAL pin⁶

pF

g_m

Oscillator Transconductance

T_J= -40 °C to 150

°C

f_XTAL≤ 8 MHz

f_XTAL≤ 20 MHz

mA/V

9

35

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

23

Oscillator and FMPLL

Table 15. XOSC External Oscillator electrical specifications

(continued)

Value

Max

Unit

Symbol

Parameter

Conditions

Min

12

f_XTAL≤ 40 MHz

43

V_EXTAL

I_XTAL

Oscillation Amplitude on the

EXTAL pin after startup⁷

XTAL current⁷,⁸

T_J= –40 °C to 150

0.5

1.6

V

°C

T_J= –40 °C to 150

°C

—

14

mA

1. The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40MHZ.

2. This value is determined by the crystal manufacturer and board design.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load

capacitor value.

5. This parameter is guaranteed by design rather than 100% tested.

6. See crystal manufacturer's specification for recommended load capacitor (C_L) values.The external oscillator requires

external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (C_{S_EXTAL}/C_{S_XTAL}

and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load

)

capacitor value is selected via S/W to match the crystal manufacturer's specification, while accounting for on-chip and PCB

capacitance. The capacitance on “EXTAL” and “XTAL” by internal capacitance array is controlled by the XOSC LOAD CAP

SEL field of the UTEST Miscellaneous DCF client. See the DCF Records chapter of the Reference Manual.

7. Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The

function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to

reduce power, distortion, and RFI, and to avoid overdriving the crystal. The operating point of the ALC is dependent on the

crystal value and loading conditions.

8. IXTAL is the oscillator bias current out on the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum

current during startup of the oscillator. The current after oscillation is typically in the 2-3 mA range and is dependant on the

load and series resistance of the crystal. Test circuit is shown in the figure below.

Table 16. Selectable load capacitance

load_cap_sel[4:0] from DCF record

Capacitance on EXTAL (C_EXTAL)/XTAL (C_XTAL)

^{, 1, 2}(pF)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

1.0

2.0

2.9

3.8

4.8

5.7

6.6

7.5

8.5

9.4

10.3

11.2

12.2

13.1

14.0

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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NXP Semiconductors

Oscillator and FMPLL

Table 16. Selectable load capacitance (continued)

load_cap_sel[4:0] from DCF record

01111

10000-11111

Capacitance on EXTAL (C_EXTAL)/XTAL (C_XTAL

15.0

N/A

)

^{, 1, 2}(pF)

1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values

vary 12% across process, 0.25% across voltage, and no variation across temperature.

2. Values in this table do not include the internal stray capacitances C_xtal/C_extal

.

V

DDOSC

Bias

Current

ALC

I_XTAL

XTAL

EXTAL

Comparator

A

OFF

VSSOSC

V

VSS

Conditions

_EXTAL=0 V

Z = R + j L

V

_XTAL=0 V

Tester

ALC INACTIVE

PCB

GND

Figure 9. Test circuit

Table 17. Internal RC Oscillator electrical specifications

Value

Typ

16

Symbol

Parameter

Conditions

Unit

Min

—

Max

—

f_Target

IRCOSC target frequency

—

MHz

%

δf_{var_noT}

IRC frequency variation without

temperature compensation

T < 150 °C

–8

—

8

δf_{var_T}

IRC frequency variation with

temperature compensation

T < 150 °C

–3

–1

—

3

1

%

δf_{var_SW}

IRC software trimming accuracy

Trimming

temperature

δf_TRIM

IRC software trimming step

—

+40/-48

—

5

kHz

µs

T_{start_noT}

Startup time to reach within fvar_noT

Factory trimming

already applied

T_{start_T}

Startup time to reach within f_{var_T}

Factory trimming

already applied

—

120

µs

Table continues on the next page...

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25

ADC modules

Table 17. Internal RC Oscillator electrical specifications (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

I_AVDD5

Current consumption on 5 V power

supply

After T_{start_T}

—

400

µA

I_DVDD12

Current consumption on 1.2 V power

supply

After T_{start_T}

—

175

µA

11 ADC modules

This device's analog sub-system contains a total of four independent 12-bit Successive

Approximation (SAR) ADCs and three independent 16-bit Sigma-Delta (S/D) ADCs.

11.1 ADC input description

The following table provides the current specifications for the analog input pad weak

pull-up and pull-down, and the resistance for the analog input bias/diagnostic pull up/

down.

Table 18. Analog Input Leakage and Pull-Up/Down DC electrical characteristics

Symbol

Parameter

Conditions

Value

Typ

Unit

Min

-200

Max

200

ILK_AD

Analog input leakage

current

Input channel off

4.5V < V_{DD_HV_IO}< 5.5V

V_{SS_HV_ADV_SAR}< V_IN

V_{DD_HV_ADV_SAR}

V_{SS_HV_ADV_SD}< V_IN< V_{DD_HV_ADV_SD}

200KΩ

—

nA

<

RPUPD

Analog input bias/

diagnostic pull up/down

resistance

130

65

200

100

5

280

140

8.8

5

KΩ

3.0V < V_{DD_HV_IO}< 5.5V

100KΩ

3.0V < V_{DD_HV_IO}< 5.5V

5KΩ

1.4

—

3.0V < V_{DD_HV_IO}< 5.5V

ΔPUPD

RPUPD pull up/down

resistance mismatch

—

%

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ADC modules

11.2 SAR ADC

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-

Digital Converter.

Offset Error OSE Gain Error GE

4095

4094

4093

4092

4091

4090

(2)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

3.3V/ 4096 = 0.806 mV

Total Unadjusted Error

TUE = +/- 6 LSB = +/- 4.84mV

code out₇

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer

curve

(5)

4

3

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

4089 4090 4091 4092 4093 4094 4095

V_in(A)(LSB_ideal

)

Offset Error OSE

Figure 10. ADC characteristics and error definitions

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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ADC modules

11.2.1 Input equivalent circuit and ADC conversion characteristics

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD_HV_IO

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

S

F

L

SW1

AD

C

V

C

P1

C

S

A

F

P2

R

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

S

F

L

R

C

R

C

SW1

AD

P

Pin Capacitance (two contributions, C and C

Sampling Capacitance

)

P1

P2

S

Figure 11. Input equivalent circuit

Table 19. ADC conversion characteristics

Symbol

Parameter

Conditions¹

Min

Typ

Max

Unit

, 2

f_CK

ADC Clock frequency (depends

on ADC configuration) (The duty

cycle depends on AD_CK³

frequency.)

—

20

—

80

MHz

f_s

Sampling frequency

Sample time⁴

Conversion time⁵

—

250

700

—

3

1.00

—

MHz

ns

pF

kΩ

Ω

t_sample

t_conv

80 MHz

—

, 6

C_S

ADC input sampling capacitance —

5

6

C_P1

ADC input pin capacitance 1

ADC input pin capacitance 2

—

5

6

C_P2

—

0.8

0.3

875

825

6

R_SW1

Internal resistance of analog

source

V_REFrange = 4.5 to 5.5 V

V_REFrange = 3.0 to 3.6 V —

—

6

R_AD

Internal resistance of analog

source

—

Ω

INL

Integral non-linearity

Differential non-linearity

Offset error

—

–2

–1

–6

—

2

1

LSB

nA

DNL

—

OFS⁷

GNE⁷

—

6

Gain error

—

6

Input (double ADC Max leakage

channel)

150 °C

300

Table continues on the next page...

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ADC modules

Table 19. ADC conversion characteristics (continued)

Symbol

Parameter

Conditions¹

Min

Typ

Max

Unit

SNR

Signal-to-noise ratio

V_REF= 3.3 V, Fin ≤ 125

kHz

66

—

dB

SNR

Signal-to-noise ratio

V_REF= 5.0 V, Fin ≤ 125

kHz

68

—

dB

THD

ENOB⁸

Total harmonic distortion

Effective number of bits

Signal-to-noise and distortion

@ 125 kHz

65

70

—

dB

bits

dB

Fin < 125 kHz

10.5

—

(6.02*ENOB)+1.76

—

SINAD

Fin < 125 kHz

TUE_IS1WINJ

Total unadjusted error for

IS1WINJ

Without current injection

–6

—

6

LSB

TUE_IS1WWINJ

I_{DD_VDDA}

Total unadjusted error for

IS1WWINJ

Without current injection

—

LSB

mA

μA

V

Maximum operating current on

VDDA

Tj = 150C VDD_LV_COR

= 1.32 V

3.7

5

I_{DD_VDDR}

Maximum operating current on

VREF

Tj = 150C VDD_LV_COR

= 1.32 V

150

600

1.236

, 9

10

V_{BG_REF}

Band gap reference for self test Trimmed,

INPSAMP=0xFF

1.164

—

1. V_{DD_HV_IO}= 3.3 V -5%,+10%, T_J= –40 to +150 °C, unless otherwise specified, and analog input voltage from V_AGNDto

V_AREF

2. SAR ADC performance is not guaranteed when IRC is used as clock source for PLL0 to generate SAR ADC clock.

3. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

4. During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_sample. After the end of the

sample time t_sample, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock t_sampledepend on programming.

5. This parameter does not include the sample time t_sample, but only the time for determining the digital result and the time to

load the result register with the conversion result.

6. See the above figure.

7. Subject to change with additional -40°C characterization on final silicon version.

8. Below 4.5V, ENOB - 9.5b, THD- 60dB at Fin= 125KHz

9. Band gap reference only applies to Cut 2 silicon.

10. Minimum and maximum values are typical +/-3%

NOTE

• For spec complaint operation, do not expose clock sources,

including crystal oscillator, IRC, PLL0, and PLL1 on the

CLKOUT pads while the SAR ADC is converting.

• The ADC performance specifications are not guaranteed if

two or more ADCs simultaneously sample the same shared

channel.

11.3 S/D ADC

The SD ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps

maximum output rate.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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29

ADC modules

Functional operating conditions are given in the DC electrical specifications. Absolute

maximum ratings are stress ratings only, and functional operation at the maxima is not

guaranteed. Stress beyond the listed maxima may affect device reliability or cause

permanent damage to the device.

Table 20. SDn ADC electrical specification

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

V_IN

ADC input signal

—

0

—

V_{DD_HV_}

V

ADV_SD

1

V_{IN_PK2PK}

Input range peak to

peak

Single ended.

V

V_{DD_HV_ADR_SD}/GAIN

V_INM= V_{SS_HV_ADR_SD}

Single ended.

2

V_{IN_PK2PK}= V_INP

–

, 3

V_INM

V_INM= 0.5*V_{DD_HV_ADR_SD}

GAIN = 1

0.5*V_{DD_HV_ADR_SD}

Single ended.

V_INM= 0.5*V_{DD_HV_ADR_SD}

GAIN = 2,4,8,16

Differential

V_{DD_HV_ADR_SD}/GAIN

0 < V_IN< V_{DD_HV_IO_MAIN}

T_J< 150 °C

f_{ADCD_M}

f_{ADCD_S}

—

S/D clock frequency

Conversion rate

4

14.4

—

16

MHz

ksps

—

T_J< 150 °C

—

24

333

256

Oversampling ratio

Internal modulator

—

RESOLUTION S/D register resolution 2's complement notation

16⁴

bit

GAIN

ADC gain

Defined through ADC_SD[PGA] register.

Only integer power of 2 are valid gain.

1

—

16

1

—

|δ_GAIN

|

Absolute value of the

ADC gain error⁵

Before calibration (applies to gain

settings =1)

After calibration⁶

—

%

0.1

Δ V_{DD_HV_ADR_SD}< 5%

Δ V_{DD_HV_ADV_SD}< 10%

T_J< 50 °C

After calibration⁶

—

0.2

20

%

Δ V_{DD_HV_ADR_SD}< 5%

Δ V_{DD_HV_ADV_SD}< 10%

T_J< 150 °C

V_OFFSET

Conversion offset

Before calibration

10*

mV

(applies to all gain settings – 1, 2, 4, 8,

16)

(1+1/

gain)

After calibration⁶

Signal to noise ratio in 4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

—

5

mV

dB

, 7

SNR_DIFF150

78

—

differential mode 150

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

ksps output rate

Table continues on the next page...

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ADC modules

Unit

Table 20. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Min

Typ

Max

GAIN = 1

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

75

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

72

69

65

72

69

66

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 16

=

T_J< 150 °C

7

SNR_DIFF333

Signal to noise ratio in 4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

differential mode 333

dB

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 1

=

ksps output rate

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

Table continues on the next page...

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ADC modules

Symbol

Table 20. SDn ADC electrical specification (continued)

Value

Parameter

Conditions

Unit

Min

Typ

Max

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

63

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

60

72

69

66

63

55

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 16

=

T_J< 150 °C

7

SNR_SE150

Signal to noise ratio in 4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

single ended mode 150

dB

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 1

=

ksps output rate

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_DS}

V^DD_HV_ADV_SD

GAIN = 16

=

T_J< 150 °C

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Table 20. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

THD_DIFF150

Total Harmonic

Distortion in differential

mode 150 ksps output

rate

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 1

65

—

dB

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

68

74

80

65

68

74

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 16

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

THD_DIFF333

Total Harmonic

Distortion in differential

mode 333 ksps output

rate

dB

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 1

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

Table continues on the next page...

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ADC modules

Symbol

Table 20. SDn ADC electrical specification (continued)

Value

Parameter

Conditions

Unit

Min

Typ

Max

GAIN = 4

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

80

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

77

68

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 16

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

THD_SE150

Total Harmonic

Distortion in single

ended mode 150 ksps

output rate

dB

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 1

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_DS}

V^DD_HV_ADV_SD

G_AIN= 16

=

T_J< 150 °C

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Table 20. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

SINAD_DIFF150Signal to Noise

Distortion Ratio in

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 1

72

—

dB

differential mode 150

ksps output rate

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

72

69

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

68.8

64.8

66

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 16

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

SINAD_DIFF333Signal to Noise

Distortion Ratio in

dB

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 1

=

differential mode 333

ksps output rate

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

66

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

Table continues on the next page...

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=

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ADC modules

Symbol

Table 20. SDn ADC electrical specification (continued)

Value

Parameter

Conditions

Unit

Min

Typ

Max

GAIN = 4

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

62

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

59

66

63

62

54

—

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 16

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

SINAD_SE150

Signal to Noise

dB

Distortion Ratio in single

ended mode 150 ksps

output rate

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 1

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 2

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 4

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_SD}

V_{DD_HV_ADV_SD}

GAIN = 8

=

T_J< 150 °C

4.5 < V_{DD_HV_ADV_SD}< 5.5⁷

V_{DD_HV_ADR_DS}

V^DD_HV_ADV_SD

G_AIN= 16

=

T_J< 150 °C

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

36

NXP Semiconductors

ADC modules

Table 20. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

SFDR

Spurious free dynamic Any GAIN

range

60

—

dB

Z_DIFF

Differential input

impedance^{8, 9}

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

—

1000

600

300

200

1400

1000

700

500

110

–12

1250

800

400

250

1800

1300

950

650

144

—

1500

1000

500

kΩ

300

Z_CM

Common Mode input

impedance^{9, 10}

2200

1600

1150

800

kΩ

800

R_BIAS

Bare bias resistance

180

kΩ

%

ΔV_INTCM

Common Mode input

reference voltage¹¹

—

+12

V_BIAS

Bias voltage

—

VDD_

HV_

—

V

ADR_S

D/2

δV_BIAS

Bias voltage accuracy

—

–2.5

55

—

+2.5

—

%

CMRR

Common mode

rejection ratio

dB

—

Anti-aliasing filter

External series resistance

Filter capacitances

0.333 * f_{ADCD_S}

—

220

–1

—

20

—

1

kΩ

pF

%

δ_RIPPLE

Pass band ripple ¹²

—

Stop band attenuation

[0.5 * f_{ADCD_S}

1.0 * f_{ADCD_S]}

[1.0 * f_{ADCD_S}

1.5 * f_{ADCD_S]}

[1.5 * f_{ADCD_S}

,

40

—

dB

45

50

55

—

2.0 * f_{ADCD_S}

[2.0 * f_{ADCD_S}

2.5 * f_{ADCD_S}

]

[2.5 * f_{ADCD_S}, f_{ADCD_M}/2]

Within pass band – Tclk is f_{ADCD_M}/ 2

OSR = 24

60

—

δ_GROUP

Group delay

—

235.5

275

Tclk

OSR = 28

OSR = 32

314.5

354

OSR = 36

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

37

ADC modules

Symbol

Table 20. SDn ADC electrical specification (continued)

Value

Parameter

Conditions

Unit

Min

—

Typ

—

Max

393.5

433

OSR = 40

OSR = 44

—

OSR = 48

—

472.5

551.5

630.5

709.5

696

OSR = 56

—

OSR = 64

—

OSR = 72

—

OSR = 75

—

OSR = 80

—

788.5

867.5

946.5

1104.5

1262.5

1420.5

1578.5

1736.5

1894.5

2210.5

2526.5

+0.5/

OSR = 88

—

OSR = 96

—

OSR = 112

OSR = 128

OSR = 144

OSR = 160

OSR = 176

OSR = 192

OSR = 224

OSR = 256

Distortion within pass band

—

–0.5/

f_{ADCD_S}

—

f_{ADCD_S}

—

f_HIGH

High pass filter 3dB

frequency

Enabled

—

10e-5*

f_{ADCD_S}

—

t_STARTUP

t_LATENCY

Start-up time from

power down state

—

100

µs

—

Latency between input HPF = ON

data and converted data

—

δ_GROUP

+

when input mux does

f_{ADCD_S}

note change¹³

HPF = OFF

—

δ_GROUP

—

t_SETTLING

Settling time after mux Analog inputs are muxed

change

2*δ

GROUP

+

HPF = ON

3*f_{ADCD_}

S

HPF = OFF

—

2*δ

GROUP

—

+

2*f_{ADCD_}

S

t_ODRECOVERY

Overdrive recovery time After input comes within range from

saturation

—

2*δ

GROUP

f_{ADCD_S}

—

+

HPF = ON

HPF = OFF

2*δ

GROUP

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

38

NXP Semiconductors

Temperature sensor

Table 20. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Max

Min

Typ

C_{S_D}

S/D ADC sampling

capacitance after

sampling switch¹⁴

GAIN = 1, 2, 4, 8

—

75*GAI

N

fF

GAIN = 16

—

600

3.5

8

fF

I_BIAS

Bias consumption

At least 1 ADCD enabled

ADCD enabled

mA

I_{ADV_D}

ADCD supply

consumption

2.5

ΣI_{ADR_D}

Reference current for

one SDADC

ADCD enabled

—

10

50

µA

1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the

signal will only be 'clipped'.

2. VINP is the input voltage applied to the positive terminal of the SD ADC.

3. VINM is the input voltage applied to the negative terminal of the SD ADC.

4. For Gain=16, SDADC Resolution is 15 bit.

5. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.

6. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*V_{DD_HV_ADR_SD}for

differential "differential mode" and single ended mode with negative input=0.5*V_{DD_HV_ADR_SD}". Offset Calibration should

be done with respect to 0 for "single ended mode with negative input=0". Both Offset and Gain Calibration is guaranteed

for +/-5% variation of V_{DD_HV_ADR_SD}, +/-10% variation of V_{DD_HV_ADV_SD}, +/-50 C temperature variation.

7. S/D ADC is functional in the range 3.6V < V_{DD_HV_ADV_SD}< 4.5V and 3.0V < V_{DD_HV_ADR_SD}< 4.5 V, SNR paramter

degrades by 9 dB.

8. Input impedance in differential mode Z_IN= Z_DIFF

9. Input impedance given at f_{ADCD_M}= 16 MHz. Impedance is inversely proportional to SDADC clock frequency. Z_DIFF

(f_{ADCD_M}) = (16 MHz / f_{ADCD_M}) * Z_DIFF, Z_CM(f_{ADCD_M}) = (16 MHz / f_{ADCD_M}) * Z_CM

10. Input impedance in single-ended mode Z_IN= (2 * Z_DIFF* Z_CM) / (Z_DIFF+ Z_CM

.

)

11. V_INTCMis the Common Mode input reference voltage for the SDADC. It has a nominal value of (V_{RH_SD}- V_{RL_SD}) / 2.

12. The 1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.873 dB.

13. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the

different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers.

The time elapsed between data availability at pin and internal S/D module registers is given by the following formula:

REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK where fADCD_S is

the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and fPBRIDGEx_CLK is the frequency

of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol refers to the number of clock cycles

uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain crossing.

Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received

from the ADC S/D module.

14. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before

sampling switch.

12 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

39

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Table 21. Temperature sensor electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

—

Junction temperature monitoring

range

–40

—

150

°C

—

T_SENS

T_ACC

Sensitivity

Accuracy

—

5.18

—

7

mV/°C

°C

–7

13 LVDS fast asynchronous serial transmission (LFAST) pad

electrical characteristics

The LFAST pad electrical characteristics apply to both the LFAST and high-speed debug

serial interfaces on the device. The same LVDS pad is used for the Microsecond Channel

(MSC) and DSPI LVDS interfaces, with different characteristics given in the following

tables.

13.1 LFAST interface timing diagrams

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

40

NXP Semiconductors

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Signal excursions above this level NOT allowed

1743 mV

Max. common mode input at RX

1600 mV

VOD

I

Maximum Differential Voltage

285 mV p-p (LFAST)

400 mV p-p (MSC/DSPI)

Minimum Data Bit Time

Opening =

0.55 * T (LFAST)

0.50 * T (MSC/SIPI)

"No-Go" Area

V_OS= 1.2 V +/- 10%

TX common mode

VOD

I

Minimum Differential

Voltage =

100 mV p-p (LFAST)

150 mV p-p (MSC/SIPI)

Data Bit Period

T = 1 / F_DATA

Min. common mode input at RX

150 mV

0 V

Signal excursions below this level NOT allowed

Figure 12. LFAST timing definition

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

41

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

H

Ifast_pwr_down

L

t

PD2NM_TX

Data Valid

Differential TX

Data Lines

pad_p/pad_n

Figure 13. Power-down exit time

V_IH

Differential TX

Data Lines

90%

10%

pad_p/pad_n

V

IL

t_fall

t_rise

Figure 14. Rise/fall time

13.2 LFAST and MSC /DSPI LVDS interface electrical

characteristics

The following table contains the electrical characteristics for the LFAST interface.

The LVDS pad electrical characteristics in this table apply to both the LFAST and High-

speed Debug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the

conditions.

All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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NXP Semiconductors

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Table 22. LVDS pad startup and receiver electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

t_{PD2NM_TX}Transmitter startup time (power

down to normal mode)¹

—

0.4

0.55

µs

—

t_{SM2NM_TX}Transmitter startup time (sleep

mode to normal mode)²

Not applicable to the MSC/

DSPI LVDS pad

—

0.2

20

—

0.5

40

µs

ns

t_{PD2NM_RX}Receiver startup time (power down

to normal mode)³

—

t_{PD2SM_RX}Receiver startup time (power down Not applicable to the MSC/

50

ns

to sleep mode)⁴

DSPI LVDS pad

I_{LVDS_BIAS}LVDS bias current consumption

Tx or Rx enabled

0.95

mA

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Z₀

Transmission line characteristic

impedance

47.5

50

52.5

105

Ω

—

Z_DIFF

Transmission line differential

impedance

95

100

RECEIVER

V_ICOM

|Δ_VI|

V_HYS

R_IN

Common mode voltage

Differential input voltage

Input hysteresis

—

0.15⁵

100

25

—

1.6⁶

—

V

mV

Ω

—

Terminating resistance

V_{DD_HV_IO}= 5.0 V 10%

80

100

115

3.5

—

120

150

6.0

0.5

V_{DD_HV_IO}= 3.3 V 10%

80

Ω

C_IN

Differential input capacitance⁷

—

pF

mA

I_{LVDS_RX}

Receiver DC current consumption

Enabled

—

1. Total transmitter startup time from power down to normal mode is t_{STRT_BIAS}+ t_{PD2NM_TX}+ 2 peripheral bridge clock

periods. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal

capacitance values.

2. Total transmitter startup time from sleep mode to normal mode is t_{SM2NM_TX}+ 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40

°C to 150 °C.

3. Total receiver startup time from power down to normal mode is t_{STRT_BIAS}+ t_{PD2NM_RX}+ 2 peripheral bridge clock periods.

4. Total receiver startup time from power down to sleep mode is t_{PD2SM_RX}+ 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

5. Absolute min = 0.15 V – (285 mV/2) = 0 V

6. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

7. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

Table 23. LFAST transmitter electrical characteristics

Value

Symbol Parameter

Conditions

Unit

Min

—

Typ

—

Max

320

1.32

285

1.5

f_DATA

V_OS

Data rate

—

Mbps

V

Common mode voltage

1.08

100

0.26

—

|V_OD

t_TR

|

Differential output voltage swing (terminated)^{1, 2}

Rise/Fall time (10%–90% of swing) ^{3, 4}

200

—

mV

ns

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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43

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Table 23. LFAST transmitter electrical characteristics (continued)

Value

Symbol Parameter

Conditions

Unit

Min

—

Typ

—

Max

10.0

8.5

C_L

External lumped differential load capacitance¹

V_{DD_HV_IO}= 4.5 V

V_{DD_HV_IO}= 3.0 V

Enabled

pF

—

I_{LVDS_TX}Transmitter DC current consumption

—

3.2

mA

1. Valid for maximum data rate f_DATA. Value given is the capacitance on each terminal of the differential pair, as shown in the

figure below.

2. Valid for maximum external load C_L.

3. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance

values.

4. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

The MSC and DSPI LVDS pad electrical characteristics are based on the application

circuit and typical worst case internal capacitance values given in Figure 14.

All MSC and DSPI LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

Table 24. MSC/DSPI LVDS transmitter electrical characteristics

Value

Symbol Parameter

Conditions

Unit

Min

Typ

Max

Data Rate

f_DATA

V_OS

Data rate

—

1.08

150

0.8

—

80

1.32

400

5.7

40

Mbps

V

Common mode voltage

—

|

Differential output voltage swing (terminated)^{1, 2}

Rise/Fall time (10%–90% of swing) ^{3, 4}

External lumped differential load capacitance³

—

200

—

mV

ns

VOD

t_TR

—

C_L

V_{DD_HV_IO}= 4.5 V

V_{DD_HV_IO}= 3.0 V

Enabled

—

pF

—

30

I_{LVDS_TX}Transmitter DC current consumption

—

4.0

mA

1. Valid for maximum data rate f_DATA. Value given is the capacitance on each terminal of the differential pair, as shown in the

figure below.

2. Valid for maximum external load C_L.

3. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance

values.

4. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

NOTE

For optimum LVDS performance, it is recommended to set the

neighbouring GPIO pads to use Weak Drive.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

44

NXP Semiconductors

LFAST PLL electrical characteristics

bond

pad

GPIO Driver

C_L

1pF

2.5pF

100 Ω

termination

LVDS Driver

GPIO Driver

bond

pad

C_L

1pF

2.5pF

Die

Package

PCB

Figure 15. LVDS pad external load diagram

14 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

The specifications in this table apply to both the interprocessor bus and debug LFAST

interfaces.

Table 25. LFAST PLL electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

10

–1

45

—

Nominal

Max

26

f_{RF_REF}

PLL reference clock frequency

—

MHz

%

ERR_REFPLL reference clock frequency error

—

1

D_CREF

PN

PLL reference clock duty cycle

—

55

%

Integrated phase noise (single side band)

f_{RF_REF}= 20 MHz

f_{RF_REF}= 10 MHz

—

–58

–64

—

dBc

—

640¹

f_VCO

PLL VCO frequency

PLL phase lock²

—

MHz

µs

t_LOCK

—

40

ΔPER_REFInput reference clock single period jitter

Single period,

f_{RF_REF}= 10 MHz

—

300

ps

(peak to peak)

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

45

Aurora LVDS electrical characteristics

Table 25. LFAST PLL electrical characteristics

(continued)

Value

Nominal

—

Symbol

Parameter

Conditions

Unit

Min

Max

Long term,

f_{RF_REF}= 10 MHz

—

–500

500

ps

ΔPER_EYEOutput Eye Jitter (peak to peak)³

—

550

—

ps

1. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO

frequency is 624 MHz.

2. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device.

3. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. Refer to the figure

below.

Data Bit Period, T

TX+

TX-

Eye Jitter

Figure 16. LFAST output 'eye' diagram

15 Aurora LVDS electrical characteristics

The following table describes the Aurora LVDS electrical characteristics.

All Aurora electrical characteristics are valid from -40 °C to 150 °C.

All specifications valid for maximum transmit data rate F_TX.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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NXP Semiconductors

Power management PMC POR LVD sequencing

Table 26. Aurora LVDS electrical characteristics

Value¹

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

Transmitter

F_TX

Transmit Data Rate

—

1.25

800

Gbps

mV

|V_{OD_LVDS}

|

Differential output voltage swing

(terminated)²

400

600

t_{TR_LVDS}Rise/Fall time (10%–90% of swing)

—

60

81

—

100

—

ps

Ω

R_{TV_L}

T_Loss

Differential Terminating resistance

120

100³

Transmission Line Loss due to loading

effects

dB

Transmission line characteristics (PCB track)

L_LINE

Z_LINE

C_AC

Transmission line length

—

45

—

50

—

20

55

cm

Ω

Transmission line characteristic impedance

External AC Coupling Capacitance

—

Values are nominal, valid

up to 50%

100

270

pF

Receiver

F_RX

Receive Data Rate

—

200

81

—

1.25

1000

120

GHz

mV

Ω

|Δ_{VI_L}

|

Differential input voltage

Terminating resistance

—

R_{RV_L}

V_{DD_HV_IO_BD}= 5V 10%

100

1. All specifications valid for maximum transmit data rate F_TX

2. The minimum value of 400 mV is only valid for differential resistance (R_{V_L}) = 99 ohm to 101 ohm. The differential output

voltage swing tracks with the value of R_{V_L}

.

3. Transimission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.

16 Power management PMC POR LVD sequencing

16.1 Power management electrical characteristics

The power management module monitors the different power supplies. It also generates

the internal supplies that are required for correct device functionality. The power

management is supplied by the V_{DD_HV_PMC}supply.

16.1.1 Recommended power transistors

The following NPN transistors are recommended for use with the on-chip voltage

regulator controller: ON Semiconductor^TMNJD2873. The collector of the external

transistor is preferably connected to the same voltage supply source as the V_{DD_HV_PMC}

pin.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

47

Power management PMC POR LVD sequencing

The following table describes the characteristics of the power transistors.

Table 27. Recommended operating characteristics

Symbol

h_FE

Parameter

Value

60-550

1.60

2.0

Unit

—

W

DC current gain (Beta)

P_D

Absolute minimum power dissipation

Maximum DC collector current

Collector to emitter saturation voltage

Base to emitter voltage

I_CMaxDC

VCE_SAT

V_BE

A

300

mV

V

0.95

2.5

V_C

Minimum voltage at transistor collector

V

16.1.2 Power management integration

In order to ensure correct functionality of the device, it is recommended to follow the

integration scheme shown below.

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NXP Semiconductors

Power management PMC POR LVD sequencing

C_{HV_PMC}

C_{HV_FLA}

VDD_HV_IO

VSS

VDD_LV

VSS

RAINIER

2

1

n x C_{HV_IO}

C_LV

1

2

One capacitance near each VDD_LV pin

One capacitance near each VDD_HV pin

Figure 17. Recommended supply pin circuits

The following table describes the supply stability capacitances required on the device for

proper operation.

Table 28. Device power supply integration

Value¹

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

C_LV

Minimum V_{DD_LV}external bulk capacitance^,

—

4.7

—

µF

2, 3

C_{HV_PMC}Minimum V_{DD_HV_PMC}external bulk

capacitance ^{2, 4}

—

4.7

—

µF

C_{HV_IO}

Minimum VDD_HV_IO external

capacitance²

C_{HV_FLA}Minimum V_{DD_HV_FLA}external capacitance^{, 5}

2.0

—

µF

C_{HV_ADC_SA}Minimum V_{DD_HV_ADV_SAR}external

10

—

capacitance^{, 6}

R

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

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49

Power management PMC POR LVD sequencing

Table 28. Device power supply integration (continued)

Value¹

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

C_{HV_ADC_SD}Minimum V_{DD_HV_ADV_SD}external

capacitance^{, 7}

1

2.2

—

µF

1. See the above figure for capacitor integration.

2. Recommended X7R or X5R ceramic low ESR capacitors, 15% variation over process, voltage, temperature, and aging.

3. Each V_{DD_LV}pin requires both a 47nF and 0.01µF capacitor for high-frequency bypass and EMC requirements. Remaining

capacitance to meet minimum CLV requirement should be placed near the emitter of NPN ballast (if using internal

regulation mode), or it should be evenly distributed across VDD_LV pins (if using external regulation mode).

4. Each V_{DD_HV_PMC}pin requires both a 47nF and 0.01µF capacitor for high-frequency bypass and EMC requirements.

5. The recommended flash regulator composition capacitor is 1.5µF typical X7R or X5R, with -50% and +35% as min and

max. This puts the min cap at 0.75 µF.

6. For noise filtering it is recommended to add high frequency bypass capacitors of three each 0.1 µF and three each 1nF

between V_{DD_HV_ADV_SAR}and V_{SS_HV_ADV_SAR}. These capacitors need to be placed very close to the MCU pins/balls to

have minimum PCB routing between pin/ball and the capacitors.

7. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V_{DD_HV_ADV_SD}and

V_{SS_HV_ADV_SD}

.

16.1.3 Regulator example for the NJD2873 transistor

VDD_HV_PMC

The bypass transistor

VRC_CTL

MUST be operated out

of saturation region.

MCU

VDD_LV

C1

Mandatory decoupling capacitor

network

VSS

VRC_CTL capacitor: may or

may not be required

Figure 18. Regulator example

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50

NXP Semiconductors

Power management PMC POR LVD sequencing

16.1.4 Regulator example for the 2SCR574d transistor

3.3V or Vcollector

Cc= 4u, 14u

ESR= 15m, 150m

VDDIO

Lb= 50n, 100n

--

+

Beta= 120, 360

Vrctl

Vref

Cb= 0.6u, 1.4u

ESR= 15m, 150m

Cl= 4u, 14u

ESR= 15m, 150m

Vdd_core

ILoad

Figure 19. Regulator example

16.1.5 Device voltage monitoring

The LVD/HVDs for the device and their levels are given in the following table. Voltage

monitoring threshold definition is provided in the following figure.

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51

Power management PMC POR LVD sequencing

V

DD_xxx

V

HVD(rise)

HVD(fall)

V

LVD(rise)

LVD(fall)

t

VDRELEASE

VDASSERT

HVD TRIGGER

(INTERNAL)

t

VDASSERT

VDRELEASE

LVD TRIGGER

(INTERNAL)

Figure 20. Voltage monitor threshold definition

For V_{DD_LV}levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on

the die. For other LVD, the IR drop is estimated by multiplying the supply current by 0.5

ohm.

LVD is released after t_VDRELEASEtemporization when upper threshold is crossed, LVD is

asserted t_VDASSERTafter detection when lower threshold is crossed.

HVD is released after t_VDRELEASEtemporization when lower threshold is crossed, HVD

is asserted t_VDASSERTafter detection when upper threshold is crossed.

Table 29. Voltage monitor electrical characteristics

Configuration

Value

Trim Mas Pow Min Typ Max

Symbol

Parameter

Conditions

Unit

bits

k

. Up

Opt.

POR085_c¹LV internal supply power on

reset

Rising voltage (power up)

N/A No Enab 870 920 970 mV

.

Falling voltage (power down)

850 900 950

Table continues on the next page...

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Power management PMC POR LVD sequencing

Table 29. Voltage monitor electrical characteristics (continued)

Configuration

Value

Trim Mas Pow Min Typ Max

Symbol

Parameter

Conditions

Unit

bits

k

. Up

Opt.

POR098_c LV internal supply power on

reset

Rising voltage (power up)

N/A No Enab 960 1010 1060 mV

.

Falling voltage (power down)

940 990 1040

LVD_core_ LV internal²supply low voltage Rising voltage (trimmed)

hot monitoring

6bit

No Enab 1146 1169 1193 mV

.

Falling voltage (trimmed)

LVD_core_ LV external³supply low voltage Rising voltage

1146 1169 1193

6bit Yes Disa 1161 1185 1208 mV

cold

monitoring

b.

Falling voltage

Rising voltage

Falling voltage

1161 1185 1208

HVD_core LV internal cold supply high

voltage monitoring

6bit Yes Disa 1353 1395 1438 mV

b.

1343 1385 1438

LVD_HV HV internal supply low voltage Rising voltage (trimmed)

6bit

No Enab 3300 3400 3500 mV

monitoring

.

Falling voltage (trimmed)

3270 3370 3470

HVD_HV HV internal supply high voltage Rising voltage

6bit Yes Disa 5530 5700 5870 mV

monitoring

b.

Falling voltage

5500 5670 5840

LVD_IO Main IO and RC oscillator

supply voltage monitoring

Rising voltage (trimmed)

Falling voltage (trimmed)

Rising voltage

6bit

No Enab 3300 3400 3500 mV

.

3270 3370 3470

LVD_SAR SAR ADC supply low voltage

monitoring

6bit Yes Disa 2820 2910 3000 mV

b.

Falling voltage

2790 2880 2970

t_VDASSERTVoltage detector threshold

crossing assertion

—

0.1

—

2.0

µs

t_VDRELEASEVoltage detector threshold

crossing de-assertion

—

5

—

20

1. POR085_c and POR096_c threshold are untrimmed value, before the completion of the power-up sequence. All other

LVD/HVD thresholds are provided after trimming.

2. LV internal supply levels are measured on device internal supply grid after internal voltage drop.

3. LV external supply levels are measured on the die size of the package bond wire after package voltage drop.

16.1.6 Power up/down sequencing

The following shows the constraints and relationships for the different power supplies.

VDD_STDBY=0 VDD_LV=0 VDD_HV_PMC=0 VDD_HV_IO_MAIN=0 VDD_HV_IO_JTAG=0 VDD_HV_IO_FEC=0 VDD_HV_IO_MSC=0 VDD_HV_ADR_SD=0

VDD_HV_ADV_SD=0 VDD_HV_ADR_SAR=0 VDD_HV_ADV_SAR=0

VDD_STDBY

VDD_LV

VDD_HV_PMC

VDD_HV_IO_MAIN

VDD_HV_IO_JTAG

VDD_HV_IO_FEC

VDD_HV_IO_MSC

VDD_HV_ADR_SD

VDD_HV_ADV_SD

VDD_HV_ADR_SAR

VDD_HV_ADV_SAR

Amps

2mA

Figure 21. Device supply relation during power-up/power-down sequence

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53

Flash memory specifications

Each column indicates that the corresponding supply is 0 and the other supplies are UP.

For example, the "Amps" cell in the "V_{DD_HV_ADV_SD}=0" column shows that when

V_{DD_HV_ADR_SD}supply is 0 and all other supplies are UP, this supply has a current in

Amp flowing into V_{DD_HV_ADR_SD}

.

17 Flash memory specifications

17.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this

section are defined for a single embedded flash memory within

an SoC, and represent average currents for given supplies and

operations.

Table 30 shows the estimated Program/Erase times.

Table 30. Flash memory program and erase specifications

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C ≤150°C ≤150°C cycles cycles

t_dwpgm

Doubleword (64 bits) program time 43

100 150 55 500

μs

t_ppgm

Page (256 bits) program time

73

200

800

300

108

396

500

μs

t_qppgm

Quad-page (1024 bits) program

time

268

1,200

2,000

t_16kers

16 KB Block erase time

16 KB Block program time

32 KB Block erase time

32 KB Block program time

64 KB Block erase time

64 KB Block program time

256 KB Block erase time

256 KB Block program time

168

34

290

45

320

50

250

40

1,000

1,200

1,600

4,000

ms

t_16kpgm

t_32kers

t_32kpgm

t_64kers

217

69

360

100

490

180

1,520

720

390

110

590

210

2,030

880

310

90

315

138

884

552

420

170

1,080

650

t_64kpgm

t_256kers

t_256kpgm

—

1. Program times are actual hardware programming times and do not include software overhead. Block program times

assume quad-page programming.

2. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 150 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

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NXP Semiconductors

Flash memory specifications

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤ T_J≤ 150°C, full spec voltage.

17.2 Flash memory Array Integrity and Margin Read

specifications

Table 31. Flash memory Array Integrity and Margin Read specifications

Symbol

Characteristic

Min

Typical

Max¹

Units

2

t_ai16kseq

Array Integrity time for sequential sequence on 16 KB block.

—

512 x

Tperiod x

Nread

—

t_ai32kseq

Array Integrity time for sequential sequence on 32 KB block.

Array Integrity time for sequential sequence on 64 KB block.

Array Integrity time for sequential sequence on 256 KB block.

—

1024 x

Tperiod x

Nread

t_ai64kseq

2048 x

Tperiod x

Nread

8192 x

Tperiod x

Nread

tai256kseq

t_mr16kseq

t_mr32kseq

t_mr64kseq

t_mr256kseq

Margin Read time for sequential sequence on 16 KB block.

Margin Read time for sequential sequence on 32 KB block.

Margin Read time for sequential sequence on 64 KB block.

Margin Read time for sequential sequence on 256 KB block.

73.81

128.43

237.65

893.01

—

110.7

192.6

μs

356.5

1,339.5

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and

Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires

6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the

address pipeline set to 2, Nread would equal 4 (or 6 - 2).)

2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

17.3 Flash memory module life specifications

Table 32. Flash memory module life specifications

Symbol

Characteristic

Conditions

Min

Typical

Units

P/E

Array P/E

cycles

Number of program/erase cycles per block

for 16 KB, 32 KB and 64 KB blocks.¹

—

250,000

—

cycles

Number of program/erase cycles per block

for 256 KB blocks.²

1,000

250,000

—

P/E

cycles

Data

retention

Minimum data retention.

Blocks with 0 - 1,000 P/E 50

cycles.

Years

Table continues on the next page...

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55

Flash memory specifications

Table 32. Flash memory module life specifications (continued)

Symbol

Characteristic

Conditions

Min

Typical

Units

Blocks with 100,000 P/E

cycles.

20

10

—

Years

Blocks with 250,000 P/E

cycles.

Years

1. Program and erase supported across standard temperature specs.

2. Program and erase supported across standard temperature specs.

17.4 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the

following figure. The spec window represents qualified limits. The extrapolated dotted

line demonstrates technology capability, however is beyond the qualification limits.

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Flash memory specifications

17.5 Flash memory AC timing specifications

Table 33. Flash memory AC timing specifications

Symbol

Characteristic

Min

Typical

Max

Units

t_psus

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

to a 1.

—

9.4

11.5

μs

plus four

system

clock

plus four

system

clock

periods

t_esus

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

to a 1.

—

16

20.8

μs

plus four

system

clock

plus four

system

clock

periods

t_res

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

—

16

100

ns

μs

t_done

t_dones

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

5

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

20.8

plus four

system

clock

plus four

system

clock

periods

t_drcv

Time to recover once exiting low power mode.

16

—

45

μs

plus seven

system

clock

plus seven

system

clock

periods.

periods

t_aistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

—

5

ns

t_aistop

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

—

80

plus fifteen

system

clock

periods

t_mrstop

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read

abort until the UT0-AID bit is set. This time also applies to the

UT0-AISUS to UT0-AID setting in the event of a Margin Read

suspend request.

10.36

—

20.42

μs

plus four

system

clock

plus four

system

clock

periods

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57

AC specifications

17.6 Flash read wait state and address pipeline control settings

Table 34 describes the recommended RWSC and APC settings at various operating

frequencies based on specified intrinsic flash access times of the C55FMC array at 150

°C.

Table 34. Flash Read Wait State and Address Pipeline Control Guidelines

Flash read latency on mini-

cache miss (# of f_SYSclock

periods)

Flash read latency on mini-

cache hit (# of f_SYSclock

periods)

Operating Frequency

f_SYS

RWSC

APC

30 MHz

100 MHz

133 MHz

167 MHz

200 MHz

0

2

3

4

5

0

1

2

3

5

6

7

8

1

18 AC specifications

18.1 Debug and calibration interface timing

18.1.1 JTAG interface timing

These specifications apply to JTAG boundary scan only. See Table 36 for functional

specifications.

Table 35. JTAG pin AC electrical characteristics

Value

#

Symbol

Characteristic

Unit

Min

100

40

—

5

Max

—

1

2

3

4

5

6

t_JCYC

t_JDC

TCK cycle time

ns

TCK clock pulse width

TCK rise and fall times

TMS, TDI data setup time

TMS, TDI data hold time

TCK low to TDO data valid

60

3

t_TCKRISE

t_TMSS, t_TDIS

t_TMSH, t_TDIH

t_TDOV

—

5

—

16¹

—

Table continues on the next page...

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AC specifications

Table 35. JTAG pin AC electrical characteristics (continued)

Value

#

Symbol

Characteristic

Unit

Max

Min

7

t_TDOI

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

TCK low to TDO data invalid

0

—

15

ns

8

TCK low to TDO high impedance

9

JCOMP assertion time

100

40

—

10

11

12

13

14

15

JCOMP setup time to TCK low

—

TCK falling edge to output valid

600²

600

—

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

TCK falling edge to output valid out of high impedance

TCK falling edge to output high impedance

Boundary scan input valid to TCK rising edge

TCK rising edge to boundary scan input invalid

—

15

—

1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

2. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

TCK

2

3

2

1

3

Figure 22. JTAG test clock input timing

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AC specifications

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 23. JTAG test access port timing

TCK

10

JCOMP

9

Figure 24. JTAG JCOMP timing

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60

NXP Semiconductors

AC specifications

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 25. JTAG boundary scan timing

18.1.2 Nexus interface timing

Nexus timing specified for the whole V_{DD_LV}and V_{DD_HV_IO}dynamic, T_A= T_Lto T_H,

and maximum loading per pad type as specified in the I/O section of the data sheet.

Table 36. Nexus debug port timing

Value

Unit

#

Symbol

Characteristic

Min

4

Max

—

, 1

1

2

3

4

t_EVTIPW

t_EVTOPW

t_TCYC

EVTI Pulse Width

EVTO Pulse Width

TCK cycle time

Absolute minimum TCK cycle time⁴(TDO sampled on posedge of

TCK)

t_CYC

40

—

ns

t_CYC

ns

1

4^{2, 3}

40⁵

—

t_TCYC

—

Table continues on the next page...

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AC specifications

Table 36. Nexus debug port timing (continued)

Value

Unit

#

Symbol

Characteristic

Min

Max

Absolute minimum TCK cycle time⁶(TDO sampled on negedge of

TCK)

20⁵

—

5

6

t_NTDIS

t_NTDIH

t_NTMSS

t_NTMSH

—

TDI data setup time

5

—

16

—

ns

TDI data hold time

7

TMS data setup time

5

8

TMS data hold time

TDO propagation delay from falling edge of TCK⁷

5

9

—

10

—

TDO hold time with respect to TCK falling edge (minimum TDO

propagation delay)

2.25

1. t_CYCis system clock period.

2. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less

than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency

being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number

greater than or equal to that specified here.

3. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute

minimum TCK period specification.

4. This value is TDO propagation time 36ns + 4ns setup time to sampling edge.

5. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the

design (system frequency / 4) depending on the actual system frequency being used.

6. This value is TDO propagation time 16ns + 4ns setup time to sampling edge.

7. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

Figure 26. Nexus output timing

TCK

EVTI

EVTO

3

Figure 27. Nexus event trigger and test clock timings

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AC specifications

TCK

5

7

6

8

TMS, TDI

9

10

TDO

Figure 28. Nexus TDI, TMS, TDO timing

18.1.3 Aurora LVDS interface timing

Table 37. Aurora LVDS interface timing specifications

Value

Typ

Symbol

Parameter

Unit

Max

Min

Data Rate

STARTUP

—

Data rate

—

1250

Mbps

t_{STRT_BIAS}

t_{STRT_TX}

t_{STRT_RX}

Bias startup time¹

Transmitter startup time²

Receiver startup time³

—

5

4

µs

1. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down

(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.

2. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is

guaranteed only after the startup time.

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AC specifications

3. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is

guaranteed only after the startup time.

18.1.3.1 Aurora debug port timing

Table 38. Aurora debug port timing

Value

#

Symbol

Parameter

Unit

Min

625

—

Max

1200

400

55

1

1a

2

t_REFCLK

t_MCYC

t_RCDC

J_RC

Reference clock frequency

Reference clock rise/fall time

Reference clock duty cycle

Reference clock jitter

MHz

ps

45

%

3

—

40

ps

4

t_STABILITY

BER

J_D

Reference clock stability

Bit error rate

50

—

PPM

—

5

—

10^-12

0.17

0.35

20

6

Transmit lane deterministic jitter

Transmit lane total jitter

Differential output skew

Lane to lane output skew

Aurora lane unit interval¹

—

OUI

ps

7

J_T

—

8

S_O

—

9

S_MO

—

1000

1600

800

ps

10

OUI

625 Mbps

1.25Gbps

1600

800

ps

1.

100 PPM

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AC specifications

1

2

CLOCK_REF

Zero Crossover

CLOCK_REF

1a

8

Tx Data

Ideal Zero Crossover

Tx Data

Tx Data [n]

Zero Crossover

Tx Data [n+1]

Zero Crossover

Tx Data [m]

Zero Crossover

9

Figure 29. Aurora timings

18.2 DSPI timing with CMOS and LVDS

DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel

bus protocol.

DSPI channel frequency support is shown in Table 39. Timing specifications are shown

in Table 40, Table 41, Table 42, Table 43, Table 44.

Table 39. DSPI channel frequency support

Max usable frequency

DSPI use mode

(MHz)¹,²

CMOS (Master mode)

Full duplex – Classic timing (Table 40)

17

30

40

Full duplex – Modified timing (Table 41)

Output only mode (SCK/SOUT/PCS) (Table 40 and Table 41)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 44)

Full duplex – Modified timing (Table 42)

LVDS (Master mode)

NXP Semiconductors

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65

AC specifications

1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

2. Maximum usable frequency does not take into account external device propagation delay.

18.2.1 DSPI master mode full duplex timing with CMOS and LVDS

pads

The values presented in these sections are target values. A complete performance

characterization of the pads (in all configuration combinations) is required before the

final specifications can be released.

18.2.1.1 DSPI CMOS master mode – classic timing

All output timing is worst case and includes the mismatching of rise and fall times of the

output pads.

NOTE

In Table 40, all output timing is worst case and includes the

mismatching of rise and fall times of the output pads.

Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA

= 0 or 1

#

Symbol

Characteristic

Condition

Pad drive²

Load (C_L)

Value¹

Unit

Min

Max

1

t_SCK

SCK cycle time

SCK drive strength

Very strong

Strong

25 pF

33.0

80.0

—

ns

50 pF

Medium

200.0

2

t_CSC

PCS to SCK delay

SCK and PCS drive strength

Very strong

Strong

25 pF

50 pF

(N³x t_SYS^{, 4}) - 16

(N³x t_SYS^{, 4}) - 29

—

ns

Medium

PCS medium and PCS = 50 pF

SCK strong

SCK = 50 pF

3

t_ASC

After SCK delay

SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

(M⁵x t_SYS⁴) - 35

(M⁵x t_SYS^{, 4}) - 35

—

ns

Strong

Medium

PCS medium and PCS = 0 pF

SCK strong

Table continues on the next page...

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AC specifications

Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA

= 0 or 1 (continued)

#

Symbol

Characteristic

Condition

Value¹

Unit

Pad drive²

Load (C_L)

Min

Max

SCK = 50 pF

4

t_SDC

SCK duty cycle⁶

SCK drive strength

Very strong

Strong

0 to 50 pF

¹/₂t_SCK- 2

¹/₂t_SCK- 5

¹/₂t_SCK+ 2

¹/₂t_SCK+ 5

ns

Medium

PCS strobe timing

5

t_PCSC

PCSx to PCSS time^,PCS and PCSS drive strength

7

Strong

25 pF

13.0

—

ns

6

t_PASC

PCSS to PCSx time⁷PCS and PCSS drive strength

Strong

25 pF

SIN setup time

t_SUI

7

SIN setup time to

SCK⁸

SCK drive strength

Very strong

Strong

25 pF

50 pF

25.0

31.0

52.0

—

ns

Medium

SIN hold time

t_HI

8

SIN hold time from

SCK⁸

SCK drive strength

Very strong

Strong

0 pF

-1.0

—

Medium

SOUT data valid time (after SCK edge)

9

t_SUO

SOUT data valid time SOUT and SCK drive strength

from SCK⁹

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

Medium

16.0

SOUT data hold time (after SCK edge)

10 t_HO

SOUT data hold time SOUT and SCK drive strength

after SCK⁹

Very strong

Strong

25 pF

50 pF

-7.7

-11.0

-15.0

—

Medium

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

4. t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t_SYS= 10

ns).

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5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

6. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds.

9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

t_CSC

t_ASC

PCSx

t_SCK

t_SDC

SCK Output

(CPOL = 0)

t_SDC

SCK Output

(CPOL = 1)

t_SUI

t_HI

First Data

SIN

Data

LastData

t_SUO

t_HO

Data

Last Data

SOUT

Figure 30. DSPI CMOS master mode – classic timing, CPHA = 0

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PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t_SUI

t_HI

Data

Fist Data

LastData

SIN

t_SUO

t_HO

Data

SOUT

Last Data

Fist Data

Figure 31. DSPI CMOS master mode – classic timing, CPHA = 1

t_PCSC

t_PASC

PCSS

PCSx

Figure 32. DSPI PCS strobe (PCSS) timing (master mode)

18.2.1.2 DSPI CMOS master mode – modified timing

All output timing is worst case and includes the mismatching of rise and fall times of the

output pads.

NOTE

In Table 41, all output timing is worst case and includes the

mismatching of rise and fall times of the output pads.

Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,

CPHA = 0 or 1

#

Symbol

Characteristic

Condition

Pad drive²

Load (C_L)

Value¹

Unit

Min

Max

1

t_SCK

SCK cycle time

SCK drive strength

Very strong

Strong

25 pF

50 pF

33.0

80.0

—

ns

Table continues on the next page...

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AC specifications

Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,

CPHA = 0 or 1 (continued)

#

Symbol

Characteristic

Condition

Pad drive²

Load (C_L)

Medium 50 pF

SCK and PCS drive strength

Value¹

Unit

Min

Max

200.0

—

2

t_CSC

PCS to SCK delay

Very strong

Strong

25 pF

50 pF

(N³x t_SYS^{, 4}) - 16

(N³x t_SYS^{, 4}) - 29

—

ns

Medium

PCS medium and PCS = 50 pF

SCK strong

SCK = 50 pF

3

t_ASC

After SCK delay

SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

(M⁵x t_SYS⁴) - 35

(M⁵x t_SYS^{, 4}) - 35

—

ns

Strong

Medium

PCS medium and PCS = 0 pF

SCK strong

SCK = 50 pF

4

t_SDC

SCK duty cycle⁶

SCK drive strength

Very strong

Strong

0 to 50 pF

¹/₂t_SCK- 2

¹/₂t_SCK- 5

¹/₂t_SCK+ 2

¹/₂t_SCK+ 5

ns

Medium

PCS strobe timing

5

t_PCSC

PCSx to PCSS time^,PCS and PCSS drive strength

7

Strong

25 pF

13.0

—

ns

6

t_PASC

PCSS to PCSx time⁷PCS and PCSS drive strength

Strong

25 pF

SIN setup time

t_SUI

7

SIN setup time to

SCK

SCK drive strength

Very strong

Strong

4

25 pF

50 pF

25 - (P⁹x t_SYS

31 - (P⁹x t_SYS

52 - (P⁹x t_SYS

)

—

ns

CPHA = 0⁸

, 4

)

, 4

Medium

)

SIN setup time to

SCK

SCK drive strength

Very strong

Strong

25 pF

50 pF

25.0

31.0

52.0

—

CPHA = 1⁸

Medium

SIN hold time

8

t_HI

SIN hold time from

SCK

SCK drive strength

Very strong

, 3

0 pF

-1 + (P⁸x t_SYS

)

—

ns

Table continues on the next page...

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Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,

CPHA = 0 or 1 (continued)

#

Symbol

Characteristic

Condition

Pad drive²

Load (C_L)

Value¹

Unit

Min

Max

—

CPHA = 0⁹

, 3

Strong

0 pF

-1 + (P⁸x t_SYS

)

, 3

Medium

—

SIN hold time from

SCK CPHA = 1⁹

SCK drive strength

Very strong

Strong

0 pF

-1.0

—

ns

Medium

SOUT data valid time (after SCK edge)

9

t_SUO

SOUT data valid time SOUT and SCK drive strength

from SCK

4

Very strong

Strong

25 pF

50 pF

—

7.0 + t_SYS

8.0 + t_SYS

ns

CPHA = 0⁹

4

Medium

16.0 + t_SYS

SOUT data valid time SOUT and SCK drive strength

from SCK

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

CPHA = 1⁹

Medium

16.0

SOUT data hold time (after SCK edge)

10 t_HO

SOUT data hold time SOUT and SCK drive strength

after SCK

4

Very strong

Strong

25 pF

50 pF

-7.7 + t_SYS

—

ns

CPHA = 0¹⁰

4

-11.0 + t_SYS

-15.0 + t_SYS

4

Medium

SOUT data hold time SOUT and SCK drive strength

after SCK

Very strong

Strong

25 pF

50 pF

-7.7

-11.0

-15.0

—

CPHA = 1¹⁰

Medium

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

4. t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t_SYS= 10

ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

6. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds.

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9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set

to 1.

10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

t_CSC

t_ASC

PCSx

t_SCK

t_SDC

SCK Output

(CPOL = 0)

t_SDC

SCK Output

(CPOL = 1)

t_SUI

t_HI

First Data

LastData

SIN

Data

t_SUO

t_HO

Data

Last Data

SOUT

Figure 33. DSPI CMOS master mode – modified timing, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

t_HI

t_SUI

t_HI

Data

First Data

SIN

LastData

t_SUO

t_HO

Data

SOUT

Last Data

First Data

Figure 34. DSPI CMOS master mode – modified timing, CPHA = 1

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t_PCSC

t_PASC

PCSS

PCSx

Figure 35. DSPI PCS strobe (PCSS) timing (master mode)1

18.2.1.3 DSPI LVDS master mode – modified timing

Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1),

CPHA = 0 or 1

#

Symbol

Characteristic

Condition

Pad drive

Value¹

Unit

Load

Min

Max

1

t_SCK

SCK cycle time

LVDS

15 pF

30.0

—

ns

to 25 pF

differential

2

3

t_CSC

PCS to SCK delay

(LVDS SCK)

PCS drive strength

Very strong

Strong

25 pF

(N²x t_SYS^{, 3}) - 10

(N²x t_SYS^{, 3}) - 32

(M⁴x t_SYS³) - 8

—

ns

50 pF

Medium

50 pF

t_ASC

After SCK delay

(LVDS SCK)

Very strong

PCS = 0 pF

SCK = 25 pF

PCS = 0 pF

SCK = 25 pF

PCS = 0 pF

SCK = 25 pF

15 pF

Strong

Medium

LVDS

(M⁴x t_SYS^{, 3}) - 8

¹/₂t_SCK- 2

—

ns

4

7

t_SDC

SCK duty cycle⁵

SIN setup time

¹/₂t_SCK+ 2

to 25 pF

differential

t_SUI

SIN setup time to

SCK

SCK drive strength

LVDS

3

15 pF

23 - (P⁷x t_SYS

)

—

ns

CPHA = 0⁶

to 25 pF

differential

SIN setup time to

SCK

SCK drive strength

LVDS

15 pF

23

CPHA = 1⁶

to 25 pF

differential

8

t_HI

SIN Hold Time

Table continues on the next page...

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AC specifications

Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1),

CPHA = 0 or 1 (continued)

#

Symbol

Characteristic

Condition

Pad drive

Value¹

Unit

Load

Min

Max

SIN hold time from

SCK

SCK drive strength

LVDS

, 3

0 pF differential

-1 + (P⁷x t_SYS

)

—

ns

CPHA = 0⁶

SIN hold time from

SCK

SCK drive strength

LVDS

0 pF differential

-1

—

ns

CPHA = 1⁶

9

t_SUO

SOUT data valid time (after SCK edge)

SOUT data valid time SOUT and SCK drive strength

from SCK

3

LVDS

15 pF

—

7.0 + t_SYS

CPHA = 0⁸

to 25 pF

differential

SOUT data valid time SOUT and SCK drive strength

from SCK

LVDS

15 pF

—

7.0

ns

CPHA = 1⁸

to 25 pF

differential

10 t_HO

SOUT data hold time (after SCK edge)

SOUT data hold time SOUT and SCK drive strength

after SCK

3

LVDS

15 pF

-7.5 + t_SYS

—

ns

CPHA = 0⁸

to 25 pF

differential

SOUT data hold time SOUT and SCK drive strength

after SCK

LVDS

15 pF

-7.5

CPHA = 1⁸

to 25 pF

differential

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable

using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same

edge of DSPI_CLKn).

3. t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t_SYS= 10

ns).

4. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable

using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK

clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge

of DSPI_CLKn).

5. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

6. Input timing assumes an input slew rate of 1 ns (10% - 90%) and LVDS differential voltage = 100 mV.

7. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set

to 1.

8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

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t_CSC

t_ASC

PCSx

t_SCK

t_SDC

SCK Output

(CPOL = 0)

t_SDC

SCK Output

(CPOL = 1)

t_SUI

t_HI

First Data

SIN

Data

LastData

t_SUO

t_HO

Data

Last Data

SOUT

Figure 36. DSPI LVDS master mode – modified timing, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t_HI

t_SUI

t_HI

Data

First Data

Last Data

SIN

t_SUO

t_HO

Data

SOUT

Last Data

First Data

Figure 37. DSPI LVDS master mode – modified timing, CPHA = 1

18.2.1.4 DSPI master mode – output only

For Table 43 :

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AC specifications

• All DSPI timing specifications apply to pins when using LVDS pads for SCK and

SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may

degrade for weaker output drivers.

• TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

Table 43. DSPI LVDS master timing - output only - timed serial bus mode TSB = 1 or ITSB =

1, CPOL = 0 or 1, continuous SCK clock

#

Symbol

Characteristic

Condition

Pad drive

LVDS

Value

Unit

Load

Min

Max

1

t_SCK

SCK cycle time

15 pF

25.0

—

ns

to 50 pF

differential

25 pF

2

3

4

t_CSV

t_CSH

t_SDC

PCS valid after SCK¹Very strong

—

6.0

ns

Strong

50 pF

(SCK with 50 pF

differential load cap.)

PCS hold after SCK¹Very strong

0 pF

-4.0

—

ns

Strong

(SCK with 50 pF

differential load cap.)

SCK duty cycle

LVDS

15 pF

¹/₂t_SCK- 2

¹/₂t_SCK+ 2

ns

(SCK with 50 pF

differential load cap.)

to 50 pF

differential

SOUT data valid time (after SCK edge)

5

t_SUO

SOUT data valid time SOUT and SCK drive strength

from SCK²

LVDS

15 pF

—

3.5

to 50 pF

differential

SOUT data hold time (after SCK edge)

6

t_HO

SOUT data hold time SOUT and SCK drive strength

after SCK²

LVDS

15 pF

-3.5

—

to 50 pF

differential

1. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

2. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

For Table 44 :

• TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

• All output timing is worst case and includes the mismatching of rise and fall times of

the output pads.

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Table 44. DSPI CMOS master timing - output only - timed serial bus mode TSB = 1 or ITSB =

1, CPOL = 0 or 1, continuous SCK clock

#

Symbol

Characteristic

Condition

Pad drive²

Load (C_L)

Value¹

Unit

Min

Max

1

t_SCK

SCK cycle time

SCK drive strength

Very strong

Strong

25 pF

33.0

80.0

—

ns

50 pF

ns

Medium

50 pF

200.0

2

t_CSV

PCS valid after SCK³SCK and PCS drive strength

Very strong

Strong

25 pF

50 pF

7

8

—

ns

Medium

16

29

PCS medium and PCS = 50 pF

SCK strong

SCK = 50 pF

3

t_CSH

PCS hold after SCK³SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

-14

-33

-35

—

ns

Strong

Medium

PCS medium and PCS = 0 pF

SCK strong

SCK = 50 pF

4

t_SDC

SCK duty cycle⁴

SCK drive strength

Very strong

Strong

0 to 50 pF

¹/₂t_SCK- 2

¹/₂t_SCK- 5

¹/₂t_SCK+ 2

¹/₂t_SCK+ 5

ns

Medium

SOUT data valid time (after SCK edge)

9

t_SUO

SOUT data valid time SOUT and SCK drive strength

from SCK

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

ns

CPHA = 1^{, 5}

Medium

16.0

SOUT data hold time (after SCK edge)

10 t_HO

SOUT data hold time SOUT and SCK drive strength

after SCK CPHA = 1⁵

Very strong

Strong

25 pF

50 pF

-7.7

-11.0

-15.0

—

ns

Medium

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may

cause incorrect operation.

3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This

timing value is due to pad delays and signal propagation delays.

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AC specifications

4. t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

5. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

PCSx

t_CSV

t_SCK

t_SDC

t_CSH

SCK Output

(CPOL = 0)

t_SUO

t_HO

First Data

Last Data

SOUT

Data

Figure 38. DSPI LVDS and CMOS master timing – output only – modified transfer format

MTFE = 1, CHPA = 1

18.2.2 DSPI CMOS slave mode

NOTE

DSPI slave operation is only supported for a single master and

single slave on the device. Timing is valid for that case only.

Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1)

#

Symbol

Characteristic¹

Condition

Pad drive

Value

Unit

Load

Min

62

16

30

—

Max

—

50

60

5

1

t_SCK

SCK Cycle Time

SS to SCK Delay

SCK to SS Delay

SCK Duty Cycle

—

ns

2

3

4

5

t_CSC

t_ASC

t_SDC

t_A

—

ns

—

Slave Access Time²Very strong

25 pF

50 pF

25 pF

50 pF

Strong

—

(SS active to SOUT

driven)

Medium

—

6

9

t_DIS

Slave SOUT Disable Very strong

—

Time²

Strong

—

5

(SS inactive to SOUT

High-Z or invalid)

Medium

—

10

t_SUI

Data Setup Time for

Inputs

—

10

—

ns

Table continues on the next page...

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Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1) (continued)

#

Symbol

Characteristic¹

Condition

Pad drive

Value

Unit

Load

Min

Max

10 t_HI

Data Hold Time for

Inputs

—

10

—

ns

11 t_SUO

SOUT Valid Time²

Very strong

Strong

25 pF

50 pF

25 pF

50 pF

—

30

50

—

ns

(after SCK edge)

Medium

Very strong

Strong

—

12 t_HO

SOUT Hold Time²

(after SCK edge)

2.5

Medium

1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.

2. All timing values for output signals in this table, are measured to 50% of the output voltage. All output timing is worst case

and includes the mismatching of rise and fall times of the output pads.

t_ASC

t_CSC

S S

t_SCK

S C K In p u t

t_SDC

(C P O L = 0 )

t_SDC

S C K In p u t

(C P O L = 1 )

t_SUO

t_HO

t_A

t_DIS

F irst D a ta

D a ta

L a st D a ta

S O U T

S IN

t_SUI

t_HI

L a st D a ta

F irst D a ta

Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0

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AC specifications

S S

S C K In p u t

(C P O L = 0 )

S C K In p u t

(C P O L = 1 )

t_SUO

t_A

t_DIS

t_HO

L a st D a ta

F irst D a ta

D a ta

S O U T

S IN

t_SUI

t_HI

F irst D a ta

L a st D a ta

Figure 40. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1

18.3 FEC timing

The FEC supports the 10/100 Mbps MII, 10/100 Mbps MII-lite, and the 10 Mbps-only 7-

wire interface.

18.3.1 MII-lite receive signal timing (RXD[3:0], RX_DV, RX_ER, and

RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at

least equal to or greater than the RX_CLK frequency.

All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels.

Table 46. MII-lite receive signal timing

Value

Unit

Spec

Characteristic

Min

5

Max

—

M1

M2

M3

M4

RXD[3:0], RX_DV, RX_ER to RX_CLK setup

RX_CLK to RXD[3:0], RX_DV, RX_ER hold

RX_CLK pulse width high

ns

5

—

ns

35%

65%

RX_CLK period

RX_CLK pulse width low

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M3

RX_CLK (input)

M4

RXD[3:0] (inputs)

RX_DV

RX_ER

M2

M1

Figure 41. MII-lite receive signal timing diagram

18.3.2 MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER,

TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz

+1%. There is no minimum frequency requirement. The system clock frequency must be

at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from

either the rising or falling edge of TX_CLK, and the timing is the same in either case.

This options allows the use of non-compliant MII PHYs.

All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels.

Table 47. MII-lite transmit signal timing

Value¹

Unit

Spec

Characteristic

Min

5

Max

—

M5

M6

M7

M8

TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

TX_CLK to TXD[3:0], TX_EN, TX_ER valid

TX_CLK pulse width high

ns

—

25

ns

35%

65%

TX_CLK period

TX_CLK pulse width low

1. Output parameters are valid for C_L= 25 p_F, where CL is the external load to the device. The internal package capacitance

is accounted for, and does not need to be subtracted from the 25 p_Fvalue.

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AC specifications

M7

TX_CLK (input)

M5

M8

TXD[3:0] (outputs)

TX_EN

TX_ER

M6

Figure 42. MII-lite transmit signal timing diagram

18.3.3 MII-lite async inputs signal timing (CRS and COL)

Table 48. MII-lite async inputs signal timing

Value

Unit

Spec

Characteristic

Min

Max

M9

CRS, COL minimum pulse width

1.5

—

TX_CLK period

CRS, COL

M9

Figure 43. MII-lite async inputs timing diagram

18.3.4 MII-lite serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

NOTE

All timing specifications are referenced from MDC = 1.4 V

(TTL levels) to the valid input and output levels, 0.8 V and 2.0

V (TTL levels). For 5 V operation, timing is referenced from

MDC = 50% to 2.2 V/3.5 V input and output levels.

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AC specifications

Table 49. MII-lite serial management channel timing

Value

Unit

Spec

Characteristic

Min

Max

M10

MDC falling edge to MDIO output invalid (minimum

propagation delay)

0

—

ns

M11

M12

M13

M14

M15

MDC falling edge to MDIO output valid (max prop delay)

MDIO (input) to MDC rising edge setup

MDIO (input) to MDC rising edge hold

MDC pulse width high

—

10

25

—

ns

0

—

ns

40%

60%

MDC period

MDC pulse width low

M14

M15

MDC (output)

M10

MDIO (output)

MDIO (input)

M11

M12

M13

Figure 44. MII-lite serial management channel timing diagram

18.3.5 RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Table 50. RMII serial management channel timing

Value

Unit

Spec

Characteristic

Min

Max

M10

MDC falling edge to

MDIO output invalid

(minimum propagation

delay)

0

—

ns

Table continues on the next page...

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AC specifications

Table 50. RMII serial management channel timing (continued)

Value

Unit

Spec

Characteristic

Min

Max

M11

MDC falling edge to

MDIO output valid (max

prop delay)

—

25

ns

M12

M13

MDIO (input) to MDC

rising edge setup

10

0

—

ns

MDIO (input) to MDC

rising edge hold

M14

M15

MDC pulse width high

MDC pulse width low

40%

60%

MDC period

M14

M15

MDC (output)

M10

MDIO (output)

MDIO (input)

M11

M12

M13

Figure 45. RMII-lite serial management channel timing diagram

18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at

least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK

frequency.

All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels.

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AC specifications

Unit

Table 51. RMII receive signal timing

Value

Spec

Characteristic

Min

4

Max

—

R1

R2

R3

R4

RXD[1:0], CRS_DV to REF_CLK setup

REF_CLK to RXD[1:0], CRS_DV hold

REF_CLK pulse width high

ns

2

—

ns

35%

65%

REF_CLK period

REF_CLK pulse width low

R3

REF_CLK (input)

R4

RXD[1:0] (inputs)

CRS_DV

R1

R2

Figure 46. RMII receive signal timing diagram

18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz +

1%. There is no minimum frequency requirement. The system clock frequency must be at

least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK

frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either

the rising or falling edge of REF_CLK, and the timing is the same in either case. This

options allows the use of non-compliant RMII PHYs.

All timing specifications are referenced from REF_CLK = 1.4 V to the valid output

levels.

Table 52. RMII transmit signal timing

Value

Unit

Spec

Characteristic

Min

2

Max

—

R5

R6

R7

R8

REF_CLK to TXD[1:0], TX_EN invalid

REF_CLK to TXD[1:0], TX_EN valid

REF_CLK pulse width high

ns

—

16

ns

35%

65%

REF_CLK period

REF_CLK pulse width low

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Obtaining package dimensions

R7

REF_CLK (input)

R5

R8

TXD[1:0] (outputs)

TX_EN

R6

Figure 47. RMII transmit signal timing diagram

18.4 UART timings

UART channel frequency support is shown in the following table.

Table 53. UART frequency support

LINFlexD clock frequency

LIN_CLK (MHz)

Oversampling rate

Voting scheme

Max usable frequency

(Mbaud)

80

16

8

3:1 majority voting

5

10

6

Limited voting on one sample

with configurable sampling

point

13.33

16

5

4

20

18.5 eMIOS timing

Table 54. eMIOS timing

Symbol

Characteristic

Condition

Min.

Max.

Unit

Value

t_MIPW

eMIOS Input Pulse Width

eMIOS_CLK = 100 MHz

2

—

cycles

19 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to http://www.nxp.com and perform a keyword search for

the drawing's document number.

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Thermal characteristics

If you want the drawing for this package

LQFP 144 PD

Then use this document number

98ASS23177W

LQFP 176 PD

98ASS23479W

98ASA00468D

98ASA00261D

MAPBGA 252 PD

MAPBGA 292 ED

20 Thermal characteristics

The following tables describe the thermal characteristics of the device.

Junction temperature is a function of die size, on-chip power dissipation, package thermal

resistance, mounting side (board) temperature, ambient temperature, air flow, power

dissipation or other components on the board, and board thermal resistance.

Table 56. Thermal characteristics for the 144-pin LQFP package

Rating

Conditions

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Symbol

R_θJA

Value

41.3

33.0

32.4

26.7

21.5

7.0

Unit

°C/W

Junction to Ambient Natural Convection ^{1, 2}

Junction to Ambient Natural Convection^{1, 2, 3}

Junction to Ambient (@200 ft/min)^{1, 3}

Junction to Board⁴

R_θJA

R_θJMA

R_θJB

Junction to Case ⁵

Junction to Package Top⁶

Junction to Package Lead⁷

—

R_θJC

ψ_JT

Natural Convection

0.25

16.5

ψ_JB

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12.

Table 57. Thermal characteristics for the 176-pin LQFP package

Rating

Conditions

Symbol

R_θJA

Value

49.9

Unit

°C/W

Junction to Ambient Natural Convection ^{1, 2}

Junction to Ambient Natural Convection^{1, 2, 3}

Single layer board (1s)

Four layer board (2s2p)

R_θJA

33.8

Table continues on the next page...

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Thermal characteristics

Table 57. Thermal characteristics for the 176-pin LQFP package (continued)

Rating

Conditions

Single layer board (1s)

Four layer board (2s2p)

—

Symbol

R_θJMA

R_θJB

Value

37.8

28.2

21.0

7.8

Unit

°C/W

Junction to Ambient (@200 ft/min)^{1, 3}

Junction to Board⁴

Junction to Case⁵

Junction to Package Top⁶

Junction to Package Lead⁷

—

R_θJC

Natural Convection

ψ_JT

0.3

ψ_JB

13.0

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12.

Table 58. Thermal characteristics for the 252-pin MAPBGA package with full solder balls

Rating

Conditions

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Symbol

R_θJA

Value

43.0

26.5

33.2

22.2

12.5

6.3

Unit

°C/W

Junction to Ambient Natural Convection ^{1, 2}

Junction to Ambient Natural Convection^{1, 2, 3}

Junction to Ambient (@200 ft/min)^{1, 3}

Junction to Board⁴

R_θJA

R_θJMA

R_θJB

Junction to Case⁵

Junction to Package Top⁶

Junction to Package Lead⁷

—

R_θJC

ψ_JT

Natural Convection

0.3

ψ_JB

8.7

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

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Thermal characteristics

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12.

Table 59. Thermal characteristics for the 252-pin MAPBGA package 16 removed balls: 12

central, 4 corner peripheral

Rating

Conditions

Symbol

R_θJA

Value

23.8

15.9

4.8

Unit

°C/W

Junction to Ambient Natural Convection^{1, 2, 3}

Junction to Board⁴

Four layer board (2s2p)

Natural Convection

R_θJB

Junction to Package Lead⁵

ψ_JB

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12.

20.1 General notes for specifications at maximum junction

temperature

An estimation of the chip junction temperature, T_J, can be obtained from this equation:

T_J= T_A+ (R_θJA× P_D)

where:

• T_A= ambient temperature for the package (°C)

• R_θJA= junction to ambient thermal resistance (°C/W)

• P_D= power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a

quick and easy estimation of thermal performance. Unfortunately, there are two values in

common usage: the value determined on a single layer board and the value obtained on a

board with two planes. For packages such as the PBGA, these values can be different by

a factor of two. Which value is closer to the application depends on the power dissipated

by other components on the board. The value obtained on a single layer board is

appropriate for the tightly packed printed circuit board. The value obtained on the board

with the internal planes is usually appropriate if the board has low power dissipation and

the components are well separated.

When a heat sink is used, the thermal resistance is expressed in the following equation as

the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

R_θJA= R_θJC+ R_θCA

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Ordering information

where:

• R_θJA= junction to ambient thermal resistance (°C/W)

• R_θJC= junction to case thermal resistance (°C/W)

• R_θCA= case to ambient thermal resistance (°C/W)

R_θJCis device related and cannot be influenced by the user. The user controls the thermal

environment to change the case to ambient thermal resistance, R_θCA. For instance, the

user can change the size of the heat sink, the air flow around the device, the interface

material, the mounting arrangement on printed circuit board, or change the thermal

dissipation on the printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks

are not used, the Thermal Characterization Parameter (Ψ_JT) can be used to determine the

junction temperature with a measurement of the temperature at the top center of the

package case using this equation:

T_J= T_T+ (Ψ_JT× P_D)

where:

• T_T= thermocouple temperature on top of the package (°C)

• Ψ_JT= thermal characterization parameter (°C/W)

• P_D= power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a

40 gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over

about 1 mm of wire extending from the junction. The thermocouple wire is placed flat

against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

21 Ordering information

Table 60. Ordering information

Part Number

SPC5746RK1MMT5

SPC5746RK1MLU3

SPC5745RK1MMT5

SPC5745RK1MLU3

SPC5743RK1MLU5

SPC5743RK1MLQ5

PPC5746R2K1MMZ5A

Device Type

Sample PD¹

Sample PD

Sample ED²

Flash/SRAM

4M / 256 KB

4M/256KB

Emulation RAM

Package

252 MAPBGA

176 LQFP

Frequency

200 MHz

150 MHz

200 MHz

150 MHz

200 MHz

-

3M/192KB

-

252 MAPBGA

176 LQFP

3M / 192 KB

2M / 128KB

2M / 128 KB

4M / 256 KB

-

176 LQFP

144 LQFP

1 MB

292 MAPBGA

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Revision history

1. "PD" refers to a production device, orderable in quantity.

2. “ED" refers to an emulation device, orderable in limited quantities. An emulation device (ED) is for use during system

development only and is not to be used in production. An ED is a Production PD chip combined with a companion chip to

form an Emulation and Debug Device (ED) and includes additional RAM memory and debug features. EDs are provided

“as is" without warranty of any kind. In the event of a suspected ED failure, NXP agrees to exchange the suspected failing

ED from the customer at no additional charge, however NXP will not analyze ED returns.

22 Revision history

Table 61. Revision history

Revision

Date

Description of changes

1

2

05/2013 Initial release.

12/2014 Overall:

• Editorial changes.

• Removed the Classification columns in spec tables and removed statements that values need

to be characterized.

• In footnotes changed cross references to figures to static text.

In section Block diagram :

• In Figure 1, changed "AIPS Bridge 0/1" to "AIPS PBridge_0/1".

• In Figure 2 :

• Changed figure title (was “Peripherals block diagram”).

• Changed "BAF" to "BAR".

• Added PBRIDGE_1, EIM, XBAR, and PBRIDGE_0.

In section Introduction, removed section "Parameter classification".

In section Absolute maximum ratings, Table 1 :

• VDD_HV_IO_FEC spec: removed row for "Using Ethernet Reference to VSS" condition.

• Corrected "VIDD_HV_IO_MSC" to "VDD_HV_IO_MSC".

• Add parameter IIOMAX.

• Deleted IMAXSEG parameter.

In section Operating conditions :

• Deleted sentence "The ranges in this table are design targets...".

• Added a NOTE that all power supplies need to be powered up.

• In Table 3 :

• Removed VDD_HV_FLA.

• Changed minimum voltage of VDD_HV_ADV_SD.

• Modified footnote for S/D ADC supply voltage.

• Modified footnote for SAR ADC supply voltage.

• Modified VRAMP spec to two separate specs for "VRAMP_VDD_LV" and

"VRAMP_VDD_HV_IO_MAIN, VRAMP_VDD_HV_PMC".

In section DC electrical specifications :

• Removed the statement that the ranges are design targets.

• In Table 5 :

• Modified I_{DD_LV}to show specs depending on device model. Modified footnote.

• Removed the “PMC only” row of the IDD_HV_PMC “internal core reg bypassed” spec.

• Removed IDD_MAIN_CORE_AC.

• Removed IDD_LKSTP_AC.

• Changed I_{DDSTBY_ON}value at 40 °C.

• Changed I_{DDSTBY_REG}parameter to "32 KB RAM Standby Regulator Current" (was

"Standby Leakage Current"); changed condition to "V_DDSTBY@1.2 V to 5.9 V, Tj =

150C" (was "V_DDSTBY@1.3 V...")

Table continues on the next page...

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Revision history

Table 61. Revision history

Revision

Date

Description of changes

• Removed IDDOFF.

• Added IDD_BD_STBY.

• Added IVDDA.

In section Input pad specifications :

• In Table 7 :

• Added footnote that supported input levels vary according to pad types.

• Corrected VILTTL Min and Max values.

• Corrected VIHAUTO, VILCMOS_H and VILCMOS Min value.

• In Table 8 :

• Modified |IWPU| Min values for condition Vin = VIH = 0.65 * VDD_HV_IO.

• Modified |IWPD| Min values for condition Vin = VIL = 0.35 * VDD_HV_IO.

• Removed the "Analog Input Leakeage and Pull-Up/Down DC electrical characteristics" table

and the preceding introductory paragraph to be moved to the ADC input description section.

In section Output pad specifications, Table 9, changed VOH and VOL specs to two separate specs

for 3V pads and 5V pads respectively. Corrected VOH Min and VOL Max values.

In section I/O pad current specifications :

• Added I/O Current Consumption tables.

• Modified NOTE on Excel file attached to the Reference Manual.

Added section Reset pad (PORST, RESET) electrical characteristics.

In section Oscillator and FMPLL :

• In Table 13, removed PLL0_PHI0 single period jitter row.

• In Table 15 :

• Modified footnote for CS_EXTAL and CS_XTAL.

• Modified gm (Oscillator Transconductance) spec.

• Removed VHYS.

In section ADC modules, revised the subsection structure and titles:

• Added section ADC input description with content moved from the "Input pad specifications"

section.

• Section "Input impedance and ADC accuracy" renamed to Input equivalent circuit and ADC

conversion characteristics with all content except Figure 11 and Table 19 removed.

• Removed erroneous section "SAR ADC electrical specification".

In section SAR ADC, Table 19 :

• Added footnote ("SAR ADC performance is not guaranteed...") to f_CKsymbol.

• Changed t_samplespecification min value to 250 ns (was 275).

• Added footnote to OFS and GNE. Changed OFS and GNE min and max values.

• Removed "Input (singe ADC channel)".

• Removed injection row for "Input (double ADC channel)".

• SNR, THD, SINAD, and ENOB specifications: changed frequency condition to 50 kHz (was

125 kHz).

• Changed SNR Min values.

• Added footnote to ENOB.

• Added I_{DD_VDDA}, I_{DD_VDDR}, and V_{BG_REF}parameters.

In section S/D ADC, Table 20 :

• For V_{IN_PK2PK}parameter second and third rows, changed V_SSin Conditions to V_DD

• For f_{ADCD_M}specification, removed sampling frequency footnote from parameter.

• Added footnote to RESOLUTION value.

.

• For |δ_GAIN| specification added footnote to parameter and added new row with more detailed

"After calibration" conditions.

• Moved footnote "S/D ADC is functional in the range..." from the Z_INto the SNR parameters.

Table continues on the next page...

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Revision history

Table 61. Revision history

Revision

Date

Description of changes

• Changed all instances of “4.0 < VDD_HV_ADV_SD < 5.5” in the Conditions column to “4.5 <

VDD_HV_ADV_SD < 5.5”. Modified voltage range in its footnote.

• Changed SNR_SE150, GAIN = 16 condition min value to 55 dB (was 60).

• Changed SINAD_SE150, GAIN = 16 condition min value to 54 dB (was 59).

• Unit for SINADDIFF150, SINADDIFF333 and SINADSE150 changed from dBFs to dB.

• For Z_INspecification, revised parameter footnote.

• Added CMRR to symbol column for Common mode rejection ratio specification. Changed min

value to 55 dB.

• For δ_GROUPspecification, revised maximum values for OSR = 24 to OSR = 256 conditions.

• Revised entire row for t_LATENCY, t_SETTLING, and t_ODRECOVERYspecifications. Footnote added to

t_LATENCYparameter.

• Added I_BIASspecification.

• Changed IADV_D and ΣIADR_D values.

In section Temperature sensor, Table 21 :

• Changed TACC values.

• Removed ITEMP_SENS spec item.

In section LFAST interface timing diagrams, Figure 12, "|ΔVOD|" changed to "|VOD|".

In section LFAST and MSC /DSPI LVDS interface electrical characteristics, Table 24, the max.

value for Rise/ Fall time specs changed from 4.0 to 5.7 ns.

In section LFAST PLL electrical characteristics, Table 25, ΔPER_EYEspecification, changed Nominal

value to 550 (was blank) and Max value to blank (was 400).

In section Recommended power transistors, Table 27, added the specification for V_C.

In section Power management integration :

• In Figure 17 :

• Changed "n x C_LV" to "C_LV".

• Changed C_{HV_ADC_S}to C_{HV_ADC_SAR}

• In Table 28 :

.

• Changed the first footnote for CHV_PMC to have the same footnote number as the first

footnote for CLV as they were identical.

• Modified Minimum V_{DD_HV_ADV_SAR}external capacitance and associated footnote.

Added section Regulator example for the NJD2873 transistor.

Added section Regulator example for the 2SCR574d transistor.

In section Device voltage monitoring, Table 29 :

• Updated following specs:

• LVD_core_hot

• LVD_core_cold

• HVD_core

• LVD_HV

• HVD_HV

• LVD_IO

• LVD_SAR

• Removed following specs:

• LVD_FLASH

• HVD_FLASH

• LVD_MSC_3V3

• LVD_MSC_5V0

• LVD_FEC_5V0

• LVD_JTAG

• HVD_SAR

Table continues on the next page...

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Revision history

Table 61. Revision history

Revision

Date

Description of changes

• LVD_SD

• HVD_SD

• Corrected Voltage detector threshold crossing assertion Unit.

In section Flash memory program and erase specifications, Table 30 :

• Removed parenthetical phrase from table title.

• Made overall updates to spec values.

• Removed footnote 7.

In section Flash memory Array Integrity and Margin Read specifications, Table 31 :

• Removed parenthetical phrase from table title.

• Made overall updates to spec values.

In section Flash memory module life specifications, Table 32, removed parenthetical phrase from

table title.

In section Flash memory AC timing specifications, Table 33, removed parenthetical phrase from

table title.

Added section Flash read wait state and address pipeline control settings.

In section Power management integration, Table 28, changed the footnotes for t_TCYCMin values to

have the same footnote number as they were identical.

In section DSPI timing with CMOS and LVDS, Table 39, LVDS (Master mode) specification:

changed Max usuable frequency to 40 MHz (was 33 MHz).

In section DSPI CMOS master mode – classic timing :

• Added NOTE.

• In Table 40, changed PCS strobe timing values.

In section DSPI CMOS master mode – modified timing :

• Added NOTE.

• In Table 41, changed PCS strobe timing values.

In section DSPI LVDS master mode – modified timing, Table 42, changed significant digits for some

values.

In section DSPI master mode – output only :

• Modified format paragraphs leading the tables. Removed NOTE.

• In Table 43, changed the t_CSVstrong drive value and t_HOLVDS value.

• In Table 44, changed significant digits for some values.

In section FEC timing, corrected the title of MII-lite and RMII serial management channel timing

subsections.

In section MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK), Table 47, modified

footnote for output parameters.

In section RMII serial management channel timing (MDIO and MDC), added Note on reference for

timing specifications.

In section RMII transmit signal timing (TXD[1:0], TX_EN), Table 52, modified R6 max value.

In section UART timings, Table 53, removed 100 MHz specification.

"Package drawings" section renamed to Obtaining package dimensions, with package drawing

document numbers to search at the Freescale website. Drawings removed from this document.

In section Thermal characteristics :

• Added table for 144 LQFP.

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

94

NXP Semiconductors

Revision history

Table 61. Revision history (continued)

Revision

Date

Description of changes

• Moved table for 176 LQFP before 252 MAPBGA and updated table.

• Replaced table for 252 MAPBGA with two separate tables for package with full solder balls

and package with 16 removed balls.

In section Ordering information, replaced the table.

3

09/2015 On the cover page:

• Changed doctype from "Data Sheet: Product Preview" to "Data Sheet: Technical Data" at the

upper left corner.

• Changed statement on status of doc at the bottom of the page.

Removed "Preliminary" and "Non-Disclosure Agreement required" from footers on each page.

In section Electromagnetic Compatibility (EMC) removed content of entire section and replaced it

with statement: "EMC measurements to IC-level IEC standards are available from Freescale on

request."

In section Operating conditions :

• In Table 3

• For VDD_HV_PMC, removed the two footnotes.

• For VDDSTBY, added statement on ramp rate to footnote.

• For VSTBY_BO, removed Min value and added Max value.

In section DC electrical specifications :

• In Table 5 :

• IDD_LV spec:

• MPC5746R/MPC5745R Max value changed to 700 mA.

• MPC5743R/MPC5742R Max value changed to 610 mA.

• IDDSTBY_ON TA=40°C and TA=85°C values updated.

• IVDDA values updated.

In section I/O pad specification, Table 6 Description for Input only pads, removed reference to

"Automotive" input.

In section Input pad specifications, Table 7 removed VIHAUTO, VILAUTO, VHYSAUTO, and

VDRFTAUTO specs and references to "Automotive" input in footnotes.

In section Output pad specifications :

• In Table 9, removed footnote for tR_F spec Parameter about transition time maximum value

approximation formula.

In section Reset pad (PORST, RESET) electrical characteristics :

• In Table 12 :

• Changed specs for VIH, VIL, and VHYS to VIH Reset, VIL Reset, and VHYS Reset

respectively.

• Added specs for VIH PORST, VIL PORST, VHYS PORST.

• Generally added Conditions and updated spec values. In the Conditions column,

changed all instances of "3.0 V" to "3.5 V".

In section Oscillator and FMPLL :

• In Table 13, for ΔPLL0LTJ spec, modified long term jitter Min and Max values.

• In Table 16, values updated.

• In Table 17, added spec for dfTRIM (IRC software trimming step).

In section ADC input description :

• In Table 18 :

• RPUPD 5KΩ spec Max value changed to 8.8KΩ.

In section Input equivalent circuit and ADC conversion characteristics :

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

95

Revision history

Table 61. Revision history (continued)

Revision

Date

Description of changes

• In Table 19 :

• In the SNR, THD, SINAD, and ENOB rows Conditions, changed "50 kHz" to "125 kHz".

Modified footnote to ENOB

• In IDD_VDDA and IDD_VDDR rows, modified values.

• In VBG_REF row's Conditions, added "INPSAMP=0xFF"

• Added NOTE "For spec complaint operation, do not expose clock sources, including crystal

oscillator, IRC, PLL0, and PLL1 on the CLKOUT pads while the SAR ADC is converting."

• Added NOTE: "The ADC performance specifications are not guaranteed if two or more ADCs

simultaneously sample the same shared channel".

In section S/D ADC :

• In Table 20 :

• For THD_DIFF333GAIN = 16, updated Min value.

• For I_{ADV_D}, updated Max value.

In section LFAST and MSC /DSPI LVDS interface electrical characteristics :

• After table Table 24 added NOTE "For optimum LVDS performance, it is recommended to set

the neighbouring GPIO pads to use Weak Drive".

In section Device voltage monitoring :

• In Table 29 :

• For LVD_core_hot, LVD_HV, and LVD_IO specs, removed the untrimmed Rising

voltage and Falling voltage rows.

• For LVD_core_hot, changed Mask Opt. value to "No".

In section Regulator example for the 2SCR574d transistor, figure "Regulator example", changed “5V

or Vcollector” to “3.3V or Vcollector”.

In section DSPI CMOS master mode – classic timing, Table 40 :

• Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF".

• In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds.

In section DSPI CMOS master mode – modified timing, Table 41 :

• Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF".

• In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds.

In section DSPI master mode – output only, Table 44, changed tSDC spec's Condition SCK drive

strength from "0 pF" to "0 to 50 pF".

Added section eMIOS timing.

In section Ordering information, Table 60 :

• Updated Part Numbers.

• Updated Emulation device footnote.

4

03/2016 In section Block diagram, Figure 2 :

• "DECIM" changed to "DECFILTER".

• "SIPI" changed to "Zipwire".

• I/O lines added to Zipwire, SIUL2, REACM, eTPU, eMIOS, IGF, and XOSC.

In section Absolute maximum ratings table "Absolute maximum ratings", removed I_IOMAXspec and

added I_MAXSEGspec.

In section Operating conditions table "Device operating conditions":

• For the FEC I/O supply voltage, MSC I/O supply voltage, and JTAG I/O supply voltage specs,

removed the LVD enabled/disabled distinction.

• Added footnote to I_MAXSEG

.

In section I/O pad current specifications :

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

96

NXP Semiconductors

Revision history

Table 61. Revision history (continued)

Revision

Date

Description of changes

• Modified the descriptions in the two paragraphs after the tables.

• Removed the third paragraph after the tables and the first Note.

Added section DSPI CMOS slave mode.

In section Ordering information table "Ordering Information", changed Part Numbers for the 176

LQFP PD and the ED.

5

10/2016 Editorial updates.

In section Operating conditions table "Device operating conditions" added foootnote to

V_{DD_HV_IO_JTAG}

In section Input pad specifications table "I/O input DC electrical characteristics" for I_LKGadded

condition "V_SS< V_IN< V_{DD_HV_IO*}

.

"

In section ADC input description table "Analog Input Leakage and Pull-Up/Down DC electrical

characteristics" for ILK_AD added conditions "V_{SS_HV_ADV_SAR}< V_IN< V_{DD_HV_ADV_SAR}" and

"V_{SS_HV_ADV_SD}< V_IN< V_{DD_HV_ADV_SD}".

In section Recommended power transistors table "Recommended operating characteristics" for

I_CMaxDCchanged the parameter from "Minimum peak collector current" to "Maximum DC collector

current".

In section SAR ADC table "ADC conversion characteristics":

• Removed the condition for t_sample

• Removed the Min and added the formula (6.02*ENOB) + 1.76 for SINAD.

• Changed the Min value from 650 to 700 for t_conv

.

In section S/D ADC table "SDn ADC electrical specification":

• Removed Z_INspecification

• Added Z_DIFF, Z_CM, and ΔV_INTCMspecifications

• For R_BIAS

:

• Changed Parameter description from "Bias resistance" to "Bare bias resistance"

• Changed Min from 100 kΩ to 110 kΩ

• Changed Typ from 125 kΩ to 144 kΩ

• Changed Max from 160 kΩ to 180 kΩ

In section Flash memory AC timing specifications table "Flash memory AC timing specifications" for

t_psus

:

• Changed Typical from 7 μs plus four system clock periods to 9.4 μs plus four system clock

periods

• Changed Max from 9.1 μs plus four system clock periods to 11.5 μs plus four system clock

periods

6

05/2017 Changed Freescale to NXP throughout the datasheet.

In Ordering information added rows for SPC5746RK1MLU3, SPC5745RK1MMT5 and

SPC5743RK1MLU5.

In Table 3 added footnote in V_{DD_HV_PMC}

In Table 28 for the rowset C_{HV_FLA}changed the Minimum and Typical values.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors

97

How to Reach Us:

Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

Home Page:

nxp.com

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nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any

particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including “typicals,” must be validated for each customer application

by customerʼs technical experts. NXP does not convey any license under its patent rights nor the

rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be

found at the following address: nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to unidentified

vulnerabilities. Customers are responsible for the design and operation of their applications and

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NXP accepts no liability for any vulnerability that is discovered. Customers should implement

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Document Number MPC5746R

Revision 6, 06/2017


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描述：	RISC Microcontroller 微控制器外围集成电路
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