935362769528_技术文档

NXP Semiconductors

MKW36A512

Data Sheet: Technical Data

Rev. 7, 09/2019

MKW36A/35A/34A Data Sheet

MKW36A512VHT4

An ultra low power, highly integrated Bluetooth® Low

Energy 5.0 wireless microcontroller

MKW36A512VFP4

MKW36A512VFT4

MKW35A512VFP4

MKW35A512VFT4

MKW34A512VFT4

48 LQFN

48 "Wettable" HVQFN

7x7 mm Pitch 0.5 mm 7x7 mm Pitch 0.5 mm

40 "Wettable" HVQFN

6x6 mm Pitch 0.5 mm

Multi-Standard Radio

System peripherals

• 2.4 GHz Bluetooth Low Energy (Bluetooth LE) version

5.0 compliant supporting up to 8 simultaneous

hardware connections

• Nine MCU low-power modes to provide power

optimization based on application requirements

• DC-DC Converter supporting Buck and Bypass

operating modes

• Generic FSK modulation

• Data Rate: 250, 500 and 1000 kbps

• Modulations: GFSK BT = 0.3, 0.5, and 0.7;

FSK/MSK

• Direct memory access (DMA) Controller

• Computer operating properly (COP) watchdog

• Serial wire debug (SWD) Interface and Micro Trace

buffer

• Modulation Index: 0.32, 0.5, 0.7, and 1.0

• Typical Receiver Sensitivity (Bluetooth LE 1 Mbps) =

-95 dBm

• Bit Manipulation Engine (BME)

Analog Modules

• Typical Receiver Sensitivity (250 kbps GFSK-BT=0.5,

h=0.5) = -99 dBm

• Programmable Transmitter Output Power: -30 dBm to

+3.5 dBm

• 16-bit Analog-to-Digital Converter (ADC)

• 6-bit High Speed Analog Comparator (CMP)

• 1.2 V voltage reference (VREF)

• Low external component counts for low cost application

• On-chip balun with single ended bidirectional RF port

Timers

• 16-bit low-power timer (LPTMR)

• 3 Timer/PWM Modules(TPM): One 4 channel TPM

and two 2 channel TPMs

• Programmable Interrupt Timer (PIT)

• Real-Time Clock (RTC)

MCU and Memories

• 256 KB program flash memory plus 256 KB FlexNVM

on KW36A/34A

• 8 KB FlexRAM supporting EEPROM emulation on

KW36A/34A

• 512 KB program flash memory on KW35A

• Up to 48 MHz Arm® Cortex®-M0+ core

• On-chip 64 KB SRAM

Communication interfaces

• 2 serial peripheral interface (SPI) modules

• 2 inter-integrated circuit (I2C) modules

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Low Power Consumption

• Low Power UART (LPUART) module with LIN

support (2x LPUART on KW36A)

• Carrier Modulator Timer (CMT)

• Transceiver current (DC-DC buck mode, 3.6 V supply)

• Typical Rx Current: 6.3 mA

• Typical Tx current: 5.7 mA (0 dBm output)

• Low Power Mode (VLLS0) Current: 258 nA

• FlexCAN module (with CAN FD support up to 3.2

Mbps baudrate) on KW36A

Clocks

Security

• 26 and 32 MHz supported for Bluetooth LE and

Generic FSK modes

• 32.768 kHz Crystal Oscillator

• AES-128 Hardware Accelerator (AESA)

• True Random Number Generator (TRNG)

• Advanced flash security on Program Flash

• 80-bit unique identification number per chip

• 40-bit unique media access control (MAC) sub-

address

Operating Characteristics

• Voltage range: 1.71 V to 3.6 V

• Ambient temperature range: –40 to 105 °C

• AEC Q100 Grade 2 Automotive Qualification

• LE Secure Connections

Human-machine interface

• General-purpose input/output

Orderable parts details

Top Line

Marking

CAN

FD

2^ndUART with

FlexRAM Package

LIN

Device

Qualification

MKW36A512VHT4 (F)M36A

Auto

Y

7X7 mm 48-pin LQFN

MKW36A512VFT4 MW36A512V4 Auto

MKW36A512VFP4 M36A9V4 Auto

MKW35A512VFT4 MW35A512V4 Auto

MKW35A512VFP4 M35A9V4 Auto

Y

N

7X7 mm 48-pin "Wettable"

HVQFN

Y

N

Y

N

Y

6X6 mm 40-pin "Wettable"

HVQFN

7X7 mm 48-pin "Wettable"

HVQFN

6X6 mm 40-pin "Wettable"

HVQFN

MKW34A512VFT4 MW34A512V4 Auto

7X7 mm 48-pin "Wettable"

HVQFN

Related Resources

Description

Type

Resource

Product

Selector

The Product Selector lets you find the right Kinetis part for your design.

W-Series Product Selector

Fact Sheet

The Fact Sheet gives overview of the product key features and its uses. KW36-35-34 Fact Sheet

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

MKW36A512RM¹

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

This document.

Chip Errata

The chip mask set Errata provides additional or corrective information for KINETIS_W_1N41U¹

a particular device mask set.

Package

drawing

Package dimensions are provided in package drawings.

• 40-pin "Wettable" HVQFN

(6x6): 98ASA01025D¹

2

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Related Resources

Description

Type

Resource

• 48-pin LQFN (7x7):

98ASA00694D¹

• 48-pin "Wettable" HVQFN

(7x7): 98ASA01307D¹

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

3

NXP Semiconductors

Table of Contents

1

2

Introduction........................................................................... 5

6.5 Peripheral operating requirements and behaviors.........45

6.5.1 Core modules.................................................... 45

6.5.2 System modules................................................46

6.5.3 Clock modules...................................................47

6.5.4 Memories and memory interfaces..................... 50

6.5.5 Security and integrity modules.......................... 53

6.5.6 Analog............................................................... 53

6.5.7 Timers................................................................61

6.5.8 Communication interfaces................................. 61

6.5.9 Human-machine interfaces (HMI)......................66

6.6 DC-DC Converter Operating Requirements.................. 66

6.7 Ratings...........................................................................68

6.7.1 Thermal handling ratings...................................68

6.7.2 Moisture handling ratings.................................. 69

6.7.3 ESD handling ratings.........................................69

6.7.4 Voltage and current operating ratings............... 69

Pin Diagrams and Pin Assignments......................................70

7.1 KW36A Signal Multiplexing and Pin Assignments.........70

7.2 KW36A Pinouts..............................................................73

7.3 KW35A Signal Multiplexing and Pin Assignments.........75

7.4 KW35A Pinouts..............................................................78

7.5 KW34A Signal Multiplexing and Pin Assignments.........80

7.6 KW34A Pinouts..............................................................83

7.7 Module Signal Description Tables................................. 84

7.7.1 Core Modules.................................................... 84

7.7.2 Radio Modules...................................................85

7.7.3 System Modules................................................86

7.7.4 Clock Modules...................................................87

7.7.5 Analog Modules.................................................87

7.7.6 Timer Modules...................................................88

7.7.7 Communication Interfaces.................................89

7.7.8 Human-Machine Interfaces(HMI)...................... 90

Package Information............................................................. 91

8.1 Obtaining package dimensions......................................91

Part identification...................................................................91

9.1 Description.....................................................................91

9.2 Format........................................................................... 92

9.3 Fields............................................................................. 92

9.4 Example.........................................................................92

Feature Descriptions.............................................................6

2.1 Block Diagram............................................................... 6

2.2 Radio features............................................................... 7

2.3 Microcontroller features................................................. 8

2.4 System features.............................................................10

2.5 Peripheral features........................................................ 12

2.6 Security Features...........................................................16

Transceiver Description........................................................ 17

3.1 Key Specifications......................................................... 18

3.2 Channel Map Frequency Plans .................................... 18

3.2.1 Channel Plan for Bluetooth Low Energy............18

3.2.2 Other Channel Plans ........................................ 20

3.3 Transceiver Functions................................................... 20

Transceiver Electrical Characteristics...................................20

4.1 Radio operating conditions............................................ 21

4.2 Receiver Feature Summary...........................................21

4.3 Transmit and PLL Feature Summary.............................23

System and Power Management..........................................26

5.1 Power Management.......................................................26

5.1.1 DC-DC Converter.............................................. 27

5.2 Modes of Operation....................................................... 27

5.2.1 Power modes.....................................................27

KW36A/35A/34A Electrical Characteristics...........................29

6.1 AC electrical characteristics...........................................29

6.2 Nonswitching electrical specifications............................30

6.2.1 Voltage and current operating requirements..... 30

6.2.2 LVD and POR operating requirements..............31

6.2.3 Voltage and current operating behaviors...........32

6.2.4 Power mode transition operating behaviors...... 33

6.2.5 Power consumption operating behaviors.......... 34

6.2.6 Diagram: Typical IDD_RUN operating behavior39

6.2.7 SoC Power Consumption.................................. 41

6.2.8 Designing with radiated emissions in mind........42

6.2.9 Capacitance attributes.......................................42

6.3 Switching electrical specifications..................................42

6.3.1 Device clock specifications................................42

6.3.2 General switching specifications....................... 43

6.4 Thermal specifications...................................................44

6.4.1 Thermal operating requirements....................... 44

6.4.2 Thermal attributes..............................................44

3

4

5

7

6

8

9

10 Revision History.................................................................... 93

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Introduction

1 Introduction

The KW36A/35A/34A wireless microcontrollers (MCU), which includes the KW36A,

KW35A, and KW34A families of devices, are highly integrated single-chip devices

that enable Bluetooth Low Energy (Bluetooth LE) and Generic FSK connectivity for

automotive embedded systems. To meet the stringent requirements of automotive

applications, the KW36A/35A/34A is fully AEC Q100 Grade 2 Automotive

Qualified. The target applications center on wirelessly bridging the embedded world

with mobile devices to enhance the human interface experience, share embedded data

between devices and the cloud and enable wireless firmware updates. Leading the

automotive applications is the Digital Key, where a smartphone can be used by the

owner as an alternative to the key FOB for unlocking and personalizing the driving

experience. For a car sharing experience, the owner can provide selective, temporary

authorization for access to the car allowing the authorized person to unlock, start and

operate the car using their mobile device using Bluetooth LE.

The KW36A/35A/34A Wireless MCU integrates an Arm® Cortex®-M0+ CPU with

up to 512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE

5.0 and Generic FSK modulations. The Bluetooth LE radio supports up to 8

simultaneous connections in any master/slave combination. The Medical Body Area

Network (MBAN) frequencies from 2.36 to 2.4 GHz are also supported enabling

wearable or implantable wireless medical devices.

The KW36A includes an integrated FlexCAN module enabling seamless integration

into a cars in-vehicle CAN communication network. The FlexCAN module can

support CAN’s flexible data-rate (CAN FD) protocol for increased bandwidth and

lower latency required by many automotive applications.

The KW36A/35A/34A devices can be used as a "BlackBox" modem in order to add

Bluetooth LE or Generic FSK connectivity to an existing host MCU or MPU

(microprocessor), or may be used as a standalone smart wireless sensor with

embedded application where no host controller is required.

The RF circuit of the KW36A/35A/34A is optimized to require very few external

components, achieving the smallest RF footprint possible on a printed circuit board.

Extremely long battery life is achieved through the efficiency of code execution in the

Cortex-M0+ CPU core and the multiple low power operating modes of the

KW36A/35A/34A. For power critical applications, an integrated DC-DC converter

enables operation from a single coin cell or Li-ion battery with a significant reduction

of peak receive and transmit current consumption.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Feature Descriptions

2 Feature Descriptions

This section provides a simplified block diagram and highlights the KW36A/35A/34A

features.

2.1 Block Diagram

Arm Cortex M0+ Core

32K Osc

32M Osc

IRC

MCG

DMA MUX

4ch DMA

Serial Wire Debug

DAP MDM

NVIC

WIC

4 MHz

DWT

MTB

IRC

32 kHz

FLL

IOPORT

Unified Bus

AHBLite

M2A

M0

Crossbar-Lite Switch (AXBS)

S2

S0

S1

SIM

ADC

BME

PIT

I2C x2

GPIO

Flash

Controller

64 KByte

SRAM

LTC(AESA)

TRNG

SMC

RCM

PMC

CMP

TPM x3

LPTMR

RTC

LPUART x2

SPI x2

Flash

AIPS-Lite

256 KB

FlexNVM

256 KB

FlexRAM

8 KB

Radio

IPS

APB

VREF

VDCDC_IN

IPS

DCDC

CMT

FlexCAN

Figure 1. KW36 Detailed Block Diagram

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Feature Descriptions

Arm Cortex M0+ Core

32K Osc

32M Osc

IRC

MCG

DMA MUX

4ch DMA

Serial Wire Debug

DAP MDM

NVIC

WIC

4 MHz

DWT

MTB

IRC

32 kHz

FLL

IOPORT

Unified Bus

AHBLite

M2A

M0

Crossbar-Lite Switch (AXBS)

S2

S0

S1

SIM

ADC

BME

PIT

I2C x2

GPIO

Flash

Controller

64 KByte

SRAM

SMC

RCM

PMC

CMP

TPM x3

LPTMR

RTC

LPUART

SPI x2

LTC(AESA)

TRNG

Flash

AIPS-Lite

512 KB

Prg Acc RAM

8 KB

Radio

IPS

VREF

APB

VDCDC_IN

DCDC

CMT

IPS

Figure 2. KW35 Detailed Block Diagram

Arm Cortex M0+ Core

32K Osc

32M Osc

IRC

MCG

DMA MUX

4ch DMA

Serial Wire Debug

DAP MDM

NVIC

WIC

4 MHz

DWT

MTB

IRC

32 kHz

FLL

IOPORT

Unified Bus

AHBLite

M2A

M0

Crossbar-Lite Switch (AXBS)

S2

S0

S1

SIM

ADC

BME

PIT

I2C x2

GPIO

Flash

Controller

64 KByte

SRAM

SMC

RCM

PMC

CMP

TPM x3

LPTMR

RTC

LPUART

SPI x2

LTC(AESA)

TRNG

Flash

AIPS-Lite

256 KB

FlexNVM

256 KB

Radio

FlexRAM

8 KB

IPS

VREF

APB

VDCDC_IN

DCDC

CMT

IPS

Figure 3. KW34 Detailed Block Diagram

2.2 Radio features

Operating frequencies:

• 2.4 GHz ISM band (2400-2483.5 MHz)

• Medical Body Area Network (MBAN) 2360-2400 MHz

Supported standards:

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

Feature Descriptions

• Bluetooth Low Energy Version 5.0 compliant radio

• Generic FSK modulation supporting data rates up to 1 Mbps

• Support for up to 8 simultaneous Bluetooth LE hardware connections in any

master, slave combination

• Bluetooth LE Application Profiles

Receiver performance:

• Receive sensitivity of up to -95 dBm for Bluetooth LE

• Receive sensitivity of up to -99 dBm for a 250 kbps GFSK mode with a modulation

index of 0.5. Receive sensitivity in Generic FSK modes depends on mode selection

and data rate.

Other features:

• Programmable transmit output power from -30 dBm to +3.5 dBm

• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK modes

• Bluetooth Low Energy version 5.0 Link Layer hardware with 1 Mbps PHY support

• Hardware acceleration for Generic FSK packet processing

• Generic FSK modulation at 250, 500 and 1000 kbps

• Supports 8 simultaneous Bluetooth LE connections in any master/slave

combination

• Enhanced Bluetooth LE automatic deep sleep modes (DSM) supporting Slave

Latency

• Up to 26 devices supported by whitelist in hardware

• Up to 8 private resolvable addresses supported in hardware

• Supports DMA capture of IQ data with sampling rate of up to 2 MHz, when using a

32 MHz crystal

• Integrated on-chip balun

• Single ended bidirectional RF port shared by transmit and receive

• Low external component count

• Supports transceiver range extension using external PA and/or LNA

2.3 Microcontroller features

Arm Cortex-M0+ CPU

• Up to 48 MHz CPU

• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline

microarchitecture for reduced power consumption and improved architectural

performance (cycles per instruction)

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Feature Descriptions

• Supports up to 32 interrupt request sources

• Binary compatible instruction set architecture with the Cortex-M0 core

• Thumb instruction set combines high code density with 32-bit performance

• Serial Wire Debug (SWD) reduces the number of pins required for debugging

• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using

system RAM as the destination memory

Nested Vectored Interrupt Controller (NVIC)

• 32 vectored interrupts, 4 programmable priority levels

• Includes a single non-maskable interrupt

Wake-up Interrupt Controller (WIC)

• Supports interrupt handling when system clocking is disabled in low power

modes

• Takes over and emulates the NVIC behavior when correctly primed by the NVIC

on entry to very-deep-sleep

• A rudimentary interrupt masking system with no prioritization logic signals for

wake-up as soon as a non-masked interrupt is detected

Debug Controller

• Two-wire Serial Wire Debug (SWD) interface

• Hardware breakpoint unit for 2 code addresses

• Hardware watchpoint unit for 2 data items

• Micro Trace Buffer for program tracing

On-Chip Memory

• Up to 512 KB Flash

• KW36A/34A contains 256 KB program flash with ECC and 256 KB

FlexNVM.

• KW35A contains 512 KB program flash with ECC.

• Flash implemented as two equal blocks each of 256 KB block. Code can

execute or read from one block while the other block is being erased or

programmed on KW35A only.

• Firmware distribution protection. Program flash can be marked execute-only

on a per-sector (8 KB) basis to prevent firmware contents from being read by

third parties.

• 64 KB SRAM

• KW36A/34A contains 8 KB FlexRAM.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

Feature Descriptions

• KW35A contains 8 KB program acceleration RAM.

• Security circuitry to prevent unauthorized access to RAM and flash contents

through the debugger

2.4 System features

Power Management Control Unit (PMC)

• Programmable power saving modes

• Available wake-up from power saving modes via internal and external sources

• Integrated Power-on Reset (POR)

• Integrated Low Voltage Detect (LVD) with reset (brownout) capability

• Selectable LVD trip points

• Programmable Low Voltage Warning (LVW) interrupt capability

• Individual peripheral clocks can be gated off to reduce current consumption

• Internal Buffered bandgap reference voltage

• Factory programmed trim for bandgap and LVD

• 1 kHz Low Power Oscillator (LPO)

DC-DC Converters

• Internal switched mode power supply supporting Buck and Bypass operating

modes

• Buck operation supports external voltage sources of 2.1 V to 3.6 V

• When DC-DC is not used, the device supports an external voltage range of 1.5 V to

3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and

VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)

• An external inductor is required to support the Buck mode

Direct Memory Access (DMA) Controller

• All data movement via dual-address transfers: read from source, write to

destination

• Programmable source and destination addresses and transfer size

• Support for enhanced addressing modes

• 4-channel implementation that performs complex data transfers with minimal

intervention from a host processor

• Internal data buffer, used as temporary storage to support 16- and 32-byte transfers

• Connections to the crossbar switch for bus mastering the data movement

• Transfer control descriptor (TCD) organized to support two-deep, nested transfer

operations

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Feature Descriptions

• 32-byte TCD stored in local memory for each channel

• An inner data transfer loop defined by a minor byte transfer count

• An outer data transfer loop defined by a major iteration count

• Channel activation via one of three methods:

• Explicit software initiation

• Initiation via a channel-to-channel linking mechanism for continuous

transfers

• Peripheral-paced hardware requests, one per channel

• Fixed-priority and round-robin channel arbitration

• Channel completion reported via optional interrupt requests

• One interrupt per channel, optionally asserted at completion of major iteration

count

• Optional error terminations per channel and logically summed together to form

one error interrupt to the interrupt controller

• Optional support for scatter/gather DMA processing

• Support for complex data structures

DMA Channel Multiplexer (DMA MUX)

• 4 independently selectable DMA channel routers

• 2 periodic trigger sources available

• Each channel router can be assigned to 1 of the peripheral DMA sources

COP Watchdog Module

• Independent clock source input (independent from CPU/bus clock)

• Choice between two clock sources

• LPO oscillator

• Bus clock

System Clocks

• Both 26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE

and Generic FSK modes

• MCU can derive its clock either from the crystal reference oscillator or the

frequency locked loop (FLL)¹

• 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth Low

Energy timing in low power modes

• Multipurpose Clock Generator (MCG)

• Internal reference clocks — Can be used as a clock source for other on-chip

peripherals

1. Clock options can have restrictions based on the chosen SoC configuration.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Feature Descriptions

• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy

across full temperature range

• On-chip 4 MHz oscillator with 5% accuracy across full temperature range

• Frequency-locked loop (FLL) controlled by internal or external reference

• 20 MHz to 48 MHz FLL output

Unique Identifiers

• 80-bit Unique ID represents a unique identifier for each chip

• 40-bit unique Media Access Control (MAC) address, which can be used to build a

unique 48-bit Bluetooth Low Energy MAC address

2.5 Peripheral features

16-bit Analog-to-Digital Converter (ADC)

• Linear successive approximation algorithm with 16-bit resolution

• Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode

• Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode

• Single or continuous conversion

• Configurable sample time and conversion speed / power

• Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec

• Input clock selection

• Operation in low power modes for lower noise operation

• Asynchronous clock source for lower noise operation

• Selectable asynchronous hardware conversion trigger

• Automatic compare with interrupt for less-than, or greater than, or equal to

programmable value

• Temperature sensor

• Battery voltage measurement

• Hardware average function

• Selectable voltage reverence

• Self-calibration mode

High-Speed Analog Comparator (CMP)

• 6-bit DAC programmable reference generator output

• Up to eight selectable comparator inputs; each input can be compared with any

input by any polarity sequence

• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of

comparator output

• Two performance modes:

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Feature Descriptions

• Shorter propagation delay at the expense of higher power

• Low power, with longer propagation delay

• Operational in all MCU power modes except VLLS0 mode

Voltage Reference(VREF1)

• Programmable trim register with 0.5 mV steps, automatically loaded with factory

trimmed value upon reset

• Programmable buffer mode selection:

• Off

• Bandgap enabled/standby (output buffer disabled)

• High power buffer mode (output buffer enabled)

• 1.2 V output at room temperature

• VREF_OUT output signal

Low Power Timer (LPTMR)

• One channel

• Operation as timer or pulse counter

• Selectable clock for prescaler/glitch filter

• 1 kHz internal LPO

• External low power crystal oscillator

• Internal reference clock

• Configurable glitch filter or prescaler

• Interrupt generated on timer compare

• Hardware trigger generated on timer compare

• Functional in all power modes

Timer/PWM (TPM)

• TPM0: 4 channels, TPM1 and TPM2: 2 channels each

• Selectable source clock

• Programmable prescaler

• 16-bit counter supporting free-running or initial/final value, and counting is up or

up-down

• Input capture, output compare, and edge-aligned and center-aligned PWM modes

• Input capture and output compare modes

• Generation of hardware triggers

• TPM1 and TPM2: Quadrature decoder with input filters

• Global time base mode shares single time base across multiple TPM instances

Programmable Interrupt Timer (PIT)

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

Feature Descriptions

• Up to 2 interrupt timers for triggering ADC conversions

• 32-bit counter resolution

• Clocked by bus clock frequency

Real-Time Clock (RTC)

• 32-bit seconds counter with 32-bit alarm

• Can be invalidated on detection of tamper detect

• 16-bit prescaler with compensation

• Register write protection

• Hard Lock requires MCU POR to enable write access

• Soft lock requires POR or software reset to enable write/read access

• Capable of waking up the system from low power modes

Inter-Integrated Circuit (I²C)

• Two channels

• Compatible with I2C bus standard and SMBus Specification Version 2 features

• Up to 400 kHz operation

• Multi-master operation

• Software programmable for one of 64 different serial clock frequencies

• Programmable slave address and glitch input filter

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Bus busy detection broadcast and 10-bit address extension

• Address matching causes wake-up when processor is in low power mode

LPUART

• One channel (2 channels on KW36A)

• Full-duplex operation

• Standard mark/space non-return-to-zero (NRZ) format

• 13-bit baud rate selection with fractional divide of 32

• Programmable 8-bit or 9-bit data format

• Programmable 1 or 2 stop bits

• Separately enabled transmitter and receiver

• Programmable transmitter output polarity

• Programmable receive input polarity

• 13-bit break character option

• 11-bit break character detection option

• Two receiver wakeup methods:

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Feature Descriptions

• Idle line wakeup

• Address mark wakeup

• Address match feature in receiver to reduce address mark wakeup ISR overhead

• Interrupt or DMA driven operation

• Receiver framing error detection

• Hardware parity generation and checking

• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise

detection

• Operation in low power modes

• Hardware Flow Control RTS\CTS

• Functional in Stop/VLPS modes

• Break detect supporting LIN

Serial Peripheral Interface (SPI)

• Two independent SPI channels

• Master and slave mode

• Full-duplex, three-wire synchronous transfers

• Programmable transmit bit rate

• Double-buffered transmit and receive data registers

• Serial clock phase and polarity options

• Slave select output

• Control of SPI operation during wait mode

• Selectable MSB-first or LSB-first shifting

• Support for both transmit and receive by DMA

Carrier Modulator Timer (CMT)

• Four modes of operation

• Time; with independent control of high and low times

• Baseband

• Frequency shift key (FSK)

• Direct software control of CMT_IRO signal

• Extended space operation in time, baseband, and FSK modes

• Selectable input clock divider

• Interrupt on end of cycle

• Ability to disable CMT_IRO signal and use as timer interrupt

General Purpose Input/Output (GPIO)

• Hysteresis and configurable pull up device on all input pins

• Independent pin value register to read logic level on digital pin

• All GPIO pins can generate IRQ and wakeup events

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

15

NXP Semiconductors

Feature Descriptions

• Configurable drive strength on some output pins

• GPIO can be configured to function as a interrupt driven keyboard scanning matrix

• In the 48-pin package there are a total of 25 digital pins

• In the 40-pin package there are a total of 18 digital pins

FlexCAN (for KW36A only)

• Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol

specification and CAN protocol specification, Version 2.0 B

• Flexible Message Buffers (MBs); there are total 32 MBs of 8 bytes data length

each, configurable as Rx or Tx, all supporting standard and extended messages

• Programmable clock source to the CAN Protocol Interface, either peripheral clock

or oscillator clock

• Capability to select priority between mailboxes and Rx FIFO during matching

process

• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either

128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual

masking capability

2.6 Security Features

Advanced Encryption Standard Accelerator(AES-128 Accelerator)

The advanced encryption standard accelerator (AESA) module is a standalone hardware

coprocessor capable of accelerating the 128-bit advanced encryption standard (AES)

cryptographic algorithms.

The AESA engine supports the following cryptographic features.

LTC includes the following features:

• Cryptographic authentication

• Message authentication codes (MAC)

• Cipher-based MAC (AES-CMAC)

• Extended cipher block chaining message authentication code (AES-

XCBC-MAC)

• Auto padding

• Integrity Check Value(ICV) checking

• Authenticated encryption algorithms

• Counter with CBC-MAC (AES-CCM)

• Symmetric key block ciphers

16

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Transceiver Description

• AES (128-bit keys)

• Cipher modes:

• AES-128 modes

• Electronic codebook (ECB)

• Cipher block chaining (CBC)

• Counter (CTR)

• Secure scan

True Random Number Generator (TRNG)

True Random Number Generator (TRNG) is a hardware accelerator module that

constitutes a high-quality entropy source.

• TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-

consuming module, such as a deterministic random number generator.

• TRNG output can be read and used by a deterministic pseudo-random number

generator (PRNG) implemented in software.

• TRNG-PRNG combination achieves NIST compliant true randomness and

cryptographic-strength random numbers using the TRNG output as the entropy

source.

• A fully FIPS 180 compliant solution can be realized using the TRNG together

with a FIPS compliant deterministic random number generator and the SoC-level

security.

Flash Memory Protection

The on-chip flash memory controller enables the following useful features:

• Program flash protection scheme prevents accidental program or erase of stored

data.

• Automated, built-in, program and erase algorithms with verify.

• Read access to one program flash block is possible while programming or erasing

data in the other program flash block.

3 Transceiver Description

• Direct Conversion Receiver (Zero IF)

• Constant Envelope Transmitter

• 2.36 GHz to 2.483 GHz PLL Range

• Low Transmit and Receive Current Consumption

• Low BOM

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

17

NXP Semiconductors

Transceiver Description

3.1 Key Specifications

KW36A/35A/34A meets or exceeds all Bluetooth Low Energy version 5.0 performance

specifications. The key specification for the KW36A/35A/34A are:

Frequency Band:

• ISM Band: 2400 to 2483.5 MHz

• MBAN Band: 2360 to 2400 MHz

Bluetooth Low Energy version 5.0 modulation scheme:

• Symbol rate: 1000 kbps

• Modulation: GFSK

• Receiver sensitivity: -95 dBm, typical

• Programmable transmitter output power: -30 dBm to +3.5 dBm

Generic FSK modulation scheme:

• Symbol rate: 250, 500 and 1000 kbps

• Modulation(s): GFSK (modulation index = 0.32, 0.5, 0.7 and 1.0, BT =0.3, 0.5, and

0.7), FSK and MSK

• Receiver Sensitivity: Mode and data rate dependent. -99 dBm typical for GFSK

(r=250 kbps, BT = 0.5, h = 0.5)

3.2 Channel Map Frequency Plans

3.2.1 Channel Plan for Bluetooth Low Energy

This section describes the frequency plan / channels associated with 2.4GHz ISM and

MBAN bands for Bluetooth Low Energy.

2.4 GHz ISM Channel numbering:

• Fc=2402 + k * 2 MHz, k=0,.........,39.

MBAN Channel numbering:

• Fc=2360 + k in MHz, for k=0,.....,39

18

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Transceiver Description

where k is the channel number.

Table 1. 2.4 GHz ISM and MBAN frequency plan and channel designations

2.4 GHz ISM¹

MBAN²

2.4GHz ISM + MBAN

Channel

Freq (MHz)

2402

2404

2406

2408

2410

2412

2414

2416

2418

2420

2422

2424

2426

2428

2430

2432

2434

2436

2438

2440

2442

2444

2446

2448

2450

2452

2454

2456

2458

2460

2462

2464

2466

2468

2470

Channel

0

Freq (MHz)

2360

2361

2362

2363

2364

2365

2366

2367

2368

2369

2370

2371

2372

2373

2374

2375

2376

2377

2378

2379

2380

2381

2382

2383

2384

2385

2386

2387

2388

2389

2390

2391

2392

2393

2394

Freq (MHz)

2390

2391

2392

2393

2394

2395

2396

2397

2398

2402

2404

2406

2408

2410

2412

2414

2416

2418

2420

2422

2424

2426

2428

2430

2432

2434

2436

2438

2440

2442

2444

2446

2448

2450

2452

0

28

29

30

31

32

33

34

35

36

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Table continues on the next page...

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NXP Semiconductors

Transceiver Electrical Characteristics

Table 1. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)

2.4 GHz ISM¹

MBAN²

2.4GHz ISM + MBAN

Channel

Freq (MHz)

2472

Channel

Freq (MHz)

2395

Channel

Freq (MHz)

2454

35

36

37

38

39

35

36

37

38

39

26

27

37

38

39

2474

2396

2456

2476

2397

2476

2478

2398

2478

2480

2399

2480

1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz

2. Per FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.

3.2.2 Other Channel Plans

The RF synthesizer can be configured to use any channel frequency between 2.36 and

2.487 GHz.

3.3 Transceiver Functions

Receive

The receiver architecture is Zero IF (ZIF) where the received signal after passing

through RF front end is down-converted to a baseband signal. The signal is filtered and

amplified before it is fed to analog-to-digital converter. The digital signal is then

decimated to a baseband clock frequency before it is digitally processed, demodulated

and passed on to packet processing/link-layer processing.

Transmit

The transmitter transmits GFSK/FSK modulation having power and channel selection

adjustment per user application. After the channel of operation is determined, coarse

and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal

lock is established, the modulated buffered signal is then routed to a multi-stage

amplifier for transmission.

4 Transceiver Electrical Characteristics

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Transceiver Electrical Characteristics

4.1 Radio operating conditions

Table 2. Radio operating conditions

Characteristic

Symbol

f_in

Min

2.360

-40

Typ

—

Max

2.480

105

Unit

GHz

°C

Input Frequency

Ambient Temperature Range

Maximum RF Input Power

T_A

25

—

P_max

f_ref

—

10

dBm

Crystal Reference Oscillator Frequency

26 MHz or 32 MHz

1

1. The recommended crystal accuracy is 40 ppm including initial accuracy, mechanical, temperature and aging factors.

4.2 Receiver Feature Summary

Table 3. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise

noted)

Characteristic¹

Symbol

I_pdn

Min.

—

Typ.

200

6.3

Max.

1000

—

Unit

nA

Supply current power down on VDD_RFx supplies

Supply current Rx On with DC-DC converter enable

(Buck; V_{DCDC_IN}= 3.6 V) ^{, 2}

I_Rxon

—

mA

Supply current Rx On with DC-DC converter disabled

(Bypass) ²

I_Rxon

—

17.2

—

mA

Input RF Frequency

f_in

2.360

—

2.4835

—

GHz

dBm

dB

GFSK Rx Sensitivity(250 kbps GFSK-BT=0.5, h=0.5)

Bluetooth LE Rx Sensitivity ³

SENS_GFSK

SENS_BLE

NF_HG

-99

-95

7.5

—

Noise Figure for maximum gain mode @ typical

sensitivity

—

Receiver Signal Strength Indicator Range⁴

Receiver Signal Strength Indicator Resolution

Typical RSSI variation over frequency

Typical RSSI variation over temperature

Narrowband RSSI accuracy⁶

RSSI_Range

RSSI_Res

-100

—

1

5⁵

—

2

dBm

dB

-2

—

-7

dB

-2

2

dB

RSSI_Acc

-3

3

dB

Bluetooth LE Co-channel Interference (Wanted signal at

-67 dBm , BER <0.1%. Measurement resolution 1

MHz).

dB

Adjacent/Alternate Channel Performance⁷

Bluetooth LE Adjacent +/- 1 MHz Interference offset

(Wanted signal at -67 dBm , BER <0.1%. Measurement

resolution 1 MHz.)

SEL_{BLE, 1 MHz}

—

2

—

dB

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

21

NXP Semiconductors

Transceiver Electrical Characteristics

Table 3. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise

noted) (continued)

Characteristic¹

Symbol

Min.

Typ.

Max.

Unit

Bluetooth LE Adjacent +/- 2 MHz Interference offset

(Wanted signal at -67 dBm , BER <0.1%. Measurement

resolution 1 MHz.)

SEL_{BLE, 2 MHz}

—

43

—

dB

Bluetooth LE Alternate +/-3 MHz Interference offset

(Wanted signal at -67 dBm, BER <0.1%. Measurement

resolution 1 MHz.)

SEL_{BLE, 3 MHz}

—

50

—

dB

Bluetooth LE Alternate ≥ +/-4 MHz Interference offset

(Wanted signal at -67 dBm, BER <0.1%. Measurement

resolution 1 MHz.)

SEL_{BLE, 4+ MHz}

Intermodulation Performance

Bluetooth LE Intermodulation with continuous wave

interferer at 3 MHz and modulated interferer is at

MHz (Wanted signal at -67 dBm , BER<0.1%.)

—

-23

-24

—

dBm

6

Bluetooth LE Intermodulation with continuous wave

interferer at 5 MHz and modulated interferer is at 10

MHz (Wanted signal at -67 dBm , BER<0.1%.)

Blocking Performance

Bluetooth LE Out of band blocking from 30 MHz to 1000

MHz and 4000 MHz to 5000 MHz (Wanted signal at -67

dBm , BER<0.1%. Interferer continuous wave signal.)⁸

—

-2

—

dBm

Bluetooth LE Out of band blocking from 1000 MHz to

2000 MHz and 3000 MHz to 4000 MHz (Wanted signal

at -67 dBm , BER<0.1%. Interferer continuous wave

signal.)

-8.4

Bluetooth LE Out of band blocking from 2001 MHz to

2339 MHz and 2484 MHz to 2999 MHz (Wanted signal

at -67 dBm , BER<0.1%. Interferer continuous wave

signal.)⁹

—

-17

—

dBm

Bluetooth LE Out of band blocking from 5000 MHz to

12750 MHz (Wanted signal at -67 dBm , BER<0.1%.

Interferer continuous wave signal.)⁹

—

10

—

dBm

dBc

Spurious Emission < 1.6 MHz offset (Measured with

100 kHz resolution and average detector. Device

transmit on RF channel with center frequency fc and

spurious power measured in 1 MHz at RF frequency f),

where |f-fc|< 1.6 MHz

-54

Spurious Emission > 2.5 MHz offset (Measured with

100 kHz resolution and average detector. Device

transmit on RF channel with center frequency fc and

spurious power measured in 1 MHz at RF frequency f),

where |f-fc|> 2.5 MHz¹⁰

—

-70

—

dBc

1. All the RX parameters are measured at the KW36A/35A/34A RF pins.

2. Transceiver power consumption.

3. Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.

4. Narrow-band RSSI mode.

5. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.

6. With one point calibration over frequency and temperature.

22

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Transceiver Electrical Characteristics

7. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.

8. Exceptions allowed for carrier frequency sub harmonics.

9. Exceptions allowed for carrier frequency harmonics.

10. Exceptions allowed for twice the reference clock frequency(fref) multiples.

Table 4. Receiver Specifications with Generic FSK Modulations

Adjacent/Alternate Channel Selectivity (dB)¹

Modulation

Type

Data

Rate

(kbps)

Channel

BW (kHz) Sensitivity signal

Typical

Desired Interferer Interferer Interferer Interferer

Co-

channel

at -/+1*

channel

BW

at -/+ 2*

channel

BW

at -/+ 3*

channel

BW

at -/+ 4*

channel

BW

(dBm)

level

(dBm)

offset

GFSK BT =

0.5, h=0.5

1000

500

2000

1000

500

-95

-97

-99

-89

-92

-93

-97

-98

-99

-91

-93

-95

-96

-97

-99

-96

-97

-99

-96

-97

-98

-67

-85

-67

-85

43

40

30

10

22

20

45

40

30

40

35

30

44

40

30

43

35

45

40

35

50

40

38

31

25

50

40

46

40

53

50

40

53

50

45

55

45

55

50

42

37

30

57

55

50

53

50

40

57

55

50

60

55

50

45

50

55

50

47

42

34

60

55

50

55

53

50

60

55

50

63

60

55

59

50

-7

250

-7

GFSK, BT =

0.5, h=0.3

1000

500

1000

800

-10

-13

-7

250

500

GFSK, BT =

0.5, h=0.7

1000

500

2000

1000

600

-7

250

-7

GMSK

BT=0.3

1000

500

1600

800

-8

-7

250

500

-7

GMSK, BT = 1000

2000

1000

600

-7

0.7

500

-7

250

-7

Generic

MSK

1000

500

3000

1600

800

-7

-8

250

-7

GFSK

BT=0.5, h=1

1000

500

3000

1400

800

-8

250

-8

1. Selectivity measured with an unmodulated blocker except for GFSK BT=0.5, h=0.5 1mbps and GFSK BT=0.5, h=0.32

1mbps. The desired signal is set at -85 dBm.

4.3 Transmit and PLL Feature Summary

• Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN

frequency bands

• Fast PLL Lock time: < 25 µs

• Reference Frequency:

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

23

NXP Semiconductors

Transceiver Electrical Characteristics

• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK

modes

Table 5. Top level Transmitter Specifications (TA=25°C, nominal process unless otherwise

noted)

Characteristic¹

Symbol

I_pdn

Min.

—

Typ.

200

5.7

Max.

—

Unit

nA

Supply current power down on VDD_RFx supplies

Supply current Tx On with P_RF= 0dBm and DC-DC

converter enabled (Buck; VDD_{DCDC_in}= 3.6 V) ^{, 2}

I_Txone

—

mA

Supply current Tx On with P_RF= 0 dBm and DC-DC

converter disabled (Bypass) ²

I_Txond

—

16

—

mA

Output Frequency

f_in

2.360

—

+3.5

-30

34

2.4835

—

GHz

dBm

dB

Maximum RF Output power ³

Minimum RF Output power ³

RF Output power control range

Bluetooth LE TX Output Spectrum 20dB BW

P_RF,max

P_RF,min

—

P_RFCR

—

TXBW_BLE

Δf1_avg,BLE

1.0

—

MHz

kHz

Bluetooth LE average frequency deviation using a

00001111 modulation sequence

250

220

Bluetooth LE average frequency deviation using a

01010101 modulation sequence

Δf2_avg,BLE

kHz

Bluetooth LE RMS FSK Error

FSK_{err BLE}

,

3%

3

Bluetooth LE Maximum Deviation of the Center

Frequency⁴

F_cdev,BLE

—

kHz

dBm

Bluetooth LE Adjacent Channel Transmit Power at 2

MHz offset⁵

P_RF2MHz,BLE

P_RF3MHz,BLE

—

-55

-59

Bluetooth LE Adjacent Channel Transmit Power at >= 3

MHz offset⁵

Bluetooth LE Frequency Hopping Support

YES

-46

2^ndHarmonic of Transmit Carrier Frequency (P_out

=

TXH2

TXH3

—

dBm/MHz

, 6

P_RF,max

)

3^rdHarmonic of Transmit Carrier Frequency (P_out

=

-58

6

P_RF,max

)

1. All the TX parameters are measured at test hardware SMA connector.

2. Transceiver power consumption.

3. Measured at the KW36A/35A/34A RF pins.

4. Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.

5. Measured at P_out= 5dBm and recommended TX match.

6. Harmonic levels based on recommended 2 component match. Transmit harmonic levels depend on the quality of

matching components. Additional harmonic margin using a 3^rdmatching component (1x shunt capacitor) is possible.

Transmit PA driver output as a function of the PA_POWER[5:0] field when measured

at the IC pins is as follows:

24

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NXP Semiconductors

Transceiver Electrical Characteristics

Figure 4. TX Pout (dBm) as function TX-PA Power Code at RF pins

Table 6. Transmit Output Power as a function of PA_POWER[5:0]

TX Pout (dBm)¹

PA_POWER[5:0]

T = -40 °C

-30.1

-24.0

-17.9

-14.5

-12.0

-10.1

-8.5

T = 25 °C

-31.1

-25.0

-19.0

-15.6

-13.1

-11.2

-9.6

T = 105 °C

-32.6

-26.4

-20.4

-17.0

-14.5

-12.6

-11.0

-9.7

1

2

4

6

8

10

12

14

-7.2

-8.3

Table continues on the next page...

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NXP Semiconductors

System and Power Management

Table 6. Transmit Output Power as a function of PA_POWER[5:0] (continued)

TX Pout (dBm)¹

PA_POWER[5:0]

T = -40 °C

-6.1

-5.1

-4.2

-3.4

-2.7

-2.0

-1.4

-0.8

-0.3

0.2

T = 25 °C

-7.2

-6.2

-5.3

-4.5

-3.8

-3.1

-2.5

-1.9

-1.4

-1.0

-0.5

-0.1

0.3

T = 105 °C

-8.6

-7.6

-6.7

-5.9

-5.2

-4.5

-3.9

-3.3

-2.8

-2.4

-1.9

-1.5

-1.1

-0.7

-0.3

0.0

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

0.6

1.1

1.5

1.9

0.7

2.2

1.1

2.6

1.4

2.9

1.8

0.3

3.2

2.1

0.6

3.5

2.4

0.9

3.7

2.6

1.2

3.9

2.9

1.5

4.2

3.1

1.7

4.4

3.3

1.9

4.5

3.5

2.1

1. TX continuous wave power output at the RF pins with the recommended matching components mounted on PCB.

5 System and Power Management

5.1 Power Management

The KW36A/35A/34A includes internal power management features that can be used to

control the power usage. The power management of the KW36A/35A/34A includes

power management controller (PMC) and a DC-DC converter which can operate in a

buck or bypass configuration. The PMC is designed such that the RF radio will remain

26

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

System and Power Management

in state-retention while the core is in various stop modes. It can make sure the device

can stay in low current consumption mode while the RF radio can wakeup quick

enough for communication.

5.1.1 DC-DC Converter

The features of the DC-DC converter include the following:

• Single inductor, multiple outputs.

• Buck mode (pin selectable; CFG=VDCDC_IN).

• Continuous or pulsed operation (hardware/software configurable).

• Power switch input to allow external control of power up, and to select DCDC

bypass mode in which all the SoC power supplies (see Table 3) are externally

provided.

• Output signal to indicate power stable. Purpose is for the rest of the chip to be

used as a POR.

• Scaled battery output voltage suitable for SAR ADC utilization.

• Internal oscillator for support when the reference oscillator is not present.

5.2 Modes of Operation

The Arm Cortex-M0+ core in the KW36A/35A/34A has three primary modes of

operation: Run, Wait, and Stop modes. For each run mode, there is a corresponding

wait and stop mode. Wait modes are similar to Arm sleep modes. Stop modes are

similar to Arm deep sleep modes. The very low power run (VLPR) operation mode

can drastically reduce runtime power when the maximum bus frequency is not

required to handle the application needs.

The WFI instruction invokes both wait and stop modes. The primary modes are

augmented in a number of ways to provide lower power based on application needs.

5.2.1 Power modes

The power management controller (PMC) provides multiple power options to allow

the user to optimize power consumption for the level of functionality needed.

Depending on the stop requirements of the user application, a variety of stop modes

are available that provide state retention, partial power down or full power down of

certain logic and/or memory. I/O states are held in all modes of operation. The

following table compares the various power modes available.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

System and Power Management

For each run mode there is a corresponding wait and stop mode. Wait modes are similar

to Arm sleep modes. Stop modes (VLPS, STOP) are similar to Arm sleep deep mode.

The very low power run (VLPR) operating mode can drastically reduce runtime power

when the maximum bus frequency is not required to handle the application needs.

The three primary modes of operation are run, wait and stop. The WFI instruction

invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System

Control Register. The primary modes are augmented in a number of ways to provide

lower power based on application needs.

Table 7. Power modes (At 25 deg C)

Power mode

Description

CPU

Radio

recovery

method

Normal Run (all

Allows maximum performance of chip.

—

Radio can be active

peripherals clock off)

Normal Wait - via WFI Allows peripherals to function, while allowing CPU to

go to sleep reducing power.

Interrupt

Normal Stop - via

WFI

Places chip in static state. Lowest power mode that

retains all registers while maintaining LVD protection.

PStop2 (Partial Stop Core and system clocks are gated. Bus clock

2)

remains active. Masters and slaves clocked by bus

clock remain in Run or VLPRun mode. The clock

generators in MCG and the on-chip regulator in the

PMC also remain in Run or VLPRun mode.

PStop1 (Partial Stop Core, system clocks and bus clock are gated. All bus

Interrupt

—

1)

masters and slaves enter Stop mode. The clock

generators in MCG and the on-chip regulator in the

PMC also remain in Run or VLPRun mode.

VLPR (Very Low

Power Run) (all

peripherals off)

Reduced frequency (1 MHz) Flash access mode,

regulator in low power mode, LVD off. Internal

oscillator can provide low power 4 MHz source for

core. (Values @2 MHz core/ 1 MHz bus and flash,

module off, execution from flash).

Radio operation is possible

only when DC-DC is

configured for continuous

mode.¹However, there may

be insufficient MIPS with a 4

MHz MCU to support much in

the way of radio operation.

Biasing is disabled when DC-DC is configured for

continuous mode in VLPR/W

VLPW (Very Low

Similar to VLPR, with CPU in sleep to further reduce

Interrupt

Power Wait) - via WFI power. (Values @4 MHz core/ 1 MHz bus, module

(all peripherals off)

off)

Biasing is disabled when DC-DC is configured for

continuous mode in VLPR/W

VLPS (Very Low

Places MCU in static state with LVD operation off.

Power Stop) via WFI Lowest power mode with ADC and all pin interrupts

functional. LPTMR, RTC, CMP can be operational.

Biasing is disabled when DC-DC is configured for

continuous mode in VLPS.

Table continues on the next page...

28

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 7. Power modes (At 25 deg C) (continued)

Power mode

Description

CPU

Radio

recovery

method

LLS3 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,

Wakeup

Interrupt

Radio SOG is in state

retention in LLSx. The

Bluetooth LE/Generic FSK

DSM²logic can be active

using the 32 kHz clock

Stop)

CMP can be operational. All of the radio Sea of

Gates(SOG) logic is in state retention.

LLS2 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,

Wakeup

Interrupt

Stop)

CMP can be operational. 16 KB or 32 KB of

programmable RAM can be powered on. All of the

radio SOG logic is in state retention.

VLLS3 (Very Low

Leakage Stop3)

Full SRAM retention. LLWU, LPTMR, RTC, CMP can

be operational. All of the radio SOG logic is in state

retention.

Wakeup

Reset

Radio SOG is in state

retention in VLLS3/2. The

Bluetooth LE/Generic FSK

DSM logic can be active

using the 32 kHz clock.

VLLS2 (Very Low

Leakage Stop2)

Partial SRAM retention. 16 KB or 32 KB of

programmable RAM can be powered on. LLWU,

LPTMR, RTC, CMP can be operational. All of the

radio SOG logic is in state retention.

Wakeup

Reset

VLLS1 (Very Low

Leakage Stop1) with file remains powered for customer-critical data.

RTC + 32 kHz OSC

All SRAM powered off. The 32-byte system register

Wakeup

Reset

Radio operation not

supported. The Radio SOG is

power-gated in VLLS1. Radio

state is lost at VLLS1 and

lower power states.

LLWU, LPTMR, RTC, CMP can be operational.

Radio logic is power gated.

VLLS1 (Very Low

Leakage Stop1) with file remains powered for customer-critical data.

All SRAM powered off. The 32-byte system register

Wakeup

Reset

LPTMR + LPO

LLWU, LPTMR, RTC, CMP can be operational.

VLLS0 (Very Low

Leakage Stop0) with

Brown-out Detection

VLLS0 is not supported with DC-DC

Wakeup

Reset

Radio operation not

supported. The Radio digital

is power-gated in VLLS0.

The 32-byte system register file remains powered for

customer-critical data. Disable all analog modules in

PMC and retains I/O state and DGO state. LPO

disabled, POR brown-out detection enabled, Pin

interrupt only. Radio logic is power gated.

VLLS0 (Very Low

Leakage Stop0)

without Brown-out

Detection

VLLS0 is not supported with DC-DC buck

configuration but is supported with bypass

configuration

Wakeup

Reset

The 32-byte system register file remains powered for

customer-critical data. Disable all analog modules in

PMC and retains I/O state and DGO state. LPO

disabled, POR brown-out detection disabled, Pin

interrupt only. Radio logic is power gated.

1. Biasing is disabled, but the Flash is in a low power mode for VLPx, so this configuration can realize some power

savings over use of Run/Wait/Stop.

2. DSM refers to Radio's deep sleep mode. DSM does not refer to the Arm sleep deep mode.

6 KW36A/35A/34A Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

29

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

6.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 5. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assume that the

output pins have the following characteristics.

• C_L=30 pF loads

• Slew rate disabled

• Normal drive strength

6.2 Nonswitching electrical specifications

6.2.1 Voltage and current operating requirements

Table 8. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.71

–0.1

Max.

3.6

Unit

V

Notes

Supply voltage

V_DDA

Analog supply voltage

3.6

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

0.1

V

0.1

V

V_IH

Input high voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

—

0.35 × V_DD

V

Table continues on the next page...

30

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

Table 8. Voltage and current operating requirements (continued)

Symbol

Description

• 2.7 V ≤ V_DD≤ 3.6 V

Min.

Max.

Unit

Notes

—

0.3 × V_DD

V

• 1.7 V ≤ V_DD≤ 2.7 V

V_HYS

I_ICIO

Input hysteresis

0.06 × V_DD

-3

—

V

IO pin negative DC injection current — single pin

• V_IN< V_SS-0.3V

1

mA

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16

contiguous pins

-25

—

mA

• Negative current injection

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V

2

V_DDvoltage required to retain RAM

1. All I/O pins are internally clamped to V_SSthrough an ESD protection diode. There is no diode connection to V_DD. If V_IN

greater than V_{IO_MIN}(= V_SS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If

this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting

resistor is calculated as R = (V_{IO_MIN}- V_IN)/|I_ICIO|.

2. Open drain outputs must be pulled to V_DD

.

6.2.2 LVD and POR operating requirements

Table 9. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling V_DDPOR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV = 01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV = 00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

—

2.70

2.80

2.90

3.00

60

2.78

2.88

2.98

3.08

—

V

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

V

• Level 4 falling (LVWV = 11)

V

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

mV

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

V

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV = 00)

1

V_LVW1L

V_LVW2L

V_LVW3L

1.74

1.84

1.94

1.80

1.90

2.00

1.86

1.96

2.06

V

• Level 2 falling (LVWV = 01)

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

31

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 9. V_DDsupply LVD and POR operating requirements (continued)

Symbol Description

V_LVW4L• Level 3 falling (LVWV = 10)

Min.

Typ.

Max.

Unit

Notes

2.04

2.10

2.16

V

• Level 4 falling (LVWV = 11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

40

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising thresholds are falling threshold + hysteresis voltage

6.2.3 Voltage and current operating behaviors

Table 10. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — Normal drive pad (except

RESET_b)

1, 2

V_DD– 0.5

—

V

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -2.5 mA

V_OH

Output high voltage — High drive pad (except

RESET_b)

1, 2

V_DD– 0.5

—

V

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -10 mA

I_OHT

V_OL

Output high current total for all ports

Output low voltage — Normal drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 2.5 mA

—

100

mA

1

—

0.5

V

V_OL

Output low voltage — High drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 10 mA

—

0.5

V

I_OLT

I_IN

Output low current total for all ports

—

100

500

mA

nA

Input leakage current (per pin) for full temperature

range

3

I_IN

Input leakage current (per pin) at 25 °C

—

0.025

5

μA

3

Input leakage current (total all pins) for full

temperature range

R_PU

Internal pullup resistors

20

50

kΩ

4

32

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

1. PTB0-1 and PTC0-3, PTC6, PTC7, PTC17, PTC18 I/O have both high drive and normal drive capability selected by

the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. The reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When

configured as a GPIO output, it acts as a pseudo open drain output.

3. Measured at V_DD= 3.6 V.

4. Measured at V_DDsupply voltage = V_DDmin and V_input= V_SS

.

6.2.4 Power mode transition operating behaviors

All specifications except t_PORand VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 48 MHz

• Bus and flash clock = 24 MHz

• FEI clock mode

POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system

frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 11. Power mode transition operating behaviors

Symbol

Description

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point V_DD

reaches 1.8 V to execution of the first instruction across the

operating temperature range of the chip.

300

μs

1

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS2 → RUN

• VLLS3 → RUN

• LLS → RUN

169.0

168.9

97.3

6.3

μs

• VLPS → RUN

• STOP → RUN

6.2

1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the

300µs spec when 1) VDD_1P5 < 1.6V at 25°C and 125°C. 2) 1.5V ≤ VDD_1P5 ≤ 1.8V. For the bypass mode special

case where VDD_1P5 = VDD_1P8, TPOR did not meet the 300µs maximum spec when the supply slew rate

<=100V/s.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

33

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

6.2.5 Power consumption operating behaviors

Table 12. Power consumption operating behaviors - Bypass Mode

Symbol

Description

Typ.

Max.

Unit

Notes

1

I_DDA

Analog supply current

—

See note

mA

I_{DD_RUNCO_C}Run mode current in compute operation - 48 MHz

2, 3

core / 24 MHz flash / bus disabled, LPTMR running

M

using LPO clock at 1kHz, CoreMark benchmark code

executing from flash at 3.0 V

6.80

4.05

8.41

4.98

mA

I_{DD_RUNCO}Run mode current in compute operation - 48 MHz

core / 24 MHz flash / bus clock disabled, code of

while(1) loop executing from flash at 3.0 V

3, 4

I_{DD_RUN}

Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks disabled, code of while(1)

loop executing from flash at 3.0 V

5.00

6.01

mA

I_{DD_RUN}

Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks enabled, code of while(1)

loop executing from flash at 3.0 V

3, 4, 5

6.48

6.77

7.13

6.70

6.96

7.90

mA

at 25 °C

at 70 °C

at 105 °C

I_{DD_WAIT}Wait mode current - core disabled / 48 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

4

3.07

2.29

4.31

3.15

mA

I_{DD_WAIT}Wait mode current - core disabled / 24 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

I_{DD_PSTOP2}Stop mode current with partial stop 2 clocking option

- core and system disabled / 10.5 MHz bus at 3.0 V

4

6

2.32

3.11

mA

μA

I_{DD_VLPRCO_}Very-low-power run mode current in compute

766.9

1538

operation - 4 MHz core / 0.8 MHz flash / bus clock

CM

disabled, LPTMR running using LPO clock at 1 kHz

reference clock, CoreMark benchmark code

executing from flash at 3.0 V

I_{DD_VLPRCO}Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus clock

disabled, code of while(1) loop executing from flash

at 3.0 V

7

158.45

377

410

μA

I_{DD_VLPR}Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks disabled,

7

5, 7

7

185.26

240.96

code of while(1) loop executing from flash at 3.0 V

I_{DD_VLPR}Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks enabled,

805.3

552.8

μA

code of while(1) loop executing from flash at 3.0 V

I_{DD_VLPW}Very-low-power wait mode current - core disabled / 4 133.95

MHz system / 0.8 MHz bus / flash disabled (flash

doze enabled), all peripheral clocks disabled at 3.0 V

Table continues on the next page...

34

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 12. Power consumption operating behaviors - Bypass Mode (continued)

Symbol

Description

Typ.

Max.

Unit

Notes

I_{DD_STOP}Stop mode current at 3.0 V

at 25 °C

at 70 °C

at 105 °C

204.98

291.89

599.46

308.3

872.5

1662

μA

I_{DD_VLPS}Very-low-power stop mode current at Bypass

mode(3.0 V),

6.4

30.64

157

18

μA

at 25 °C

at 70 °C

at 105 °C

76.6

328

I_{DD_LLS3}

Low-leakage stop mode 3 current at Bypass

mode(3.0 V),

2.57

11.76

50.92

4.31

26.07

105.4

μA

at 25 °C

at 70 °C

at 105 °C

I_{DD_LLS2}

Low-leakage stop mode 2 current at Bypass

mode(3.0 V),

2.35

9.74

3.30

21.40

80.23

μA

at 25 °C

at 70 °C

at 105 °C

42.34

I_{DD_VLLS3}Very-low-leakage stop mode 3 current at Bypass

mode(3.0 V),

2.13

10.78

46.70

3.3

μA

at 25 °C

at 70 °C

at 105 °C

22.97

83.54

I_{DD_VLLS2}Very-low-leakage stop mode 2 current at Bypass

mode(3.0 V),

1.84

7.88

2.40

15.19

57.85

μA

at 25 °C

at 70 °C

at 105 °C

34.76

I_{DD_VLLS1}Very-low-leakage stop mode 1 current at Bypass

mode(3.0 V),

851.45

3.57

1027.8

6.28

nA

μA

at 25°C

at 70°C

at 105°C

17.62

23.06

I_{DD_VLLS0}Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 0) at 3.0 V

433.00

3.15

720.3

6.14

23.2

nA

μA

at 25 °C

at 70 °C

at 105 °C

17.2

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

35

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 12. Power consumption operating behaviors - Bypass Mode (continued)

Symbol

Description

Typ.

Max.

Unit

Notes

I_{DD_VLLS0}Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 1) at 3.0 V

8

258.12

2.97

516.43

5.81

nA

μA

at 25 °C

at 70 °C

at 105 °C

16.9

22.4

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. MCG configured for FEI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for

balanced.

3. Radio is off.

4. MCG configured for FEI mode.

5. Incremental current consumption from peripheral activity is not included.

6. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized

for balanced.

7. MCG configured for BLPI mode.

8. No brownout.

Table 13. Power consumption operating behaviors - Buck Mode1

Symbol

Description

Typ.

Max.

Unit

Notes

2

I_DDA

Analog supply current

—

See note

mA

I_{DD_RUNCO}Run mode current in compute operation - 48 MHz

core / 24 MHz flash / bus clock disabled, code of

while(1) loop executing from flash at 3.0 V

3, 4

3.51

4.00

—

mA

I_{DD_RUN}

Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks disabled, code of while(1)

loop executing from flash at 3.0 V

3, 4

I_{DD_RUN}

Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks enabled, code of while(1)

loop executing from flash at 3.0 V

3, 4, 5

5.81

5.92

6.36

—

mA

at 25 °C

at 70 °C

at 105 °C

I_{DD_WAIT}Wait mode current - core disabled / 48 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

3

2.97

2.51

—

mA

I_{DD_WAIT}Wait mode current - core disabled / 24 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

I_{DD_PSTOP2}Stop mode current with partial stop 2 clocking option

- core and system disabled / 10.5 MHz bus at 3.0 V

3

6

2.33

—

mA

μA

I_{DD_VLPRCO}Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus clock

disabled, code of while(1) loop executing from flash

at 3.0 V

101.75

Table continues on the next page...

36

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 13. Power consumption operating behaviors - Buck Mode1 (continued)

Symbol

Description

Typ.

Max.

Unit

Notes

I_{DD_VLPR}Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks disabled,

6

132.17

—

μA

code of while(1) loop executing from flash at 3.0 V

I_{DD_VLPR}Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks enabled,

5, 6

6

167.65

—

μA

code of while(1) loop executing from flash at 3.0 V

I_{DD_VLPW}Very-low-power wait mode current - core disabled / 4 105.72

MHz system / 0.8 MHz bus / flash disabled (flash

doze enabled), all peripheral clocks disabled at 3.0 V

I_{DD_STOP}Stop mode current at 3.0 V

at 25 °C

at 70 °C

at 105 °C

1.43

1.56

1.99

2.32

4.35

4.68

mA

I_{DD_VLPS}Very-low-power stop mode current at Buck mode(3.0

V),

7

4.18

44.30

218.64

14.98

110

μA

at 25 °C

at 70 °C

at 105 °C

446

I_{DD_LLS3}

Low-leakage stop mode 3 current at Buck mode(3.0

V),

2.64

15.27

81.93

4.89

25.51

104.35

μA

at 25 °C

at 70 °C

at 105 °C

I_{DD_LLS2}

Low-leakage stop mode 2 current at Buck mode(3.0

V),

2.46

10.14

63.49

3.80

21.14

80.21

μA

at 25 °C

at 70 °C

at 105 °C

I_{DD_VLLS3}Very-low-leakage stop mode 3 current at Buck

mode(3.0 V),

2.03

12.44

62.23

3.28

23.8

83.9

μA

at 25 °C

at 70 °C

at 105 °C

I_{DD_VLLS2}Very-low-leakage stop mode 2 current at Buck

mode(3.0 V),

1.79

8.87

2.43

16.7

μA

at 25 °C

at 70 °C

at 105 °C

49.39

62.94

I_{DD_VLLS1}Very-low-leakage stop mode 1 current at Buck

mode(3.0 V),

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

37

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 13. Power consumption operating behaviors - Buck Mode1

Symbol

Description

Typ.

Max.

Unit

Notes

at 25 °C

0.830

1.07

μA

at 70 °C

4.95

10.67

36.14

μA

at 105 °C

27.51

1. The device was configured in buck mode auto-start to perform the measurements. The DCDC_IN was powered with 3.0

V. VDD_1P8OUT was configured to output 1.8 V and VDD_1P5OUT_PMCIN was configured to output 1.5 V.

2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

3. MCG configured for FEI mode.

4. Radio is off.

5. Incremental current consumption from peripheral activity is not included.

6. MCG configured for BLPI mode.

7. DCDC configured in pulsed mode.

Table 14. Low power mode peripheral adders — typical value (Bypass Mode)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

I_IREFSTEN4MHz

4 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 4 MHz IRC enabled.

46

47

µA

I_{IREFSTEN32KHz}

32 kHz internal reference clock (IRC)

adder. Measured by entering STOP mode

with the 32 kHz IRC enabled.

88

91

90

89

88

µA

I_{EREFSTEN32KHz}

External 32 kHz crystal clock adder by

means of the RTC bits. Measured by

entering all modes with the crystal

enabled.

1.4

1.6

2.7

1.8

2.6

22

1.3

1.5

1.9

1.4

1.7

19

1.6

1.9

2.9

1.7

2.8

20

2.4

4.2

7.7

4.1

7.6

21

4.1

7.7

15

VLLS1

VLLS2

VLLS3

LLS2

μA

8

15.2

21

LLS3

I_CMP

CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and a

single external input for compare. Includes

6-bit DAC power consumption.

µA

I_RTC

RTC peripheral adder measured by placing

the device in VLLS1 mode with external 32

kHz crystal enabled by means of the

1.4

1.3

1.6

2.4

4.3

RTC_CR[OSCE] bit and the RTC ALARM

set for 1 minute. Includes ERCLK32K (32

kHz external crystal) power consumption.

I_LPUART

LPUART peripheral adder measured by

placing the device in STOP or VLPS mode

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 14. Low power mode peripheral adders — typical value (Bypass Mode) (continued)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

with selected clock source waiting for RX

data at 115200 baud rate. Includes

selected clock source power consumption.

53

54

µA

MCGIRCLK (4 MHz internal reference

clock)

I_LPTMR

LPTMR peripheral adder measured by

placing the device in VLLS1 mode with

LPTMR enabled using LPO.

30

85

100

nA

I_TPM

TPM peripheral adder measured by

placing the device in STOP or VLPS mode

with selected clock source configured for

output compare generating 100 Hz clock

signal. No load is placed on the I/O

generating the clock signal. Includes

selected clock source and I/O switching

currents.

58

76

59

82

59

85

59

87

59

87

µA

MCGIRCLK (4 MHz internal reference

clock)

I_BG

Bandgap adder when BGEN bit is set and

device is placed in VLPx, LLS, or VLLSx

mode.

I_ADC

ADC peripheral adder combining the

measured values at V_DDand V_DDAby

placing the device in STOP or VLPS mode.

ADC is configured for low-power mode

using the internal clock and continuous

conversions.

331

327

328

6.2.6 Diagram: Typical IDD_RUN operating behavior

The following data was measured from previous devices with same MCU core (Arm®

Cortex-M0+) under these conditions:

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

NOTE

The results in the following graphs are obtained using the

device in Bypass mode.

Figure 6. Run mode supply current vs. core frequency

40

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

Figure 7. VLPR mode current vs. core frequency

6.2.7 SoC Power Consumption

Full KW36A/35A/34A system-on-chip (SoC) power consumption is a function of the

many configurations possible for the MCU platform and its peripherals including the

2.4 GHz radio and the DC-DC converter. A few measured SoC configurations are as

follows:

Table 15. SoC Power Consumption

MCU State

Flash State

Radio State

DCDC State

Typical

Average IC

current

Unit

STOP

Doze

Rx

Buck (V_{DCDC_IN}=3.6 V)

8.5

7.8

9.2

mA

Tx (at 0 dBm)

Tx (at +3.5

dBm)

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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KW36A/35A/34A Electrical Characteristics

Table 15. SoC Power Consumption (continued)

MCU State

Flash State

Radio State

DCDC State

Typical

Average IC

current

Unit

RUN

Enabled

Rx

Buck (V_{DCDC_IN}=3.6 V)

10.4

9.9

mA

Tx (at 0 dBm)

Tx (at +3.5

dBm)

11.7

STOP

Doze

Rx

Disabled/Bypass

17.3

15.9

18.3

mA

Tx (at 0 dBm)

Tx (at +3.5

dBm)

RUN

Enabled

Rx

Disabled/Bypass

21.5

19.9

22.4

mA

Tx (at 0 dBm)

Tx (at +3.5

dBm)

6.2.8 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com

2. Perform a keyword search for “EMC design.”

6.2.9 Capacitance attributes

Table 16. Capacitance attributes

Symbol

Description

Min.

Max.

Unit

C_IN

Input capacitance

—

7

pF

6.3 Switching electrical specifications

42

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NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

6.3.1 Device clock specifications

Table 17. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Normal run mode

f_SYS

f_BUS

f_FLASH

f_LPTMR

System and core clock

Bus clock

—

48

24

MHz

Flash clock

LPTMR clock

VLPR and VLPS modes¹

f_SYS

f_BUS

System and core clock

Bus clock

—

4

1

MHz

f_FLASH

f_LPTMR

f_ERCLK

Flash clock

LPTMR clock²

1

24

16

8

External reference clock

f_{LPTMR_ERCLK}LPTMR external reference clock

f_TPM

TPM asynchronous clock

f_LPUART0

LPUART0 asynchronous clock

12

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing

specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN

or from VLPR.

2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

6.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO,

LPUART, CAN (for KW36A only), CMT and I²C signals.

Table 18. General switching specifications

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock cycles

1, 2

NMI_b pin interrupt pulse width (analog filter enabled) —

Asynchronous path

200

20

—

ns

3

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External RESET_b input pulse width (digital glitch filter

disabled)

100

Port rise and fall time(high drive strength)

• Slew enabled

4, 5

—

25

16

ns

Table continues on the next page...

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KW36A/35A/34A Electrical Characteristics

Table 18. General switching specifications (continued)

Description

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

• Slew disabled

Min.

Max.

Unit

Notes

—

8

ns

—

6

ns

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

Port rise and fall time(low drive strength)

6, 7

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

• Slew disabled

—

24

16

10

6

ns

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

—

ns

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes.

2. The greater of synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized.

4. PTB0, PTB1, PTC0, PTC1, PTC2, PTC3, PTC6, PTC7, PTC17, PTC18.

5. 75 pF load.

6. Ports A, B, and C.

7. 25 pF load.

6.4 Thermal specifications

6.4.1 Thermal operating requirements

Table 19. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Notes

Die junction temperature

Ambient temperature

T_A

105

°C

1

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed the maximum. The simplest method to

determine T_Jis: T_J= T_A+ R_θJA× chip power dissipation.

44

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KW36A/35A/34A Electrical Characteristics

6.4.2 Thermal attributes

Table 20. Thermal attributes

Board type

Four-layer (2s2p)

—

Symbol

Description

48-pin

LQFN

40-pin

"Wettable"

HVQFN

48-pin

"Wettable"

HVQFN

Unit

°C/W

Notes

1, 2

R_θJA

Thermal resistance, junction

to ambient (natural

convection)

48.3

0.5

19.2

21.6

Ψ_JT

Thermal characterization

parameter, junction to

package top (natural

convection)

0.1

0.2

1, 3

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

construction.

2. Determined according to JEDEC Standard JESD51-2A.

3. Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2A.

The thermal characterization parameter (Ψ_JT) can be used to determine the junction

temperature with a measurement of the temperature at the top of the package case

using the following equation:

T_J= T_T+ Ψ_JTx chip power dissipation

where T_Tis the thermocouple temperature at the top of the package.

6.5 Peripheral operating requirements and behaviors

6.5.1 Core modules

6.5.1.1 SWD electricals

Table 21. SWD full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

J1

SWD_CLK frequency of operation

• Serial wire debug

0

25

—

MHz

ns

J2

J3

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1/J1

20

—

ns

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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KW36A/35A/34A Electrical Characteristics

Table 21. SWD full voltage range electricals (continued)

Symbol

J4

Description

Min.

—

10

0

Max.

3

Unit

ns

SWD_CLK rise and fall times

J9

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

—

ns

J10

J11

J12

—

ns

—

5

32

—

ns

J2

J4

J3

SWD_CLK (input)

J4

Figure 8. Serial wire clock input timing

SWD_CLK

SWD_DIO

J9

J10

Input data valid

J11

Output data valid

J12

J11

Output data valid

Figure 9. Serial wire data timing

6.5.2 System modules

There are no specifications necessary for the device's system modules.

46

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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KW36A/35A/34A Electrical Characteristics

6.5.3 Clock modules

6.5.3.1 MCG specifications

Table 22. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}Internal reference frequency (slow clock) —

—

32.768

—

kHz

factory trimmed at nominal V_DDand 25 °C

f_{ints_t}

Internal reference frequency (slow clock) —

user trimmed

31.25

—

39.0625

0.6

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using C3[SCTRIM] and C4[SCFTRIM]

0.3

%f_dco

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

+0.5/-0.7

0.4

3

%f_dco

1, 2

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70 °C

1.5

f_{intf_ft}

Internal reference frequency (fast clock) —

factory trimmed at nominal V_DDand 25 °C

—

4

—

3

MHz

Δf_{intf_ft}

Frequency deviation of internal reference clock

(fast clock) over temperature and voltage —

factory trimmed at nominal V_DDand 25 °C

+1/-2

%f_{intf_ft}

2

f_{intf_t}

Internal reference frequency (fast clock) —

user trimmed at nominal V_DDand 25 °C

3

—

5

MHz

kHz

f_{loc_low}

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

—

f_{loc_high}Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

FLL

FLL reference frequency range

31.25

20

—

39.0625

25

kHz

f_{fll_ref}

f_dco

DCO output

Low range (DRS = 00)

20.97

MHz

3, 4

5, 6

frequency range

640 × f_{fll_ref}

Mid range (DRS = 01)

1280 × f_{fll_ref}

40

—

41.94

23.99

47.97

180

48

—

1

MHz

ps

f_{dco_t_DMX3}DCO output

Low range (DRS = 00)

732 × f_{fll_ref}

frequency

2

Mid range (DRS = 01)

1464 × f_{fll_ref}

J_{cyc_fll}

FLL period jitter

• f_VCO= 48 MHz

7

8

t_{fll_acquire}FLL target frequency acquisition time

—

ms

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. The deviation is relative to the factory trimmed frequency at nominal V_DDand 25 °C, f_{ints_ft}

.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.

4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation

(Δf_{dco_t}) over voltage and temperature must be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification is based on standard deviation (RMS) of period or frequency.

8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

6.5.3.2 Reference Oscillator Specification

The KW36A/35A/34A has been designed to meet targeted standard specifications for

frequency error over the life of the part, which includes the temperature, mechanical

and aging effects.

The table below lists the recommended crystal specifications. Note that these are

recommendations only and deviation may be allowed. However, deviations may result

in degraded RF performance or possibly a failure to meet RF protocol certification

standards. Designers must ensure that the crystal(s) they use will meet the requirements

of their application.

Table 23. Recommended Crystal and Oscillator Specification

Symbol

Description

F0 = 32.0 MHz

F0 = 26.0 MHz

Unit

Notes

Min

Typ

Max

Min

Typ

Max

T_A

Operating

-40

—

105

-40

—

105

°C

1

Temperature

Crystal initial

frequency

tolerance

-10

—

10

25

-10

-25

—

10

24

ppm

2,3

2,4

Crystal frequency -25

stability and aging

—

ppm

Oscillator variation -12

—

15

50

-12

-50

—

16

50

ppm

5

6

Total reference

oscillator tolerance

for Bluetooth LE

applications

-50

C_L

Load capacitance

7

10

13

7

10

13

pF

fF

2, 7

2,7

C₀

Shunt capacitance 0.469

0.67

2.05

0.871

2.665

0.42

1.435

0.6

2.05

0.78

2.665

Cm1

Motional

1.435

capacitance

Lm1

Motional

8.47

12.1

15.73

12.81

18.3

23.79

mH

2,7

inductance

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KW36A/35A/34A Electrical Characteristics

Table 23. Recommended Crystal and Oscillator Specification (continued)

Symbol

Description

F0 = 32.0 MHz

F0 = 26.0 MHz

Unit

Notes

Min

Typ

Max

Min

Typ

Max

Rm1

ESR

P_d

Motional

resistance

—

25

50

—

35

—

10

50

Ohms

uW

2

Equivalent series

resistance

—

60

—

60

2,8

2

Maximum crystal

drive

10

200

T_S

Trim sensitivity

6.30

—

9.00

500

11.70

—

6.39

—

9.12

500

11.86

—

ppm/pF 2,7

μs

T_OSC

Oscillator Startup

Time

9

1. Full temperature range of this device. A reduced range can be chosen to meet application needs.

2. Recommended crystal specification.

3. Measured at 25°C.

4. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over

desired lifetime of system.

5. Variation due to temperature, process, and aging of MCU.

6. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB

manufacturing variation must not exceed this value.

7. Typical is target. 30% tolerances shown.

8. ESR = Rm1 * (1 + [C₀/C_L])^2.

9. Time from oscillator enable to clock ready. Dependent on the complete hardware configuration of the oscillator.

Figure 10. Crystal Electrical Model

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

6.5.3.3 32 kHz Oscillator Frequency Specifications

Table 24. 32 kHz Crystal and Oscillator Specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

f_{osc_lo}

Crystal

—

32.768

—

kHz

frequency

T_A

Operating

temperature

-40

—

105

500

°C

1

Total crystal

frequency

tolerance

-500

ppm

2,3

C_L

Load

capacitance

—

12.5

—

pF

2

ESR

Equivalent

series

80

kOhms

resistance

t_start

Crystal start-up

time

—

1000

32.768

—

ms

kHz

V

4

5

6

f_{ec_extal32}

v_{ec_extal32}

External input

clock frequency

—

External input

0.7

V_DD

clock amplitude

1. Full temperature range of this device. A reduced range can be chosen to meet application needs.

2. Recommended crystal specification.

3. Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.

4. Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.

5. External oscillator connected to EXTAL32K. XTAL32K must be unconnected.

6. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the applied

clock must be within the range of VSS to VDD.

6.5.4 Memories and memory interfaces

6.5.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

6.5.4.1.1 Flash timing specifications — commands

Table 25. Flash command timing specifications

Symbol Description1

Read 1s Block execution time

• 256 KB program/data flash

Min.

Typ.

Max.

Unit

Notes

t_rd1blk256k

—

2

ms

t_rd1sec2kRead 1s Section execution time (2 KB flash)

t_pgmchkProgram Check execution time

—

75

95

μs

Table continues on the next page...

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NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 25. Flash command timing specifications (continued)

Symbol Description1

t_rdrsrcRead Resource execution time

t_pgm8

Min.

—

Typ.

—

Max.

40

Unit

μs

Notes

Program Phrase execution time

Erase Flash Block execution time

• 256 KB program/data flash

—

90

225

μs

2

t_ersblk256k

t_ersscr

125

2125

ms

Erase Flash Sector execution time

—

12

10

130

—

ms

t_pgmsec2kProgram Section execution time (2 KB flash)

Read 1s All Blocks execution time

t_rd1allx

t_rd1alln

• FlexNVM devices

—

3.5

ms

• Program flash only devices

t_rdonce

Read Once execution time

—

90

30

—

μs

t_pgmonceProgram Once execution time

t_ersall

t_vfykey

t_ersallu

Erase All Blocks execution time

Verify Backdoor Access Key execution time

Erase All Blocks Unsecure execution time

Swap Control execution time

• control code 0x01

262

—

4380

35

ms

μs

2

262

4380

ms

t_swapx01

t_swapx02

t_swapx04

t_swapx08

t_swapx10

—

280

100

—

μs

• control code 0x02

235

35

• control code 0x04

• control code 0x08

• control code 0x10

100

235

Program Partition for EEPROM execution time

• 32 KB EEPROM backup

t_pgmpart32k

t_pgmpart256k

—

252

262

—

ms

• 256 KB EEPROM backup

Set FlexRAM Function execution time:

• Control Code 0xFF

t_setramff

t_setram32k

t_setram256k

—

115

0.8

—

μs

ms

• 32 KB EEPROM backup

• 256 KB EEPROM backup

1.2

4.5

6.1

Byte-write to FlexRAM execution time:

• 32 KB EEPROM backup

3

t_eewr8b32k

—

385

1700

3800

μs

t_eewr8b256k

• 256 KB EEPROM backup

1015

16-bit write to FlexRAM execution time:

• 32 KB EEPROM backup

3

t_eewr16b32k

t_eewr16b256k

—

385

1700

μs

• 256 KB EEPROM backup

1015

360

3800

2000

t_eewr32bers32-bit write to erased FlexRAM location

execution time

—

μs

3

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Table 25. Flash command timing specifications (continued)

Symbol Description1

32-bit write to FlexRAM execution time:

Min.

Typ.

Max.

Unit

Notes

3

t_eewr32b32k

t_eewr32b256k

• 32 KB EEPROM backup

• 256 KB EEPROM backup

—

630

2000

4100

μs

1890

1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external

clocks).

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. 1st time EERAM writes after a Reset or SETRAM command may incur additional overhead for EEE cleanup, resulting in

up to 2x the times shown.

NOTE

Under certain circumstances maximum times for writes to

FlexRAM may be exceeded. In this case the user or

application may wait, or assert reset to the FTFE module to

stop the operation.

6.5.4.1.2 Reliability specifications

Table 26. NVM reliability specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Program and Data Flash

t_nvmret1kData retention after up to 1 K cycles

n_nvmcycCycling endurance

20

—

years

1

2

1 K

cycles

FlexRAM as Emulated EEPROM

5

t_nvmreteeData retention

Write endurance

n_nvmwree16

—

years

1, 3

4, 5, 6

• EEPROM backup to FlexRAM used ratio = 16

100 K

1.6 M

—

writes

n_nvmwree256

• EEPROM backup to FlexRAM used ratio =

256

1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.

2. Program and Erase are supported across product temperature specification. Cycling endurance is per flash sector.

3. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years.

4. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product

temperature specification. Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM.

5. For usage of any EEE driver other than the FlexMemory feature, the endurance specification will fall back to the Data

Flash endurance value of 1K.

6. FlexMemory calculator tool is available on the NXP web site for help in estimating the maximum write endurance

achievable at specific EEPROM/FlexRAM ratios. The "In Spec" portions of the online calculator refer to the NVM

reliability specifications section of the data sheet. This calculator only applies to the Kinetis FlexMemory feature.

52

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KW36A/35A/34A Electrical Characteristics

6.5.4.1.3 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set

size can be set to any of several non-zero values.

The bytes not assigned to data flash via the FlexNVM partition code are used by the

FTFE to obtain an effective endurance increase for the EEPROM data. The built-in

EEPROM record management system raises the number of program/erase cycles that

can be attained prior to device wear-out by cycling the EEPROM data through a larger

EEPROM NVM storage space.

While different partitions of the FlexNVM are available, the intention is that a single

choice for the FlexNVM partition code and EEPROM data set size is used throughout

the entire lifetime of a given application.

6.5.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.5.6 Analog

6.5.6.1 ADC electrical specifications

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications. The following specification is defined with the DC-DC converter

operating in Bypass mode.

6.5.6.1.1 16-bit ADC operating conditions

Table 27. 16-bit ADC operating conditions

Symbol Description

V_DDASupply voltage

ΔV_DDASupply voltage

Conditions

Min.

1.71

-100

1.13

Typ.¹

Max.

3.6

Unit

V

Notes

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

0

+100

V_DDA

mV

V

2

3

ΔV_SSA

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

V_REFH

ADC reference

voltage high

V_DDA

V_REFL

V_ADIN

ADC reference

voltage low

V_SSA

V

3

Input voltage

• 16-bit differential mode

• All other modes

VSSA

—

31/32 ×

VREFH

Table continues on the next page...

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KW36A/35A/34A Electrical Characteristics

Table 27. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

• 16-bit mode

Min.

—

Typ.¹

Max.

10

Unit

Notes

C_ADIN

Input

8

4

pF

capacitance

• 8-bit / 10-bit / 12-bit

modes

—

5

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

4

—

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

2.0

—

18.0

12.0

MHz

5

6

ADC conversion 16-bit mode

clock frequency

ADC conversion ≤ 13-bit modes

rate

No ADC hardware averaging

20.000

37.037

—

818.330

461.467

kS/s

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

6

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. For packages without dedicated VREFH and VREFL pins, V_REFHis internally tied to V_DDA, and V_REFLis internally tied to

V_SSA

.

4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

54

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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KW36A/35A/34A Electrical Characteristics

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

ZADIN

SIMPLIFIED

Pad

leakage

ZAS

CHANNEL SELECT

CIRCUIT

ADC SAR

ENGINE

RADIN

RAS

VADIN

CAS

VAS

RADIN

INPUT PIN

RADIN

CADIN

Figure 11. ADC input impedance equivalency diagram

6.5.6.1.2 16-bit ADC electrical characteristics

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

mA

3

ADC asynchronous

clock source

• ADLPC=1, ADHSC=0

• ADLPC=1, ADHSC=1

• ADLPC=0, ADHSC=0

• ADLPC=0, ADHSC=1

2.4

4.0

5.2

6.2

MHz t_ADACK=

1/f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

DNL Differential non-

linearity

• 12-bit mode; Buck

Mode⁶

• 12-bit mode; Bypass

Mode

—

0.7

0.5

–1.1 to +1.9

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

55

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KW36A/35A/34A Electrical Characteristics

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

INL

Integral non-

linearity

• 12-bit mode; Buck

Mode⁶

—

1.0

–2.7 to +1.9

LSB⁴

5

• 12-bit mode; Bypass

Mode

—

0.6

–2.7 to +1.9

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴V_ADIN

V_DDA

=

5

Quantization error

LSB⁴

0.5

ENOB Effective number of 16-bit differential mode; Buck

7

bits

Mode⁶

12

12.75

11.75

—

bits

• Avg = 32

• Avg = 4

11.25

16-bit single-ended mode;

Buck Mode⁶

• Avg = 32

• Avg = 4

11

11.5

10.5

—

9.5

16-bit differential mode;

Bypass Mode

• Avg = 32

• Avg = 4

12.5

13

12

—

11.25

16-bit single-ended mode;

Bypass Mode

• Avg = 32

• Avg = 4

11

10

11.75

10.5

—

Signal-to-noise

plus distortion

See ENOB

SINAD

6.02 × ENOB + 1.76

dB

THD Total harmonic

distortion

16-bit differential mode; Buck

Mode⁶

8

• Avg = 32

—

-90

-88

—

dB

16-bit single-ended mode;

Buck Mode⁶

• Avg = 32

—

16-bit differential mode;

Bypass Mode

• Avg = 32

—

-89

16-bit single-ended mode;

Bypass Mode

• Avg = 32

—

-87

Table continues on the next page...

56

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

Signal-to-noise

SINAD

See ENOB

6.02 × ENOB + 1.76

dB

plus distortion

SFDR Spurious free

dynamic range

distortion

16-bit differential mode; Buck

Mode⁶

8

• Avg = 32

85

89

87

—

dB

16-bit single-ended mode;

Buck Mode⁶

• Avg = 32

—

16-bit differential mode;

Bypass Mode

• Avg = 32

87

85

94

16-bit single-ended mode;

Bypass Mode

• Avg = 32

88

E_IL

Input leakage error

I_In× R_AS

mV

I_In=

leakage

current

(see

Voltage

and

current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.67

706

1.74

716

1.81

726

mV/°

C

9

V_TEMP25Temp sensor

voltage

25 °C

mV

9

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

.

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N.

5. ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).

6. VREFH = Output of Voltage Reference(VREF).

7. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

9. ADC conversion clock < 3 MHz.

6.5.6.2 Voltage reference electrical specifications

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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KW36A/35A/34A Electrical Characteristics

Table 29. VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Min.

Max.

Unit

V

Notes

Supply voltage

Temperature

1.71

3.6

-40 to 105

100

°C

nF

C_L

Output load capacitance

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature range

of the device.

Table 30. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim at

1.190

1.1950

1.2

V

1

nominal V_DDAand temperature=25°C

V_out

Voltage reference output with user trim at

nominal V_DDAand temperature=25°C

1.1945

1.1950

1.1955

V

1

V_step

V_tdrift

Voltage reference trim step

—

0.5

—

mV

1

Temperature drift (V_max-V_minacross the full

temperature range)

20

I_bg

I_lp

Bandgap only current

—

80

360

1

µA

uA

mA

µV

Low-power buffer current

High-power buffer current

1

I_hp

ΔV_LOADLoad regulation

• current = 1.0 mA

1, 2

—

200

—

T_stup

Buffer startup time

—

100

35

µs

T_{chop_osc_st}Internal bandgap start-up delay with chop

ms

oscillator enabled

up

V_vdrift

Voltage drift (V_max-V_minacross the full voltage

range)

—

2

—

mV

1

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 31. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

70

°C

Table 32. VREF limited-range operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_tdrift

Temperature drift (V_max-V_minacross the limited

temperature range)

—

15

mV

58

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

6.5.6.3 CMP and 6-bit DAC electrical specifications

Table 33. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

50

250

—

7

—

0.5

200

600

40

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

μA

LSB³

LSB

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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KW36A/35A/34A Electrical Characteristics

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

60

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KW36A/35A/34A Electrical Characteristics

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.5.7 Timers

See General switching specifications.

6.5.8 Communication interfaces

6.5.8.1 CAN switching specifications

See General switching specifications.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

61

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KW36A/35A/34A Electrical Characteristics

6.5.8.2 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. See the

DSPI chapter of the Reference Manual for information on the modified transfer formats

used for communicating with slower peripheral devices.

Table 34. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

12

Unit

V

Notes

Operating voltage

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

2 x t_BUS

—

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

(t_BUSx 2) −

2

—

ns

1

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

2

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-2

8.5

—

ns

16.2

0

1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

SPI_PCSn

DS1

DS3

DS2

DS4

SPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

SPI_SIN

DS5

DS6

First data

Data

Last data

SPI_SOUT

Figure 14. DSPI classic SPI timing — master mode

Table 35. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

3.6

6

Unit

V

Operating voltage

2.7

Frequency of operation

MHz

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

62

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KW36A/35A/34A Electrical Characteristics

Table 35. Slave mode DSPI timing (limited voltage range) (continued)

Num

DS9

Description

DSPI_SCK input cycle time

Min.

Max.

Unit

ns

4 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) − 2

(t_SCK/2) + 2

DSPI_SCK to DSPI_SOUT valid

—

0

21.4

—

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

2.6

7.0

—

14

SPI_SS

DS10

DS9

SPI_SCK

(POL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

SPI_SOUT

Data

DS13

First data

Last data

SPI_SIN

Figure 15. DSPI classic SPI timing — slave mode

6.5.8.3 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. See

the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 36. Master mode DSPI timing (full voltage range)

Num

Description

Min.

1.71

Max.

3.6

12

Unit

V

Notes

Operating voltage

1

Frequency of operation

—

MHz

ns

DS1

DS2

DSPI_SCK output cycle time

DSPI_SCK output high/low time

2 x t_BUS

—

(t_SCK/2) - 4 (t_SCK/2)+ 4

Table continues on the next page...

ns

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63

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KW36A/35A/34A Electrical Characteristics

Table 36. Master mode DSPI timing (full voltage range) (continued)

Num

Description

Min.

Max.

Unit

Notes

DS3

DSPI_PCSn valid to DSPI_SCK delay

(t_BUSx 2) −

4

—

ns

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

4

—

ns

3

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-1.2

23.3

0

10

—

ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

SPI_PCSn

DS1

DS3

DS2

DS4

SPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

SPI_SIN

DS5

DS6

First data

Data

Last data

SPI_SOUT

Figure 16. DSPI classic SPI timing — master mode

Table 37. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

V

Operating voltage

1.71

3.6

Frequency of operation

—

6

MHz

ns

DS9

DSPI_SCK input cycle time

4 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) - 4

(t_SCK/2)+ 4

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

29.1

—

ns

3.2

7.0

—

ns

—

ns

25

ns

64

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

SPI_SS

DS10

DS9

SPI_SCK

(POL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

SPI_SOUT

Data

DS13

First data

SPI_SIN

Figure 17. DSPI classic SPI timing — slave mode

6.5.8.4 Inter-Integrated Circuit Interface (I²C) timing

Table 38. I ²C timing

Characteristic

Symbol

Standard Mode

Fast Mode

Unit

Minimum Maximum

SCL Clock Frequency

f_SCL

0

4

100

—

0

400

—

kHz

µs

Hold time (repeated) START condition. t_HD; STA

After this period, the first clock pulse is

generated.

0.6

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.3

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

Data hold time for I²C bus devices

t_HD; DAT

t_SU; DAT

t_r

0¹

250⁴

—

3.45²

—

0³

100^{2, 5}

20 +0.1C_b

0.6

0.9¹

—

µs

ns

µs

Data set-up time

6

5

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

1000

300

—

300

—

t_f

—

t_SU; STO

t_BUF

4

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and

SCL lines.

2. The maximum t_HD; DAT must be met only if the device does not stretch the LOW period (t_LOW) of the SCL signal.

3. Input signal Slew = 10 ns and Output Load = 50 pF.

4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.

5. A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement t_{SU; DAT}≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

65

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

+ t_{SU; DAT}= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is

released.

6. C_b= total capacitance of the one bus line in pF.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 18. Timing definition for fast and standard mode devices on the I²C bus

6.5.8.5 LPUART

See General switching specifications.

6.5.9 Human-machine interfaces (HMI)

6.5.9.1 GPIO

The maximum input voltage on PTC0/1/2/3 is VDD+0.3V. For rest of the GPIO

specification, see General switching specifications.

6.6 DC-DC Converter Operating Requirements

Table 39. DC-DC Converter operating conditions

Characteristic

Symbol

VDD_RF1

VDD_RF2, VDD_RF3

Min

Typ

Max

Unit

Bypass Mode Supply Voltage (RF and Analog)

,

1.425

—

3.6

Vdc

Bypass Mode Supply Voltage (Digital)

VDD_X, V_{DCDC_IN}

VDD_A

,

1.71

2.1

—

3.6

Vdc

Buck Mode Supply Voltage ^{1, 2}

DCDC Inductor

Value

V_{DCDC_IN}

—

10

<0.2

26

—

<0.5

—

μH

ESR

Ohms

MHz

DCDC internal oscillator

DCDC_{Int_Osc}

66

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

1. In Buck mode, DC-DC converter needs 2.1 V minimum to start, the supply can drop to 1.8V after DC-DC converter

settles.

2. In Buck mode, DC-DC converter will generate 1.8V at VDD_1P8OUT and 1.5V at VDD_1P5OUT_PMCIN pins.

VDD_1P8OUT should supply to VDD₁, VDD₂and VDD_A. VDD_1P5OUT_PMCIN should supply to VDD_RF₁and

VDD_RF₂. VDD_XTALcan be either supplied by 1.5V or 1.8V.

Table 40. DC-DC Converter Specifications

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

DC-DC Converter Output

Power

Total power output of Pdcdc_out

1p8V and 1p5V

—

125¹

mW

Switching Frequency²

DCDC_FREQ

—

DCDC

reference

—

MHz

frequency

divided by 16

3

Half FET Threshold

Double FET Threshold

Buck Mode

I_half_FET

—

5

—

mA

I_double_FET

40

DC-DC Conversion Efficiency

DCDC_EFF_buck

VDD_1P8_buck

—

90%

—

1.71

min(VDCD Vdc

C_IN_buc

1.8V Output Voltage

k, 3.5)^{4, 5}

VDD_1P8 = 1.8V,

VDC_1P5 = 1.5V

IDD_1P8_buck1

IDD_1P8_buck2

—

45

mA

1.8V Output Current^{6, 7}

VDD_1P8 = 3.0V,

VDC_1P5 = 1.5V

27

1.5V Output Voltage

1.5V Output Current^{6, 9}

Consumed by Radio VDD_1P5_buck

IDD_1P5_buck

1.425

—

1.5⁸

—

1.65

30

Vdc

mA

μs

DCDC Transition Operating

Behavior

LSS➔Run

t_DCDCbuck_LSS➔

—

50

—

RUN

DCDC Turn on Time

T_{DCDC_ON}

—

2.2¹⁰

3.11

—

ms

DCDC Settling Time for

increasing voltage

T_{DCDC_SETTLE_buck}

ms/V

DCDC Settling Time for

decreasing voltage

C = capacitance

attached to the

DCDC V1P8 output

rail.

T_{DCDC_SETTLE_buck}

—

(C*(V1-

V2)/I2

—

s

V1 = the initial output

voltage of the DCDC

V2 = the final output

voltage of the DCDC

I2 = the load on the

DCDC output

expressed in

Amperes.

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

67

NXP Semiconductors

KW36A/35A/34A Electrical Characteristics

Table 40. DC-DC Converter Specifications (continued)

Characteristics

VDD_1P8 ripple

Conditions

Symbol

Min

Typ

Max

Unit

Typical ripple based VDD_1P8_ripple

on NXP

—

30

—

mV

recommended

hardware

configuration and

typical loading (MCU

only; no extra loads

placed on DCDC

outputs)

VDD_1P5 ripple

Typical ripple based VDD_1P5_ripple

on NXP

—

30

—

mV

recommended

hardware

configuration and

typical loading (MCU

only; no extra loads

placed on DCDC

outputs)

1. This is the steady state DC output power. Excessive transient current load from external device will cause 1p8V and 1P5

output voltage unregulated temporary.

2. This is the frequency that will be observed at LN and LP pins.

3. DCDC reference frequency is derived from the RF oscillator or the DCDC internal oscillator.

4. The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.

5. In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For

example, if VDCDC_IN = 2.1 V, maximum VDD_1P8 is 2.05 V. If VDCDC_IN = 3.6 V, maximum VDD_1P8 is 3.5 V.

6. The output current specification in buck mode represents the maximum current the DC-DC converter can deliver. The

KW36A/35A/34A radio and MCU blocks current consumption is not excluded. Note that the maximum output power of

the DC-DC converter is 125mW. The available supply current for external device depends on the energy consumed by

the internal peripherals in KW36A/35A/34A.

7. When using DC-DC in low power mode (pulsed mode), current load must be less than 1mA.

8. User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case

minimum of 1.425V is available as VDD_1P5_buck for radio operation. VDD_1P5 must not be programmed higher than

VDD_1P8.

9. 1.5V is intended to supply power to KW36A/35A/34A. It is not designed to supply power to an external device.

10. Turn on time is measured from the application of power (to DCDC_IN) till the DCDC_REG0[DCDC_STS_DC_OK] bit is

set. Code execution may begin before the DCDC_REG0[DCDC_STS_DC_OK] bit is set. The full device specification is

not guaranteed until the bit sets.

6.7 Ratings

6.7.1 Thermal handling ratings

Table 41. Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

68

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

KW36A/35A/34A Electrical Characteristics

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.7.2 Moisture handling ratings

Table 42. Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.7.3 ESD handling ratings

Table 43. ESD handling ratings

Symbol

V_HBM

Description

Min.

–2000

–500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

I_LAT

Latch-up current at ambient temperature of 105 °C

–100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

6.7.4 Voltage and current operating ratings

Table 44. Voltage and current operating ratings

Symbol

V_DD

I_DD

Description

Min.

–0.3

—

Max.

3.8

Unit

V

Digital supply voltage

Digital supply current

IO pin input voltage

120

mA

V

V_IO

–0.3

–25

V_DD+ 0.3

25

I_D

Instantaneous maximum current single pin limit (applies to

all port pins)

mA

V_DDA

Analog supply voltage

V_DD– 0.3

GND

V_DD+ 0.3

VDCDC

V

V_{IO_DCDC}

IO pins in the DCDC voltage domain (DCDC_CFG and

PSWITCH)

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

69

NXP Semiconductors

Pin Diagrams and Pin Assignments

7 Pin Diagrams and Pin Assignments

7.1 KW36A Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control and Interrupt Module

is used to select the functionality for each GPIO pin. ALT0 is reserved for analog

functions on some GPIO pins. ALT1 – ALT9 are assigned to the available digital

functions on each GPIO pin. GPIO pins with a default of “disabled” are high impedance

after reset – their input and output buffers are disabled.

40

48

LQF

N

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett "Wett

able" able"

HVQ

FN

HVQ

FN

—

4

5

PTA16

PTA17

PTA18

PTA19

DISABLED

PTA16/

LLWU_P4

SPI1_

SOUT

LPUART1_

RTS_b

TPM0_

CH0

5

PTA17/

LLWU_P5

SPI1_SIN

LPUART1_ CAN0_TX

RX

TPM_

CLKIN1

6

PTA18/

LLWU_P6

SPI1_SCK

LPUART1_ CAN0_RX

TX

TPM2_

CH0

7

ADC0_SE5 ADC0_SE5 PTA19/

SPI1_

PCS0

LPUART1_

CTS_b

TPM2_

CH1

LLWU_P7

24

ADC0_DP0 ADC0_

DP0/

ADC0_

DP0/

CMP0_IN0 CMP0_IN0

—

25

41

25

41

ADC0_

DM0

ADC0_

DM0/

CMP0_IN1 CMP0_IN1

ADC0_

DM0/

PTC5

DISABLED

PTC5/

LLWU_

P13/

LPTMR0_

ALT2

LPUART0_ TPM1_

RTS_b CH1

BSM_CLK

RF_NOT_

ALLOWED

—

42

43

42

43

PTC6

DISABLED

PTC6/

LLWU_

P14/

RF_

RFOSC_

EN

I2C1_SCL

I2C1_SDA

LPUART0_ TPM2_

RX CH0

BSM_

FRAME

PTC7

PTC7/

LLWU_P15 PCS2

SPI0_

LPUART0_ TPM2_

TX CH1

BSM_

DATA

70

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

Pin Diagrams and Pin Assignments

40

48

LQF

N

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett "Wett

able" able"

HVQ

FN

HVQ

FN

1

48

PTC19

DISABLED

PTC19/

LLWU_P3/

RF_

SPI0_

PCS0

I2C0_SCL

LPUART0_ BSM_CLK

CTS_b

LPUART1_

CTS_b

EARLY_

WARNING

2

3

4

1

2

3

1

2

3

PTA0

SWD_DIO

SWD_CLK

RESET_b

PSWITCH

PTA0

PTA1

PTA2

SPI0_

PCS1

TPM1_

CH0

SWD_DIO

SWD_CLK

RESET_b

PTA1

SPI1_

PCS0

TPM1_

CH1

PTA2

TPM0_

CH3

5

6

8

9

8

9

PSWITCH

DCDC_

CFG

DCDC_

CFG

DCDC_

CFG

7

8

9

10

11

13

VDCDC_IN VDCDC_IN VDCDC_IN

10

11

DCDC_LP

DCDC_

GND

DCDC_

GND

DCDC_

GND

10

11

12

13

12

14

DCDC_LN

VDD_

1P8OUT

12

13

14

15

—

DCDC_LN

15

VDD_

1P5OUT_

PMCIN

1P5OUT_

PMCIN

1P5OUT_

PMCIN

14

16

PTB0

DISABLED

PTB0/

LLWU_P8/

RF_

RFOSC_

EN

I2C0_SCL

CMP0_

OUT

TPM0_

CH1

CLKOUT

CAN0_TX

CAN0_RX

15

16

17

18

19

17

18

19

PTB1

PTB2

PTB3

ADC0_

SE1/

ADC0_

SE1/

PTB1/

RF_

DTM_RX

I2C0_SDA

DTM_TX

LPTMR0_

ALT1

TPM0_

CH2

CMT_IRO

CMP0_IN5 CMP0_IN5 PRIORITY

ADC0_

SE3/

ADC0_

SE3/

PTB2/

RF_NOT_

TPM1_

CH0

CMP0_IN3 CMP0_IN3 ALLOWED

ADC0_

SE2/

ADC0_

SE2/

PTB3/

ERCLK32K RTS_b

LPUART1_

CLKOUT

TPM1_

CH1

RTC_

CLKOUT

CMP0_IN4 CMP0_IN4

VDD_0 VDD_0

EXTAL32K EXTAL32K PTB16

18

19

20

21

20

21

VDD_0

PTB16

LPUART1_ I2C1_SCL

RX

TPM2_

CH0

20

22

PTB17

XTAL32K

PTB17

LPUART1_ I2C1_SDA

TX

TPM2_

CH1

BSM_CLK

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

71

NXP Semiconductors

Pin Diagrams and Pin Assignments

40

48

LQF

N

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett "Wett

able" able"

HVQ

FN

HVQ

FN

21

23

PTB18

NMI_b

ADC0_

SE4/

PTB18

LPUART1_ I2C1_SCL

CTS_b

TPM_

CLKIN0

TPM0_

CH0

NMI_b

CMP0_IN2

22

23

26

27

26

27

VREFL/

VSSA

VREFL/

VSSA

VREFL/

VSSA

VREFH/

VREF_

OUT

VREFH/

VREF_

OUT

VREFH/

VREF_

OUT

24

25

26

27

28

29

30

31

32

33

28

29

30

31

32

33

34

35

36

37

28

29

30

31

32

33

34

35

36

37

VDDA

XTAL_OUT XTAL_OUT XTAL_OUT

EXTAL

XTAL

EXTAL

XTAL

VDD_RF3

ANT

VDD_RF3

ANT

VDD_RF3

ANT

GANT

VDD_RF2

VDD_RF1

PTC1

VDD_RF2

VDD_RF1

DISABLED

VDD_RF2

VDD_RF1

PTC1/

RF_

I2C0_SDA

LPUART0_ TPM0_

RTS_b CH2

SPI1_SCK

BSM_CLK

EARLY_

WARNING

34

35

36

38

39

40

38

39

40

PTC2

PTC3

PTC4

DISABLED

PTC2/

LLWU_P10 SWITCH

TX_

I2C1_SCL

I2C1_SDA

TX

EXTRG_IN LPUART0_ TPM1_

CTS_b CH0

LPUART0_ CMT_IRO

RX

DTM_RX

DTM_TX

SPI1_

SOUT

BSM_

FRAME

PTC3/ RX_

LLWU_P11 SWITCH

LPUART0_ TPM0_

SPI1_SIN

CAN0_TX

CAN0_RX

CH1

PTC4/

LLWU_

P12/

BSM_

DATA

SPI1_

PCS0

BLE_RF_

ACTIVE

37

38

44

45

44

45

VDD_1

PTC16

VDD_1

DISABLED

PTC16/

LLWU_P0/

RF_

SPI0_SCK

I2C0_SDA

I2C1_SCL

I2C1_SDA

LPUART0_ TPM0_

RTS_b CH3

LPUART1_

RTS_b

STATUS

39

46

47

PTC17

PTC18

DISABLED

PTC17/

SPI0_

SOUT

LPUART0_ BSM_

RX FRAME

DTM_RX

DTM_TX

LPUART1_

RX

LLWU_P1/

RF_EXT_

OSC_EN

40

41

47

49

DISABLED

NA

PTC18/

LLWU_P2

SPI0_SIN

LPUART0_ BSM_

TX DATA

LPUART1_

TX

49-64 Ground

72

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

Pin Diagrams and Pin Assignments

7.2 KW36A Pinouts

KW36A device pinouts are shown in the figures below.

GANT

30

PTC19

PTA0

1

2

41

ANT

29

28

27

26

25

24

23

22

21

VDD_RF3

XTAL

PTA1

3

PTA2

4

EXTAL

PSWITCH

DCDC_CFG

VDCDC_IN

DCDC_LP

DCDC_GND

DCDC_LN

5

XTAL_OUT

VDDA

6

7

VREFH/VREF_OUT

VREFL/VSSA

PTB18

8

9

10

*pin 41 is ground

Figure 19. 40-pin "Wettable" HVQFN pinout diagram

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

73

NXP Semiconductors

Pin Diagrams and Pin Assignments

VDD_RF1

VDD_RF2

GANT

36

35

34

33

32

31

30

29

28

27

26

25

PTA0

PTA1

1

2

PTA2

3

49

53

57

61

50

54

58

62

51

55

59

63

52

56

60

64

ANT

PTA16

4

VDD_RF3

XTAL

PTA17

5

PTA18

6

PTA19

EXTAL

7

PSWITCH

DCDC_CFG

VDCDC_IN

DCDC_LP

DCDC_LN

XTAL_OUT

VDDA

8

9

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

10

11

12

*pin 49 - 64 are ground

Figure 20. 48-pin LQFN pinout diagram

74

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

Pin Diagrams and Pin Assignments

VDD_RF1

VDD_RF2

GANT

36

35

34

33

32

31

30

29

28

27

26

25

PTA0

1

2

PTA1

49

PTA2

PTA16

3

ANT

4

VDD_RF3

XTAL

PTA17

5

PTA18

6

PTA19

EXTAL

7

PSWITCH

XTAL_OUT

VDDA

8

DCDC_CFG/VDCDC_IN

9

DCDC_LP

DCDC_GND

DCDC_LN

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

10

11

12

*pin 49 is ground

Figure 21. 48-pin "Wettable" HVQFN pinout diagram

7.3 KW35A Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control and Interrupt

Module is used to select the functionality for each GPIO pin. ALT0 is reserved for

analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available

digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high

impedance after reset – their input and output buffers are disabled.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

75

NXP Semiconductors

Pin Diagrams and Pin Assignments

40

48

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett "Wett

able" able"

HVQ

FN

HVQ

FN

—

4

PTA16

DISABLED

ADC0_SE5

PTA16/

LLWU_P4

SPI1_SOUT

SPI1_SIN

TPM0_CH0

5

PTA17

PTA17/

LLWU_P5

TPM_

CLKIN1

6

PTA18

PTA18/

LLWU_P6

SPI1_SCK

SPI1_PCS0

TPM2_CH0

7

PTA19

ADC0_SE5

PTA19/

LLWU_P7

TPM2_CH1

24

25

ADC0_DP0

ADC0_DP0/ ADC0_DP0/

CMP0_IN0

ADC0_DM0 ADC0_

DM0/

ADC0_

DM0/

CMP0_IN1

—

41

42

PTC5

DISABLED

PTC5/

LPTMR0_

ALT2

LPUART0_

RTS_b

TPM1_CH1

TPM2_CH0

BSM_CLK

LLWU_P13/

RF_NOT_

ALLOWED

PTC6

DISABLED

PTC6/

LLWU_P14/

RF_

I2C1_SCL

LPUART0_

RX

BSM_

FRAME

RFOSC_EN

—

1

43

48

PTC7

DISABLED

PTC7/

LLWU_P15

SPI0_PCS2 I2C1_SDA

SPI0_PCS0 I2C0_SCL

LPUART0_

TX

TPM2_CH1

BSM_CLK

BSM_DATA

PTC19

PTC19/

LLWU_P3/

RF_

LPUART0_

CTS_b

EARLY_

WARNING

2

3

4

5

6

1

2

3

8

9

PTA0

SWD_DIO

SWD_CLK

RESET_b

PSWITCH

PTA0

PTA1

PTA2

SPI0_PCS1

SPI1_PCS0

TPM1_CH0

TPM1_CH1

TPM0_CH3

SWD_DIO

SWD_CLK

RESET_b

PTA1

PTA2

PSWITCH

DCDC_

CFG

DCDC_

CFG

DCDC_

CFG

7

8

9

VDCDC_IN

DCDC_LP

VDCDC_IN

DCDC_LP

VDCDC_IN

DCDC_LP

10

11

DCDC_

GND

DCDC_

GND

DCDC_

GND

10

11

12

13

DCDC_LN

VDD_

1P8OUT

12

14

DCDC_LN

76

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

Pin Diagrams and Pin Assignments

40

48

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett "Wett

able" able"

HVQ

FN

HVQ

FN

13

14

15

16

VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

PTB0

DISABLED

PTB0/

I2C0_SCL

CMP0_OUT TPM0_CH1

CLKOUT

LLWU_P8/

RF_

RFOSC_EN

15

16

17

18

19

PTB1

PTB2

PTB3

ADC0_SE1/ ADC0_SE1/ PTB1/

DTM_RX

I2C0_SDA

DTM_TX

LPTMR0_

ALT1

TPM0_CH2

TPM1_CH0

TPM1_CH1

CMT_IRO

CMP0_IN5

RF_

PRIORITY

ADC0_SE3/ ADC0_SE3/ PTB2/

CMP0_IN3

RF_NOT_

ALLOWED

ADC0_SE2/ ADC0_SE2/ PTB3/

CLKOUT

RTC_

CMP0_IN4

ERCLK32K

CLKOUT

18

19

20

21

20

21

22

23

VDD_0

PTB16

PTB17

PTB18

VDD_0

EXTAL32K

XTAL32K

NMI_b

EXTAL32K

XTAL32K

PTB16

PTB17

I2C1_SCL

I2C1_SDA

I2C1_SCL

TPM2_CH0

TPM2_CH1

TPM0_CH0

BSM_CLK

NMI_b

ADC0_SE4/ PTB18

CMP0_IN2

TPM_

CLKIN0

22

23

26

27

VREFL/

VSSA

VREFL/

VSSA

VREFL/

VSSA

VREFH/

VREF_OUT VREF_OUT VREF_OUT

24

25

26

27

28

29

30

31

32

33

28

29

30

31

32

33

34

35

36

37

VDDA

XTAL_OUT

EXTAL

XTAL

XTAL_OUT

EXTAL

XTAL_OUT

EXTAL

XTAL

VDD_RF3

ANT

VDD_RF3

ANT

VDD_RF3

ANT

GANT

VDD_RF2

VDD_RF1

PTC1

VDD_RF2

VDD_RF1

DISABLED

VDD_RF2

VDD_RF1

PTC1/

RF_

I2C0_SDA

LPUART0_

RTS_b

TPM0_CH2

SPI1_SCK

BSM_CLK

EARLY_

WARNING

34

35

36

38

39

40

PTC2

PTC3

PTC4

DISABLED

PTC2/

LLWU_P10

TX_

SWITCH

I2C1_SCL

I2C1_SDA

EXTRG_IN

LPUART0_

RX

CMT_IRO

DTM_RX

DTM_TX

SPI1_SOUT BSM_

FRAME

PTC3/

LLWU_P11

RX_

SWITCH

LPUART0_

TX

TPM0_CH1

TPM1_CH0

SPI1_SIN

PTC4/

LLWU_P12/

LPUART0_

CTS_b

BSM_DATA SPI1_PCS0

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

77

NXP Semiconductors

Pin Diagrams and Pin Assignments

40

48

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett "Wett

able" able"

HVQ

FN

HVQ

FN

BLE_RF_

ACTIVE

37

38

44

45

VDD_1

PTC16

VDD_1

DISABLED

PTC16/

LLWU_P0/

RF_

SPI0_SCK

I2C0_SDA

LPUART0_

RTS_b

TPM0_CH3

STATUS

39

46

PTC17

DISABLED

PTC17/

SPI0_SOUT I2C1_SCL

LPUART0_

RX

BSM_

FRAME

DTM_RX

DTM_TX

LLWU_P1/

RF_EXT_

OSC_EN

40

41

47

49

PTC18

Ground

DISABLED

NA

PTC18/

LLWU_P2

SPI0_SIN

I2C1_SDA

LPUART0_

TX

BSM_DATA

7.4 KW35A Pinouts

KW35A device pinouts are shown in the figures below.

78

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Pin Diagrams and Pin Assignments

GANT

30

29

28

27

26

25

24

23

22

21

PTC19

PTA0

1

2

41

ANT

VDD_RF3

XTAL

PTA1

3

PTA2

4

EXTAL

PSWITCH

DCDC_CFG

VDCDC_IN

DCDC_LP

DCDC_GND

DCDC_LN

5

XTAL_OUT

VDDA

6

7

VREFH/VREF_OUT

VREFL/VSSA

PTB18

8

9

10

*pin 41 is ground

Figure 22. 40-pin "Wettable" HVQFN pinout diagram

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

79

NXP Semiconductors

Pin Diagrams and Pin Assignments

VDD_RF1

VDD_RF2

GANT

36

35

34

33

32

31

30

29

28

27

26

25

PTA0

PTA1

1

2

49

PTA2

3

ANT

PTA16

4

VDD_RF3

XTAL

PTA17

5

PTA18

6

PTA19

EXTAL

7

PSWITCH

XTAL_OUT

VDDA

8

9

DCDC_CFG/VDCDC_IN

DCDC_LP

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

10

11

12

DCDC_GND

DCDC_LN

*pin 49 is ground

Figure 23. 48-pin "Wettable" HVQFN pinout diagram

7.5 KW34A Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control and Interrupt Module

is used to select the functionality for each GPIO pin. ALT0 is reserved for analog

functions on some GPIO pins. ALT1 – ALT9 are assigned to the available digital

functions on each GPIO pin. GPIO pins with a default of “disabled” are high impedance

after reset – their input and output buffers are disabled.

80

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Pin Diagrams and Pin Assignments

48

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett

able"

HVQ

FN

1

2

3

4

PTA0

PTA1

PTA2

PTA16

SWD_DIO

SWD_CLK

RESET_b

DISABLED

PTA0

SPI0_PCS1

SPI1_PCS0

TPM1_CH0

TPM1_CH1

TPM0_CH3

TPM0_CH0

SWD_DIO

SWD_CLK

RESET_b

PTA1

PTA2

PTA16/

LLWU_P4

SPI1_SOUT

SPI1_SIN

5

6

7

PTA17

DISABLED

ADC0_SE5

PSWITCH

PTA17/

LLWU_P5

TPM_

CLKIN1

PTA18

PTA18/

LLWU_P6

SPI1_SCK

SPI1_PCS0

TPM2_CH0

PTA19

ADC0_SE5

PSWITCH

PTA19/

LLWU_P7

TPM2_CH1

8

9

PSWITCH

DCDC_

CFG/

DCDC_

CFG/

DCDC_

CFG/

VDCDC_IN

10

11

12

13

DCDC_LP

DCDC_GND DCDC_GND DCDC_GND

DCDC_LN

VDD_

1P8OUT

14

15

DCDC_LN

VDD_

1P5OUT_

PMCIN

1P5OUT_

PMCIN

1P5OUT_

PMCIN

16

PTB0

DISABLED

PTB0/

I2C0_SCL

CMP0_OUT TPM0_CH1

CLKOUT

LLWU_P8/

RF_

RFOSC_EN

17

18

19

PTB1

PTB2

PTB3

ADC0_SE1/ ADC0_SE1/ PTB1/

DTM_RX

I2C0_SDA

DTM_TX

LPTMR0_

ALT1

TPM0_CH2

TPM1_CH0

TPM1_CH1

CMT_IRO

CMP0_IN5

RF_

PRIORITY

ADC0_SE3/ ADC0_SE3/ PTB2/

CMP0_IN3

RF_NOT_

ALLOWED

ADC0_SE2/ ADC0_SE2/ PTB3/

CLKOUT

RTC_

CMP0_IN4

ERCLK32K

CLKOUT

20

21

22

23

VDD_0

PTB16

PTB17

PTB18

VDD_0

EXTAL32K

XTAL32K

NMI_b

EXTAL32K

XTAL32K

PTB16

PTB17

I2C1_SCL

I2C1_SDA

I2C1_SCL

TPM2_CH0

TPM2_CH1

TPM0_CH0

BSM_CLK

NMI_b

ADC0_SE4/ PTB18

CMP0_IN2

TPM_

CLKIN0

24

ADC0_DP0

ADC0_DP0/ ADC0_DP0/

CMP0_IN0 CMP0_IN0

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

81

NXP Semiconductors

Pin Diagrams and Pin Assignments

48

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett

able"

HVQ

FN

25

26

27

ADC0_DM0

ADC0_DM0/ ADC0_DM0/

CMP0_IN1

VREFL/

VSSA

VREFL/

VSSA

VREFL/

VSSA

VREFH/

VREF_OUT

28

29

30

31

32

33

34

35

36

37

VDDA

XTAL_OUT

EXTAL

XTAL

XTAL_OUT

EXTAL

XTAL_OUT

EXTAL

XTAL

VDD_RF3

ANT

VDD_RF3

ANT

VDD_RF3

ANT

GANT

VDD_RF2

VDD_RF1

PTC1

VDD_RF2

VDD_RF1

DISABLED

VDD_RF2

VDD_RF1

PTC1/

RF_EARLY_

WARNING

I2C0_SDA

LPUART0_

RTS_b

TPM0_CH2

SPI1_SCK

BSM_CLK

38

39

40

PTC2

PTC3

PTC4

DISABLED

PTC2/

LLWU_P10

TX_

SWITCH

I2C1_SCL

I2C1_SDA

EXTRG_IN

LPUART0_

RX

CMT_IRO

DTM_RX

DTM_TX

SPI1_SOUT BSM_

FRAME

PTC3/

LLWU_P11

RX_

SWITCH

LPUART0_

TX

TPM0_CH1

TPM1_CH0

SPI1_SIN

PTC4/

LPUART0_

CTS_b

BSM_DATA SPI1_PCS0

BSM_CLK

LLWU_P12/

BLE_RF_

ACTIVE

41

42

43

PTC5

PTC6

PTC7

DISABLED

PTC5/

LPTMR0_

ALT2

LPUART0_

RTS_b

TPM1_CH1

TPM2_CH0

LLWU_P13/

RF_NOT_

ALLOWED

PTC6/

LLWU_P14/

RF_

I2C1_SCL

LPUART0_

RX

BSM_

FRAME

RFOSC_EN

PTC7/

LLWU_P15

SPI0_PCS2

SPI0_SCK

I2C1_SDA

I2C0_SDA

LPUART0_

TX

TPM2_CH1

TPM0_CH3

BSM_DATA

44

45

VDD_1

PTC16

VDD_1

DISABLED

PTC16/

LLWU_P0/

RF_

LPUART0_

RTS_b

STATUS

46

PTC17

DISABLED

PTC17/

LLWU_P1/

SPI0_SOUT I2C1_SCL

LPUART0_

RX

BSM_

FRAME

DTM_RX

82

NXP Semiconductors

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

Pin Diagrams and Pin Assignments

48

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

"Wett

able"

HVQ

FN

RF_EXT_

OSC_EN

47

48

PTC18

PTC19

DISABLED

PTC18/

LLWU_P2

SPI0_SIN

I2C1_SDA

I2C0_SCL

LPUART0_

TX

BSM_DATA

BSM_CLK

DTM_TX

PTC19/

SPI0_PCS0

LPUART0_

CTS_b

LLWU_P3/

RF_EARLY_

WARNING

49

Ground

NA

7.6 KW34A Pinouts

KW34A device pinouts are shown in the figure below.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

83

NXP Semiconductors

Pin Diagrams and Pin Assignments

VDD_RF1

VDD_RF2

GANT

36

35

34

33

32

31

30

29

28

27

26

25

PTA0

1

2

PTA1

49

PTA2

PTA16

3

ANT

4

VDD_RF3

XTAL

PTA17

5

PTA18

6

PTA19

EXTAL

7

PSWITCH

XTAL_OUT

VDDA

8

DCDC_CFG/VDCDC_IN

9

DCDC_LP

DCDC_GND

DCDC_LN

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

10

11

12

*pin 49 is ground

Figure 24. 48-pin "Wettable" HVQFN pinout diagram

7.7 Module Signal Description Tables

The following sections correlate the chip-level signal name with the signal name used in

the module's chapter. They also briefly describe the signal function and direction.

84

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NXP Semiconductors

Pin Diagrams and Pin Assignments

7.7.1 Core Modules

This section contains tables describing the core module signal descriptions.

Table 45. SWD Module Signal Descriptions

SoC Signal Name

SWD_DIO

Module Signal Name

SWD_DIO

Description

I/O

Serial Wire Debug Data

Input/Output¹

Serial Wire Clock²

I/O

I

SWD_CLK

1. Pulled up internally by default

2. Pulled down internally by default

7.7.2 Radio Modules

This section contains tables describing the radio signals.

Table 46. Radio Module Signal Descriptions

Module Signal Name

ANT

Pin Direction

Pin Name

Pin Description

O

ANT

Antenna

BLE_RF_ACTIVE

An output which is asserted prior to any Radio

event and remains asserted for the duration of the

event.

BSM_CLK

O

BSM_CLK

Bit Streaming Mode (BSM) clock signal. 1 MHz bit

rate clock. BSM_DATA and BSM_FRAME are

synchronized to BSM_CLK. External device should

capture BSM_FRAME and BSM_DATA on rising

edge of BSM_CLK.

BSM_DATA

O

BSM_DATA

Serial Bluetooth LE packet bit stream, LSB-first.

Valid on rising edge of BSM_CLK.

BSM_FRAME

Framing signal to indicate the start of reception.

Active high.

DTM_RX

DTM_TX

GANT

I

DTM_RX

DTM_TX

GANT

Direct Test Mode Receive

Direct Test Mode Transmit

Antenna ground

O

I

RF_STATUS

O

RF_STATUS

An output which indicates when the Radio is in an

RX or TX event; software can also control this

signal directly.

RF_PRIORITY

O

RF_PRIORITY

An output which indicates to the external WiFi

device that the Radio event is a high priority and it

needs access to the 2.4GHz antenna.

RF_EARLY_WARNING O

RF_EARLY_WARNING Bluetooth LE LL generated signal which can be

used to wake an external sensor to make a

measurement before a Bluetooth LE event.

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

85

NXP Semiconductors

Pin Diagrams and Pin Assignments

Table 46. Radio Module Signal Descriptions (continued)

Module Signal Name

Pin Direction

Pin Name

Pin Description

RF_NOT_ALLOWED

I

RF_NOT_ALLOWED

External signal which causes the internal Radio to

cease radio activity.

RF_TX_CONF

Signal from an external Radio which indicates the

availability of the 2.4GHz antenna to the internal

Radio.

NOTE: This is a GPIO, not a dedicated PIN.

RX_SWITCH

TX_SWITCH

O

RX_SWITCH

TX_SWITCH

Front End Module receive mode signal.

Front End Module transmit mode signal.

Table 47. Radio Module Miscellaneous Pin Descriptions

Pin Name

Pad Direction

Pin Name

Pin Description

RF_INT_OSC_EN

I

RF_RFOSC_EN

External request to turn on the Radio's internal RF

oscillator.

RF_EXT_OSC_EN

O

RF_EXT_OSC_EN

Internal request to turn on an External oscillator for

use by the internal Radio. The request can also be

from the SoC if it is using the RF oscillator as its

clock.

7.7.3 System Modules

This section contains tables describing the system signals.

Table 48. System Module Signal Descriptions

SoC Signal Name

NMI_b

Module Signal Name

Description

Non-maskable interrupt

Reset bidirectional signal

Power supply

I/O

—

I

RESET_b

I/O

VDD_[1:0]

Ground

VDD

I

VSS

Ground

I

VDD_RF[3:1]

VDCDC_IN

VDD_1P8OUT

VDD_RF

VDCDC_IN

VDD_1P8

Radio power supply

VDCDC_IN

I

DCDC 1.8 V Regulated

Output / Input in bypass

I/O

VDD_1P5OUT_PMCIN

VDD_1P5/VDD_PMC

DCDC 1.5 V Regulated

I/O

Output / PMC Input in bypass

PSWITCH

DCDC_CFG

DCDC_LP

DCDC_LN

PSWITCH

DCDC_CFG

DCDC_LP

DCDC_LN

DCDC enable switch

I

DCDC switch mode select

DCDC inductor input positive I/O

DCDC inductor input negative I/O

Table continues on the next page...

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86

NXP Semiconductors

Pin Diagrams and Pin Assignments

Table 48. System Module Signal Descriptions (continued)

SoC Signal Name

DCDC_GND

Module Signal Name

DCDC_GND

Description

DCDC ground

I/O

I

Table 49. LLWU Module Signal Descriptions

SoC Signal Name

LLWU_P[15:0]

Module Signal Name

LLWU_P[15:0]

Description

Wakeup inputs

I/O

I

7.7.4 Clock Modules

This section contains tables for Clock signal descriptions.

Table 50. Clock Module Signal Descriptions

SoC Signal Name

EXTAL

Module Signal Name

EXTAL

Description

I/O

26 MHz/32 MHz External

clock/Oscillator input

I

XTAL

26 MHz/32 MHz Oscillator

input

I

XTAL_OUT

XTAL_OUT_EN

EXTAL32K

XTAL_OUT

XTAL_OUT_ENABLE

EXTAL32K

26 MHz/32 MHz Clock

output

O

I

26 MHz/32 MHz Clock

output enable for XTAL_OUT

32 kHz External clock/

Oscillator input

I

XTAL32K

CLKOUT

XTAL32K

CLKOUT

32 kHz Oscillator input

Internal clocks monitor

I

O

7.7.5 Analog Modules

This section contains tables for Analog signal descriptions.

Table 51. ADC0 Signal Descriptions

SoC Signal Name

ADC0_DM0

Module Signal Name

DADM0

Description

I/O

ADC Channel 0 Differential

Input Negative

I

ADC0_DP0

DADP0

ADC Channel 0 Differential

Input Positive

Table continues on the next page...

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NXP Semiconductors

Pin Diagrams and Pin Assignments

Table 51. ADC0 Signal Descriptions (continued)

SoC Signal Name

ADC0_SE[5:1]

Module Signal Name

AD[5:1]

Description

I/O

ADC Channel 0 Single-

ended Input n

I

VREFH

V_REFSH

Voltage Reference Select

High

VDDA

VSSA

V_DDA

V_SSA

Analog Power Supply

Analog Ground

I

Table 52. CMP0 Signal Descriptions

SoC Signal Name

Module Signal Name

IN[5:0]

CMP0

Description

Analog voltage inputs

Comparator output

I/O

CMP0_IN[5:0]

CMP0_OUT

I

O

Table 53. VREF Signal Descriptions

SoC Signal Name

VREF_OUT

Module Signal Name

VREF_OUT

Description

I/O

Internally generated voltage

reference output

O

7.7.6 Timer Modules

This section contains tables describing timer module signals.

Table 54. TPM0 Module Signal Descriptions

SoC Signal Name

TPM_CLKIN[1:0]

TPM0_CH[3:0]

Module Signal Name

TPM_EXTCLK

TPM_CH[3:0]

Description

External clock

TPM channel

I/O

I

I/O

Table 55. TPM1 Module Signal Descriptions

SoC Signal Name

Module Signal Name

TPM_EXTCLK

TPM_CH[1:0]

Description

External clock

TPM channel

TPM_CLKIN[1:0]

TPM1_CH[1:0]

I

I/O

88

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Pin Diagrams and Pin Assignments

Table 56. TPM2 Module Signal Descriptions

SoC Signal Name

TPM_CLKIN[1:0]

TPM2_CH[1:0]

Module Signal Name

TPM_EXTCLK

TPM_CH[1:0]

Description

External clock

TPM channel

I/O

I

I/O

Table 57. LPTMR0 Module Signal Descriptions

SoC Signal Name

LPTMR0_ALT[2:1]

Module Signal Name

Description

I/O

LPTMR0_ALT[2:1]

Pulse counter input pin

I

Table 58. RTC Module Signal Descriptions

SoC Signal Name

RTC_CLKOUT

Module Signal Name

RTC_CLKOUT

Description

1 Hz square-wave output

O

7.7.7 Communication Interfaces

This section contains tables for the signal descriptions for the communication

modules.

Table 59. SPI0 Module Signal Descriptions

SoC Signal Name

SPI0_PCS0

Module Signal Name

PCS0/SS

Description

Chip Select/Slave Select

Chip Select

I/O

O

SPI0_PCS[2:1]

SPI0_SCK

PCS[2:1]

SCK

Serial Clock

I/O

I

SPI0_SIN

SIN

Data In

SPI0_SOUT

SOUT

Data Out

O

Table 60. SPI1 Module Signal Descriptions

SoC Signal Name

Module Signal Name

SPI1_PCS0

Description

Chip Select/Slave Select

Serial Clock

I/O

SPI1_PCS0

SPI1_SCK

SPI1_SIN

I/O

I

SCK

SIN

Data In

SPI1_SOUT

SOUT

Data Out

O

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89

NXP Semiconductors

Pin Diagrams and Pin Assignments

Table 61. I2C0 Module Signal Descriptions

SoC Signal Name

I2C0_SCL

I2C0_SDA

Module Signal Name

SCL

SDA

Description

I2C serial clock line

I2C serial data line

I/O

Table 62. I2C1 Module Signal Descriptions

SoC Signal Name

Module Signal Name

SCL

SDA

Description

I2C serial clock line

I2C serial data line

I2C1_SCL

I2C1_SDA

I/O

Table 63. CAN0 Signal Descriptions (KW36 only)

SoC Signal Name

Module Signal Name

CAN RX

CAN TX

Description

CAN Receive Pin

CAN Transmit Pin

CAN0_RX

CAN0_TX

I

O

Table 64. LPUART0 Module Signal Descriptions

SoC Signal Name

Module Signal Name

LPUART CTS

Description

Clear To Send

LPUART0_CTS_b

LPUART0_RTS_b

LPUART0_RX

I

LPUART RTS

LPUART RxD

LPUART TxD

Request To Send

Receive Data

Transmit Data¹

O

I

LPUART0_TX

I/O

1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

transmit direction is configured for receive data

Table 65. LPUART1 Module Signal Descriptions (KW36 only)

SoC Signal Name

LPUART1_CTS_b

Module Signal Name

LPUART CTS

Description

Clear To Send

I/O

I

LPUART1_RTS_b

LPUART1_RX

LPUART1_TX

LPUART RTS

LPUART RxD

LPUART TxD

Request To Send

Receive Data

Transmit Data¹

O

I

I/O

1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

transmit direction is configured for receive data

90

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Package Information

7.7.8 Human-Machine Interfaces(HMI)

This section contains tables describing the HMI signals.

Table 66. GPIO Module Signal Descriptions

SoC Signal Name

PTA[19:16][2:0]

Module Signal Name

Description

I/O

PORTA19-16, 2-0

General Purpose Input/

Output

I/O

PTB[18:16][3:0]

PTC[19:16][7:1]

PORTB18-16, 3-0

PORTC19-16, 7-1

General Purpose Input/

Output

General Purpose Input/

Output

8 Package Information

8.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

Table 67. Packaging Dimensions

If you want the drawing for this package

40-pin "Wettable" HVQFN (6x6)

Then use this document number

98ASA01025D

48-pin LQFN (7x7)

98ASA00694D

98ASA01307D

48-pin "Wettable" HVQFN (7x7)

9 Part identification

9.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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NXP Semiconductors

Part identification

9.2 Format

Part numbers for this device have the following format:

Q KW## A FFF R T PP CC N

9.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Table 68. Part number fields descriptions

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

KW##

Kinetis Wireless family

• KW34

• KW35

• KW36

A

Key attribute

• A = Automotive Qualification

• 512 = 512 KB

FFF

T

Program flash memory size

Temperature range (°C)

• V = –40 to 105

• C = –40 to 85

PP

Package identifier

• HT = 48 LQFN (7 mm x 7 mm)

• FP = 40 "Wettable" HVQFN (6 mm x 6 mm)

• FT = 48 "Wettable" HVQFN (7 mm x 7 mm)

CC

N

Maximum CPU frequency (MHz)

Packaging type

• 4 = 48 MHz

• (Blank) = Tray

• R = Tape and reel

9.4 Example

This is an example part number:

MKW36A512VFT4

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MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Revision History

10 Revision History

Table 69. Revision History

Rev. No.

Date

Substantial Changes

Rev 7

09/2019

• Removed flash access control feature from Security Features.

• Added the following footnote to Table 13 : "The device was configured in buck mode auto-

start to perform the measurements. The DCDC_IN was powered with 3.0 V.

VDD_1P8OUT was configured to output 1.8 V and VDD_1P5OUT_PMCIN was configured

to output 1.5 V."

• Added the following footnote to VLPS, LLSx and VLLSx modes: "DCDC configured in

pulsed mode." in Table 13.

• Added thermal attributes for 48-pin "Wettable" HVQFN package, and replaced standard

JESD51-2 with JESD51-2A in the footnotes in Thermal attributes.

• Removed "Flash timing specifications – program and erase" and "Flash high voltage

current behaviors" tables.

• Added DCDC internal oscillator row in Table 39.

• Updated Table 40 as follows:

• In Switching Frequency row, updated the Typical value to DCDC reference

frequency divided by 16 and added the following footnote to it: "DCDC reference

frequency is derived from the RF oscillator or the DCDC internal oscillator".

• Added VDD_1P8 ripple and VDD_1P5 ripple rows.

• Updated introductory text beginning "The Port Control and Interrupt Module is used to

select the functionality for...." in KW36A Signal Multiplexing and Pin Assignments. Same

update done for KW35A and KW34A as well.

• Updated "DEFAULT" column to correct "DISABLED" status of PTA19, PTB1/2/3 pin

names in KW36/35/34 pinouts.

Rev 7

Draft B

04/2019

• Added "Top Line Marking" column to the Orderable parts details table.

• Removed "Galois counter mode (AES-GCM)" and "DES modes" features of LTC from

Security Features.

• Removed "Logic Input Voltage Low/High" rows from Table 2.

• Removed the following footnote from Table 12 : "Supported through the connectivity

software in its pre-defined Deep Sleep Modes.".

• Updated Typical value of I_{DD_RUN}at 70 °C to 5.92 in Table 13.

• Added "48-pin Wettable HVQFN" column to Thermal attributes.

• Corrected name of v_{ec_xtal32}to v_{ec_extal32}in 32 kHz Oscillator Frequency Specifications.

• Updated minimum and maximum values of "1.5V Output Voltage" in Table 40. Also

specified the condition as "Consumed by radio".

• Corrected location of ground pins in 48-pin LQFN pinout diagram - Figure 20.

• Removed CAN0 and LPUART1 references from KW34A Signal Multiplexing and Pin

Assignments.

Rev 7

Draft A

11/2018

• Added following part numbers: MKW36A512VFT4, MKW35A512VFT4, and

MKW34A512VFT4

• Added 48 "Wettable" QFN package details including pin diagrams and assignments.

• Changed 40-pin "Wettable" QFN and 48-pin "Wettable" QFN to 40-pin "Wettable" HVQFN

and 48-pin "Wettable" HVQFN throughout.

• Applied new NXP Brand Guidelines for Bluetooth Low Energy.Removed references of

BLE and replaced with Bluetooth LE.

• Added the following footnote in Table 6 : "TX continuous wave power output at the RF

pins with the recommended matching components mounted on PCB.".

• Corrected maximum value of VDD_1P8 output in the footnote 6, in Table 42. DC-DC

Converter Specifications, from 3 V to 3.5 V.

• Removed silicon revision (R) field from Table 68. Part number fields descriptions.

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

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Revision History

Table 69. Revision History (continued)

Rev. No.

Date

09/2018

Substantial Changes

Rev 6

• Changed ARM to Arm and applied registered trademark to Cortex on first instance.

• Updated Related Resources table for Web release.

• Updated Introduction section to remove industrial details.

• Added space between value and unit throughout.

• Removed SPI Clock Rate row from Radio Operating Conditions.

• Added figure title to Figure 3 in the topic Transmit and PLL Feature Summary.

• Updated max values of IDD_STOP, IDD_LLS3/LLS2, IDD_VLLS0 (POR PO = ) in Table

12

• Updated Table 23 and Table 24.

• Updated Table 25 - Flash command timing specifications.

• Updated Table 26 - NVM reliability specifications.

• Backpage was also updated.

Rev 5

07/2018

• Updated title of the document to 'MKW36A/35A Data Sheet' from 'MKW35A/36A Data

Sheet'.

• Updated SoC name KW35A with KW36A/35A throughout.

• Replaced QFN with "Wettable" QFN throughout

• Added package drawings on front page and updated features under Multi-Standard Radio

section as follows: Modulation index: added 1.0 to the list.

• Updated Typical Rx Current and Typical Tx current values to 6.3 mA and 5.7 mA

respectively.

• Updated Low Power Mode (VLLS0) Current value to 258 nA from 182 nA.

• Replaced column name "Tier" with "Qualification" in this table.

• Updated Introduction section.

• Removed Radio version number "V2.1" from Block Diagram.

• Updated Radio features, Microcontroller features, and System features.

• Appended "(Zero IF)" to Direct Conversion Receiver in Transceiver Description.

• Edited Key Specifications.

• Updated Receiver Sensitivity to -99 from -100 dBm in Radio features. Also added support

of 1 Mbps PHY to BLE link Layer hardware.

• Updated typical and minimum values in Table 3. Also updated footnote 7 to "BLE adjacent

and alternate selectivity performance is measured with modulated interference signals.".

• In Table 4 :

• updated and added receiver specifications with GFSK modulations, and

• updated footnote as follows: "Selectivity measured with an unmodulated blocker

except for GFSK BT=0.5, h=0.5 1mbps and GFSK BT=0.5, h=0.32 1mbps. The

desired signal is set at -85 dBm."

.

• Updated typical and maximum values in Table 5. Also updated footnote for TXH2 and

TXH3 symbols as follows: "Harmonic Levels based on recommended 2 component match.

Transmit harmonic levels depend on the quality of matching components. Additional

harmonic margin using a 3^rdmatching component (1x shunt capacitor) is possible."

• Updated typical and maximum values in Table 12 and Table 13.

• Updated typical values in Table 15. Also added specifications of STOP and RUN modes of

radio state Tx (at +3.5 dBm).

• Updated 48-pin LQFN and 40-pin QFN values in Thermal attributes table. Removed

thermal metrics and kept thermal attributes R_θJAand Ψ_JT. Also updated notes and added

information about how to use the thermal characterization parameter, Ψ_JT.

• Added following text in Reference Oscillator Specification : "The table below shows the

recommended crystal specifications. Note that these are recommendations.....". Also

updated 32M/26M typical values of Oscillator Startup Time to 500 μs.

• Updated typical and maximum values in Table 1

• Updated minimum, typical and maximum value of Temp sensor slope in Table 28

• Updated Table 1.

Table continues on the next page...

94

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors

Revision History

Table 69. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Added a footnote under Buck Mode Supply Voltage in Table 39.

• Corrected spec name of Buck mode in DC-DC configuration to V_{DCDC_IN}from VDD_{DCDC_IN}

throughout.

• In Table 40,

• added a footnote for maximum value of DC-DC Converter Output Power,

• updated footnote example corresponding to '1.8V Output Voltage',

• updated maximum value in '1.8V Output Voltage' from "min(VDCDC_IN_buck, 3)" to

"min(VDCDC_IN_buck, 3.5)",

• added VDD_1P8 = 1.8V and VDD_1P5 = 1.5V conditions in 1.8V Output Current,

and

• added the following information to the footnote corresponding to '1.5V Output

Voltage': "VDD_1P5 must not be programmed higher than VDD_1P8."

• Added V_{IO_DCDC}row in Voltage and current operating ratings.

• Removed 48-pin LQFN pinout diagram and signal names from KW35A Signal Multiplexing

and Pin Assignments. Also updated signal name at pin 17 and pin 19 of 40 "Wettable"

QFN and 48 LQFN in ALT1 functionality to PTB3/ERCLK32K in KW36A Signal

Multiplexing and Pin Assignments and KW35A Signal Multiplexing and Pin Assignments.

Rev 4

10/2017

• BLE version 4.2 updated to 5.0.

• Updated maximum value of voltage range to 3.6 V.

• Updated Generic FSK modulation BT and receiver sensitivity from -100 dBm to -99 dBm.

• Added support of up to 26 devices by Whitelist and 8 private resolvable addresses in

hardware in the section Radio features.

• Updated number of GPIO digital pins in the 48-pin package to 25 in Peripheral features.

• Updated note text in Radio operating conditions as follows: "The recommended crystal

accuracy is 40 ppm including initial accuracy, mechanical, temperature and aging

factors."

• Updated maximum values in Power mode transition operating behaviors.

• Updated Typical values in Table 12 and Table 13.Also added the following note to the

tables for Run mode: "Radio is off".

• Minor updates in introductory text of Reference Oscillator Specification section. Also

updated typical value of T_OSCto 680 μs in .

• Added 32 kHz Oscillator Frequency Specifications section.

• Updated Table 40 section.

• Added the following parameters: Switching Frequency, Half FET Threshold, Double

FET Threshold, DC-DC Conversion Efficiency, DCDC Settling Time for increasing

voltage and DCDC Settling Time for decreasing voltage.

• Updated Typ. value of the 'DCDC Turn on Time' parameter and added a footnote.

Rev 3

Rev 2

06/2017

03/2017

Updated Typical values in Table 12 and Table 13.

• Modified structure of the document to include orderable part numbers and Related

Resources table after the features list.

• Specified all supported part numbers on the front page.

• Specified the baudrate supported by FlexCAN in the features list.

• Updated value of minimum input voltage to 1.71 V and output voltage to 1.8 V from 2.7 V.

Also updated minimum voltage value in DCDC buck mode to 2.1 V from 2.7 V.

• Changed RSSI Range maximum value to 5 dBm in Table 3 and added the following

footnote: "With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF

input losses.".

• Added Table 6 to show mapping relationship between TX_POWER and DBM. Also added

the corresponding graph.

• Added DCDC Inductor specifications in Table 39.

• Updated Table 40 :

• Removed repetitive fields from the table.

Table continues on the next page...

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

95

NXP Semiconductors

Revision History

Table 69. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Specified Typ. value of "DCDC Transition Operating Behavior" as 50 us.

• Updated footnote 3 as follows: "In Buck mode, the maximum VDD_1P8 output is the

minimum of either VDCDC_IN_BUCK minus 50 mV or 3 V. For example, if

VDCDC_IN = 1.85 V, maximum VDD_1P8 is 1.8 V. If VDCDC_IN = 4.2 V, maximum

VDD_1P8 is 3 V.".

• Replaced Laminate QFN with LQFN throughout.

• Added radio signals in Table 46.

• Added document numbers of the supported package drawings in Table 67.

• Added Part identification section.

Rev 1

01/2017

• Updated maximum supply voltage from 4.2 to 4.25 V.

• Corrected MBAN Channel numbering in Channel Plan for Bluetooth Low Energy.

• Corrected "Radio" description for VLLS1 and VLLS0 power modes in Table 7.

• Updated Section 9 Pin Diagrams and Pin Assignments.

• Corrected pin name from VDD_1P45OUT_PMCIN to VDD_1P5OUT_PMCIN

• Added ground pads in the pin diagrams

• Put Typ. values as TBDs in Table 13, Power consumption operating behaviors - Buck

Mode.

• Added the following note in Diagram: Typical IDD_RUN operating behavior : "The results

in the following graphs are obtained using the device in Bypass mode."

• Put Typ. values as TBDs in Table 15, SoC Power Consumption.

• Added T_OSCrow in , Reference Crystal Specification.

• Added DCDC Transition Operating Behavior and DCDC Turn on Time in Table 40, DC-DC

Converter Specifications.

• Added the following note in Table 46 for the RF_TX_CONF pin: "This is a GPIO, not a

dedicated PIN."

Rev 0

11/2016

Initial Internal Release

96

MKW36A/35A/34A Data Sheet, Rev. 7, 09/2019

NXP Semiconductors


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