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935380411574 [NXP]

Microcontroller;
935380411574
型号： 935380411574
厂家： NXP    NXP
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Microcontroller

微控制器 外围集成电路
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NXP Semiconductors  
Data Sheet: Technical Data  
An Energy Efficient Solution by NXP  
Document Number: MC9S08QL8  
Rev. 1, 07/2018  
                                                                                                                     
                                                                                                                       
                                                                                                                         
                                                                                                                           
                                                                                                                              
                                                                                                                                
                                                                                                                                  
                                                                                                                                    
                                                                                                                                      
                                                                                                                                        
                                                                                                                                           
                                                                                                                                             
                                                                                                                                               
                                                                                                                                                
                                                                                                                                                  
                                                                                                                                                     
                                                                                                                                                        
                                                                                                                                                          
                                                                                                                                                            
                                                                                                                                                              
                                                                                                                                                                
                                                                                                                                                                   
                                                                                                                                                                     
MC9S08QL8  
MC9S08QL8 Series  
Covers: MC9S08QL8 and  
MC9S08QL4  
20-Pin TSSOP  
Case 948E  
16-Pin TSSOP  
Case 948F  
• Development Support  
Features  
– Single-wire background debug interface  
– Breakpoint capability to allow single breakpoint setting  
during in-circuit debugging  
• 8-Bit HCS08 Central Processor Unit (CPU)  
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature  
range of –40 °C to 85 °C  
– HC08 instruction set with added BGND instruction  
– Support for up to 32 interrupt/reset sources  
• On-Chip Memory  
• Peripherals  
– ADC — 8-channel, 12-bit resolution; 2.5 s conversion  
time; automatic compare function; 1.7 mV/°C  
temperature sensor; internal bandgap reference channel;  
operation in stop3; fully functional from 3.6 V to 1.8 V.  
– ACMP — Analog comparator with selectable interrupt  
on rising, falling, or either edge of comparator output;  
compare option to fixed internal bandgap reference  
voltage; output can be tied internally to TPM input  
capture; operation in stop3  
– TPM — One 1-channel timer/pulse-width modulator  
(TPM) module; selectable input capture, output  
compare, or buffered edge- or center-aligned PWM on  
each channel; ACMP output can be tied internally to  
input capture  
– Up to 8 KB flash memory read/program/erase over full  
operating voltage and temperature  
– Up to 512 bytes random-access memory (RAM)  
– Security circuitry to prevent unauthorized access to  
RAM and flash contents  
• Power-Saving Modes  
– Two very low power stop modes  
– Peripheral clock enable register can disable clocks to  
unused modules, thereby reducing currents  
– Low power run  
– Low power wait  
– 6 s typical wakeup time from stop3 mode  
– Typical stop current of 250 nA at 3 V, 25 °C  
• Clock Source Options  
– MTIM — 8-bit modulo timer module with optional  
prescaler  
– RTC — (Real-time counter) 8-bit modulo counter with  
binary or decimal based prescaler; external clock source  
for precise time base, time-of-day, calendar or task  
scheduling functions; free running on-chip low power  
oscillator (1 kHz) for cyclic wakeup without external  
components; runs in all MCU modes  
– SCI — Full duplex non-return to zero (NRZ); LIN  
master extended break generation; LIN slave extended  
break detection; wakeup on active edge  
– KBI — 8-pin keyboard interrupt with selectable edge  
and level detection modes  
– Oscillator (XOSC) — Very low-power, loop-control  
Pierce oscillator; crystal or ceramic resonator range of  
31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz  
– Internal Clock Source (ICS) — Internal clock source  
module containing a frequency-locked-loop (FLL)  
controlled by internal reference; precision trimming of  
internal reference allows 0.2% resolution and 2%  
deviation over temperature and voltage; supports bus  
frequencies from 1 MHz to 10 MHz  
• System Protection  
– Watchdog computer operating properly (COP) reset  
with option to run from dedicated 1 kHz internal clock  
source or bus clock  
– Low-voltage detection with reset or interrupt; selectable  
trip points  
– Illegal opcode detection with reset  
– Illegal address detection with reset  
– Flash block protection  
• Input/Output  
– 18 GPIOs include one input-only and one output-only  
pin.  
– Hysteresis and configurable pullup device on all input  
pins; configurable slew rate and drive strength on all  
output pins except PTA5.  
• Package Options  
– 20-pin TSSOP, 16-pin TSSOP  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  
© 2018 NXP B.V. All rights reserved.  
Table of Contents  
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
4.10.2.TPM Module Timing . . . . . . . . . . . . . . . 20  
4.11. Analog Comparator (ACMP) Electricals . . . . . . 21  
4.12. ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 21  
4.13. Flash Specifications . . . . . . . . . . . . . . . . . . . . . 25  
4.14. EMC Performance . . . . . . . . . . . . . . . . . . . . . . 26  
5. Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
6. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 28  
6.1. Mechanical Drawings . . . . . . . . . . . . . . . . . . . . 28  
2. MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7  
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
4.2. Parameter Classification . . . . . . . . . . . . . . . . . . . 7  
4.3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . 7  
4.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . 8  
4.5. ESD Protection and Latch-Up Immunity . . . . . . . 9  
4.6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 10  
4.7. Supply Current Characteristics . . . . . . . . . . . . . 14  
4.8. External Oscillator (XOSC) Characteristics . . . 15  
4.9. Internal Clock Source (ICS) Characteristics . . . 17  
4.10. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . 19  
4.10.1.Control Timing . . . . . . . . . . . . . . . . . . . . 19  
Revision History  
To provide the most up-to-date information, the revision of our documents on the World Wide Web will  
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information  
available, refer to:  
http://nxp.com/  
The following revision history table summarizes changes contained in this document.  
Rev  
Date  
Description of Changes  
0
1
06/12/2018  
07/16/2018  
Initial creation.  
Added TSSOP 20 package mechanical drawing.  
Related Documentation  
Find the most current versions of all documents at: http://www.nxp.com  
Reference Manual (MC9S08QL8RM)  
Contains extensive product information including modes of operation, memory,  
resets and interrupts, register definition, port pins, CPU, and all module  
information.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
2
NXP Semiconductors  
Ordering Information  
1
Ordering Information  
Table 1. Ordering Information  
MC9S08QL8  
MC9S08QL4  
Part Number  
CTJ  
CTG  
CTJ  
CTG  
Max. frequency (MHz)  
Flash memory (KB)  
RAM (B)  
20  
20  
20  
20  
8
8
4
4
512  
512  
256  
256  
12-bit ADC  
ACMP  
8 ch  
8 ch  
8 ch  
8 ch  
1
1
1
1
16-bit TPM  
8-bit Modulo timer  
RTC  
1 ch  
1 ch  
1 ch  
1 ch  
1
1
1
1
Yes  
Yes  
Yes  
Yes  
SCI (LIN Capable)  
KBI pins  
1
1
1
1
8
18  
8
14  
8
18  
8
14  
GPIO1  
Package  
20-TSSOP  
16-TSSOP  
20-TSSOP  
16-TSSOP  
1
Port I/O count includes the output-only PTA4 and the input-only PTA5 pins.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
3
MCU Block Diagram  
2
MCU Block Diagram  
The block diagram shows the structure of the MC9S08QL8 MCU.  
HCS08 CORE  
PTA5/IRQ/TCLK/RESET  
PTA4/ACMPO/BKGD/MS  
PTA3/KBIP3/ADP3  
BDC  
CPU  
ANALOG COMPARATOR  
(ACMP)  
PTA2/KBIP2/ADP2  
HCS08 SYSTEM CONTROL  
PTA1/KBIP1/ADP1/ACMP–  
PTA0/KBIP0/TPMCH0/ADP0/ACMP  
VREFL/VSSA  
VREFH/VDDA  
12-BIT  
ANALOG-TO-DIGITAL  
CONVERTER (ADC)  
RESETS AND INTERRUPTS  
MODES OF OPERATION  
POWER MANAGEMENT  
PTB7/EXTAL  
PTB6/XTAL  
COP  
IRQ  
LVD  
8-BIT MODULO TIMER  
MODULE (MTIM)  
PTB5/TPMCH0  
PTB4  
PTB3/KBIP7/ADP7  
PTB2/KBIP6/ADP6  
PTB1/KBIP5/TxD/ADP5  
PTB0/KBIP4/RxD/ADP4  
REAL-TIME COUNTER  
(RTC)  
USER FLASH  
(MC9S08QL8 = 8192 BYTES)  
(MC9S08QL4=4096BYTES)  
16-BIT TIMER/PWM  
MODULE (TPM)  
USER RAM  
(MC9S08QL8 = 512 BYTES)  
(MC9S08QL4 = 256 BYTES)  
SERIAL COMMUNICATIONS  
INTERFACE MODULE (SCI)  
PTC3  
PTC2  
PTC1  
PTC0  
KEYBOARD INTERRUPT  
(KBI)  
20 MHz INTERNAL CLOCK  
SOURCE (ICS)  
LOW-POWER OSCILLATOR  
31.25 kHz to 38.4 kHz  
1 MHz to 16 MHz  
(XOSC)  
VSS  
VDD  
VOLTAGE REGULATOR  
pins not available on 16-pin package  
VDDA/VREFH and VSSA/VREFL are double bonded to VDD and VSS  
1
Figure 1. MC9S08QL8 Series Block Diagram  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
4
NXP Semiconductors  
Pin Assignments  
3
Pin Assignments  
This chapter shows the pin assignments for the MC9S08QL8 series devices.  
Table 2. Pin Availability by Package Pin-Count  
Pin  
Number  
<-- Lowest Priority --> Highest  
20  
16  
Port Pin  
PTA5  
Alt 1  
IRQ  
Alt 2  
TCLK  
Alt 3  
Alt 4  
1
2
1
2
RESET  
MS  
PTA4  
ACMPO  
BKGD  
3
3
VDD  
VSS  
4
4
5
5
PTB7  
PTB6  
PTB5  
PTB4  
PTC3  
PTC2  
PTC1  
PTC0  
PTB3  
EXTAL  
XTAL  
6
6
7
7
TPMCH01  
8
8
9
—
—
—
—
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
KBIP7  
KBIP6  
KBIP5  
KBIP4  
KBIP3  
KBIP2  
KBIP1  
KBIP0  
ADP7  
ADP6  
ADP5  
ADP4  
ADP3  
ADP2  
ADP12  
10 PTB2  
11 PTB1  
12 PTB0  
13 PTA3  
14 PTA2  
15 PTA1  
16 PTA0  
TxD  
RxD  
ACMP–2  
ACMP+2  
TPMCH0 ADP02  
1
2
TPMCH0 pin can be repositioned using at PTB5 TPMCH0PS in SOPT2,  
default reset location is PTA0.  
If ADC and ACMP are enabled, both modules will have access to the pin.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
5
Pin Assignments  
PTA0/KBIP0/TPMCH0/ADP0/ACMP+  
PTA1/KBIP1/ADP1/ACMP–  
PTA2/KBIP2/ADP2  
1
20  
19  
18  
17  
16  
15  
14  
13  
PTA5/IRQ/TCLK/RESET  
2
PTA4/ACMPO/BKGD/MS  
VDD  
3
4
PTA3/KBIP3/ADP3  
VSS  
5
PTB0/KBIP4/RxD/ADP4  
PTB1/KBIP5/TxD/ADP5  
PTB2/KBIP6/ADP6  
PTB7/EXTAL  
PTB6/XTAL  
PTB5/TPMCH0  
PTB4  
6
7
8
PTB3/KBIP7/ADP7  
9
PTC3  
PTC2  
12  
11  
PTC0  
PTC1  
10  
Pins shown in bold type are lost in the next lower pin count package.  
Figure 2. MC9S08QL8 Series in 20-Pin TSSOP Package  
16  
15  
14  
13  
PTA0/KBIP0/TPMCH0/ADP0/ACMP+  
PTA1/KBIP1/ADP1/ACMP–  
PTA2/KBIP2/ADP2  
1
2
3
4
5
6
7
8
PTA5/IRQ/TCLK/RESET  
PTA4/ACMPO/BKGD/MS  
VDD  
PTA3/KBIP3/ADP3  
VSS  
12  
11  
PTB0/KBIP4/RxD/ADP4  
PTB1/KBIP5/TxD/ADP5  
PTB2/KBIP6/ADP6  
PTB7/EXTAL  
PTB6/XTAL  
10  
9
PTB5/TPMCH0  
PTB4  
PTB3/KBIP7/ADP7  
Figure 3. MC9S08QL8 Series in 16-Pin TSSOP Package  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
6
NXP Semiconductors  
Electrical Characteristics  
4
Electrical Characteristics  
4.1  
Introduction  
This chapter contains electrical and timing specifications for the MC9S08QL8 series of microcontrollers  
available at the time of publication.  
4.2  
Parameter Classification  
The electrical parameters shown in this supplement are guaranteed by various methods. To give the  
customer a better understanding the following classification is used and the parameters are tagged  
accordingly in the tables where appropriate:  
Table 3. Parameter Classifications  
Those parameters are guaranteed during production testing on each individual device.  
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant  
sample size across process variations.  
Those parameters are achieved by design characterization on a small sample size from typical devices  
under typical conditions unless otherwise noted. All values shown in the typical column are within this  
category.  
T
Those parameters are derived mainly from simulations.  
D
NOTE  
The classification is shown in the column labeled “C” in the parameter  
tables where appropriate.  
4.3  
Absolute Maximum Ratings  
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not  
guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent  
damage to the device. For functional operating conditions, refer to the remaining tables in this section.  
This device contains circuitry protecting against damage due to high static voltage or electrical fields;  
however, it is advised that normal precautions be taken to avoid application of any voltages higher than  
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused  
inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable  
SS  
DD  
pull-up resistor associated with the pin is enabled.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
7
Electrical Characteristics  
Table 4. Absolute Maximum Ratings  
Rating  
Symbol  
Value  
Unit  
Supply voltage  
VDD  
IDD  
VIn  
–0.3 to 3.8  
120  
V
mA  
V
Maximum current into VDD  
Digital input voltage  
–0.3 to VDD + 0.3  
Instantaneous maximum current  
ID  
25  
mA  
Single pin limit (applies to all port pins)1, 2, 3  
Storage temperature range  
Tstg  
–55 to 150  
C  
1
Input must be current limited to the value specified. To determine the value of the required  
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp  
voltages, then use the larger of the two resistance values.  
2
3
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD  
.
Power supply must maintain regulation within operating VDD range during instantaneous and  
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than  
IDD, the injection current may flow out of VDD and could result in external power supply going  
out of regulation. Ensure external VDD load will shunt current greater than maximum injection  
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if  
no system clock is present, or if the clock rate is very low (which would reduce overall power  
consumption).  
4.4  
Thermal Characteristics  
This section provides information about operating temperature range, power dissipation, and package  
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in  
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the  
MCU design. To take P into account in power calculations, determine the difference between actual pin  
I/O  
voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high  
SS  
DD  
pin current (heavy loads), the difference between pin voltage and V or V will be very small.  
SS  
Table 5. Thermal Characteristics  
DD  
Rating  
Symbol  
Value  
Unit  
TL to TH  
–40 to 85  
Operating temperature range (packaged)  
TA  
C  
Maximum junction temperature  
TJM  
95  
C  
Thermal resistance 16-pin TSSOP  
JA  
129  
C/W  
The average chip-junction temperature (T ) in C can be obtained from:  
J
T = T + (P   )  
JA  
Eqn. 1  
J
A
D
where:  
T = Ambient temperature, C  
A
= Package thermal resistance, junction-to-ambient, C/W  
JA  
P = P P  
D
int  
I/O  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
8
NXP Semiconductors  
Electrical Characteristics  
P
P
= I V , Watts — chip internal power  
DD DD  
= Power dissipation on input and output pins — user determined  
int  
I/O  
For most applications, P  P and can be neglected. An approximate relationship between P and T  
I/O  
int  
D
J
(if P is neglected) is:  
I/O  
P = K (T + 273C)  
Eqn. 2  
D
J
Solving Equation 1 and Equation 2 for K gives:  
2
K = P (T + 273C) +   (P )  
Eqn. 3  
D
A
JA  
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring  
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by  
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .  
A
4.5  
ESD Protection and Latch-Up Immunity  
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early  
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.  
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels  
of static without suffering any permanent damage.  
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade  
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body  
model (HBM), the machine model (MM) and the charge device model (CDM).  
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device  
specification. Complete DC parametric and functional testing is performed per the applicable device  
specification at room temperature followed by hot temperature, unless instructed otherwise in the device  
specification.  
Table 6. ESD and Latch-up Test Conditions  
Model  
Description  
Series resistance  
Symbol  
Value  
1500  
100  
3
Unit  
R1  
C
Human  
Body  
Storage capacitance  
Number of pulses per pin  
Series resistance  
pF  
—
R1  
C
0
Machine Storage capacitance  
Number of pulses per pin  
200  
3
pF  
—
Minimum input voltage limit  
Latch-up  
–2.5  
7.5  
V
V
Maximum input voltage limit  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
9
Electrical Characteristics  
Table 7. ESD and Latch-Up Protection Characteristics  
No.  
Rating1  
Symbol  
Min  
Max  
Unit  
1
2
Human body model (HBM)  
Charge device model (CDM)  
Latch-up current at TA = 85C  
VHBM  
VCDM  
ILAT  
2000  
500  
100  
—
—
—
V
V
3
mA  
1
Parameter is achieved by design characterization on a small sample size from typical devices  
under typical conditions unless otherwise noted.  
4.6  
DC Characteristics  
This section includes information about power supply requirements and I/O pin characteristics.  
Table 8. DC Characteristics  
Num C  
Characteristic  
Symbol  
Condition  
Min  
Typical1  
Max  
Unit  
1
2
P Operating Voltage  
VDD  
—
1.8  
—
3.6  
V
All I/O pins,  
low-drive strength  
VDD > 1.8 V,  
ILoad = –2 mA  
C
P
C
D
C
P
C
D
VDD – 0.5  
VDD – 0.5  
—
—
—
—
—
—
—
—
—
—
Output high  
voltage  
VDD > 2.7 V,  
ILoad = –10 mA  
VOH  
V
mA  
V
All I/O pins,  
high-drive strength  
V
DD > 1.8V,  
ILoad = –2 mA  
V
DD – 0.5  
—
Output high  
current  
Max total IOH for all ports IOHT  
VOUT < VDD  
0
–80  
0.5  
0.5  
0.5  
80  
3
4
All I/O pins,  
low-drive strength  
VDD > 1.8 V,  
ILoad = 0.6 mA  
—
—
—
0
Output low  
voltage  
VDD > 2.7 V,  
ILoad = 10 mA  
VOL  
All I/O pins,  
high-drive strength  
VDD > 1.8 V,  
ILoad = 3 mA  
5
6
Output low  
current  
Max total IOL for all ports  
all digital inputs  
IOLT  
VIH  
VOUT VSS  
mA  
V
P
C
P
C
VDD 2.7 V  
VDD 1.8 V  
VDD 2.7 V  
VDD 1.8 V  
0.70 x VDD  
—
—
—
—
—
Input high  
voltage  
0.85 x VDD  
—
—
—
0.35 x VDD  
0.30 x VDD  
Input low  
voltage  
7
8
all digital inputs  
VIL  
Input  
hysteresis  
C
all digital inputs Vhys  
—
0.06 x VDD  
—
—
mV  
nA  
Input  
P leakage  
current  
all input only pins  
|IIn|  
9
VIn = VDD or VSS  
—
—
200  
(Per pin)  
Hi-Z  
(off-state)  
leakage  
all input/output  
10  
P
|IOZ  
|
VIn = VDD or VSS  
—
—
200  
nA  
(per pin)  
current  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
10  
NXP Semiconductors  
Electrical Characteristics  
Table 8. DC Characteristics (continued)  
Num C  
Characteristic  
Symbol  
Condition  
Min  
Typical1  
Max  
Unit  
Total  
leakage  
combined  
for all inputs  
and Hi-Z  
pins  
10  
C
All input only and I/O |IOZTOT  
|
VIn = VDD or VSS  
—
—
2
A  
Pullup,  
11 P Pulldown  
resistors  
all digital inputs except  
PTA5/IRQ/TCLK/RESET,  
when enabled  
RPU,  
RPD  
—
—
17.5  
17.5  
—
—
52.5  
52.5  
k  
k  
Pullup,  
12 C Pulldown  
resistors  
PTA5/IRQ/TCLK/RESET, RPU,  
when enabled2  
RPD  
Single pin limit  
–0.2  
–5  
—
—
0.2  
5
mA  
mA  
DCinjection  
13 D current 3, 4,  
IIC  
VIN < VSS, VIN > VDD  
Total MCU limit, includes  
sum of all stressed pins  
5
14 C Input Capacitance, all pins  
15 C RAM retention voltage  
16 C POR re-arm voltage6  
17 D POR re-arm time  
CIn  
—
—
—
—
—
—
—
0.6  
1.4  
—
8
pF  
V
VRAM  
VPOR  
tPOR  
1.0  
2.0  
—
0.9  
10  
V
s  
VDD falling  
VDD rising  
1.80  
1.88  
1.84  
1.92  
1.88  
1.96  
18 P Low-voltage detection threshold  
VLVD  
VLVW  
V
V
VDD falling  
VDD rising  
19 P Low-voltage warning threshold  
Low-voltage inhibit reset/recover  
2.08  
2.14  
2.26  
20  
C
Vhys  
VBG  
—
—
—
80  
—
mV  
V
hysteresis  
21 P Bandgap Voltage Reference7  
1.15  
1.17  
1.18  
1
2
Typical values are measured at 25 C. Characterized, not tested  
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear lower when  
measured externally on the pin.  
3
4
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD  
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate  
resistance values for positive and negative clamp voltages, then use the larger of the two values.  
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current  
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could  
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum  
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is  
present, or if clock rate is very low (which would reduce overall power consumption).  
6
7
Maximum is highest voltage that POR is guaranteed.  
Factory trimmed at VDD = 3.0 V, Temp = 25 C  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
11  
Electrical Characteristics  
PULLUP RESISTOR TYPICALS  
40  
35  
30  
25  
20  
PULLDOWN RESISTOR TYPICALS  
85C  
40  
35  
30  
25  
20  
85C  
25C  
25C  
–40C  
–40C  
1.8  
2
2.2 2.4 2.6 2.8  
VDD (V)  
3
3.2 3.4 3.6  
1.8  
2.3  
2.8  
VDD (V)  
3.3  
3.6  
Figure 4. Pullup and Pulldown Typical Resistor Values (V = 3.0 V)  
DD  
TYPICAL VOL VS IOL AT VDD = 3.0 V  
TYPICAL VOL VS VDD  
0.2  
0.15  
0.1  
1.2  
1
85C  
25C  
–40C  
0.8  
0.6  
0.4  
0.2  
0
85  
25  
–40  
C, IOL = 2 mA  
0.05  
0
C, IOL = 2 mA  
C, IOL = 2 mA  
1
2
3
4
0
5
10  
15  
20  
VDD (V)  
I
OL (mA)  
Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)  
TYPICAL VOL VS VDD  
TYPICAL VOL VS IOL AT VDD = 3.0 V  
1
0.4  
0.3  
0.2  
0.1  
85C  
85C  
25C  
–40C  
25C  
0.8  
–40C  
0.6  
0.4  
0.2  
I
OL = 10 mA  
IOL = 6 mA  
I
OL = 3 mA  
VDD (V)  
0
0
0
10  
20  
30  
1
2
3
4
IOL (mA)  
Figure 6. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
12  
NXP Semiconductors  
Electrical Characteristics  
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V  
TYPICAL VDD – VOH VS VDD AT SPEC IOH  
1.2  
1
0.25  
0.2  
0.15  
0.1  
0.05  
0
85C  
85  
25  
–40  
C, IOH = 2 mA  
C, IOH = 2 mA  
C, IOH = 2 mA  
25C  
–40C  
0.8  
0.6  
0.4  
0.2  
0
0
–5  
–10  
IOH (mA))  
–15  
–20  
1
2
3
4
VDD (V)  
Figure 7. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)  
TYPICAL VDD – VOH VS VDD AT SPEC IOH  
0.4  
85C  
25C  
–40C  
TYPICAL V – V VS I AT V = 3.0 V  
DD  
OH  
OH  
DD  
0.3  
0.2  
0.1  
0.8  
85C  
25C  
0.6  
0.4  
0.2  
0
–40C  
IOH = –10 m  
IOH = –6 mA  
I
OH = –3 mA  
0
0
–5  
–10  
–15  
–20  
–25  
–30  
1
2
3
4
I
(mA)  
OH  
VDD (V)  
Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
13  
Electrical Characteristics  
4.7  
Supply Current Characteristics  
This section includes information about power supply current in various operating modes.  
Table 9. Supply Current Characteristics  
Parameter  
Run supply current  
VDD  
(V)  
Bus  
Temp  
Typical1  
Num  
C
Symbol  
Max  
Unit  
Freq  
(C)  
P
T
T
T
10 MHz  
1 MHz  
10 MHz  
1 MHz  
5.60  
0.80  
3.60  
0.75  
165  
6
1
RIDD  
mA  
–40 to 85C  
–40 to 85C  
FEI mode, all modules on  
3
3
—
—
—
Run supply current  
FEI mode, all modules off  
2
3
RIDD  
mA  
Run supply current  
LPRS=0, all modules off  
16 kHz  
FBILP  
T
T
T
—
—
—
RIDD  
3
A  
–40 to 85C  
–40 to 85C  
16 kHz  
FBELP  
105  
7.3  
Run supply current  
LPRS=1, all modules off  
16 kHz  
FBELP  
RIDD  
WIDD  
WIDD  
4
5
6
3
3
A  
A  
A  
T
T
Wait mode supply current  
FEI mode, all modules off  
10 MHz  
1 MHz  
570  
290  
1
—
—
–40 to 85C  
–40 to 85C  
Wait mode supply current  
LPRS = 1, all mods off  
16 kHz  
FBELP  
3
3
T
—
P
C
P
C
C
C
P
C
P
C
C
C
—
—
—
—
—
—
—
—
—
—
—
—
0.25  
0.5  
1
0.65  
0.8  
2
–40 to 25C  
70C  
85C  
7
Stop2 mode supply current  
S2IDD  
A  
0.2  
0.3  
0.7  
0.45  
1
0.5  
0.6  
1.6  
0.80  
1.8  
5.8  
0.6  
1.5  
5.0  
–40 to 25C  
70C  
2
3
2
85C  
–40 to 25C  
70C  
3
85C  
Stop3 mode supply current  
no clocks active  
8
S3IDD  
A  
0.3  
0.8  
2.5  
–40 to 25C  
70C  
85C  
1
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
14  
NXP Semiconductors  
Electrical Characteristics  
Table 10. Stop Mode Adders  
Temperature  
Num  
C
Parameter  
Condition  
Units  
–40C  
25C  
70C  
85C  
1
2
3
4
T
T
T
T
LPO  
—
50  
75  
1000  
70  
100  
1100  
77  
150  
1500  
81  
nA  
nA  
A  
nA  
ERREFSTEN  
IREFSTEN1  
RTC  
RANGE = HGO = 0  
—
1000  
63  
Does not include clock source  
current  
50  
75  
100  
150  
5
6
7
T
T
T
LVD1  
LVDSE = 1  
90  
18  
95  
100  
20  
110  
22  
115  
23  
A  
A  
A  
ACMP1  
ADC1  
Not using the bandgap (BGBE = 0)  
ADLPC = ADLSMP = 1  
106  
114  
120  
Not using the bandgap (BGBE = 0)  
1
Not available in stop2 mode.  
4.8  
External Oscillator (XOSC) Characteristics  
Reference Figure 9 and Figure 10 for crystal or resonator circuits.  
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85C Ambient)  
Num  
C
Characteristic  
Symbol  
Min  
Typ1  
Max  
Unit  
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)  
Low range (RANGE = 0)  
High range (RANGE = 1), high gain (HGO = 1)  
High range (RANGE = 1), low power (HGO = 0)  
flo  
fhi  
fhi  
32  
1
1
—
—
—
38.4  
16  
8
kHz  
MHz  
MHz  
1
C
Load capacitors  
Low range (RANGE=0), low power (HGO=0)  
Other oscillator settings  
See Note 2  
See Note 3  
C1,C2  
2
3
D
D
Feedback resistor  
Low range, low power (RANGE = 0, HGO = 0)2  
Low range, high gain (RANGE = 0, HGO = 1)  
High range (RANGE = 1, HGO = X)  
—
—
—
—
10  
1
—
—
—
RF  
M  
k  
Series resistor —  
Low range, low power (RANGE = 0, HGO = 0)2  
—
—
—
—
100  
0
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)  
High range, low power (RANGE = 1, HGO = 0)  
High range, high gain (RANGE = 1, HGO = 1)  
RS  
4
5
D
C
8 MHz  
4 MHz  
1 MHz  
—
—
—
0
0
0
0
10  
20  
Crystal start-up time 4  
Low range, low power  
Low range, high gain  
High range, low power  
High range, high gain  
t
—
—
—
—
600  
400  
5
—
—
—
—
CSTL  
ms  
t
CSTH  
15  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
15  
Electrical Characteristics  
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85C Ambient)  
Num  
C
Characteristic  
Symbol  
Min  
Typ1  
Max  
Unit  
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)  
FEE mode  
fextal  
6
D
0.03125  
0
—
—
20  
20  
MHz  
FBE or FBELP mode  
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.  
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.  
See crystal or resonator manufacturer’s recommendation.  
Proper PC board layout procedures must be followed to achieve specifications.  
XOSCVLP  
EXTAL  
XTAL  
RS  
RF  
Crystal or Resonator  
C1  
C2  
Figure 9. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain  
XOSCVLP  
EXTAL  
XTAL  
Crystal or Resonator  
Figure 10. Typical Crystal or Resonator Circuit: Low Range/Low Power  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
16  
NXP Semiconductors  
Electrical Characteristics  
4.9  
Internal Clock Source (ICS) Characteristics  
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)  
Num  
C
Characteristic  
Symbol  
Min.  
Typical1  
Max.  
Unit  
Average internal reference frequency — factory trimmed  
at VDD = 3.6 V and temperature = 25 C  
fint_t  
1
P
—
32.768  
—
kHz  
Internal reference frequency — user trimmed  
Internal reference start-up time  
fint_ut  
tIRST  
2
3
P
T
31.25  
—
—
60  
—
39.06  
100  
kHz  
s  
DCO output frequency range — Low range (DRS = 00)  
trimmed2  
16  
fdco_t  
4
5
6
7
P
P
C
C
20  
—
MHz  
MHz  
DCO output frequency2  
Reference = 32768 Hz and DMX32 = 1  
fdco_DMX32  
fdco_res_t  
fdco_res_t  
—
—
—
19.92  
0.1  
Resolution of trimmed DCO output frequency at fixed voltage  
and temperature (using FTRIM)  
%fdco  
%fdco  
0.2  
0.4  
Resolution of trimmed DCO output frequency at fixed voltage  
and temperature (not using FTRIM)  
0.2  
Total deviation of DCO output from trimmed frequency3  
Over full voltage and temperature range  
Over fixed voltage and temperature range of 0 to 70 C  
fdco_t  
%fdco  
8
C
—
–1.0 to 0.5  
2  
1  
0.5  
FLL acquisition time4  
tAcquire  
CJitter  
10  
C
C
—
—
—
1
ms  
Long term jitter of DCO output clock (averaged over 2-ms  
interval)5  
%fdco  
11  
0.02  
0.2  
1
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.  
2
3
4
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.  
This parameter is characterized and not tested on each device.  
This specification applies to any time the FLLreference source or reference divider is changed, trim value changed or changing  
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,  
this specification assumes it is already running.  
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus  
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise  
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for  
a given interval.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
17  
Electrical Characteristics  
1.00%  
0.50%  
0.00%  
-0.50%  
-1.00%  
-1.50%  
-2.00%  
-60  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
Temperature  
Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
18  
NXP Semiconductors  
Electrical Characteristics  
4.10 AC Characteristics  
This section describes timing characteristics for each peripheral system.  
4.10.1 Control Timing  
Table 13. Control Timing  
Num  
C
D
D
D
D
Rating  
Symbol  
fBus  
Min  
Typical1  
Max  
10  
Unit  
MHz  
s  
Bus frequency (tcyc = 1/fBus  
)
1
2
3
4
DC  
700  
—
—
—
—
tLPO  
Internal low power oscillator period  
1300  
—
External reset pulse width2  
Reset low drive  
textrst  
trstdrv  
100  
ns  
34 x tcyc  
—
ns  
BKGD/MS setup time after issuing background  
debug force reset to enter user or BDM modes  
tMSSU  
tMSH  
5
6
D
D
500  
100  
—
—
—
—
ns  
BKGD/MS hold time after issuing background debug  
force reset to enter user or BDM modes 3  
s  
IRQ pulse width  
Asynchronous path2  
Synchronous path4  
tILIH, IHIL  
t
100  
1.5 x tcyc  
—
—
—
—
ns  
ns  
7
D
8
D
Keyboard interrupt pulse width  
Asynchronous path2  
tILIH, IHIL  
t
100  
1.5 x tcyc  
—
—
—
—
Synchronous path4  
Port rise and fall time —  
Low output drive (PTxDS = 0) (load = 50 pF)5  
Slew rate control disabled (PTxSE = 0)  
Slew rate control enabled (PTxSE = 1)  
tRise  
tFall  
,
,
ns  
—
—
16  
23  
—
—
9
D
Port rise and fall time —  
High output drive (PTxDS = 1) (load = 50 pF)5  
Slew rate control disabled (PTxSE = 0)  
Slew rate control enabled (PTxSE = 1)  
tRise  
tFall  
ns  
—
—
5
9
—
—
Voltage regulator recovery time  
tVRR  
10  
D
—
4
—
s  
1
2
3
Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated.  
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.  
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD  
rises above VLVD  
.
4
5
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or  
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.  
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 85C.  
textrst  
RESET PIN  
Figure 12. Reset Timing  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
19  
Electrical Characteristics  
tIHIL  
KBIPx  
IRQ/KBIPx  
tILIH  
Figure 13. IRQ/KBIPx Timing  
4.10.2 TPM Module Timing  
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that  
can be used as the optional external source to the timer counter. These synchronizers operate from the  
current bus rate clock.  
Table 14. TPM Input Timing  
No.  
C
Function  
Symbol  
Min  
Max  
Unit  
1
2
3
4
5
D
D
D
D
D
External clock frequency  
External clock period  
fTEXT  
tTEXT  
DC  
4
1/4 fop  
—
MHz  
tCYC  
tCYC  
tCYC  
tCYC  
External clock high time  
External clock low time  
Input capture pulse width  
tTCLKH  
tTCLKL  
fICPW  
1.5  
1.5  
1.5  
—
—
—
tCYC  
ipg_clk  
tTEXT  
EXTERNAL  
CLOCK  
tTCLKL  
tTCLKH  
tICPW  
INPUT  
CAPTURE  
Figure 14. Timer Input Capture Pulse  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
20  
NXP Semiconductors  
Electrical Characteristics  
4.11 Analog Comparator (ACMP) Electricals  
Table 15. Analog Comparator Electrical Specifications  
C
Characteristic  
Symbol  
Min  
Typical  
Max  
Unit  
D
D
D
P
C
P
C
Supply voltage  
VPWR  
IDDAC  
VAIN  
VAIO  
VH  
1.8  
—
20  
—
3.6  
35  
V
Supply current (active)  
—
VSS – 0.3  
—
A  
V
Analog input voltage  
VDD  
40  
Analog input offset voltage  
Analog comparator hysteresis  
Analog input leakage current  
Analog comparator initialization delay  
20  
9.0  
—
mV  
mV  
A  
s  
3.0  
15.0  
1.0  
1.0  
IALKG  
tAINIT  
—
—
—
4.12 ADC Characteristics  
Table 16. 12-Bit ADC Operating Conditions  
Characteristic  
Conditions  
Symbol  
Min  
Typical1  
Max  
Unit  
Comment  
Absolute  
Delta to VDD (VDD – VDDA  
VDDA  
1.8  
—
3.6  
V
Supply voltage  
2
)
VDDA  
–100  
0
100  
mV  
2
Ground voltage Delta to VSS (VSS – VSSA  
)
VSSA  
IDDAD  
VADIN  
–100  
—
0
0.007  
—
100  
0.8  
mV  
A  
V
Supply Current  
Input Voltage  
Stop, Reset, Module Off  
VREFL  
VREFH  
Input  
Capacitance  
CADIN  
—
—
4.5  
5
5.5  
7
pF  
Input  
Resistance  
RADIN  
k  
12 bit mode  
fADCK > 4MHz  
fADCK < 4MHz  
—
—
—
—
2
5
Analog Source  
Resistance  
10 bit mode  
RAS  
k  
External to MCU  
fADCK > 4MHz  
fADCK < 4MHz  
—
—
—
—
5
10  
8 bit mode (all valid fADCK  
)
—
—
—
10  
ADC  
High Speed (ADLPC = 0)  
0.4  
8.0  
Conversion  
Clock Freq.  
fADCK  
MHz  
Low Power (ADLPC = 1)  
0.4  
—
4.0  
1
2
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference  
only and are not tested in production.  
DC potential difference.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
21  
Electrical Characteristics  
NOTE  
V
/V  
pins do not exist in package. The signals are derived internally  
DDA SSA  
by double bonding to V /V pair of pins.  
DD SS  
SIMPLIFIED  
INPUT PIN EQUIVALENT  
CIRCUIT  
ZADIN  
SIMPLIFIED  
CHANNEL SELECT  
CIRCUIT  
Pad  
ZAS  
leakage  
ADC SAR  
ENGINE  
due to  
input  
RAS  
RADIN  
protection  
+
VADIN  
–
CAS  
VAS  
+
–
RADIN  
RADIN  
RADIN  
INPUT PIN  
INPUT PIN  
INPUT PIN  
CADIN  
Figure 15. ADC Input Impedance Equivalency Diagram  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
22  
NXP Semiconductors  
Electrical Characteristics  
Table 17. 12-Bit ADC Characteristics (V  
= V  
, V  
= V  
)
SSA  
REFH  
DDA  
REFL  
Characteristic  
Conditions  
C
Symbol  
Min  
Typical1  
Max  
Unit  
Comment  
Supply Current  
ADLPC=1  
ADLSMP=1  
ADCO=1  
T
IDDAD  
—
120  
—
—
—
1
A  
A  
A  
mA  
Supply Current  
ADLPC=1  
ADLSMP=0  
ADCO=1  
T
T
T
IDDAD  
IDDAD  
IDDAD  
—
—
—
202  
288  
Supply Current  
ADLPC=0  
ADLSMP=1  
ADCO=1  
Supply Current  
ADLPC=0  
ADLSMP=0  
ADCO=1  
0.532  
Supply Current Stop, Reset, Module Off  
T
P
IDDAD  
—
2
0.007  
3.3  
0.8  
5
A  
ADC  
Asynchronous  
Clock Source  
High Speed (ADLPC = 0)  
Low Power (ADLPC = 1)  
tADACK  
=
fADACK  
MHz  
1/fADACK  
1.25  
—
2
3.3  
—
Short Sample  
(ADLSMP = 0)  
20  
Conversion  
Time(Including  
sample time)  
ADCK  
cycles  
T
T
tADC  
Long Sample  
(ADLSMP = 1)  
See reference  
manual for  
conversion  
—
—
—
40  
3.5  
—
—
—
Short Sample  
(ADLSMP = 0)  
time variances  
ADCK  
cycles  
Sample Time  
tADS  
ETUE  
DNL  
Long Sample  
(ADLSMP = 1)  
23.5  
12-bit mode  
10-bit mode  
8-bit mode  
12-bit mode  
10-bit mode  
8-bit mode  
T
P
T
T
P
T
—
—
—
—
—
—
—
—
—
—
—
—
—
Total  
Unadjusted  
Error  
Includes  
quantization  
1.5  
0.7  
—
LSB2  
LSB2  
0.5  
0.3  
Differential  
Non-Linearity  
Monotonicity and No-Missing-Codes guaranteed  
12-bit mode  
10-bit mode  
8-bit mode  
T
—
—
—
—
—
—
—
Integral  
Non-Linearity  
INL  
0.5  
0.3  
LSB2  
C
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
23  
Electrical Characteristics  
Table 17. 12-Bit ADC Characteristics (V  
= V  
, V  
= V  
) (continued)  
SSA  
REFH  
DDA  
REFL  
Characteristic  
Conditions  
12-bit mode  
C
Symbol  
Min  
Typical1  
Max  
Unit  
Comment  
C
P
T
T
T
T
—
—
—
—
—
—
—
—
—
—
0
—
1.5  
0.5  
—
—
2.1  
0.7  
—
Zero-Scale  
Error  
10-bit mode  
8-bit mode  
12-bit mode  
10-bit mode  
8-bit mode  
12-bit mode  
10-bit mode  
8-bit mode  
12-bit mode  
10-bit mode  
8-bit mode  
40C– 25C  
25C– 85C  
EZS  
EFS  
EQ  
LSB2  
VADIN = VSSA  
Full-Scale  
Error  
LSB2  
LSB2  
LSB2  
VADIN = VDDA  
1  
1.5  
0.5  
—
0.5  
—
Quantization  
Error  
D
D
—
0.5  
0.5  
—
—
—
Input Leakage  
Error  
Pad leakage3 *  
RAS  
EIL  
0.2  
0.1  
1.646  
1.769  
4  
0
1.2  
—
—
—
Temp Sensor  
Slope  
D
D
m
mV/C  
—
Temp Sensor  
Voltage  
25C  
VTEMP25  
—
701.2  
—
mV  
1
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference  
only and are not tested in production.  
1 LSB = (VREFH – VREFL)/2N  
2
3
Based on input pad leakage current. Refer to pad electricals.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
24  
NXP Semiconductors  
Electrical Characteristics  
4.13 Flash Specifications  
This section provides details about program/erase times and program-erase endurance for the flash  
memory.  
Program and erase operations do not require any special power sources other than the normal V supply.  
DD  
For more detailed information about program/erase operations, see the memory section.  
Table 18. Flash Characteristics  
C
Characteristic  
Symbol  
Min  
Typical  
Max  
Unit  
Supply voltage for program/erase  
-40C to 85C  
D
Vprog/erase  
VRead  
fFCLK  
1.8  
1.8  
150  
5
3.6  
3.6  
V
D
D
D
D
D
D
D
D
D
Supply voltage for read operation  
Internal FCLK frequency1  
Internal FCLK period (1/FCLK)  
Byte program time (random location)(2)  
Byte program time (burst mode)(2)  
Page erase time2  
V
200  
6.67  
kHz  
s  
tFcyc  
tprog  
9
tFcyc  
tFcyc  
tFcyc  
tFcyc  
mA  
mA  
tBurst  
4
4000  
20,000  
4
tPage  
Mass erase time(2)  
tMass  
Byte program current3  
RIDDBP  
RIDDPE  
—
—
—
—
Page erase current3  
6
Program/erase endurance4  
TL to TH = –40C to + 85C  
T = 25 C  
C
—
10,000  
15  
—
100,000  
—
—
cycles  
years  
C
Data retention5  
tD_ret  
100  
—
1
2
The frequency of this clock is controlled by a software setting.  
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied  
for calculating approximate time to program and erase.  
3
4
5
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures  
with VDD = 3.0 V, bus frequency = 4.0 MHz.  
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how  
NXP defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.  
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and  
de-rated to 25C using the Arrhenius equation. For additional information on how NXP defines typical data retention,  
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
NXP Semiconductors  
25  
4.14 EMC Performance  
Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the  
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external  
components as well as MCU software operation all play a significant role in EMC performance. The  
system designer should consult NXPapplications notes such as AN2321, AN1050, AN1263, AN2764, and  
AN1259 for advice and guidance specifically targeted at optimizing EMC performance.  
5
Part Identification  
This section contains ordering information for the device numbering system.  
Example of the device numbering system:  
8
C
XX  
MC 9 S08 QL  
Status  
(MC = Fully Qualified)  
Package designator (see Table 19)  
Temperature range  
(C = –40 C to 85 C)  
Memory  
(9 = Flash-based)  
Core  
Approximate flash size in KB  
Family  
Package Information  
6
Package Information  
Table 19. Package Descriptions  
Pin Count  
Package Type  
Abbreviation  
Designator  
Case No.  
Document No.  
20  
16  
Thin Shrink Small Outline Package  
Thin Shrink Small Outline Package  
TSSOP  
TSSOP  
TJ  
948E  
948F  
98ASH70169A  
98ASH70247A  
TG  
6.1  
Mechanical Drawings  
The following pages are mechanical drawings for the packages described in Table 19.  
MC9S08QL8 Series MCU Data Sheet, Rev. 1  
28  
NXP Semiconductors  
Information in this document is provided solely to enable system and software implementers to use  
NXP products. There are no express or implied copyright licenses granted hereunder to design or  
fabricate any integrated circuits based on the information in this document. NXP reserves the right to  
make changes without further notice to any products herein.  
How to Reach Us:  
Home Page:  
nxp.com  
Web Support:  
nxp.com/support  
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any  
particular purpose, nor does NXP assume any liability arising out of the application or use of any  
product or circuit, and specifically disclaims any and all liability, including without limitation  
consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets  
and/or specifications can and do vary in different applications, and actual performance may vary over  
time. All operating parameters, including "typicals," must be validated for each customer application  
by customer's technical experts. NXP does not convey any license under its patent rights nor the  
rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be  
found at the following address: nxp.com/SalesTermsandConditions.  
While NXP has implemented advanced security features, all products may be subject to unidentified  
vulnerabilities. Customers are responsible for the design and operation of their applications and  
products to reduce the effect of these vulnerabilities on customer's applications and products, and  
NXP accepts no liability for any vulnerability that is discovered. Customers should implement  
appropriate design and operating safeguards to minimize the risks associated with their applications  
and products.  
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,  
EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE  
CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,  
MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,  
TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C‑5, CodeTEST, CodeWarrior,  
ColdFire, ColdFire+, C‑Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,  
mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play, SafeAssure,  
the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet,  
Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, and UMEMS  
are trademarks of NXP B.V. All other product or service names are the property of their respective  
owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink,  
CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP,  
RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS,  
ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its  
subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of  
patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered  
trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word marks and the  
Power and Power.org logos and related marks are trademarks and service marks licensed by  
Power.org.  
© 2018 NXP B.V.  
Document Number MC9S08QL8  
Revision 1, 07/2018  

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