98ASH70169A_技术文档

Document Number MC9S08PA16

Rev. 4, 03/2020

NXP Semiconductors

Data Sheet: Technical Data

MC9S08PA16

MC9S08PA16 Series Data

MC9S08PA16A and MC9S08PA8A

are recommended for new design

Sheet

Supports: MC9S08PA16(A) and

MC9S08PA8(A)

Key features

• Development support

– Single-wire background debug interface

– Breakpoint capability to allow three breakpoints

setting during in-circuit debugging

– On-chip in-circuit emulator (ICE) debug module

containing two comparators and nine trigger modes

• 8-Bit S08 central processor unit (CPU)

– Up to 20 MHz bus at 2.7 V to 5.5 V across operating

temperature range of -40 °C to 105 °C for V part and

-40 °C to 125 °C for M part.

– Supporting up to 40 interrupt/reset sources

– Supporting up to four-level nested interrupt

– On-chip memory

– Up to 16 KB flash read/program/erase over full

operating voltage and temperature

– Up to 256 byte EEPROM; 2-byte erase sector;

program and erase while executing flash

– Up to 2048 byte random-access memory (RAM)

– Flash and RAM access protection

• Peripherals

– ACMP - one analog comparator with both positive

and negative inputs; separately selectable interrupt

on rising and falling comparator output; filtering

– ADC - 12-channel, 12-bit resolution; 2.5 µs

conversion time; data buffers with optional

watermark; automatic compare function; internal

bandgap reference channel; operation in stop mode;

optional hardware trigger

• Power-saving modes

– CRC - programmable cyclic redundancy check

module

– One low-power stop mode; reduced power wait

mode

– Peripheral clock enable register can disable clocks to

unused modules, reducing currents; allows clocks to

remain enabled to specific peripherals in stop3 mode

– FTM - two flex timer modulators modules including

one 6-channel and one 2-channel ones; 16-bit

counter; each channel can be configured for input

capture, output compare, edge- or center-aligned

PWM mode

• Clocks

– Oscillator (XOSC) - loop-controlled Pierce

oscillator; crystal or ceramic resonator range of

31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz

– Internal clock source (ICS) - containing a frequency-

locked-loop (FLL) controlled by internal or external

reference; precision trimming of internal reference

allowing 1% deviation across temperature range of 0

°C to 70 °C and 2% deviation across the whole

operating temperature; up to 20 MHz

– IIC - One inter-integrated circuit module; up to 400

kbps; multi-master operation; programmable slave

address; supporting broadcast mode and 10-bit

addressing; supporting SMBUS and PMBUS

– MTIM - One modulo timer with 8-bit prescaler and

overflow interrupt

– RTC - 16-bit real timer counter (RTC)

– SCI - two serial communication interface (SCI/

UART) modules optional 13-bit break; full duplex

non-return to zero (NRZ); LIN extension support

– SPI - one 8-bit serial peripheral interface (SPI)

modules; full-duplex or single-wire bidirectional;

master or slave mode

• System protection

– Watchdog with independent clock source

– Low-voltage detection with reset or interrupt;

selectable trip points

– Illegal opcode detection with reset

– Illegal address detection with reset

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• Input/Output

– Up to 37 GPIOs including one output-only pin

– One 8-bit keyboard interrupt module (KBI)

– Two true open-drain output pins

– Four, ultra-high current sink pins supporting 20 mA source/sink current

• Package options

– 44-pin LQFP

– 32-pin LQFP

– 20-pin SOIC; 20-pin TSSOP

– 16-pin TSSOP

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

2

NXP Semiconductors

Table of Contents

1

2

3

MCU block diagram...........................................................................4

6.2.1 Control timing..............................................................17

6.2.2 Debug trace timing specifications................................18

6.2.3 FTM module timing.....................................................19

6.3 Thermal specifications...............................................................20

6.3.1 Thermal characteristics................................................ 20

Peripheral operating requirements and behaviors..............................21

7.1 External oscillator (XOSC) and ICS characteristics..................21

7.2 NVM specifications...................................................................22

7.3 Analog........................................................................................24

7.3.1 ADC characteristics..................................................... 24

7.3.2 Analog comparator (ACMP) electricals...................... 27

7.4 Communication interfaces.........................................................27

7.4.1 SPI switching specifications........................................ 27

Dimensions.........................................................................................30

8.1 Obtaining package dimensions..................................................30

Pinout................................................................................................. 31

9.1 Signal multiplexing and pin assignments.................................. 31

9.2 Device pin assignment...............................................................33

Orderable part numbers......................................................................5

Part identification...............................................................................6

3.1 Description.................................................................................6

3.2 Format........................................................................................6

3.3 Fields..........................................................................................6

3.4 Example..................................................................................... 6

Parameter Classification.....................................................................7

Ratings................................................................................................7

5.1 Thermal handling ratings...........................................................7

5.2 Moisture handling ratings..........................................................7

5.3 ESD handling ratings.................................................................8

5.4 Voltage and current operating ratings........................................8

General............................................................................................... 9

6.1 Nonswitching electrical specifications...................................... 9

6.1.1 DC characteristics........................................................ 9

6.1.2 Supply current characteristics......................................15

6.1.3 EMC performance........................................................16

6.2 Switching specifications............................................................ 17

7

4

5

6

8

9

10 Revision history................................................................................. 35

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

3

MCU block diagram

1 MCU block diagram

The block diagram below shows the structure of the MCUs.

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

1

HCS08 CORE

PTA2/KBI0P2/RxD0/SDA

PTA3/KBI0P3/TxD0/SCL

1

2

PTA4/ACMPO/BKGD/MS

PTA5/IRQ/TCLK0/RESET

PTA6/FTM2FAULT1/ADP2

PTA7/FTM2FAULT2/ADP3

CPU

BDC

PTB0/KBI0P4/RxD0/ADP4

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTB3/KBI0P7/MOSI0/ADP7

SYSTEM INTEGRATION

KEYBOARD INTERRUPT

MODULE (SIM)

MODULE (KBI0)

3

PTB4/FTM2CH4/MISO0

3

WDG

IRQ

LVD

PTB5/FTM2CH5/SS0

INTER-INTEGRATED

CIRCUIT BUS (IIC)

PTB6/SDA/XTAL

PTB7/SCL/EXTAL

1 kHz OSC

PTC0/FTM2CH0/ADP8

PTC1/FTM2CH1/ADP9

PTC2/FTM2CH2/ADP10

PTC3/FTM2CH3/ADP11

PTC4/FTM0CH0

PTC5/FTM0CH1

PTC6/RxD1

PTC7/TxD1

8-BIT MODULO TIMER

INTERRUPT PRIORITY

(MTIM0)

CONTROLLER(IPC)

2-CH FLEX TIMER

ON-CHIP ICE AND

DEBUG MODUE (DBG)

MODULE (FTM0)

6-CH FLEX TIMER

3

USER FLASH

MC9S08PA16 = 16,384 bytes

MC9S08PA8 = 8,192 bytes

MODULE (FTM2)

PTD0/FTM2CH2

PTD1/FTM2CH3

3

SERIAL COMMUNICATION

PTD2

PTD3

PTD4

PTD5

PTD6

PTD7

INTERFACE (SCI0)

USER EEPROM

MC9S08PA16 = 256 bytes

MC9S08PA8 = 256 bytes

SERIAL COMMUNICATION

INTERFACE (SCI1)

ANALOG COMPARATOR

PTE0/SPSCK0

PTE1/MOSI0

PTE2/MISO0

PTE3/BUSOUT

PTE4/TCLK2

USER RAM

MC9S08PA16 = 2,048 bytes

MC9S08PA8 = 2,048 bytes

(ACMP)

REAL-TIME CLOCK

(RTC)

20 MHz INTERNAL CLOCK

SOURCE (ICS)

SERIAL PERIPHERAL

INTERFACE (SPI0)

EXTAL

XTAL

EXTERNAL OSCILLATOR

SOURCE (XOSC)

V

V_DD

V

DD

SS

4

POWER MANAGEMENT

CONTROLLER (PMC)

4

SS

V

REFH

DDA

REFL

SSA

12-CH 12-BIT

ANALOG-TO-DIGITAL

CONVERTER(ADC)

CYCLIC REDUNDANCY

CHECK (CRC)

1. PTA2 and PTA3 operate as true-open drain when working as output.

2. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin.

3. PTD0, PTD1, PTB4 and PTB5 can provide high sink/source current drive.

4. The secondary power pair of V and V (pin 11, 27 and 28 in 44-pin package) are not bonded in 32-pin, 20-pin or 16-pin packages.

DD

SS

Figure 1. MCU block diagram

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

4

NXP Semiconductors

Orderable part numbers

2 Orderable part numbers

The following table summarizes the part numbers of the devices covered by this

document.

Table 1. Ordering information

Feature

MC9S08PA16(A)

VWJ

MC9S08PA8(A)

VWJ

Part

Number

VLD

VLC

VTJ

MTJ

20

VTG

MTG

20

VLD

VLC

VTJ

VTG

MTG

20

Max.

frequency

(MHz)

20

16

20

8

20

Flash

memory

(KB)

16

8

RAM (KB)

2

EEPROM

(B)

256

12-bit

ADC

12ch

10ch

6ch

12ch

10ch

6ch

16-bit

6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 2ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 6ch+2ch 2ch+2ch

FlexTimer

8-bit

1

Modulo

timer

ACMP

RTC

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

8-bit SPI

I2C

1

SCI (LIN

Capable)

2

1

2

1

Watchdog

CRC

Yes

4

Yes

4

Yes

2

Yes

2

Yes

2

Yes

4

Yes

4

Yes

2

Yes

2

Yes

2

20mA

high-drive

pins

KBI pins

GPIO

8

37

28

18

14

37

28

18

14

Package 44-LQFP 32-LQFP 20-SOIC

20-

16-

44-LQFP 32-LQFP 20-SOIC

20-

16-

TSSOP

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

5

Part identification

3 Part identification

3.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

3.2 Format

Part numbers for this device have the following format:

MC 9 S08 PA AA (V) B CC

3.3 Fields

This table lists the possible values for each field in the part number (not all combinations

are valid):

Field

Description

Values

• MC = fully qualified, general market flow

• 9 = flash based

MC

9

Qualification status

Memory

S08

PA

AA

Core

• S08 = 8-bit CPU

Device family

• PA

Approximate flash size in KB

• 16 = 16 KB

• 8 = 8 KB

(V)

Mask set version

• (blank) = Any version

• A = Rev. 2 or later version, this is

recommended for new design

B

Operating temperature range (°C)

Package designator

• M = –40 to 125

• V = –40 to 105

CC

• LD = 44-LQFP

• LC = 32-LQFP

• TJ = 20-TSSOP

• WJ = 20-SOIC

• TG = 16-TSSOP

3.4 Example

This is an example part number:

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

6

NXP Semiconductors

Parameter Classification

MC9S08PA16AVLD

4 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods.

To give the customer a better understanding, the following classification is used and the

parameters are tagged accordingly in the tables where appropriate:

Table 2. Parameter Classifications

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size

across process variations.

T

Those parameters are achieved by design characterization on a small sample size from typical devices under

typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the

parameter tables where appropriate.

5 Ratings

5.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

5.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

7

Ratings

5.3 ESD handling ratings

Symbol

V_HBM

V_CDM

I_LAT

Description

Min.

-6000

-500

Max.

+6000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

Electrostatic discharge voltage, charged-device model

1

2

V

Latch-up current at ambient temperature of 105 °C for

V part and 125 °C for M part

-100

+100

mA

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

5.4 Voltage and current operating ratings

Absolute maximum ratings are stress ratings only, and functional operation at the

maxima is not guaranteed. Stress beyond the limits specified in below table may affect

device reliability or cause permanent damage to the device. For functional operating

conditions, refer to the remaining tables in this document.

This device contains circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid

application of any voltages higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate

logic voltage level (for instance, either V_SSor V_DD) or the programmable pullup resistor

associated with the pin is enabled.

Symbol

V_DD

Description

Min.

–0.3

—

Max.

6.0

Unit

V

Supply voltage

I_DD

Maximum current into V_DD

120

mA

V

V_DIO

Digital input voltage (except RESET, EXTAL, XTAL, or true

open drain pin PTA2 and PTA3)

–0.3

V_DD+ 0.3

Digital input voltage (true open drain pin PTA2 and PTA3)

Analog¹, RESET, EXTAL, and XTAL input voltage

-0.3

–0.3

–25

6

V_DD+ 0.3

25

V

V_AIO

I_D

Instantaneous maximum current single pin limit (applies to all

port pins)

mA

V_DDA

Analog supply voltage

V_DD– 0.3

V_DD+ 0.3

V

1. All digital I/O pins, except open-drain pin PTA2 and PTA3, are internally clamped to V_SSand V_DD. PTA2 and PTA3 is only

clamped to V_SS

.

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

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NXP Semiconductors

General

6 General

6.1 Nonswitching electrical specifications

6.1.1 DC characteristics

This section includes information about power supply requirements and I/O pin

characteristics.

Table 3. DC characteristics

Symbol

—

C

—

C

Descriptions

Operating voltage

Output high All I/O pins, standard- 5 V, I_load

Min

2.7

Typical¹

Max

5.5

—

Unit

V

—

V_OH

=

V_DD- 0.8

V

voltage

drive strength

-5 mA

C

D

3 V, I_load

-2.5 mA

V_DD- 0.8

—

V

High current drive

pins, high-drive

strength²

5 V, I_load

-20 mA

3 V, I_load

-10 mA

V

I_OHT

Output high

current

Max total I_OHfor all

ports

5 V

3 V

—

-100

-50

mA

V_OL

C

D

Output low All I/O pins, standard- 5 V, I_load= 5

0.8

V

voltage

drive strength

mA

3 V, I_load

2.5 mA

=

—

0.8

High current drive

pins, high-drive

strength²

5 V, I_load

=20 mA

V

3 V, I_load

10 mA

=

V

I_OLT

V_IH

V_IL

Output low

current

Max total I_OLfor all

ports

5 V

—

100

mA

3 V

50

P

C

P

C

Input high

voltage

All digital inputs

V_DD>4.5V

V_DD>2.7V

V_DD>4.5V

V_DD>2.7V

—

0.70 × V_DD

0.75 × V_DD

—

V

Input low

voltage

0.30 × V_DD

0.35 × V_DD

—

V_hys

|I_In|

Input

0.06 × V_DD

mV

µA

hysteresis

P

Input leakage

current

All input only pins

(per pin)

V_IN= V_DDor

V_SS

—

0.1

1

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

9

Nonswitching electrical specifications

Table 3. DC characteristics (continued)

Symbol

|I_OZ

C

Descriptions

Min

Typical¹

Max

Unit

|

P

Hi-Z (off-

state) leakage

current

All input/output (per V_IN= V_DDor

—

0.1

1

µA

pin)

V_SS

|I_OZTOT

|

C

P

Total leakage All input only and I/O V_IN= V_DDor

—

2

µA

kΩ

combined for

all inputs and

Hi-Z pins

V_SS

—

R_PU

Pullup

resistors

All digital inputs,

when enabled (all I/O

pins other than PTA2

and PTA3)

30.0

50.0

60.0

3

R_PU

P

D

Pullup

PTA2 and PTA3 pin

—

30.0

kΩ

resistors

I_IC

DC injection

current^{4, 5, 6}

Single pin limit

V_IN< V_SS

V_IN> V_DD

,

-0.2

-5

—

2

mA

Total MCU limit,

includes sum of all

stressed pins

25

C_In

C

Input capacitance, all pins

RAM retention voltage

—

7

pF

V

V_RAM

2.0

—

1. Typical values are measured at 25 °C. Characterized, not tested.

2. Only PTB4, PTB5, PTD0, PTD1 support ultra high current output.

3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured

externally on the pin.

4. All functional non-supply pins, except for , are internally clamped to V_SSand V_DD

.

5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the large one.

6. Power supply must maintain regulation within operating V_DDrange during instantaneous and operating maximum current

conditions. If the positive injection current (V_In> V_DD) is higher than I_DD, the injection current may flow out of V_DDand could

result in external power supply going out of regulation. Ensure that external V_DDload will shunt current higher than

maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is

very low (which would reduce overall power consumption).

Table 4. LVD and POR Specification

Symbol

V_POR

C

D

C

Description

Min

1.5

4.2

Typ

1.75

4.3

Max

2.0

Unit

V

POR re-arm voltage^{1, 2}

V_LVDH

Falling low-voltage detect

threshold - high range (LVDV

= 1)³

4.4

V

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

C

Falling low- Level 1 falling

4.3

4.5

4.6

4.7

4.4

4.5

4.6

4.7

4.5

4.6

4.7

4.8

V

voltage

warning

threshold -

high range

(LVWV = 00)

Level 2 falling

(LVWV = 01)

Level 3 falling

(LVWV = 10)

Level 4 falling

(LVWV = 11)

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

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NXP Semiconductors

Nonswitching electrical specifications

Table 4. LVD and POR Specification (continued)

Symbol

C

Description

Min

Typ

Max

Unit

V_HYSH

C

High range low-voltage

—

100

—

mV

detect/warning hysteresis

V_LVDL

C

Falling low-voltage detect

threshold - low range (LVDV =

0)

2.56

2.61

2.66

V

V_LVDW1L

V_LVDW2L

V_LVDW3L

V_LVDW4L

V_HYSDL

V_HYSWL

V_BG

C

P

Falling low- Level 1 falling

2.62

2.72

2.82

2.92

—

2.7

2.8

2.9

3.0

40

2.78

2.88

2.98

3.08

—

V

voltage

warning

threshold -

low range

(LVWV = 00)

Level 2 falling

(LVWV = 01)

Level 3 falling

(LVWV = 10)

V

Level 4 falling

(LVWV = 11)

V

Low range low-voltage detect

hysteresis

mV

V

Low range low-voltage

warning hysteresis

Buffered bandgap output ⁴

—

80

—

1.14

1.16

1.18

1. Maximum is highest voltage that POR is guaranteed.

2. POR ramp time must be longer than 20us/V to get a stable startup.

3. Rising thresholds are falling threshold + hysteresis.

4. Voltage factory trimmed at V_DD= 5.0 V, Temp = 25 °C

0.6

0.5

0.4

125°C

105°C

25°C

0.3

V_DD-V_OH(V)

0.2

0.1

0

-40°C

1

2

3

4

5

6

I_OH(mA)

Figure 2. Typical I_OHVs. V_DD-V_OH(standard drive strength) (V_DD= 5 V)

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

11

Nonswitching electrical specifications

1

0.9

0.8

0.7

0.6

125°C

105°C

25°C

0.5

V_DD-V_OH(V)

0.4

0.3

0.2

0.1

-40°C

0

1

2

3

4

5

6

I_OH(mA)

Figure 3. Typical I_OHVs. V_DD-V_OH(standard drive strength) (V_DD= 3 V)

0.7

0.6

0.5

0.4

125°C

105°C

25°C

V_DD-V_OH(V)

0.3

0.2

0.1

0

-40°C

5

10

15

20

25

I_OH(mA)

Figure 4. Typical I_OHVs. V_DD-V_OH(high drive strength) (V_DD= 5 V)

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

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NXP Semiconductors

Nonswitching electrical specifications

1.2

1

0.8

0.6

0.4

0.2

0

125°C

105°C

25°C

V_DD-V_OH(V)

-40°C

0

5

10

15

20

25

30

I_OH(mA)

Figure 5. Typical I_OHVs. V_DD-V_OH(high drive strength) (V_DD= 3 V)

0.5

0.4

0.3

0.2

0.1

0.0

125°C

105°C

25°C

V_OL(V)

-40°C

1

2

3

4

5

6

I_OL(mA)

Figure 6. Typical I_OLVs. V_OL(standard drive strength) (V_DD= 5 V)

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

13

Nonswitching electrical specifications

0.9

0.8

0.7

0.6

0.5

125°C

105°C

25°C

V_OL(V)

0.4

0.3

0.2

0.1

0

-40°C

1

2

3

4

5

6

I_OL(mA)

Figure 7. Typical I_OLVs. V_OL(standard drive strength) (V_DD= 3 V)

0.6

0.5

0.4

0.3

0.2

0.1

0

125°C

105°C

25°C

V_OL(V)

-40°C

5

10

15

20

25

I_OL(mA)

Figure 8. Typical I_OLVs. V_OL(high drive strength) (V_DD= 5 V)

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

14

NXP Semiconductors

Nonswitching electrical specifications

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

125°C

105°C

25°C

V_OL(V)

-40°C

5

10

15

20

25

I_OL(mA)

Figure 9. Typical I_OLVs. V_OL(high drive strength) (V_DD= 3 V)

6.1.2 Supply current characteristics

This section includes information about power supply current in various operating

modes.The data in the following table was based on the operating temperature range

unless otherwise stated.

Table 5. Supply current characteristics

Num

C

Parameter

Symbol

Bus Freq

20 MHz

10 MHz

1 MHz

V_DD(V)

Typical¹

7.60

4.65

1.90

7.05

4.40

1.85

5.88

3.70

1.85

5.35

3.42

1.80

10.9

6.10

1.69

Max

—

Unit

1

Run supply current FEI mode,

all modules on; run from flash

RI_DD

5

mA

—

C

20 MHz

10 MHz

1 MHz

3

5

3

5

—

2

3

C

Run supply current FEI mode,

all modules off & gated; run

from flash

RI_DD

20 MHz

10 MHz

1 MHz

—

mA

—

C

20 MHz

10 MHz

1 MHz

—

P

C

Run supply current FBE

mode, all modules on; run

from RAM

RI_DD

20 MHz

10 MHz

1 MHz

15.0

—

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

15

Nonswitching electrical specifications

Table 5. Supply current characteristics (continued)

Num

C

P

Parameter

Symbol

Bus Freq

20 MHz

10 MHz

1 MHz

20 MHz

10 MHz

1 MHz

20 MHz

10 MHz

1 MHz

20 MHz

10 MHz

1 MHz

20 MHz

10 MHz

1 MHz

—

V_DD(V)

Typical¹

8.18

5.14

1.44

8.50

5.07

1.59

6.11

4.10

1.34

5.95

3.50

1.24

5.45

3.25

1.20

1.35

1.3

Max

—

Unit

3

C

—

4

P

C

Run supply current FBE

mode, all modules off &

gated; run from RAM

RI_DD

5

3

5

3

14.0

—

mA

—

P

C

—

5

P

C

Wait mode current FEI mode,

all modules on

WI_DD

—

mA

—

C

—

6

7

C

Stop3 mode supply current

no clocks active (except 1kHz

LPO clock)^{2, 3}

S3I_DD

—

5

3

—

µA

—

C

ADC adder to stop3

ADLPC = 1

—

5

3

40

39

—

ADLSMP = 1

ADCO = 1

MODE = 10B

ADICLK = 11B

LVD adder to stop3⁴

8

C

—

5

3

128

124

—

µA

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. RTC adder cause <1 µA I_DDincrease typically, RTC clock source is 1kHz LPO clock.

3. ACMP adder cause <10 µA I_DDincrease typically.

4. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.

6.1.3 EMC performance

Electromagnetic compatibility (EMC) performance is highly dependent on the

environment in which the MCU resides. Board design and layout, circuit topology

choices, location and characteristics of external components as well as MCU software

operation all play a significant role in EMC performance. The system designer should

consult NXP applications notes such as AN2321, AN1050, AN1263, AN2764, and

AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

16

NXP Semiconductors

Switching specifications

6.1.3.1 EMC radiated emissions operating behaviors

Table 6. EMC radiated emissions operating behaviors for 44-pin LQFP package

Symbol

Description

Frequency

band (MHz)

Typ.

Unit

Notes

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

8

5

N

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of

Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the

measured orientations in each frequency range.

2. V_DD= 5.0 V, T_A= 25 °C, f_OSC= 10 MHz (crystal), f_SYS= 20 MHz, f_BUS= 20 MHz

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method

6.2 Switching specifications

6.2.1 Control timing

Table 7. Control timing

Num

C

P

Rating

Bus frequency (t_cyc= 1/f_Bus

Symbol

f_Bus

Min

DC

Typical¹

Max

20

Unit

MHz

KHz

ns

1

2

3

)

—

1.0

—

C

D

Internal low power oscillator frequency

External reset pulse width²

f_LPO

—

t_extrst

1.5 ×

t_cyc

—

4

5

D

Reset low drive

t_rstdrv

34 × t_cyc

500

—

ns

BKGD/MS setup time after issuing background

debug force reset to enter user or BDM modes

t_MSSU

6

7

D

BKGD/MS hold time after issuing background

debug force reset to enter user or BDM modes³

t_MSH

t_ILIH

100

—

ns

IRQ pulse width

Asynchronous

path²

D

Synchronous path⁴

t_IHIL

t_ILIH

1.5 × t_cyc

100

—

ns

8

Keyboard interrupt pulse

width

Asynchronous

path²

D

Synchronous path

t_IHIL

1.5 × t_cyc

—

ns

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

17

Switching specifications

Table 7. Control timing (continued)

Num

C

Rating

Symbol

t_Rise

Min

—

Typical¹

10.2

Max

—

Unit

ns

9

Port rise and fall time -

standard drive strength

(load = 50 pF)⁵

—

t_Fall

—

9.5

—

ns

C

Port rise and fall time -

high drive strength (load =

50 pF)⁵

t_Rise

t_Fall

—

5.4

4.6

—

ns

1. Typical values are based on characterization data at V_DD= 5.0 V, 25 °C unless otherwise stated.

2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.

3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of t_MSHafter

V_DDrises above V_LVD

.

4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

5. Timing is shown with respect to 20% V_DDand 80% V_DDlevels, across operating temperature range.

t_extrst

RESET PIN

Figure 10. Reset timing

t_IHIL

KBIPx

IRQ/KBIPx

t_ILIH

Figure 11. IRQ/KBIPx timing

6.2.2 Debug trace timing specifications

Table 8. Debug trace operating behaviors

Symbol

Description

Min.

Max.

Unit

MHz

ns

t_cyc

t_wl

t_wh

t_r

Clock period

Frequency dependent

Low pulse width

High pulse width

Clock and data rise time

Clock and data fall time

Data setup

2

—

3

ns

—

3

ns

t_f

3

ns

t_s

—

ns

t_h

Data hold

2

ns

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

18

NXP Semiconductors

Switching specifications

TRACECLK

T

r

T

f

T

wh

wl

T

cyc

Figure 12. TRACE_CLKOUT specifications

TRACE_CLKOUT

TRACE_D[3:0]

Ts

Th

Ts

Th

Figure 13. Trace data specifications

6.2.3 FTM module timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the

fastest clock that can be used as the optional external source to the timer counter. These

synchronizers operate from the current bus rate clock.

Table 9. FTM input timing

No.

C

Function

Symbol

Min

Max

Unit

1

D

External clock

frequency

f_TCLK

0

f_Bus/4

Hz

2

3

4

5

D

External clock

period

t_TCLK

t_clkh

4

—

t_cyc

External clock

high time

1.5

External clock

low time

t_clkl

Input capture

pulse width

t_ICPW

t_TCLK

t_clkh

TCLK

t_clkl

Figure 14. Timer external clock

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

19

Thermal specifications

t_ICPW

FTMCHn

t_ICPW

Figure 15. Timer input capture pulse

6.3 Thermal specifications

6.3.1 Thermal characteristics

This section provides information about operating temperature range, power dissipation,

and package thermal resistance. Power dissipation on I/O pins is usually small compared

to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-

determined rather than being controlled by the MCU design. To take P_I/Ointo account in

power calculations, determine the difference between actual pin voltage and V_SSor V_DD

and multiply by the pin current for each I/O pin. Except in cases of unusually high pin

current (heavy loads), the difference between pin voltage and V_SSor V_DDwill be very

small.

Table 10. Thermal characteristics

Rating

Symbol

Value

Unit

1

Operating temperature range T_A

(packaged)

T_Lto T_H

°C

• -40 to 125 for M part

• -40 to 105 for V part

Junction temperature range

T_J

• -40 to 135 for M part

• -40 to 125 for V part

Thermal resistance single-layer board

44-pin LQFP

32-pin LQFP

20-pin SOIC

20-pin TSSOP

16-pin TSSOP

R_θJA

76

°C/W

88

82

116

130

Thermal resistance four-layer board

44-pin LQFP

32-pin LQFP

20-pin SOIC

20-pin TSSOP

16-pin TSSOP

R_θJA

54

59

54

76

87

°C/W

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

20

NXP Semiconductors

Peripheral operating requirements and behaviors

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed the maximum. The simplest method to

determine T_Jis: T_J= T_A+ R_θJAx chip power dissipation.

7 Peripheral operating requirements and behaviors

7.1 External oscillator (XOSC) and ICS characteristics

Table 11. XOSC and ICS specifications (temperature range = -40 to 105 °C for V part and -40

to 125 °C for M part ambient)

Num

C

Characteristic

Low range (RANGE = 0)

Symbol

Min

31.25

4

Typical¹

32.768

—

Max

39.0625

20

Unit

kHz

1

Oscillator

crystal or

resonator

f_lo

f_hi

High range (RANGE = 1)

FEE or FBE mode²

MHz

C

High range (RANGE = 1),

high gain (HGO = 1),

FBELP mode

f_hi

4

—

20

MHz

High range (RANGE = 1),

low power (HGO = 0),

FBELP mode

f_hi

2

3

D

Load capacitors

C1, C2

R_F

See Note³

—

Feedback

resistor

Low Frequency, Low-Power

Mode⁴

—

MΩ

Low Frequency, High-Gain

Mode

10

1

High Frequency, Low-

Power Mode

High Frequency, High-Gain

Mode

1

4

5

D

Series resistor -

Low Frequency

Low-Power Mode ⁴

High-Gain Mode

Low-Power Mode⁴

R_S

—

200

—

kΩ

Series resistor -

High Frequency

D

Series resistor -

High

Frequency,

High-Gain Mode

4 MHz

8 MHz

16 MHz

—

0

—

kΩ

6

7

C

Crystal start-up

time Low range

= 32.768 kHz

crystal; High

Low range, low power

Low range, high power

High range, low power

High range, high power

t_CSTL

—

1000

800

3

—

ms

t_CSTH

range = 20 MHz

1.5

crystal⁵, ⁶

T

Internal reference start-up time

t_IRST

—

20

50

µs

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

21

Peripheral operating requirements and behaviors

Table 11. XOSC and ICS specifications (temperature range = -40 to 105 °C for V part and -40

to 125 °C for M part ambient) (continued)

Num

C

D

Characteristic

FEE or FBE mode²

FBELP mode

Symbol

Min

0.03125

0

Typical¹

Max

5

Unit

MHz

8

Square wave

input clock

frequency

f_extal

—

20

9

P

Average internal reference frequency -

trimmed

f_{int_t}

—

31.25

—

kHz

10

11

P

DCO output frequency range - trimmed

f_{dco_t}

16

—

20

MHz

Total deviation

of DCO output

from trimmed

frequency⁵

Over full voltage and

temperature range

Δf_{dco_t}

2.0

%f_dco

C

Over fixed voltage and

temperature range of 0 to

70 °C

1.0

12

13

C

FLL acquisition time⁵, ⁷

t_Acquire

C_Jitter

—

2

ms

Long term jitter of DCO output clock

(averaged over 2 ms interval)⁸

0.02

0.2

%f_dco

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.

2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25

kHz to 39.0625 kHz.

3. See crystal or resonator manufacturer's recommendation.

4. Load capacitors (C₁,C₂), feedback resistor (R_F) and series resistor (R_S) are incorporated internally when RANGE = HGO =

0.

5. This parameter is characterized and not tested on each device.

6. Proper PC board layout procedures must be followed to achieve specifications.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or

changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as

the reference, this specification assumes it is already running.

8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_Bus

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FLL circuitry via V_DDand V_SSand variation in crystal oscillator frequency increase the C_Jitterpercentage

for a given interval.

XOSC

EXTAL

XTAL

R_S

R_F

Crystal or Resonator

C₁

C₂

Figure 16. Typical crystal or resonator circuit

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

22

NXP Semiconductors

Peripheral operating requirements and behaviors

7.2 NVM specifications

This section provides details about program/erase times and program/erase endurance for

the flash and EEPROM memories.

Table 12. Flash clock characteristics

C

Characteristic

Symbol

Min

Typical

Max

Unit

D

Supply voltage for program/erase

V_prog/erase

2.7

—

5.5

V

across the operating temperature range

D

C

Supply voltage for read operation

NVM Bus frequency

V_Read

f_NVMBUS

f_NVMOP

n_FLPE

2.7

1

—

5.5

20

V

MHz

Cycles

NVM operating frequency

0.8

10 k

1.0

1.05

—

FLASH Program/erase endurance T_Lto

T_Hin the operating temperature range

100 k

C

EEPROM Program/erase endurance T_L

to T_Hin the operating temperature

range

n_FLPE

50 k

15

500 k

100

—

Cycles

years

Data retention at an average junction

temperature of T_Javg= 85°C after up to

10,000 program/erase cycles

t_{D_ret}

All timing parameters are a function of the bus clock frequency, F_NVMBUS. All program

and erase times are also a function of the NVM operating frequency, f_NVMOP

.

Each command timing is given by:

t_command=f_NVMOPcycle × 1/f_NVMOP+ f_NVMBUScycle × 1/f_NVMBUS

Table 13. Flash timing characteristics

C

D

Characteristic

Erase Verify All Blocks

Erase Verify Flash Block

Erase Verify EEPROM Block

Erase Verify Flash Section

Erase Verify EEPROM Section

Read Once

Symbol

t_VFYALL

t_RD1BLK

t_RD1SEC

t_DRD1SEC

t_RDONCE

t_PGM2

f_NVMOPcycle

f_NVMBUScycle

5050

4631

810

—

494

—

555

—

450

Program Flash (2 word)

Program Flash (4 word)

Program Once

68

1407

2138

2090

1371

2120

2869

3618

5455

t_PGM4

122

47

t_PGMONCE

t_DPGM1

t_DPGM2

t_DPGM3

t_DPGM4

t_ERSALL

Program EEPROM (1 Byte)

Program EEPROM (2 Byte)

Program EEPROM (3 Byte)

Program EEPROM (4 Byte)

Erase All Blocks

94

141

188

100066

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

23

Peripheral operating requirements and behaviors

Table 13. Flash timing characteristics (continued)

C

D

Characteristic

Erase Flash Block

Symbol

t_ERSBLK

t_ERSPG

f_NVMOPcycle

100060

20015

5015

f_NVMBUScycle

4954

Erase Flash Sector

878

Erase EEPROM Sector

Unsecure Flash

t_DERSPG

t_UNSECU

t_VFYKEY

t_MLOADU

756

100066

—

5442

Verify Backdoor Access Key

Set User Margin Level

464

—

413

Program and erase operations do not require any special power sources other than the

normal V_DDsupply. For more detailed information about program/erase operations, see

the Memory section.

7.3 Analog

7.3.1 ADC characteristics

Table 14. 5 V 12-bit ADC operating conditions

Characteri

stic

Conditions

Symb

Min

Typ¹

Max

Unit

Comment

Supply

voltage

Absolute

V_DDA

ΔV_DDA

ΔV_SSA

2.7

—

0

5.5

V

—

Delta to V_DD(V_DD-V_DDAD

)

-100

+100

mV

2

Ground

voltage

Delta to V_SS(V_SS-V_SSA

)

0

Input

voltage

V_ADIN

C_ADIN

R_ADIN

R_AS

V_REFL

—

4.5

3

V_REFH

5.5

V

Input

capacitance

pF

kΩ

Input

resistance

—

5

—

Analog

source

resistance

12-bit mode

f_ADCK> 4 MHz

f_ADCK< 4 MHz

External to

MCU

—

2

5

•

10-bit mode

f_ADCK> 4 MHz

f_ADCK< 4 MHz

—

5

•

10

8-bit mode

(all valid f_ADCK

)

ADC

conversion

clock

High speed (ADLPC=0)

Low power (ADLPC=1)

f_ADCK

0.4

—

8.0

4.0

MHz

—

frequency

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

24

NXP Semiconductors

Peripheral operating requirements and behaviors

1. Typical values assume V_DDA= 5.0 V, Temp = 25°C, f_ADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2. DC potential difference.

SIMPLIFIED

INPUT PIN EQUIVALENT

z _ADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

Z_AS

leakage

due to

input

ADC SAR

ENGINE

R _AS

R _ADIN

protection

v _ADIN

C _AS

v _AS

R _ADIN

INPUT PIN

C _ADIN

Figure 17. ADC input impedance equivalency diagram

Table 15. 12-bit ADC Characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Characteristic

Supply current

ADLPC = 1

Conditions

C

Symb

Min

Typ¹

Max

Unit

T

I_DDA

—

133

—

µA

ADLSMP = 1

ADCO = 1

Supply current

ADLPC = 1

T

I_DDA

—

218

327

582

—

µA

ADLSMP = 0

ADCO = 1

Supply current

ADLPC = 0

I_DDA

ADLSMP = 1

ADCO = 1

Supply current

ADLPC = 0

I_DDAD

990

ADLSMP = 0

ADCO = 1

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

25

Peripheral operating requirements and behaviors

Table 15. 12-bit ADC Characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Characteristic

Conditions

C

Symb

Min

Typ¹

Max

Unit

Supply current

Stop, reset, module

off

T

I_DDA

—

0.011

1

µA

ADC asynchronous High speed (ADLPC

P

T

f_ADACK

2

1.25

—

3.3

2

5

3.3

—

MHz

clock source

= 0)

Low power (ADLPC

= 1)

Conversion time

(including sample

time)

Short sample

(ADLSMP = 0)

t_ADC

20

ADCK

cycles

Long sample

—

40

(ADLSMP = 1)

Sample time

Short sample

(ADLSMP = 0)

t_ADS

—

3.5

23.5

ADCK

cycles

Long sample

—

(ADLSMP = 1)

Total unadjusted

Error²

12-bit mode

10-bit mode

8-bit mode

T

P

T

P

T

C

P

T

D

E_TUE

DNL

INL

—

5.0

1.5

—

LSB³

2.0

1.0

—

0.7

Differential Non-

Linearity

12-bit mode

10-bit mode⁴

8-bit mode⁴

1.0

0.25

0.15

1.0

0.5

0.25

—

Integral Non-Linearity 12-bit mode

10-bit mode

0.3

0.5

0.25

—

8-bit mode

0.15

2.0

Zero-scale error⁵

Full-scale error⁶

Quantization error

12-bit mode

10-bit mode

8-bit mode

E_ZS

0.25

0.65

2.5

1.0

—

12-bit mode

10-bit mode

8-bit mode

E_FS

0.5

1.0

0.5

≤12 bit modes

E_Q

E_IL

m

—

LSB³

mV

Input leakage error⁷all modes

I_In* R_AS

3.266

3.638

1.396

Temp sensor slope

-40°C– 25°C

25°C– 125°C

—

mV/°C

Temp sensor voltage 25°C

D

V_TEMP25

V

1. Typical values assume V_DDA= 5.0 V, Temp = 25°C, f_ADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2. Includes quantization.

3. 1 LSB = (V_REFH- V_REFL)/2^N

4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes

5. V_ADIN= V_SSA

6. V_ADIN= V_DDA

7. I_In= leakage current (refer to DC characteristics)

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

26

NXP Semiconductors

Peripheral operating requirements and behaviors

7.3.2 Analog comparator (ACMP) electricals

Table 16. Comparator electrical specifications

C

D

T

Characteristic

Supply voltage

Symbol

V_DDA

I_DDA

V_AIN

V_AIO

V_H

Min

2.7

Typical

—

Max

5.5

20

Unit

V

Supply current (Operation mode)

Analog input voltage

—

10

µA

V

D

P

C

T

V_SS- 0.3

—

V_DDA

40

Analog input offset voltage

Analog comparator hysteresis (HYST=0)

Analog comparator hysteresis (HYST=1)

Supply current (Off mode)

Propagation Delay

—

mV

nA

µs

—

15

20

V_H

—

20

30

I_DDAOFF

t_D

—

60

—

C

—

0.4

1

7.4 Communication interfaces

7.4.1 SPI switching specifications

The serial peripheral interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables

provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of

the chip's reference manual for information about the modified transfer formats used for

communicating with slower peripheral devices. All timing is shown with respect to 20%

V_DDand 70% V_DD, unless noted, and 100 pF load on all SPI pins. All timing assumes

high drive strength is enabled for SPI output pins.

Table 17. SPI master mode timing

Nu

m.

Symbol Description

Min.

Max.

Unit

Comment

1

f_op

Frequency of operation

f_Bus/2048

f_Bus/2

Hz

f_Busis the bus

clock

2

3

4

5

6

7

8

t_SPSCK

t_Lead

t_Lag

SPSCK period

Enable lead time

Enable lag time

2 x t_Bus

1/2

2048 x t_Bus

ns

t_SPSCK

ns

t_Bus= 1/f_Bus

—

1/2

—

t_WSPSCKClock (SPSCK) high or low time

t_Bus- 30

15

1024 x t_Bus

t_SU

t_HI

t_v

Data setup time (inputs)

Data hold time (inputs)

—

25

ns

0

ns

Data valid (after SPSCK edge)

—

ns

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

27

Peripheral operating requirements and behaviors

Table 17. SPI master mode timing (continued)

Nu

m.

Symbol Description

Min.

Max.

Unit

Comment

9

t_HO

t_RI

Data hold time (outputs)

0

—

ns

—

10

Rise time input

Fall time input

Rise time output

Fall time output

—

t_Bus- 25

t_FI

11

t_RO

t_FO

—

25

ns

—

1

SS

(OUTPUT)

3

2

10

11

4

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

8

MSB IN

LSB IN

9

MOSI

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 18. SPI master mode timing (CPHA=0)

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

28

NXP Semiconductors

Peripheral operating requirements and behaviors

1

SS

(OUTPUT)

2

10

11

4

3

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

LSB IN

MSB IN

9

8

MOSI

(OUTPUT)

2

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 19. SPI master mode timing (CPHA=1)

Table 18. SPI slave mode timing

Nu

m.

Symbol

Description

Min.

Max.

Unit

Comment

1

f_op

Frequency of operation

0

f_Bus/4

Hz

f_Busis the bus clock as

defined in .

2

3

4

5

6

7

8

t_SPSCK

t_Lead

t_Lag

SPSCK period

Enable lead time

Enable lag time

4 x t_Bus

—

ns

t_Bus

ns

t_Bus= 1/f_Bus

1

—

t_WSPSCKClock (SPSCK) high or low time

t_Bus- 30

15

—

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

—

ns

25

—

ns

—

t_Bus

ns

Time to data active from

high-impedance state

9

t_dis

Slave MISO disable time

—

t_Bus

ns

Hold time to high-

impedance state

10

11

12

t_v

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

—

0

25

—

ns

—

t_HO

t_RI

—

t_Bus- 25

t_FI

Fall time input

13

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

29

Dimensions

SS

(INPUT)

2

12

13

4

SPSCK

(CPOL=0)

(INPUT)

5

3

SPSCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 20. SPI slave mode timing (CPHA = 0)

SS

(INPUT)

4

2

12

13

3

SPSCK

(CPOL=0)

(INPUT)

5

SPSCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

8

6

7

MOSI

(INPUT)

MSB IN

NOTE: Not defined

Figure 21. SPI slave mode timing (CPHA=1)

8 Dimensions

8.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

30

NXP Semiconductors

Pinout

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

16-pin TSSOP

Then use this document number

98ASH70247A

20-pin SOIC

98ASB42343B

20-pin TSSOP

98ASH70169A

32-pin LQFP

98ASH70029A

44-pin LQFP

98ASS23225W

9 Pinout

9.1 Signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

Table 19. Pin availability by package pin-count

Pin Number

Lowest Priority <-- --> Highest

44-LQFP 32-LQFP 20-TSSOP 16-TSSOP

Port Pin

PTD1¹

PTD0¹

PTE4

PTE3

—

Alt 1

Alt 2

FTM2CH3

FTM2CH2

TCLK2

BUSOUT

—

Alt 3

Alt 4

—

1

2

1

2

—

3

—

3

—

3

—

3

—

4

—

5

—

V_DD

V_REFH

V_REFL

V_SS

EXTAL

XTAL

Vss

—

6

4

—

4

—

4

—

V_DDA

V_SSA

—

7

5

—

8

6

—

9

7

5

PTB7

PTB6

—

PTB5¹

PTB4¹

PTC3

PTC2

PTD7

PTD6

—

SCL

SDA

—

10

11

12

13

14

15

16

17

8

6

—

9

—

7

—

7

—

FTM2CH5

FTM2CH4

FTM2CH3

FTM2CH2

—

SS0

MISO0

ADP11

ADP10

—

10

11

12

—

8

—

9

—

10

—

Table continues on the next page...

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

31

Pinout

Table 19. Pin availability by package pin-count (continued)

Pin Number

44-LQFP 32-LQFP 20-TSSOP 16-TSSOP

Lowest Priority <-- --> Highest

Port Pin

PTD5

PTC1

PTC0

PTB3

PTB2

PTB1

PTB0

PTA7

PTA6

—

Alt 1

Alt 2

—

Alt 3

Alt 4

—

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

—

13

14

15

16

17

18

19

20

—

21

22

23

24

25

26

27

28

—

29

30

31

32

—

11

12

13

14

15

16

—

17

18

19

20

—

1

—

9

—

ADP9

ADP8

ADP7

ADP6

ADP5

ADP4

ADP3

ADP2

—

FTM2CH1

FTM2CH0

MOSI0

SPSCK0

TXD0

—

KBI0P7

KBI0P6

KBI0P5

KBI0P4

—

10

11

12

—

13

14

15

16

—

1

—

RXD0

—

FTM2FAULT2

FTM2FAULT1

—

Vss

V_DD

—

PTD4

PTD3

PTD2

PTA3²

PTA2²

PTA1

PTA0

PTC7

PTC6

PTE2

PTE1

PTE0

PTC5

PTC4

PTA5

PTA4

—

KBI0P3

KBI0P2

KBI0P1

KBI0P0

—

TXD0

SCL

SDA

ACMP1

ACMP0

—

RXD0

—

FTM0CH1

FTM0CH0

TxD1

ADP1

ADP0

—

RxD1

—

MISO0

MOSI0

SPSCK0

FTM0CH1

FTM0CH0

TCLK0

ACMPO

—

IRQ

—

RESET

MS

2

BKGD

1. This is a high current drive pin when operated as output.

2. This is a true open-drain pin when operated as output.

Note

When an alternative function is first enabled, it is possible to

get a spurious edge to the module. User software must clear any

associated flags before interrupts are enabled. The table above

illustrates the priority if multiple modules are enabled. The

highest priority module will have control over the pin. Selecting

a higher priority pin function with a lower priority function

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

32

NXP Semiconductors

Pinout

already enabled can cause spurious edges to the lower priority

module. Disable all modules that share a pin before enabling

another module.

9.2 Device pin assignment

2

1

33

32

31

30

29

28

27

26

25

24

23

PTA2/KBI0P2/RxD0/SDA

1

2

PTD1/FTM2CH3

PTD0/FTM2CH2

2

PTA3/KBI0P3/TxD0/SCL

PTD2

PTD3

PTD4

3

PTE4/TCLK2

PTE3/BUSOUT

4

V

5

DD

V

/V

REFH

6

V

DDA

DD

V

/V

REFL

7

V

SSA

SS

V

8

SS

PTA6/FTM2FAULT1/ADP2

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

9

PTA7/FTM2FAULT2/ADP3

PTB0/KBI0P4/RxD0/ADP4

PTB1/KBI0P5/TxD0/ADP5

10

11

V

SS

Pins in bold are not available on less pin-count packages.

1. High source/sink current pins

2. True open drain pins

Figure 22. MC9S08PA16 44-pin LQFP package

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

33

Pinout

1

2

1

2

3

4

5

6

7

8

PTD1/FTM2CH3

PTD0/FTM2CH2

24

23

22

21

20

19

18

17

PTA2/KBI0P2/RxD0/SDA

2

PTA3/KBI0P3/TxD0/SCL

V

PTD2

PTD3

DD

DDA REFH

V

/V

V

PTA6/FTM2FAULT1/ADP2

PTA7/FTM2FAULT2/ADP3

PTB0/KBI0P4/RxD0/ADP4

PTB1/KBI0P5/TxD0/ADP5

SSA REFL

V

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

Pins in

are not available on less pin-count packages.

bold

1. High source/sink current pins

2. True open drain pins

Figure 23. MC9S08PA16 32-pin LQFP package

PTA5/IRQ/TCLK0/RESET

PTA4/ACMPO/BKGD/MS

20

19

18

17

16

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

1

2

V

PTA2/KBI0P2/RxD0/SDA

3

DD

2

V

PTA3/KBI0P3/TxD0/SCL

SS

4

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

PTB0/KBI0P4/RxD0/ADP4

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTB3/KBI0P7/MOSI0/ADP7

PTC0/FTM2CH0/ADP8

5

15

14

13

6

1

PTB5/FTM2CH5/SS0

7

1

PTB4/FTM2CH4/MISO0

8

PTC3/FTM2CH3/ADP11

PTC2/FTM2CH2/ADP10

12

11

9

10

PTC1/FTM2CH1/ADP9

Pins in bold are not available on less pin-count packages.

1. High source/sink current pins

2. True open drain pins

Figure 24. MC9S08PA16 20-pin SOIC and TSSOP package

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

34

NXP Semiconductors

Revision history

16

PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0

PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1

PTA5/IRQ/TCLK0/RESET

PTA4/ACMPO/BKGD/MS

1

2

3

4

5

6

7

8

15

14

13

2

V

PTA2/KBI0P2/RxD0/SDA

DD

2

V

PTA3/KBI0P3/TxD0/SCL

SS

PTB7/SCL/EXTAL

PTB6/SDA/XTAL

12

11

10

9

PTB0/KBI0P4/RxD0/ADP4

PTB1/KBI0P5/TxD0/ADP5

PTB2/KBI0P6/SPSCK0/ADP6

PTB3/KBI0P7/MOSI0/ADP7

1

PTB5/FTM2CH5/SS0

1

PTB4/FTM2CH4/MISO0

Pins in

bold are not available on less pin-count packages.

1. High source/sink current pins

2. True open drain pins

Figure 25. MC9S08PA16 16-pin TSSOP package

10 Revision history

The following table provides a revision history for this document.

Table 20. Revision history

Rev. No.

Date

Substantial Changes

1

2

10/2012

09/2014

Initial public release

• Updated V_OHand V_OLin DC characteristics

• Updated footnote on the S3I_DDin Supply current characteristics

• Added EMC radiated emissions operating behaviors

• Updated the typical of f_{int_t}to 31.25 kHz and updated footnote to

t_Acquirein External oscillator (XOSC) and ICS characteristics

• Updated the assumption for all the timing values in SPI switching

specifications

• Updated the rating descriptions for t_Riseand t_Fallin Control timing

• Updated the part number format to add new field for new part

numbers in Fields

3

4

06/2015

03/2020

• Corrected the Min. of the t_extrstin Control timing

• Updated Thermal characteristics to add footnote to the T_Aand

removed redundant information.Updated the symbol of θ_JAto R_θJA

.

• Added MCU block diagram.

• Added new parts of MC9S08PA16AMTJ, MC9S08PA16AMTG and

MC9S08PA8AMTG and updated related information in the whole

book.

• Added new section of Orderable part numbers

• Updated T_jin the Thermal characteristics.

• Updated flash characteristics in the NVM specifications

• Updated S3I_DDvalues in the Supply current characteristics

MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020

NXP Semiconductors

35

How to Reach Us:

Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

Home Page:

nxp.com

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any

particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including “typicals,” must be validated for each customer application

by customerʼs technical experts. NXP does not convey any license under its patent rights nor the

rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be

found at the following address: nxp.com/SalesTermsandConditions.

While NXP has implemented advanced security features, all products may be subject to unidentified

vulnerabilities. Customers are responsible for the design and operation of their applications and

products to reduce the effect of these vulnerabilities on customer's applications and products, and

NXP accepts no liability for any vulnerability that is discovered. Customers should implement

appropriate design and operating safeguards to minimize the risks associated with their applications

and products.

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the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV, mobileGT, PEG, PowerQUICC,

Processor Expert, QorIQ, QorIQ Qonverge, SafeAssure, the SafeAssure logo, StarCore, Symphony,

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Engine, Tower, TurboLink, EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP

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Document Number MC9S08PA16

Revision 4, 03/2020


型号：	98ASH70169A
厂家：	NXP
描述：	MC9S08PA16A and MC9S08PA8A are recommended for new design
文件：	总36页 (文件大小：757K)
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