ADC1113D125_11 [NXP]
Dual 11-bit ADC; serial JESD204A interface; 双11位ADC ; JESD204A串行接口型号: | ADC1113D125_11 |
厂家: | NXP |
描述: | Dual 11-bit ADC; serial JESD204A interface |
文件: | 总41页 (文件大小:537K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
Rev. 3 — 10 February 2011
Product data sheet
1. General description
The ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimized
for high dynamic performance and low power at a sample rate of 125 Msps. Pipelined
architecture and output error correction ensure the ADC1113D125 is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A format. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a programmable full-scale SPI to allow flexible input
voltage range of 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1113D125 ideal for use in communications, imaging,
and medical applications.
2. Features and benefits
SNR, 66.5 dBFS; SFDR, 86 dBc
Input bandwidth, 600 MHz
Power dissipation, 1270 mW
SPI register programming
Sample rate: 125 Msps
Clock input divided by 2 for less jitter
contribution
3 V, 1.8 V single supplies
Duty Cycle Stabilizer (DCS)
High IF capability
Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
Two configurable serial outputs
Offset binary, two’s complement, gray
code
Two JESD204A serial outputs
Power-down mode and Sleep mode
Pin compatible with ADC1613D series, HVQFN56 package
ADC1413D series, and
ADC1213D series
3. Applications
Wireless and wired broadband
Portable instrumentation
communications
Spectral analysis
Ultrasound equipment
Imaging systems
Software defined radio
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msps)
Package
Name
Description
Version
ADC1113D125HN/C1 125
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
5. Block diagram
CFG (0 to 3)
SDIO
SPI
SCLK
CS
ERROR
CORRECTION AND
DIGITAL
SYNCP
SYNCN
PROCESSING
INAP
INAM
SWING_n
T/H
INPUT
STAGE
ADC A CORE
11-BIT
PIPELINED
D11 to D0
OTR
SERIALIZER A
CMLPA
CMLNA
8-bit
8-bit
10-bit
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
OUTPUT
BUFFER A
CLKP
CLKM
DLL
PLL
ERROR
CORRECTION AND
DIGITAL
CMLPB
CMLNB
SERIALIZER B
8-bit
8-bit
10-bit
PROCESSING
OUTPUT
BUFFER B
OTR
INBP
INBM
T/H
INPUT
STAGE
ADC B CORE
11-BIT
PIPELINED
D11 to D0
SWING_n
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC1113D
REFBT
REFBB
VCMB
SENSE VREF
REFAB
REFAT
VCMA
SCRAMBLER RESET
005aaa165
Fig 1. Block diagram
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
2 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INAP
INAM
DGND
DGND
VDDD
CMLPA
CMLNA
VDDD
DGND
DGND
VDDD
CMLNB
CMLPB
VDDD
DGND
DGND
3
VCMA
REFAT
REFAB
AGND
CLKP
4
5
6
7
ADC1113D
8
CLKM
AGND
REFBB
REFBT
VCMB
INBM
9
10
11
12
13
14
INBP
005aaa166
Transparent top view
Fig 2. Pinning diagram
6.2 Pin description
Table 2.
Symbol
INAP
Pin description
Pin
1
Type [1]
Description
I
channel A analog input
INAM
2
I
channel A complementary analog input
channel A output common voltage
channel A top reference
channel A bottom reference
analog ground
VCMA
REFAT
REFAB
AGND
CLKP
3
O
O
O
G
I
4
5
6
7
clock input
CLKM
AGND
REFBB
REFBT
VCMB
INBM
8
I
complementary clock input
analog ground
9
G
O
O
O
I
10
11
12
13
channel B bottom reference
channel B top reference
channel B output common voltage
channel B complementary analog input
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
3 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
Table 2.
Pin description …continued
Type [1]
Symbol
INBP
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Description
I
channel B analog input
analog power supply 3 V
analog power supply 3 V
SPI clock
VDDA
VDDA
SCLK
P
P
I
SDIO
I/O
I
SPI data IO
CS
chip select
AGND
RESET
SCRAMBLER
CFG0
G
I
analog ground
JEDEC digital IP reset
scrambler enable and disable
see Table 28 (input) or OTRA (output)[2]
see Table 28 (input) or OTRB (output)[2]
see Table 28 (input)
I
I/O
I/O
I/O
I/O
P
G
G
G
P
O
O
P
G
G
P
O
O
P
G
G
I
CFG1
CFG2
CFG3
see Table 28 (input)
VDDD
DGND
DGND
DGND
VDDD
CMLPB
CMLNB
VDDD
DGND
DGND
VDDD
CMLNA
CMLPA
VDDD
DGND
DGND
SYNCP
SYNCN
DGND
VDDD
SWING_0
SWING_1
DNC
digital power supply 1.8 V
digital ground
digital ground
digital ground
digital power supply 1.8 V
channel B output
channel B complementary output
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
digital power supply 1.8 V
digital ground
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
I
G
P
I
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
do not connect
I
O
P
G
G
VDDA
AGND
AGND
analog power supply 3 V
analog ground
analog ground
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
4 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
Table 2.
Pin description …continued
Symbol
VDDA
SENSE
VREF
Pin
53
54
55
56
Type [1]
Description
P
analog power supply 3 V
reference programming pin
voltage reference input/output
analog power supply 3 V
I
I/O
P
VDDA
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B.
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA
VDDD
Tstg
Parameter
Conditions
Min
−0.4
−0.4
−55
−40
-
Max
+4.6
+2.5
+125
+85
Unit
V
analog supply voltage
digital supply voltage
storage temperature
ambient temperature
junction temperature
V
°C
°C
°C
Tamb
Tj
125
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
17.8
6.8
K/W
K/W
Rth(j-c)
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
ADC1113D125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
5 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
9. Static characteristics
Table 5.
Symbol
Supplies
VDDA
Static characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
digital supply voltage
analog supply current
2.85
1.65
-
3.0
1.8
343
3.4
1.95
-
V
VDDD
V
IDDA
fclk = 125 Msps;
fi = 70 MHz
mA
IDDD
digital supply current
fclk = 125 Msps;
fi = 70 MHz
-
150
-
mA
Ptot
P
total power dissipation
power dissipation
fclk = 125 Msps
Power-down mode
Standby mode
-
-
-
1270
30
-
-
-
mW
mW
mW
200
Clock inputs: pins CLKP and CLKM (AC-coupled)
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Vi(clk)dif
differential clock input
voltage
peak-to-peak
-
-
±1.6
±3.0
-
-
V
V
SINE
Vi(clk)dif
differential clock input
voltage
peak-to-peak
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDDA
-
V
V
0.7VDDA
Logic inputs, Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, SWING_1, and RESET
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
-
0
-
V
-
0.66VDDD
-
V
−6
−30
-
-
+6
+30
μA
μA
IIH
SPI: pins CS, SDIO, and SCLK
VIL
VIH
IIL
LOW-level input voltage
0
-
0.3VDDA
VDDA
+10
V
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0.7VDDA
−10
−50
-
-
V
-
μA
μA
pF
IIH
CI
-
+50
4
-
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
6 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
Table 5.
Symbol
Static characteristics[1] …continued
Parameter Conditions
Min
Typ
Max
Unit
Analog inputs: pins INAP, INAM, INBP, and INBM
II
input current
track mode
track mode
track mode
track mode
−5
-
-
+5
-
μA
Ω
RI
input resistance
input capacitance
15
5
CI
-
-
pF
V
VI(cm)
common-mode input
voltage
0.9
1.5
2
Bi
input bandwidth
-
600
-
-
MHz
V
VI(dif)
differential input voltage peak-to-peak
1
2
Voltage controlled regulator output: pins VCMA and VCMB
VO(cm)
common-mode output
voltage
-
-
VDDA / 2
4
-
-
V
IO(cm)
common-mode output
current
mA
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
output
input
0.5
0.5
-
-
1
1
V
V
Data outputs: pins CMLPA, CMLNA
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.5
-
-
-
-
V
V
V
V
1.35
1.8
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.65
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.45
1.275
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.625
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.4
1.2
1.8
1.6
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.35
1.125
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.575
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.3
-
-
-
-
V
V
V
V
1.05
1.8
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.55
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
7 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
Table 5.
Symbol
Static characteristics[1] …continued
Parameter Conditions
Min
Typ
Max
Unit
Serial configuration: pins SYNCCP, SYNCCN
VIL
LOW-level input voltage differential; input
HIGH-level input voltage differential; input
-
-
0.95
1.47
-
-
V
V
VIH
Accuracy
INL
integral non-linearity
−5
-
+5
LSB
LSB
DNL
differential non-linearity no missing codes
guaranteed
−0.95
±0.25
+0.95
Eoffset
EG
offset error
-
-
-
±2
-
-
-
mV
%
gain error
full-scale
± 0.5
1.1
MG(CTC)
channel-to-channel gain
matching
%
Supply
PSRR
power supply rejection
ratio
200 mV (p-p) on pin
VDDA; fi = DC
-
−54
-
dB
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode;
100 Ω differential applied to serial outputs; unless otherwise specified.
ADC1113D125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
8 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 6.
Symbol
Dynamic characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
Analog signal processing
α2H
second harmonic level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
87
85
83
α3H
third harmonic level
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
86
84
82
THD
ENOB
SNR
SFDR
IMD
total harmonic distortion
effective number of bits
signal-to-noise ratio
84
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
83
81
79
10.7
10.7
10.7
10.6
66.2
66.2
66.0
65.8
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
bits
bits
bits
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
spurious-free dynamic range fi = 3 MHz
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
86
84
82
intermodulation distortion
channel crosstalk
fi = 3 MHz
89
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 70 MHz
88
86
84
αct(ch)
100
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode;
100 Ω differential applied to serial outputs; unless otherwise specified.
ADC1113D125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
9 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
10.2 Clock and digital output timing
Table 7.
Symbol
Characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
data latency time
clock duty cycle
100
-
-
125
-
Msps
tlat(data)
δclk
14
50
50
0.8
76
clock cycle
DCS_EN = logic 1
DCS_EN = logic 0
30
45
-
70
55
-
%
%
td(s)
sampling delay time
wake-up time
ns
μs
twake
-
-
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode;
100 W differential applied to serial outputs; unless otherwise specified.
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC coupling with two different receiver common-mode voltages
005aaa088
Fig 3. Eye diagram at 1 V receiver common-mode
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
10 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
005aaa089
Fig 4. Eye diagram at 2 V receiver common-mode
10.4 SPI timing
Table 8.
Symbol
Serial Peripheral Interface timing
SPI timing characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
tw(SCLK)
SCLK pulse width
-
-
40
16
-
-
ns
ns
tw(SCLKH)
SCLK HIGH pulse
width
tw(SCLKL)
tsu
SCLK LOW pulse
width
-
16
-
ns
set-up time
data to SCLK H
CS to SCLK H
data to SCLK H
CS to SCLK H
-
-
-
-
-
5
-
-
-
-
-
ns
5
ns
th
hold time
2
ns
2
ns
fclk(max)
maximum clock
frequency
25
MHz
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF. Minimum and maximum
values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V;
VI (INAP, INBP) − VI (INAM,INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial
outputs; unless otherwise specified.
t
t
su
w(SCLKL)
t
h
t
h
su
t
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 5. SPI timing
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
11 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1113D125 supports a differential or a single-ended input
drive. Optimal performance is achieved using differential inputs with the common-mode
input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2 and Table 21).
Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
package
ESD
parasitics
switch
R
= 15 Ω
on
4 pF
1, 14
INAP
INBP
C
s
internal
clock
switch
on
R
= 15 Ω
4 pF
2, 13
INAM
INBM
C
s
internal
clock
005aaa069
Fig 6. Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
ADC1113D125
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
12 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
INPA/
INBP
R
R
C
INAM/
INBM
001aan679
Fig 7. Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Table 9.
RC coupling versus input frequency - typical values
Input frequency (MHz)
Resistance (Ω)
Capacitance (pF)
3
25
12
12
12
8
70
170
8
11.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
100 nF
25 Ω
INAP
100 nF
ADT1-1WT
Analog
INBP
input
25 Ω
12 pF
100 nF
25 Ω
100 nF
25 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa070
Fig 8. Single transformer configuration
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
ADT1-1WT
ADT1-1WT
12 Ω
INAP
INBP
100 nF
50 Ω
50 Ω
50 Ω
Analog
input
8.2 pF
50 Ω
12 Ω
INAM
INBM
100 nF
VCM
100 nF
100 nF
005aaa071
Fig 9. Dual transformer configuration
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1113D125 has a stable and accurate built-in internal reference voltage to adjust
the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF
an SENSE (see Figure 11 to Figure 14), in 1 dB steps between 0 dB and −6 dB, via SPI
control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21). The equivalent
reference circuit is shown in Figure 10. An external reference is also possible by providing
a voltage on pin VREF as described in Figure 13.
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
REFAT/
REFBT
REFERENCE
AMP
REFAB/
REFBB
VREF
EXT_ref
EXT_ref
BANDGAP
REFERENCE
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
001aan670
Fig 10. Reference equivalent schematic
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 10.
Table 10. Reference modes
Mode
SPI Bit, “Internal
reference”
SENSE pin
VREF pin
Full-scale
(V (p-p))
Internal (Figure 11)
Internal (Figure 12)
External (Figure 13)
0
0
0
1
GND
330 pF capacitor
to GND
2
VREF pin = SENSE pin and
330 pF capacitor to GND
1
VDDA
external voltage 1 to 2
from 0.5 V to 1 V
Internal, SPI mode
(Figure 14)
VREF pin = SENSE pin and
330 pF capacitor to GND
1 to 2
ADC1113D125
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NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
VREF
330 pF
0.1 μF
V
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 13. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
11.2.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 11).
Table 11. Programmable full-scale
INTREF[2:0]
000
Level (dB)
Full-scale (V (p-p))
0
2
001
−1
1.78
1.59
1.42
1.26
1.12
1
010
−2
011
−3
100
−4
101
−5
110
−6
111
not used
x
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Dual 11-bit ADC; serial JESD204A interface
11.2.3 Common-mode output voltage (VO(cm)
)
An 0.1 μF filter capacitor should be connected between the pins VCMA and VCMB and
ground to ensure a low-noise common-mode output voltage. When AC-coupled, these
pins can be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCMA
VCMB
0.1 μF
ADC CORE
005aaa077
Fig 15. Reference equivalent schematic
11.2.4 Biasing
The common-mode input voltage, VI(cm), at the inputs to the sample-and-hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
11.3 Clock input
11.3.1 Drive modes
The ADC1113D125 can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
CLKP
CLKM
LVCMOS
clock input
CLKP
CLKM
LVCMOS
clock input
005aaa174
005aaa053
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
CLKP
CLKM
Sine
clock input
CLKP
CLKM
Sine
clock input
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKM
LVPECL
clock input
005aaa172
c. LVPECL clock input
Fig 17. Differential clock input
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via 5 kΩ internal resistors.
package
ESD
parasitics
CLKP
CLKM
V
cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
005aaa081
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3 Clock input divider
The ADC1113D125 contains an input clock divider that divides the incoming clock by a
factor of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user
to deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.3.4 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12. Duty cycle stabilizer
Bit DCS_EN
Description
0
1
duty cycle stabilizer disable
duty cycle stabilizer enable
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
VDDD
50 Ω
CMLPA/CLMPB
100 Ω
RECEIVER
CMLNA/CLMNB
AGND
+
−
12 mA to 26 mA
005aaa082
Fig 19. CML output connection to the receiver (DC-coupled)
The output should be terminated when 100 Ω (typical) is reached at the receiver side.
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
VDDD
50 Ω
CMLPA/CMLPB
10 nF
100 Ω
RECEIVER
CMLNA/CMLNB
10 nF
+
−
12 mA to 26 mA
005aaa083
Fig 20. CML output connection to the receiver (AC-coupled)
11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
L LANES
F octets
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
N bits from Cr
+
8-bit/
10-bit
0
SCRAMBLER
SER
LANE 0
CS bits for control
TX transport layer
SYNC~
TX CONTROLLER
samples stream to
lane stream mapping
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
N bits from Cr
CS bits for control
+
8-bit/
10-bit
M−1
F octets
SCRAMBLER
SER
LANE 1
N' = N+CS
S samples per frame cycle
CF: position of control bits
HD: frame boundary break
Padding with Tail bits (TT)
005aaa084
Mx(N'xS) bits
Lx(F) octets
L octets
Fig 21. General overview of the JESD204A serializer
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
ADC_MODE[1:0]
SCR_IN_MODE[1:0]
PRBS
11
N
&
CS
LANE_MODE[1:0]
10 00
DUMMY
11 + 1 10
11 + 1
N + CS
8
00
01
8-bit/
10-bit
SCR
PRBS
LANE_POL
ADC_PD
ADC A
'0'
01
10
11
SER
11 + 1 00
'0/1'
bypass alignment
disable_char_repl
PRBS
FSM
(frame assembly
character
replication
ILA
× 1
× F
frame CLK
PLL
AND
DLL
FRAME
ASSEMBLY
character CLK
SWING_SEL[2:0]
× 10F bit CLK
test mode)
PRBS
'0/1'
'0'
11
10
sync_request
SER
ADC B
11 + 1 00
01
ADC_PD
LANE_POL
PRBS
8
01
00
8-bit/
10-bit
10 00
SCR
N
&
CS
11 + 1 10
11
11 + 1
N + CS
DUMMY
PRBS
LANE_MODE[1:0]
SCR_IN_MODE[1:0]
005aaa167
ADC_MODE[1:0]
Fig 22. Detailed view of the JESD204A serializer with debug functionality
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13. Output codes
VINP − VINM
< −1
Offset binary
000 0000 0000
000 0000 0000
000 0000 0001
000 0000 0010
000 0000 0011
000 0000 0100
....
Two’s complement
100 0000 0000
100 0000 0000
100 0000 0001
100 0000 0010
100 0000 0011
100 0000 0100
....
OTR pin
1
0
0
0
0
0
0
0
0
0
0
0
0
0
−1.0000000
−0.9990234
−0.9980469
−0.9970703
−0.996093
....
−0.0019531
−0.0009766
0.0000000
+0.0009766
+0.0019531
....
011 1111 1110
011 1111 1111
100 0000 0000
100 0000 0001
100 0000 0010
....
111 1111 1110
111 1111 1111
000 0000 0000
000 0000 0001
000 0000 0010
....
+0.9960938
111 1111 1011
011 1111 1011
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
Table 13. Output codes
VINP − VINM
+0.9970703
+0.9980469
+0.9990234
+1.0000000
> +1
Offset binary
111 1111 1100
111 1111 1101
111 1111 1110
111 1111 1111
111 1111 1111
Two’s complement
011 1111 1100
011 1111 1101
011 1111 1110
011 1111 1111
011 1111 1111
OTR pin
0
0
0
0
1
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1113D125 serial interface is a synchronous serial communications port allowing
for easy interfacing with many industry microprocessors. It provides access to the
registers that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and pin CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14. SPI instruction bytes
MSB
7
LSB
0
Bit
6
5
4
3
2
1
Description
R/W[1]
W1
A6
W0
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
A7
[1] R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte.
Table 15. Read or Write mode access description
R/W[1]
Description
0
1
Write mode operation
Read mode operation
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16. Number of bytes to be transferred
W1
0
W0
0
Number of bytes transferred
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
The steps involved in a data transfer are as follows:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
CS
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
11.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel receives the next
SPI-instruction. By default the channel A and B receives the same instructions in write
mode. In read mode only A is active.
ADC1113D125
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Product data sheet
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23 of 41
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17. Register allocation map
Address Register name Access[1]
(hex)
Bit definition
Bit 3
Default
(bin)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
ADC control registers
0003
0005
Channel index
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
ADCB
ADCA
1111 1111
Reset and
Power-down
modes
SW_RST
PD[1:0]
0000 0000
0006
0007
0013
0014
0015
0016
Clock
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
SE_SEL
-
DIFF_SE
-
CLKDIV2_SEL
INTREF[2:0]
DCS_EN
0000 0001
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Vref
INTREF_EN
Offset
DIG_OFFSET[5:0]
Test pattern 1
Test pattern 2
Test pattern 3
-
-
-
TESTPAT_1[2:0]
-
TESTPAT_2[10:3]
-
TESTPAT_3[2:0]
-
-
-
JESD204A control
0801
Ser_Status
R
RXSYNC_
ERROR
RESERVED[2:0]
0
0
0
POR_TST
0
RESERVED 0001 0000
0802
Ser_Reset
R/W
SW_RST
0
0
0
0
0
0
FSM_SW_
RST
0
0000 0000
0803
0805
Ser_Cfg_Setup
Ser_Control1
R/W
R/W
0
0
CFG_SETUP[3:0]
0000 1000
TRISTATE_ SYNC_
SYNC_
SINGLE_
ENDED
1
0
REV_SCR
REV_
ENCODER
REV_SERIAL 0100 1001
CFG_PINS
POL
0806
Ser_Control2
R/W
0
0
0
0
0
0
0
SWAP_
LANE_1_2
SWAP_
0000 0011
ADC_0_1
0808
0809
080A
080B
0820
0821
0822
0823
0824
0825
Ser_Analog_Ctrl R/W
Ser_ScramblerA R/W
Ser_ScramblerB R/W
Ser_PRBS_Ctrl R/W
0
0
0
0
SWING_SEL[2:0]
0000 0011
0000 0000
1111 1111
0000 0000
1110 1101
0000 1010
0000 0000
0000 0001
0000 1000
0000 0000
LSB_INIT[6:0]
MSB_INIT[7:0]
0
0
0
0
0
0
0
PRBS_TYPE[1:0]
Cfg_0_DID
Cfg_1_BID
Cfg_3_SCR_L
Cfg_4_F
R*
DID[7:0]
R/W*
R/W*
R/W*
R/W*
R/W*
0
SCR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BID[3:0]
0
0
0
L
F[2:0]
Cfg_5_K
0
K[4:0]
0
Cfg_6_M
0
0
0
0
M
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17. Register allocation map …continued
Address Register name Access[1]
(hex)
Bit definition
Bit 3
Default
(bin)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
0826
0827
0828
0829
082C
082D
084C
084D
0870
Cfg_7_CS_N
Cfg_8_Np
Cfg_9_S
R/W*
R/W
0
0
CS[0]
0
0
0
0
0
0
0
N[3:0]
0100 0001
0000 1111
0000 0000
0000 0000
0001 1011
0001 1100
0000 0000
0000 0000
0
0
0
0
0
NP[4:0]
0
R/W*
0
0
0
0
0
0
S
Cfg_10_HD_CF R/W*
HD
0
0
CF[1:0]
Cfg_01_2_LID
Cfg_02_2_LID
R/W*
R/W*
LID[4:0]
LID[4:0]
0
Cfg01_13_FCHK R
Cfg02_13_FCHK R
FCHK[7:0]
FCHK[7:0]
0
LaneA_0_Ctrl
R/W
0
0
SCR_IN_
MODE
LANE_MODE[1:0]
LANE_MODE[1:0]
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD 0000 0001
0871
LaneB_0_Ctrl
R/W
SCR_IN_
MODE
0
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD 0000 0000
0890
0891
ADCA_0_Ctrl
ADCB_0_Ctrl
R/W
R/W
0
0
0
0
ADC_MODE[1:0]
ADC_MODE[1:0]
0
0
0
0
0
0
ADC_PD
ADC_PD
0000 0001
0000 0000
[1] an "*" in the Access column means that this register is subject to control access conditions in Write mode.
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control registers
Table 18. Register Channel Index (address 0003h)
Default values are highlighted.
Bit
7 to 2
1
Symbol
-
Access Value
Description
-
111111
not used
ADCB
R/W
ADC B gets the next SPI command:
ADC B not selected
0
1
ADC B selected
0
ADCA
R/W
ADC A gets the next SPI command:
ADC A not selected
0
1
ADC A selected
Table 19. Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7
SW_RST
R/W
reset digital part:
no reset
0
1
performs a reset of the digital part
not used
6 to 2
-
-
00000
1 to 0 PD[1:0]
R/W
power-down mode:
normal (power-up)
full power-down
sleep
00
01
10
11
normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit
7 to 5
4
Symbol
-
Access Value
Description
-
000
not used
SE_SEL
R/W
select SE clock input pin:
select CLKM input
select CLKP input
differential/single-ended clock input select:
fully differential
single-ended
0
1
3
DIFF_SE
R/W
0
1
0
2
1
-
-
not used
CLKDIV2_SEL
R/W
select clock input divider by 2:
disable
0
1
active
0
DCS_EN
R/W
duty cycle stabilizer enable:
disable
0
1
active
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
Table 21. Register Vref (address 0008h)
Default values are highlighted.
Bit
7 to 4
3
Symbol
Access Value
Description
-
-
0000
not used
INTREF_EN
R/W
enable internal programmable VREF mode:
disable
0
1
active
2 to 0 INTREF[2:0]
R/W
programmable internal reference:
0 dB (FS=2 V)
000
001
010
011
100
101
110
111
−1 dB (FS=1.78 V)
−2 dB (FS=1.59 V)
−3 dB (FS=1.42 V)
−4 dB (FS=1.26 V)
−5 dB (FS=1.12 V)
−6 dB (FS=1 V)
not used
Table 22. Digital offset adjustment (address 0013h)
Default values are highlighted.
Register offset:
Decimal
DIG_OFFSET[5:0]
+31
...
011111
...
+31 LSB
...
0
000000
...
0
...
...
−32
100000
−32 LSB
Table 23. Register Test pattern 1 (address 0014h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
not used
2 to 0 TESTPAT_1[2:0]
R/W
digital test pattern:
000
001
010
011
100
101
110
111
off
mid-scale
− FS
+ FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern, to be written in register 0015h and 0016h
‘010101...’
‘101010...’
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Table 24. Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0
TESTPAT_2[10:3]
R/W 00000000 custom digital test pattern (bit 10 to 3)
Table 25. Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 TESTPAT_3[2:0]
R/W 00000000 custom digital test pattern (bit 2 to 0)
11.6.4 JESD204A digital control registers
Table 26. Ser_Status (address 0801h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7
RXSYNC_ERROR
R
-
0
set to 1 when a synchronization error occurs
6 to 4 RESERVED[2:0]
001
0
reserved
3 to 2
-
-
not used
1
0
POR_TST
RESERVED
R
-
0
power-on-reset
reserved
0
Table 27. Ser_Reset (address 0802h)
Default values are highlighted.
Bit
7
Symbol
SW_RST
-
Access Value
Description
R/W
-
0
initiates a software reset of the JESD204A unit
6 to 4
3
000
0
not used
FSM_SW_RST
R/W
initiates a software reset of the internal state machine of
JESD204A unit
2 to 0
-
-
000
not used
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Table 28. Ser_Cfg_Setup (address 0803h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4
-
-
0000
1000
not used
3 to 0 CFG_SETUP[3:0]
R/W
quick configuration of JESD204A. These settings overrule the
configuration of pins CFG3 to CFG0 (see Table 29).
Table 29. JESD204A configuration table
CFG_SETUP[3:0] ADC A ADC B Lane 0 Lane 1 F[1] HD[1] K[1] M[1] L[1]
Comment
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
(F × K) ≥ 17
CS[1] CF[1] S[1]
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
ON
ON
ON
ON
ON
ON
ON
OFF
ON
2
3
3
1
1
2
2
2
2
0
0
0
1
1
0
0
0
0
9
2
2
2
1
1
1
1
1
1
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
6
2
ON
ON
OFF
ON
6
3
ON
OFF
ON
ON
17
4
OFF
ON
ON
ON
17
5
OFF
OFF
ON
ON
OFF
ON
9
9
6
ON
OFF
ON
7
OFF
OFF
OFF
ON
9
8
ON
OFF
9
9
reserved
reserved
reserved
reserved
reserved
9
10
11
12
13
14
ON
ON
ON
ON
2
2
0
0
2
2
2
2
test: loop
alignment
1
1
0
0
1
1
15
1111
OFF
OFF
OFF
OFF
9
chip
power-down
[1] F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
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Table 30. Ser_Control1 (address 0805h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
-
-
0
not used
6
TRISTATE_CFG_PINS
R/W
1
pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
5
4
SYNC_POL
R/W
defines the sync signal polarity:
0
synchronization signal is active LOW
1
synchronization signal is active HIGH
SYNC_SINGLE_ENDED R/W
defines the input mode of the sync signal:
0
1
1
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
3
2
-
-
-
not used
REV_SCR
LSBs are swapped with MSBs at the scrambler input:
0
disable
1
enable
1
0
REV_ENCODER
REV_SERIAL
-
-
LSBs are swapped with MSBs at the 8-bit/10-bit encoder input:
0
disable
1
enable
LSBs are swapped with MSBs at the lane input:
0
disable
1
enable
Table 31. Ser_Control2 (address 0806h)
Default values are highlighted.
Bit
7 to 2
1
Symbol
Access Value
Description
-
-
000000
not used
SWAP_LANE_1_2
R/W
outputs of the JESD204A unit are swapped. (Output buffer A is
connected to Lane 1, Output buffer B is connected to Lane 0):
0
disable
1
enable
0
SWAP_ADC_0_1
R/W
inputs of the JESD204A unit are swapped. (ADC A output is
connected to Input B, ADC B is connected to Input A):
0
disable
1
enable
Table 32. Ser_Analog_Ctrl (address 0808h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
not used
2 to 0 SWING_SEL[2:0]
R/W
011
defines the swing of output buffers A and B
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Table 33. Ser_ScramblerA (address 0809h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7
-
-
0
not used
6 to 0 LSB_INIT[6:0]
R/W
0000000 defines the initialization vector for the scrambler polynomial
(lower)
Table 34. Ser_ScramblerB (address 080Ah)
Default values are highlighted.
Bit
Symbol
Access Value
R/W
Description
7 to 0 MSB_INIT[7:0]
11111111 defines the initialization vector for the scrambler polynomial
(upper)
Table 35. Ser_PRBS_Ctrl (address 080Bh)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 2
-
-
000000
not used
1 to 0 PRBS_TYPE[1:0]
R/W
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset)
PRBS-7
PRBS-7
PRBS-23
PRBS-31
01
10
11
Table 36. Cfg_0_DID (address 0820h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 DID[7:0]
R
11101101 defines the device (= link) identification number
Table 37. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4
-
-
0000
not used
3 to 0 BID[3:0]
R/W
1010
defines the bank ID – extension to DID
Table 38. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
SCR
R/W
-
0
scrambling enabled
6 to 1
0
-
000000
0
not used
L
R/W
defines the number of lanes per converter device, minus 1
Table 39. Cfg_4_F (address 0823h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
001
not used
2 to 0 F[2:0]
R/W
defines the number of octets per frame, minus 1
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Table 40. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 K[4:0]
R/W
01000
defines the number of frames per multiframe, minus 1
Table 41. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit
7 to 1
0
Symbol
Access Value
Description
-
-
0000000 not used
M
R/W
0
defines the number of converters per device, minus 1
Table 42. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
-
-
0
not used
6
CS[0]
-
R/W
-
1
defines the number of control bits per sample, minus 1
not used
5 to 4
00
0001
3 to 0 N[3:0]
R/W
defines the converter resolution
Table 43. Cfg_8_Np (address 0827h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 NP[4:0]
R/W
01111
defines the total number of bits per sample, minus 1
Table 44. Cfg_9_S (address 0828h)
Default values are highlighted.
Bit
7 to 1
0
Symbol
Access Value
Description
-
-
0000000 not used
S
R/W
0
defines number of samples per converter per frame cycle
Table 45. Cfg_10_HD_CF (address 0829h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
HD
-
R/W
-
0
defines high density format
6 to 2
00000
00
not used
1 to 0 CF[1:0]
R/W
defines number of control words per frame clock cycle per link.
Table 46. Cfg_01_2_LID (address 082Ch)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 LID[4:0]
R/W
11011
defines lane 1 identification number
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Table 47. Cfg_02_2_LID (address 082Dh)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 LID[4:0]
R/W
11100
defines lane 2 identification number
Table 48. Cfg01_13_fchk (address 084Ch)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 FCHK[7:0]
R
00000000 defines the checksum value for lane 1
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 49. Cfg02_13_fchk (address 084Dh)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 FCHK[7:0]
R
00000000 defines the checksum value for lane 2
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 50. Lane0_0_ctrl (address 0870h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
-
-
0
not used
6
SCR_IN_MODE
R/W
defines the input type for scrambler and 8-bit/10-bit units:
0 (reset)
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_Ctrl register)
5 to 4 LANE_MODE[1:0]
R/W
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0 × 0)
toggle mode: lane output is toggling between 0 × 0 and 0 × 1
01
10
11
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
3
2
-
-
0
not used
LANE_POL
R/W
defines lane polarity:
lane polarity is normal
lane polarity is inverted
defines lane clock polarity:
0
1
1
LANE_CLK_POS_EDGE R/W
0
lane clock provided to the serializer is active on positive
edge
1
lane clock provided to the serializer is active on negative edge
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Dual 11-bit ADC; serial JESD204A interface
Table 50. Lane0_0_ctrl (address 0870h) …continued
Default values are highlighted.
Bit
Symbol
Access Value
Description
0
LANE_PD
R/W
lane power-down control:
lane is operational
0
1
lane is in Power-down mode
Table 51. Lane2_0_ctrl (address 0871h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
-
-
0
not used
6
SCR_IN_MODE
R/W
defines the input type for scrambler and 8b/10b units:
0 (reset)
(normal mode) = input of the scrambler and 8b/10b units is
the output of the Frame Assembly unit.
1
input of the scrambler and 8b/10b units is the PRBS generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_Ctrl
register)
5 to 4 LANE_MODE[1:0]
R/W
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0x0)
toggle mode: lane output is toggling between 0x0 and 0x1
01
10
11
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
3
2
-
-
0
not used
LANE_POL
R/W
defines lane polarity:
lane polarity is normal
lane polarity is inverted
defines lane clock polarity:
0
1
1
0
LANE_CLK_POS_EDGE R/W
0
lane clock provided to the serializer is active on positive
edge
1
lane clock provided to the serializer is active on negative edge
lane power-down control:
Lane_PD
R/W
0
lane is operational
1
lane is in Power-down mode
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Table 52. ADCA_0_ctrl (address 0890h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 6
-
-
00
not used
5 to 4 ADC_MODE[1:0]
R/W
defines input type of JESD204A unit:
ADC output is connected to the JESD204A input
not used
00 (reset)
01
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[10:0] = “1001101110”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
3 to 1
0
-
-
000
not used
ADC_PD
R/W
ADC power-down control:
ADC is operational
0
1
ADC is in Power-down mode
Table 53. ADCB_0_ctrl (address 0891h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 6
-
-
00
not used
5 to 4 ADC_MODE[1:0]
R/W
defines input type of JESD204A unit
ADC output is connected to the JESD204A input
not used
00 (reset)
01
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[10:0] = “1001101110”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
3 to 1
0
-
-
000
not used
ADC_PD
R/W
ADC power-down control:
ADC is operational
ADC is in Power-down mode
0
1
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Dual 11-bit ADC; serial JESD204A interface
12. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
SOT684-7
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
e
v
w
C A
B
C
1/2 e
b
L
y
C
1
y
15
28
14
29
e
E
h
e
2
1/2 e
1
42
terminal 1
index area
56
43
X
D
h
0
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
(1)
E
A
A
1
b
c
D
D
h
E
h
e
e
1
e
2
L
v
w
y
y
1
max 1.00 0.05 0.30
mm nom 0.85 0.02 0.21 0.2 8.0 5.80 8.0 6.40 0.5 6.5 6.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 7.9 5.65 7.9 6.25 0.3
8.1 5.95 8.1 6.55
0.5
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot684-7_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
08-11-19
09-03-04
SOT684-7
MO-220
Fig 24. Package outline SOT684-7 (HVQFN56)
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
13. Abbreviations
Table 54. Abbreviations
Acronym
ADC
Description
Analog-to-Digital Converter
Duty Cycle Stabilizer
ElectroStatic Discharge
Intermediate Frequency
InterModulation Distortion
Least Significant Bit
DCS
ESD
IF
IMD
LSB
LVCMOS
LVPECL
MSB
OTR
Low Voltage Complementary Metal Oxide Semiconductor
Low-Voltage Positive Emitter-Coupled Logic
Most Significant Bit
OuT-of-Range
PRBS
SFDR
SNR
Pseudo-Random Binary Sequence
Spurious-Free Dynamic Range
Signal-to-Noise Ratio
SPI
Serial Peripheral Interface
TX
Transmitter
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14. Revision history
Table 55. Revision history
Document ID
Release date
Data sheet status
Change Supersedes
notice
ADC1113D125 v.3
Modifications:
20110210
Product data sheet
-
ADC1113D125 v.2
• Data sheet status changed from Preliminary to Product.
• Text and drawings updated throughout entire data sheet.
• Table 29 “JESD204A configuration table” added to Section 11.6.4.
• All tables in Section 11.6.2 have been updated.
• Section 13 “Abbreviations” added to the data sheet.
ADC1113D125 v.2
ADC1113D125 v.1
20100423
Preliminary data sheet
-
ADC1113D125 v.1
-
20100412
Objective data sheet
-
ADC1113D125
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Dual 11-bit ADC; serial JESD204A interface
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
ADC1113D125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
39 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1113D125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
40 of 41
ADC1113D125
NXP Semiconductors
Dual 11-bit ADC; serial JESD204A interface
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
15
Legal information . . . . . . . . . . . . . . . . . . . . . . 39
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40
15.1
15.2
15.3
15.4
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
16
17
Contact information . . . . . . . . . . . . . . . . . . . . 40
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . . 10
Serial output timing. . . . . . . . . . . . . . . . . . . . . 10
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.1
10.2
10.3
10.4
11
11.1
Application information. . . . . . . . . . . . . . . . . . 12
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input stage description . . . . . . . . . . . . . . . . . . 12
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 12
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System reference and power management . . 14
Internal/external reference . . . . . . . . . . . . . . . 14
Programmable full-scale. . . . . . . . . . . . . . . . . 16
Common-mode output voltage (VO(cm)) . . . . . 17
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Equivalent input circuit . . . . . . . . . . . . . . . . . . 18
Clock input divider . . . . . . . . . . . . . . . . . . . . . 19
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 19
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial output equivalent circuit . . . . . . . . . . . . 19
JESD204A serializer. . . . . . . . . . . . . . . . . . . . 20
Digital JESD204A formatter . . . . . . . . . . . . . . 20
ADC core output codes versus input voltage . 21
Serial Peripheral Interface (SPI). . . . . . . . . . . 22
Register description . . . . . . . . . . . . . . . . . . . . 22
Channel control . . . . . . . . . . . . . . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . 26
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.5
11.5.1
11.5.2
11.6
11.6.1
11.6.2
11.6.3
11.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 26
11.6.4
JESD204A digital control registers . . . . . . . . . 28
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 38
12
13
14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 February 2011
Document identifier: ADC1113D125
相关型号:
ADC1113S125HN/C1
ADC, Proprietary Method, 11-Bit, 1 Func, 1 Channel, Serial Access, PQCC32, 7 X 7 MM, 0.80 MM HEIGHT, PLASTIC, SOT1152-1, HVQFN-32
IDT
ADC1115S125HN-C1
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
IDT
ADC1115S125HN/C1
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
NXP
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