ADC1213D125 [NXP]
Dual 12-bit ADC; 65, 80, 105 or 125 Msps; 双通道12位ADC ; 65 ， 80 ， 105或125 MSPS
| 型号： | ADC1213D125 |
| 厂家： | 
NXP |
| 描述： | Dual 12-bit ADC; 65, 80, 105 or 125 Msps |
| 文件： | 总38页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC1213D065/080/105/125
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Rev. 02 — 17 June 2009
Objective data sheet
1. General description
The ADC1213D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V
source for analog and a 1.8 V source for the output driver, it can output data in serial
mode, because of the two lanes of differential outputs, which are compliant with the
JESD204A standard. An integrated Serial Peripheral Interface (SPI) allows the user to
easily configure the ADC. A set of IC configurations is also available via the binary level
control pins, which are used at power-up. The device also includes a programmable gain
amplifier with flexible input voltage range.
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging and
medicine.
2. Features
I SNR, 73 dB
I Input bandwidth, 600 MHz
I Power dissipation, 995 mW at 80 Msps
I SPI interface
I SFDR, 90 dBc
I Sample rate up to 125 Msps
I Dual channel 12-bit pipelined ADC core I Duty cycle stabilizer
I 3.3 V, 1.8 V single supplies
I High IF capability
I Offset binary, 2’s complement, gray
code
I Flexible input voltage range:
1 V (p-p) to 2 V (p-p) with 6 dB
programmable fine gain
I 2 configurable serial outputs
I Compliant with JESD204A serial
transmission standard
I Power-down and Sleep modes
I HVQFN56 package
I INL ± 1 LSB; DNL ± 0.5 LSB
3. Applications
I Wireless and wired broadband communications
I Spectral analysis
I Portable instrumentation
I Imaging systems
I Ultrasound equipment
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msample/s)
Package
Name
Description
Version
ADC1213D125HN/C1 125
ADC1213D105HN/C1 105
ADC1213D080HN/C1 80
ADC1213D065HN/C1 65
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
2 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
5. Block diagram
ERROR
CORRECTION AND
DIGITAL
SPI INTERFACE
SYNCP
SYNCN
PGA
PROCESSING
INAP
SWING
T/H
INPUT
STAGE
ADCA CORE
12-BIT
PIPELINED
D11 to D0
OTR
INAM
SERIALIZER A
OUTPUT BUF A
CMLAP
CMLAN
8b
8b
10b
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
CLKP
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
CMLBP
CMLBN
SERIALIZER B
OUTPUT BUF B
PGA
PROCESSING
8b
8b
10b
OTR
INBP
T/H
INPUT
STAGE
ADCB CORE
12-BIT
PIPELINED
D11 to D0
SWING
INBM
SYSTEM
REFERENCE AND
POWER
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
MANAGEMENT
ADC1213D
005aaa120
Fig 1. Block diagram
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
3 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
6. Pinning information
6.1 Pinning
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INAP
INAM
DGND
DGND
VDDD
CMLPA
CMLNA
VDDD
DGND
DGND
VDDD
CMLNB
CMLPB
VDDD
DGND
DGND
3
VCMA
REFAT
REFAB
AGND
CLKP
4
5
6
7
ADC1213D
8
CLKN
AGND
REFBB
REFBT
VCMB
INBM
9
10
11
12
13
14
INBP
005aaa121
Transparent top view
Fig 2. Pinning diagram
6.2 Pin description
Table 2.
Symbol
INAP
Pin description
Pin
1
Type[1]
Description
I
channel A complementary analog input
channel A analog input
INAM
2
I
VCMA
REFAT
REFAB
AGND
CLKP
3
O
O
O
G
I
channel A output common voltage
channel A top reference
Channel A bottom reference
analog ground
4
5
6
7
clock input
CLKN
8
I
complementary clock Input
analog ground
AGND
REFBB
REFBT
VCMB
INBM
9
G
O
O
O
I
10
11
12
13
channel B bottom reference
channel B top reference
channel B output common voltage
channel B complementary analog input
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
4 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 2.
Pin description …continued
Symbol
INBP
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Type[1]
I
Description
channel B analog input
analog power supply 3.3 V
analog power supply 3.3 V
SPI clock / data format select
SPI data IO/duty cycle stabilizer
chip select bar
VDDA
P
VDDA
P
SCLK/DFS
SDIO/DCS
CSB
I
I/O
I
AGND
G
I
analog ground
RESET
SCRAMBLER
CFG0
JEDEC digital IP reset
scrambler enable /disable
JEDEC link config or OTRA
JEDEC link config or OTRB
JEDEC link config
I
I/O
I/O
I/O
I/O
P
CFG1
CFG2
CFG3
JEDEC link config
VDDD
digital power supply 1.8 V
digital ground
DGND
DGND
DGND
VDDD
G
G
G
P
digital ground
digital ground
digital power supply 1.8 V
channel B output
CMLPB
CMLNB
VDDD
O
O
P
channel B complementary output
digital power supply 1.8 V
digital ground
DGND
DGND
VDDD
G
G
P
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
CMLNA
CMLPA
VDDD
O
O
P
digital power supply 1.8 V
digital ground
DGND
DGND
SYNCP
SYNCN
DGND
VDDD
G
G
I
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
I
G
P
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
Set when internal PLL is locked
analog power supply 3.3 V
analog ground
SWING_0
SWING_1
PLL_LOCK
VDDA
I
I
O
P
AGND
G
G
P
AGND
analog ground
VDDA
analog power supply 3.3 V
reference programming pin
voltage reference input/output
analog power supply 3.3 V
SENSE
VREF
I
I/O
P
VDDA
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
5 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA
VDDD
∆VCC
Tstg
Parameter
Conditions
Min
2.85
1.65
Max
3.6
Unit
V
[1]
[2]
analog supply voltage
digital supply voltage
supply voltage difference
storage temperature
ambient temperature
junction temperature
1.95
V
VDDA − VDDD
<tbd> <tbd>
V
−55
−40
-
+125
+85
°C
°C
°C
Tamb
Tj
125
[1] The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage
differences ∆VCC are respected.
[2] The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ∆VCC are respected.
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Rth(j-a)
Parameter
Conditions
Typ
20.9[2]
Unit
K/W
K/W
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
Rth(j-c)
<tbd>
[1] In compliance with JEDEC test board, in free air.
[2] Value for 4 layers and 36 vias.
9. Static characteristics
Table 5.
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Characteristics
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Supplies
VDDA
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
digital supply voltage
analog supply current
2.85
1.65
-
3.0
1.8
310
3.4
3.6
-
V
VDDD
V
IDDA
fclk = 125 Msample/s;
fi =70 MHz
mA
IDDD
Ptot
digital supply current
total power dissipation
fclk = 125 Msample/s;
fi = 70 MHz
-
145
-
mA
fclk = 125 Msample/s
fclk = 105 Msample/s
fclk = 80 Msample/s
fclk = 65 Msample/s
-
-
-
-
1177
1045
995
-
-
-
-
mW
mW
mW
mW
885
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
6 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 5.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
30
Max
Unit
mW
mW
P
power dissipation
Power-down mode
Standby mode
-
-
-
-
200
Digital inputs
Clock inputs: pins CLKP and CLKM, AC coupled
LVPECL, LVDS and Sinewave modes compatible
Vi(clk)dif
differential clock input
voltage
peak-to-peak
0.2
0.8
-
<tbd>
V (p-p)
V
LVCMOS mode
VI
input voltage
0.3VDDA
0.7VDDA
Logic Inputs: Power-down: pin CF 0 to 3, pin Scrambler , Swing_0, Swing_1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
-
0
-
V
-
0.66VDDD
-
V
−6
−30
-
-
+6
+30
µA
µA
IIH
Serial Peripheral Interface: pin CSB, SDIO, SCLK, pin DFS, pin DCS
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
Input capacitance
0
-
0.3VDDA
VDDA
+10
V
0.7VDDA
−10
−50
-
-
V
-
µA
µA
pF
IIH
CI
-
+50
4
-
Analog inputs: pins INAP and INAM, pins INBP and INBM
II
Input current
−5
-
-
+5
-
µA
Ω
Ri
input resistance
input capacitance
15
5
CI
-
-
pF
V
VI(cm)
common-mode input
voltage
0.9
1.5
2
Bi
input bandwidth
-
600
-
-
MHz
Vpp
VI(dif)
differential input voltage
1
2
Voltage controlled regulator output: pin VCMA, VCMB
VO(cm)
common-mode output
voltage
-
-
0.5VDDA
<tbd>
-
-
V
IO(cm)
common-mode output
current
µA
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
output
input
-
0.5 to 1
-
-
V
V
0.5
1
Reference mode selection: pin SENSE
VSENSE voltage on pin SENSE
-
pin AGND;
-
V
VVREF; VDDA
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
7 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 5.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Data outputs: CMLPA, CMLNA
Output levels, VDDD = 1.8 V. {Swing_2, Swing_1, Swing_0} = {0,0,0}
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output
voltage
DC coupled, output
AC coupled
-
-
-
-
1.5
-
-
-
-
V
V
V
V
1.65
1.8
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.35
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, Swing_0} = {0,0,1}
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.45
1.625
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.275
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, swing_0} = {0,1,0}
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.4
1.6
1.8
1.2
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
Output levels, VDDD = 1.8 V {Swing_2, Swing_1, Swing_0} = {0,1,1}
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.35
1.575
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.125
Output levels, VDDD = 1.8 V {Swing_2, Swing_1,Swing_0} = {1,0,0}
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.3
-
-
-
-
V
V
V
V
1.55
1.8
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.05
Serial configuration : SYNC_P, SYNC_N
VIL
LOW-level input voltage Differential; input
High-level input voltage Differential; input
-
-
0.95
1.47
-
-
V
V
VIH
Accuracy
INL
integral non-linearity
−1.25
−0.25
±0.25
±0.12
+1.25
+0.25
LSB
LSB
DNL
differential non-linearity no missing codes
guaranteed
Eoffset
EG
offset error
gain error
-
-
±2
-
-
mV
± 0.5
% FS
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
8 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 5.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MG(CTC)
channel-to-channel gain
matching
-
<tbd>
-
%
Supply
PSRR
Power Supply Rejection 100 mV (p-p) on VDDA
Ratio
-
35
-
dBc
10. Dynamic characteristics
Table 6.
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Characteristics
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
Conditions
ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit
Min
Typ
Max Min
Typ
Max Min
Typ
Max Min
Typ
Max
Analog signal processing
α2H
second
harmonic level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
93
90
88
92
91
90
88
88
87
86
83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
93
91
88
93
92
90
87
88
87
86
83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
96
92
91
85
91
91
90
88
87
87
85
82
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
96
93
91
85
90
89
87
87
87
86
84
82
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Bits
Bits
Bits
Bits
tbd
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
α3H
third harmonic fi = 3 MHz
level
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
THD
ENOB
total harmonic fi = 3 MHz
distortion
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
effective
number of bits
fi = 3 MHz
11.3 -
11.2 -
11.1 -
11.3 -
11.3 -
11.2 -
11.1 -
11.3 -
11.3 -
11.2 -
11.1 -
11.3 -
11.2 -
11.2 -
11.1 -
11.3 -
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
tbd
tbd
tbd
tbd
Nth(RMS) RMS thermal
noise
-
-
-
-
SNR
signal-to-noise fi = 3 MHz
-
-
-
-
70.7 -
70.2 -
69.9 -
69.5 -
-
-
-
-
70.6 -
70.2 -
69.9 -
69.5 -
-
-
-
-
70.5 -
70.2 -
69.8 -
69.4 -
-
-
-
-
70.3 -
70.1 -
69.7 -
69.3 -
dBFS
dBFS
dBFS
dBFS
ratio
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
9 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 6.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
Conditions
ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit
Min
Typ
91
90
89
86
94
93
92
89
87
Max Min
Typ
91
90
89
86
94
93
92
89
85
Max Min
Typ
90
90
88
85
93
93
91
88
86
Max Min
Typ
90
89
87
85
93
92
90
88
85
Max
SFDR
IMD
spurious-free
dynamic range
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
intermodulation fi = 3 MHz
distortion
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
αct(ch)
crosstalk
between
channels
fi = 70 MHz
11. Clock and digital output timing
Table 7.
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Characteristics
VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit
Min
Typ
Max Min
Typ
Max Min
Typ
Max Min
Typ
Max
Clock timing input: pins CLKP and CLKM
fclk
clock
frequency
20
17
-
65
20
60
17
-
80
20
60
17
-
105 60
-
-
125 Msps
tlat(data)
δclk
data latency
time
-
-
-
20
17
20
clk/cy
clock duty
cycle
DCS en
DCS dis
30
45
-
50
50
0.8
70
55
-
30
45
-
50
50
0.8
70
55
-
30
45
-
50
50
0.8
70
55
-
30
45
-
50
50
0.8
70
55
-
%
%
ns
td(s)
sampling
delay time
twake
wake-up time
-
tbd
-
tbd
-
-
tbd
-
-
tbd
-
ns
11.1 Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 ˚C
• DC coupling with 2 different receiver common-mode voltages.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
10 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
005aaa088
Fig 3. Eye diagram at 1 V receiver Common mode
005aaa089
Fig 4. Eye diagram at 2 V receiver Common mode
12. SPI timing
Table 8.
Characteristics
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Serial Peripheral Interface timings
tw(SCLK)
tw(SCLKH)
tw(SCLKL)
tsu
SCLK pulse width
SCLK pulse width HIGH
SCLK pulse width LOW
set-up time
40
16
16
5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
data to SCLKH
CSB to SCLKH
5
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
11 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 8.
Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V ;
Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ns
th
hold time
data to SCLKH
CSB to SCLKH
2
2
-
-
-
-
-
-
ns
fclk(max)
maximum clock
frequency
25
MHz
13. Application information
13.1 Analog inputs
13.1.1 Input stage description
The ADC1213D inputs can be configured as single-ended or differential (selected via SPI
control bit DIFF/SE; see Table 20). Optimal performance is achieved using differential
inputs with the common-mode input voltage, VI(CM), set to 0.5VDDA
.
The full scale analog input voltage range is configurable between ±1 V (p-p) and
±2 V (p-p) via a programmable internal reference (see Section 13.2 and Table 21 for
further details).
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in Figure 5.
Package
ESD
Parasitics
Switch
Ron = 14 Ω
4 pF
1, 14
INAP
INBP
Sampling
Capacitor
internal
clock
Switch
Ron = 14 Ω
4 pF
2, 13
INAM
INBM
Sampling
internal Capacitor
clock
005aaa069
Fig 5. Input sampling circuit
The sample phase HIGH, because of the NMOS transistors. The voltage is then held on
the sampling capacitors. When the clock signal goes LOW, the stage enters the hold
phase and the voltage information is transmitted to the ADC core.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
12 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.1.2 Anti-kickback circuitry
Anti-kickback circuitry is needed to counteract the effects of charge injection generated by
the sampling capacitance. This consists of an RC filter containing a resistor in series
(typically 12 Ω to 25 Ω) and a capacitor in parallel (typically 8 pF to 12 pF).
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time too much.
The RC coupling is determined by the input frequency and should be selected so as not to
affect the input bandwidth.
Table 9.
RC coupling versus input frequency
Input frequency
3 MHz
R
C
25 Ω
12 Ω
12 Ω
12 pF
8 pF
8 pF
70 MHz
170 MHz
13.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 6 would be suitable for a baseband application.
100 nF
25 Ω
INAP
100 nF
ADT1-1WT
Analog
INBP
lnput
25 Ω
12 pF
100 nF
25 Ω
100 nF
25 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa070
Fig 6. Single transformer configuration
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
13 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
ADT1-1WT
ADT1-1WT
12 Ω
INAP
INBP
100 nF
50 Ω
50 Ω
50 Ω
Analog
lnput
8.2 pF
50 Ω
12 Ω
INAM
INBM
100 nF
VCM
100 nF
100 nF
005aaa071
Fig 7. Dual transformer configuration
The configuration shown in Figure 7 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
13.2 System reference and power management
13.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage. This
reference voltage can be set internally, externally or programmed, in 1 dB steps between
0 dB and −6 dB, via SPI control bits INTREF (when bit INTREF_EN = 1; see Table 21).
The equivalent reference circuit is shown in Figure 8.
REFT
REFERENCE
REFB
AMP
BANDGAP
REFERENCE
VREF
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa072
Fig 8. Reference equivalent schematic
Rev. 02 — 17 June 2009
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
14 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
The following Table 10 show how to chose between the different internal/external modes:
Table 10. Reference modes
Mode
SPI Bit, “Internal
reference”
SENSE pin
VREF pin
Full Scale,
V (p-p)
Internal
0
0
0
1
Gnd
330 pF capacitor
to GND
2
Internal
VREF PIN = SENSE PIN and
330 pF capacitor to GND
1
External
VDDA
External voltage 1 to 2
from 0.5 V to 1 V
Internal, SPI mode
VREF PIN = SENSE PIN and
330 pF capacitor to GND
1 to 2
Figure 9, Figure 10, Figure 11 and Figure 12 indicate how to connect the SENSE and
VREF pins.
VREF
REFT
REFB
VREF
REFT
REFB
330 pF
330 pF
SENSE
SENSE
005aaa100
005aaa074
Fig 9. Internal reference, 2 V (p-p) full scale
Fig 10. Internal reference, 1 V (p-p) full scale
VREF
REFT
REFB
VREF
REFT
REFB
0.1 µF
330 pF
V
SPI SETTINGS
int_Ref = 1, active
Programmable_int_ref = XXX
SENSE
SENSE
VCCA
005aaa075
005aaa076
Fig 11. Internal reference, SPI, 1 V (p-p) to 2 V (p-p)
full scale
Fig 12. External reference, 1 V (p-p) to 2 V (p-p) full
scale
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
15 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.2.2 Gain control
The gain is programmable between 0 dB to −6 dB in steps of 1 dB via the SPI
(see Table 21). This makes it possible to improve the Spurious-Free Dynamic Range
(SFDR) of the ADC1213D. The corresponding full scale input voltage range varies
between 2 V (p-p) and 1 V (p-p), as shown in Table 11:
Table 11. Reference SPI gain control
Programmable_int_ref
Level
0dB
Full Scale, V (p-p)
000
001
010
011
100
101
110
111
2
−1dB
−2dB
−3dB
−4dB
−5dB
−6dB
not used
1.78
1.59
1.42
1.26
1.12
1
x
13.2.3 Common-mode output voltage (VI(CM)
)
An 0.1 µF filter capacitor should be connected between on the one hand the pins VCMA
and VCMB and on the other hand ground to ensure a low-noise common-mode output
voltage. When AC-coupled, these pins can be used to set the common-mode reference
for the analog inputs, for instance via a transformer middle point.
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCMA
VCMB
0.1 µF
ADC CORE
005aaa077
Fig 13. Reference equivalent schematic
13.2.4 Biasing
The common-mode output voltage, VO(cm, should be set externally to 1.5 V (typical).
The common-mode input voltage , VI(cm), at the inputs to the sample and hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance. The graph in Figure 14 illustrates how the SFDR and SNR characteristics
vary with changes in the common-mode input voltage.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
16 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
dB
SFDR (x MHz)
SNR (x MHz)
2 V
0.9 V
V
I(cm)
005aaa052
Fig 14. SFDR and SNR performances versus common-mode voltage
13.3 Clock input
13.3.1 Drive modes
The ADC1213D can be driven differentially (SINE, LVPECL or LVDS) without the
performance being affected by the choice of configuration. It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor).
CLKP
CLKM
CLKP
CLKM
LVCMOS
clock input
LVCMOS
clock input
005aaa078
Fig 15. LVCMOS single-ended clock input
CLKP
CLKP
Sine
Clock lnput
Sine
Clock lnput
CLKM
CLKM
005aaa079
Fig 16. Sine differential clock input
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
17 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
CLKP
CLKM
LVDS
Clock lnput
005aaa080
Fig 17. LVDS differential clock input
13.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal resistors of 5 kΩ resistors.
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk)
Sel_SE
Sel_SE
5 k
5 k
CLKM
005aaa081
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface
(see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via
control bit SE_SEL.
If single-ended is implemented without setting SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
13.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between
30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the
input clock signal should have a duty cycle of between 45 % and 55 %.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
18 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 12. Duty cycle stabilizer
DCS_enable SPI
Description
0
1
Duty cycle stabilizer disable
Duty cycle stabilizer enable
13.4 Digital outputs
13.4.1 Serial output equivalent circuit
The JESD204A standard specifies that in case of connecting the receiver and the
transmitter in DC coupling, both of them need to be provided by the same supply.
V
DDD
50 Ω
+
CMLP
CMLN
100 Ω
RECEIVER
−
+
AGND
12 to 26 mA
005aaa082
Fig 19. CML output connection to the receiver in DC coupling
The output should be terminated when 100 Ω (typical) has been reached at the receiver
side.
V
DDD
50 Ω
+
CMLP
CMLN
10 nF
10 nF
100 Ω
RECEIVER
−
+
12 to 26 mA
005aaa083
Fig 20. CML output connection to the receiver in AC coupling
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
19 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.5 JESD204A serializer
13.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
L LANES
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
N bits from Cr
CS bits for control
+
0
F octets
SCRAMBLER
8b/10b
SER
LANE
0
TX transport layer
SYNC~
TX CONTROLLER
samples stream to
lane stream mapping
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
N bits from Cr
CS bits for control
+
M−1
F octets
SCRAMBLER
8b/10b
SER
LANE
−1
N' = N+CS
S samples per frame cycle
CF: position of controls bits
HD: frame boundary break
Padding with Tails bits (TT)
005aaa084
Mx(N'xS) bits
Lx(F) octets
L octets
Fig 21. General overview of the JESD204A serializer
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
20 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
ADC_mode [1-0]
scramb_in_mode [1-0]
PRBS
11
N
&
CS
lane_mode [1-0]
DUMMY
14 + 1 10
14 + 1
N + CS
8
00
01
SCR
8b/10b
10 00
01
PRBS
lane_polarity
ADC_power down
'0'
SER
14 + 1 00
ADC
0
'0/1'
10
bypass alignment
disable_char_repl
PRBS
11
x 1
x F
frame CLK
char CLK
PLL
&
DLL
FSM (f assy,
char repl, ILA,
test mode)
FRAME
ASSEMBLY
swing [2-0]
x 10F bit CLK
PRBS
'0/1'
'0'
11
10
sync_request
SER
ADC
1
14 + 1 00
01
ADC_power down
lane_polarity
PRBS
8
01
00
10 00
8b/10b
SCR
N
&
CS
14 + 1 10
14 + 1
N + CS
DUMMY
PRBS
lane_mode [1-0]
11
scramb_in_mode [1-0]
005aaa085
ADC_mode [1-0]
Fig 22. Detailed view of the JESD204A serializer with debug functionality
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
21 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
13.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13. Output codes versus input voltage
INP-INM (V)
< −1
Offset binary
Two’s complement
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
10 0000 0000 0011
10 0000 0000 0100
....
OTR
1
00 0000 0000 0000
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
00 0000 0000 0011
00 0000 0000 0100
....
−1
0
−0.9998779
−0.9997559
−0.9996338
−0.9995117
....
0
0
0
0
0
−0.0002441
−0.0001221
0
01 1111 1111 1110
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
....
11 1111 1111 1110
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
....
0
0
0
0.0001221
0.0002441
....
0
0
0
0.9995117
0.9996338
0.9997559
0.9998779
1
11 1111 1111 1011
11 1111 1111 1100
11 1111 1111 1101
11 1111 1111 1110
11 1111 1111 1111
11 1111 1111 1111
01 1111 1111 1011
01 1111 1111 1100
01 1111 1111 1101
01 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
0
0
0
0
0
> 1
1
13.6 Serial Peripheral Interface (SPI)
13.6.1 Register description
The ADC1213D serial interface is a synchronous serial communications port allowing for
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CSB acts as the serial chip select bar.
Each read/write operation is sequenced by the CSB signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14. Instruction bytes for the SPI
MSB
LSB
0
Bit
7
6
5
4
3
2
1
Description
R/W[1]
A7
W1
A6
W0
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
[1] R/W indicates whether a read or write transfer occurs after the instruction byte
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
22 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 15. Read or Write mode access description
R/W[1]
Description
0
1
Write mode operation
Read mode operation
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16. Number of bytes to be transferred
W1
0
W0
0
Number of bytes
1 byte transferred
0
1
2 bytes transferred
3 bytes transferred
4 or more bytes transferred
1
0
1
1
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on CSB in combination with a rising edge on SCLK determine the
start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but will
always be a multiple of 8 bits. The MSB is always sent first (for instruction and data
bytes):
CSB
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3 wires mode)
13.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel will receive the next
SPI-instruction. By default the channel A and B will receive the same instructions.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
23 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 17. Register allocation map
Addr Register name
Hex
R/W Bit definition
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
0003 Channel index
R/W
-
-
-
-
-
ADCB
ADCA
1111
1111
0005 Reset and
Operating mode
R/W SW_
RST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD[1:0]
0000
0000
0006 Clock
R/W -
R/W -
R/W -
R/W -
R/W -
SE_SEL DIFF/SE
CLKDIV2_ DCS_EN 0000
SEL
000X
0008 Vref
-
INTREF_ INTREF[2:0]
EN
0000
0000
0011 Output data
standard
LVDS/
CMOS
OUTBUF
-
DATA_FORMAT
000X
0XXX
0013 Offset
DIG_OFFSET[5:0]
0000
0000
0014 Test pattern 1
0015 Test pattern 2
0016 Test pattern 3
-
-
-
TESTPAT_1[2:0]
0000
0000
R/W TESTPAT_2[13:6]
R/W TESTPAT_3[5:0]
0000
0000
0000
0000
JESD204A control
0801 Ser_Status
R
0
RESERVED[2:0]
0
0
0
POR_TST PLL_
0000
INLOCK 0000
FSM_SW_
RST
0802 Ser_Reset
R/W SW_
RST
0
0
0
0
0
0
0
0
0000
0000
0803 Ser_Cfg_Setup
0805 Ser_Control1
R/W 0
R/W 0
CFG_SETUP[3:0]
0000 ****
TriState SYNC_ SYNC_
_CFG_ POL
PAD
1
0
0
RESERVED[2:0]
0100
1000
SINGLE
ENDED
0806 Ser_Control2
R/W 0
0
0
0
0
0
0
0
SWAP_
SWAP_ 0000
LANE_1_2 ADC_0_ 00**
1
0808 Ser_Analog_Ctrl R/W 0
SWING_SEL[2:0]
0000
01**
0809 Ser_ScramblerA
080A Ser_ScramblerB
080B Ser_PRBS_Ctrl
0820 Cfg_0_DID
R/W 0
LSB_INIT[6:0]
0000
0000
R/W MSB_INIT[7:0]
1111
1111
R/W 0
R/W*
0
0
0
0
0
PRBS_TYPE[1:0]
0000
0000
DID[7:0]
1110
1101
0821 Cfg_1_BID
R/W* 0
R/W* SCR
R/W* 0
0
0
0
0
0
0
0
0
0
BID[3:0]
0000
1010
0822 Cfg_3_SCR_L
0823 Cfg_4_F
0
0
0
0
L
*000
000*
F[2:0]
0000
0***
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
24 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 17. Register allocation map …continued
Addr Register name
Hex
R/W Bit definition
Default
Bit 7
R/W* 0
Bit 6
Bit 5
Bit 4
K[4:0]
0
Bit 3
Bit 2
Bit 1
Bit 0
Bin
0824 Cfg_5_K
0825 Cfg_6_M
0
0
0
0
000* ****
R/W* 0
0
0
0
0
M
0000
000*
0826 Cfg_7_CS_N
0827 Cfg_8_Np
R/W* 0
CS[0]
0
0
0
0
0
0
0
N[2:0]
0100
0***
R
0
0
0
0
0
0
NP[4:0]
0
0000
1111
0828 Cfg_9_S
R/W* 0
R/W* HD
R/W* 0
R/W* 0
0
0
0
0
0
S
0000
0000
0829 Cfg_10_HD_CF
082C Cfg_01_2_LID
082D Cfg_02_2_LID
084C Cfg01_13_FCHK
084D Cfg02_13_FCHK
0870 Lane01_0_Ctrl
0
CF[1:0]
*000
0000
LID[4:0]
LID[4:0]
0001
1011
0001
1100
R
FCHK[7:0]
FCHK[7:0]
0000
0000
R
0000
0000
R/W 0
SCR_ LANE_MODE[1:0] 0
LANE_ LANE_
POL
LANE_ 0000
CLK_POS PD 000*
IN_
MODE
_EDGE
0871 Lane02_0_Ctrl
R/W 0
SCR_ LANE_MODE[1:0] 0
IN_
LANE_ LANE_
POL
LANE_ 0000
CLK_POS PD
000*
MODE
_EDGE
0890 Adc01_0_Ctrl
0891 Adc02_0_Ctrl
R/W 0
R/W 0
0
0
ADC_MODE[1:0]
ADC_MODE[1:0]
0
0
0
0
0
0
ADC_PD 0000
000*
ADC_PD 0000
000*
[1] an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0],
Scrambler).
[2] an "*" in the Access column means that this register is subject to control access conditions in Write mode.
13.6.3 Register description
Table 18. Register channel Index(address 0003h)
Bit
Symbol
Access Value
Description
1
ADCB
R/W
ADCB will get the next SPI command:
ADCB not selected
0
1
ADCB selected
0
ADCA
R/W
ADCA will get the next SPI command:
ADCA not selected
0
1
ADCA selected
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
25 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 19. Register reset and Power-down mode (address 0005h)
Bit
Symbol
Access Value
Description
7
SW_RST
R/W
Reset digital part:
no reset
0
1
performs a reset of the digital part
Power-down mode:
normal (power-up)
full power-down
sleep
1 to 0 PD
R/W
00
01
10
11
normal (power-up)
Table 20. Register clock (address 0006h)
Bit
Symbol
Access Value
Description
4
SE_SEL
R/W
Select SE clock input pin:
Select CLKM input
Select CLKP input
Differential/single ended clock input select:
Fully differential
0
1
3
1
0
DIFF/SE
R/W
0
1
Single-ended
CLKDIV2_SEL
DCS_EN
R/W
Select clk input divider by 2:
disable
0
1
active
R/W
Duty cycle stabilizer enable:
disable
0
1
active
Table 21. Register Vref (address 0008h)
Bit
Symbol
Access Value
Description
3
INTREF_EN
R/W
Enable internal programmable Vref mode:
disable
0
1
active
2 to 0 INTREF
R/W
000
001
010
011
100
101
110
111
Programmable internal reference:
0dB (FS = 2 V)
−1dB (FS = 1.78 V)
−2dB (FS = 1.59 V)
−3dB (FS = 1.42 V)
−4dB (FS = 1.26 V)
−5dB (FS = 1.12 V)
−6dB (FS = 1 V)
not used
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
26 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 22. Digital offset adjust
Register offset: (address 0013h)
Dec
+31
...
Digital_Offset_Adjust[5:0]
011111
...
+31 LSB
...
0
000000
...
0
...
...
−32
100000
−32 LSB
Table 23. Register test pattern 1 (address 0014h)
Bit
Symbol
Access Value
Description
2 to 0 TESTPAT_1
R/W
000
001
010
011
100
101
110
111
Digital test pattern:
off
midscale
− FS
+ FS
toggle ‘1111..1111’/’0000..0000’
Custom test pattern, to be written in register 0015h & 0016h
‘010101...’
‘101010...’
Table 24. Register test pattern 2 (address 0015h)
Bit
Symbol
Access Value
Description
13 to 6 TESTPAT_2
R/W
Custom digital test pattern
-
Table 25. Register test pattern 3 (address 0016h)
Bit
Symbol
Access Value
Description
5 to 0 TESTPAT_3
R/W
Custom digital test pattern
-
13.6.4 JESD204A digital control registers
Table 26. SER status (address 0801h)
Bit
7 to 1
0
Symbol
Access Value
Description
-
Not used
PLL_Inlock
R
0
Indicates status of PLL
Table 27. SER reset (address 0802h)
Bit
7
Symbol
SW_RST
-
Access Value
Description
R/W
R/W
0
Initiates a software reset of the JEDEC204A unit
Not used
6 to 4
3
000
0
FSM_SW_RST
Initiates a software reset of the internal state machine of JEDEC204A
unit
2 to 0
-
000
Not used
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
27 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 28. SER cfg set-up (address 0803h)
Bit
Symbol
Access Value
Description
7 to 4
-
R
0000
Not used
3 to 0 CFG_SETUP
R/W
0000
(reset)
Defines quick JEDEC204A configuration. These settings overrule the
CFG_PAD configuration
0000
0001
0010
0011
0100
0101
0110
0111
1000
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2[1]
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5;
M = 2; L = 1[1]
ADC0: ON; ADC1: ON; Lane0: OFF; Lane1: ON; F = 4; HD = 0; K = 5;
M = 2; L = 1 swap line = 1[1]
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2[1]
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2; swap adc = 1[1]
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1[1]
ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap line = 1[1]
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap adc = 1[1]
ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; swap adc = 1; swap line = 1[1]
1001 to
1101
Reserved
1110
ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2; loop alignment = 1[1]
1111
ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0;
K = 9; M = 2; L = 2 → PD[1]
[1] F : number of byte per frame; HD : High density; K : number of frames per multi frame; M : number of converters; L : number of lanes
See the information about the JESD204A standard on the JEDEC web site.
Table 29. SER control1 (address 0805h)
Bit
7
Symbol
Access Value
Description
-
R
0
Not used
6
TRISTATE_CFG_PAD
R/W
0
1 (default)
CFG pads (3 to 0) are set to high-impedance
Defines the synchronization signal polarity:
synchronization signal is active high
5
4
3
SYNC_POL
R/W
0 (default)
1
synchronization signal is active low
SYNC_SINGLE_ENDED R/W
Defines the input mode of the synchronization signal:
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
Not used
0 (default)
1
1
-
R
-
2 to 0 RESERVED
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
28 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 30. SER control2 (address 0806h)
Bit
7 to 2
1
Symbol
Access Value
Description
-
R
000000
Not used
SWAP_LANE_1_2
R/W
Controls the JESD204A output mux:
0 (default)
1
Outputs of the JESD204A unit are swapped. (Output0 is
connected to Lane1, Output1 is connected to Lane0)
0
SWAP_ADC_0_1
R/W
Controls the JESD204A input multiplexer:
0 (default)
1
Inputs of the JESD204A unit are swapped. (ADC0 output is
connected to Input1, ADC1 is connected to Input0
Table 31. SER analog ctrl (address 0808h)
Bit
Symbol
Access Value
Description
7 to 3
-
R
0
Not used
2 to 0 SWING_SEL
R/W
000
Defines the swing output for the lane pads
Table 32. SER scramblerA (address 0809h)
Bit
Symbol
Access Value
Description
7
-
R
0
Not used
6 to 0 LSB_INIT
R/W
0000000 Defines the initialization vector for the scrambler polynomial
(Lower)
Table 33. SER scramblerB (address 080Ah)
Bit Symbol Access Value
7 to 0 UPP_VECT_INIT R/W
Description
11111111 Defines the initialization vector for the scrambler polynomial
(Upper)
Table 34. SER PRBS Ctrl (address 080Bh)
Bit
Symbol
Access Value
Description
7 to 2
-
R
000000
Not used
1 to 0 PRBS_TYPE
R/W
00 (reset)
Defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used
00
01
10
11
PRBS-7
PRBS-7
PRBS-23
PRBS-31
Table 35. Cfg_0_DID (address 0820h)
Bit Symbol Access Value
Description
7 to 0 DID
R
11101101 Defines the device (= link) identification number
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
29 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 36. Cfg_1_BID (address 0821h)
Bit
Symbol
Access Value
Description
7 to 4
-
R
0000
1010
Not used
3 to 0 BID
R/W
Defines the bank ID – extension to DID
Table 37. Cfg_3_SCR_L (address 0822h)
Bit
7
Symbol
Access Value
Description
SCR
R/W
R
0
Scrambling enabled
6 to 1
0
-
000000
0
Not used
L
R/W
Defines the number of lanes per converter device
Table 38. Cfg_4_F (address 0823h)
Bit
Symbol
Access Value
Description
7 to 3
2 to 0
-
R
00000
000
Not used
F
R/W
Defines the number of octets per frame
Table 39. Cfg_5_K (address 0824h)
Bit
Symbol
Access Value
Description
7 to 5
4 to 0
-
R
000
Not used
K
R/W
00000
Defines the number of frames per multiframe
Table 40. Cfg_6_M (address 0825h)
Bit
7 to 1
0
Symbol
Access Value
Description
-
R
0000000 Not used
M
R/W
0
Defines the number of converters per device
Table 41. Cfg_7_CS_N (address 0826h)
Bit
Symbol
Access Value
Description
7
-
R
0
Not used
6
CS
-
R/W
R
0
Defines the number of control bits per sample
Not used
5 to 4
3 to 0
00
0000
N
R/W
Defines the converter resolution
Table 42. Cfg_8_Np (address 0827h)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
Not used
4 to 0 NP
R/W
00000
Defines the total number of bits per sample
Table 43. Cfg_9_S (address 0828h)
Bit
7 to 1
0
Symbol
Access Value
Description
-
R
0000000 Not used
S
R/W
0
Defines number of samples per converter per frame cycle
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
30 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 44. Cfg_10_HD_CF (address 0829h)
Bit
7
Symbol
Access Value
Description
HD
-
R/W
R
0
Defines high density format
6 to 2
00000
00
Not used
1 to 0 CF
R/W
Defines number of control words per frame clock cycle per link
Table 45. Cfg01_2_LID (address 082Ch)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
Not used
4 to 0 LID
R/W
11011
Defines lane1 identification number
Table 46. Cfg02_2_LID (address 082Dh)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
Not used
4 to 0 LID
R/W
11100
Defines lane2 identification number
Table 47. Cfg02_13_fchk (address 084Ch)
Bit Symbol Access Value
7 to 0 FCHK
Description
R
00000000 Defines the checksum value for lane1
Checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 48. Cfg01_13_fchk (address 084Dh)
Bit Symbol Access Value
7 to 0 FCHK
Description
R
00000000 Defines the checksum value for lane1
Checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 49. Lane01_0_ctrl (address 0870h)
Bit
7
Symbol
Access Value
Description
-
R
0
Not used
6
SCR_IN_MODE
R/W
Defines the input type for scrambler and 8b/10b units:
0 (reset)
1
(Normal mode) = Input of the scrambler and 8b/10b units is the
output of the Frame Assembly unit.
Input of the scrambler and 8b/10b units is the PRSB generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl
register)
5 to 4 LANE_MODE
R/W
Defines output type of lane output unit:
00 (reset)
Normal mode: Lane output is the 8b/10b output unit
Constant mode: Lane output is set to a constant (0 × 0)
Toggle mode: Lane output is toggling between 0 × 0 and 0 × 1
01
10
11
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3
-
R
0
Not used
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
31 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 49. Lane01_0_ctrl (address 0870h) …continued
Bit
Symbol
Access Value
Description
2
LANE_POL
R/W
Defines lane polarity:
0 (default)
Lane polarity is normal
1
Lane polarity is inverted
1
0
LANE_CLK_POS_EDGE R/W
Defines lane clock polarity:
0 (default)
1
Lane clock provided to the serializer is active on positive edge
Lane clock provided to the serializer is active on negative edge
Lane power-down control:
Lane_PD
R/W
0 (default)
1
Lane is in Power-down mode
Table 50. Lane02_0_ctrl (address 0871h)
Bit
7
Symbol
Access Value
Description
-
R
0
Not used
6
SCR_IN_MODE
R/W
Defines the input type for scrambler and 8b/10b units.
0 (reset)
1
Normal mode = Input of the scrambler and 8b/10b units is the
output of the Frame Assembly unit.
input of the scrambler and 8b/10b units is the PRSB generator
(PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_ctrl register)
5 to 4 LANE_MODE
R/W
Defines output type of lane output unit:
00 (reset)
Normal mode: Lane output is the 8b/10b output unit
Constant mode: Lane output is set to a constant (0 × 0)
Toggle mode: Lane output is toggling between 0 × 0 and 0 × 1
01
10
11
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3
2
-
R
0
Not used
LANE_POL
R/W
0
Defines lane polarity:
0 (default)
1
Lane polarity is normal
Lane polarity is inverted
1
0
LANE_CLK_POS_EDGE R/W
Defines lane clock polarity:
0 (default)
1
Lane clock provided to the serializer is active on positive edge
Lane clock provided to the serializer is active on negative edge
Lane power-down control:
Lane_PD
R/W
0 (default)
1
Lane is in Power-down mode
Table 51. ADC01_0_ctrl (address 0890h)
Bit
Symbol
Access Value
00
Description
7 to 6
-
R
Not used
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
32 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 51. ADC01_0_ctrl (address 0890h) …continued
Bit
Symbol
Access Value
Description
5 to 4 ADC_MODE
R/W
Defines input type of JESD204A unit:
ADC output is connected to the JESD204A input
Not used
00 (reset)
01
10
11
JESD204A input is fed with a dummy constant (set to 0x0000)
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3 to 1
0
-
R
000
Not used
ADC_PD
R/W
ADC power-down control:
0 (default)
1
ADC is in Power-down mode
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
33 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
Table 52. ADC02_0_ctrl (address 0891h)
Bit
Symbol
Access Value
Description
7 to 6
-
R
00
Not used
5 to 4 ADC_MODE
R/W
Defines input type of JESD204A unit:
ADC output is connected to the JESD204A input
Not used
00 (reset)
01
10
11
JESD204A input is fed with a dummy constant (set to 0x0000)
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3 to 1
0
-
R
000
Not used
ADC_PD
R/W
ADC power-down control:
0 (default)
1
ADC is in Power-down mode
13.6.5 Serial interface timings
The Figure 24 shows the SPI timings:
t
t
w(SCLKL)
t
su
t
t
h
h
su
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 24. SPI timings
The timing specification link to the Figure 24 is described in the Table 8.
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
34 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
14. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
SOT684-7
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
e
v
C A
C
B
1/2 e
b
L
y
y
w
C
1
15
28
14
29
e
E
e
2
h
1/2 e
1
42
terminal 1
index area
56
43
X
D
h
0
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
(1)
E
A
A
b
c
D
D
h
E
e
e
1
e
2
L
v
w
y
y
1
1
h
max 1.00 0.05 0.30
mm nom 0.85 0.02 0.21 0.2 8.0 5.80 8.0 6.40 0.5 6.5 6.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 7.9 5.65 7.9 6.25 0.3
8.1 5.95 8.1 6.55
0.5
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot684-7_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
08-11-19
09-03-04
SOT684-7
MO-220
Fig 25. Package outline SOT684-1 (HVQFN56)
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
35 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
15. Revision history
Table 53. Revision history
Document ID
Release date
Data sheet status
Change Supersedes
notice
ADC1213D065_080_105_125_2 20090617
Objective data sheet
-
ADC1213D065_080_105_125_1
Modifications: • Values in Table 7 have been updated.
ADC1213D065_080_105_125_1 20090528
Objective data sheet
-
-
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
36 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1213D065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 17 June 2009
37 of 38
ADC1213D065/080/105/125
NXP Semiconductors
Dual 12-bit ADC; 65, 80, 105 or 125 Msps
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
16.3
16.4
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
17
18
Contact information . . . . . . . . . . . . . . . . . . . . 37
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics. . . . . . . . . . . . . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . 10
Serial output timings . . . . . . . . . . . . . . . . . . . 10
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
11.1
12
13
13.1
Application information. . . . . . . . . . . . . . . . . . 12
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input stage description . . . . . . . . . . . . . . . . . . 12
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13
Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System reference and power management . . 14
Internal/external reference . . . . . . . . . . . . . . . 14
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Common-mode output voltage (VI(CM)). . . . . . 16
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Equivalent input circuit . . . . . . . . . . . . . . . . . . 18
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 18
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial output equivalent circuit . . . . . . . . . . . . 19
JESD204A serializer. . . . . . . . . . . . . . . . . . . . 20
Digital JESD204A formatter . . . . . . . . . . . . . . 20
ADC core output codes versus input voltage . 22
Serial Peripheral Interface (SPI) . . . . . . . . . . . 22
Register description . . . . . . . . . . . . . . . . . . . . 22
Channel control. . . . . . . . . . . . . . . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . 25
JESD204A digital control registers . . . . . . . . . 27
Serial interface timings . . . . . . . . . . . . . . . . . . 34
13.1.1
13.1.2
13.1.3
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.3.1
13.3.2
13.3.3
13.4
13.4.1
13.5
13.5.1
13.5.2
13.6
13.6.1
13.6.2
13.6.3
13.6.4
13.6.5
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 36
16
16.1
16.2
Legal information. . . . . . . . . . . . . . . . . . . . . . . 37
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 June 2009
Document identifier: ADC1213D065_080_105_125_2
相关型号：
ADC1213D125C1
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
NXP
ADC1213D125HN
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
NXP
ADC1213D125HN-C1
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
IDT
ADC1213D125HN/C1,5
Dual 12-bit ADC; 125 Msps, SOT684-7 Package, Standard Markigg, Reel Dry Pack, SMD, 13"
IDT
ADC1213S065C1
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface
NXP
ADC1213S065HN
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface
NXP
©2020 ICPDF网 联系我们和版权申明