BF1201 [NXP]
N-channel dual-gate PoLo MOS-FETs; N沟道双栅MOS POLO - FET的
| 型号： | BF1201 |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate PoLo MOS-FETs |
| 文件： | 总16页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF1201; BF1201R; BF1201WR
N-channel dual-gate PoLo
MOS-FETs
Product specification
2000 Mar 29
Supersedes data of 1999 Dec 01
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
FEATURES
PINNING
PIN
• Short channel transistor with high
forward transfer admittance to input
capacitance ratio
DESCRIPTION
3
4
1
2
3
4
source
drain
• Low noise gain controlled amplifier
gate 2
gate 1
2
1
• Partly internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
Top view
MSB035
BF1201R marking code: LBp
APPLICATIONS
Fig.2 Simplified outline
(SOT143R).
• VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
3
4
4
3
page
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1201,
BF1201R and BF1201WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
1
2
2
1
Top view
MSB842
Top view
MSB014
BF1201 marking code: LAp.
BF1201WR marking code: LA
Fig.1 Simplified outline
(SOT143B).
Fig.3 Simplified outline
(SOT343R).
QUICK REFERENCE DATA
SYMBOL
VDS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
10
UNIT
drain-source voltage
drain current
−
−
−
−
−
−
V
ID
30
200
35
3.1
30
1.8
−
mA
mW
mS
pF
Ptot
yfs
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
23
−
28
2.6
15
1
Cig1-ss
Crss
F
f = 1 MHz
−
fF
f = 400 MHz
−
dB
Xmod
cross-modulation
input level for k = 1% at
40 dB AGC
105
−
dBµV
Tj
operating junction temperature
−
−
150
°C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
2000 Mar 29
2
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN.
MAX.
10
UNIT
VDS
ID
−
−
−
−
V
drain current (DC)
gate 1 current
30
mA
mA
mA
IG1
IG2
Ptot
±10
±10
gate 2 current
total power dissipation
BF1201; BF1201R
BF1201WR
Ts ≤ 113 °C; note 1
Ts ≤ 109 °C; note 1
−
−
200
200
+150
150
mW
mW
°C
Tstg
Tj
storage temperature
operating junction temperature
−65
−
°C
Note
1. Ts is the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-s
thermal resistance from junction to soldering point
BF1201; BF1201R
185
155
K/W
K/W
BF1201WR
MCD934
250
handbook, halfpage
P
tot
(mW)
200
(1)
(2)
150
100
50
0
0
50
100
150
200
T
(°C)
s
(1) BF1201WR.
(2) BF1201 and BF1201R.
Fig.4 Power derating curve.
2000 Mar 29
3
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
STATIC CHARACTERISTICS
Tj = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0; ID = 10 µA
VG2-S = VDS = 0; IG1-S = 10 mA
VG1-S = VDS = 0; IG2-S = 10 mA
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VG2-S = 4 V; VDS = 5 V; ID = 100 µA
VG1-S = VDS = 5 V; ID = 100 µA
10
6
−
V
V(BR)G1-SS gate 1-source breakdown voltage
V(BR)G2-SS gate 2-source breakdown voltage
−
V
6
−
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
0.5
0.5
0.3
0.3
11
1.5
1.5
1.0
1.2
19
V
V
V
V
VG2-S = 4 V; VDS = 5 V; RG1 = 62 kΩ;
mA
note 1
IG1-SS
IG2-SS
gate 1 cut-off current
gate 2 cut-off current
VG2-S = VDS = 0; VG1-S = 5 V
VG1-S = VDS = 0; VG2-S = 4 V
−
−
50
20
nA
nA
Note
1. RG1 connects G1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified.
SYMBOL
yfs
PARAMETER
CONDITIONS
MIN.
23
TYP. MAX. UNIT
forward transfer admittance pulsed; Tj = 25 °C
input capacitance at gate 1 f = 1 MHz
input capacitance at gate 2 f = 1 MHz
28
2.6
1.1
0.9
15
5
35
3.1
−
mS
pF
pF
pF
fF
Cig1-ss
Cig2-ss
Coss
−
−
−
−
−
−
−
−
output capacitance
f = 1 MHz
−
Crss
reverse transfer capacitance f = 1 MHz
30
7
F
noise figure
power gain
f = 10.7 MHz; GS = 20 mS; BS = 0
dB
dB
dB
dB
f = 400 MHz; YS = YS opt
1
1.8
2.5
−
f = 800 MHz; YS = YS opt
1.9
33.5
Gtr
f = 200 MHz; GS = 2 mS; BS = BS opt
;
;
GL = 0.5 mS; BL = BL opt
f = 400 MHz; GS = 2 mS; BS = BS opt
GL = 1 mS; BL = BL opt
f = 800 MHz; GS = 3.3 mS; BS = BS opt
GL = 1 mS; BL = BL opt
;
−
−
29
24
−
−
dB
dB
;
;
;
Xmod
cross-modulation
input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 1
at 0 dB AGC
at 10 dB AGC
at 40 dB AGC
90
−
−
−
−
−
dBµV
dBµV
dBµV
95
−
105
Note
1. Measured in Fig.21 test circuit.
2000 Mar 29
4
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
MCD935
MCD936
25
24
handbook, halfpage
handbook, halfpage
3.5 V
3 V
V
= 4 V
G2-S
I
D
(mA)
20
V
= 1.8 V
I
G1-S
D
(mA)
2.5 V
2 V
1.7 V
16
1.6 V
1.5 V
1.4 V
15
10
8
1.3 V
1.2 V
1.5 V
5
0
1 V
0
0
0
0.5
1
1.5
2
2.5
(V)
2
4
6
8
10
(V)
V
V
DS
G1-S
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 °C.
Tj = 25 °C.
Fig.5 Transfer characteristics; typical values.
Fig.6 Output characteristics; typical values.
MCD937
MCD938
100
40
handbook, halfpage
handbook, halfpage
V
= 4 V
I
G2-S
G1
(µA)
3.5 V
3 V
y
fs
V
= 4 V
(mS)
G2-S
80
30
3.5 V
60
40
20
10
0
2.5 V
3 V
2.5 V
2 V
20
2 V
1.5 V
0
0
0.5
1
1.5
2
2.5
(V)
0
5
10
15
20
I
25
(mA)
V
D
G1-S
VDS = 5 V.
VDS = 5 V.
Tj = 25 °C.
Tj = 25 °C.
Fig.7 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.8 Forward transfer admittance as a function
of drain current; typical values.
2000 Mar 29
5
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
MCD940
MCD939
20
16
handbook, halfpage
handbook, halfpage
I
D
I
D
(mA)
16
(mA)
12
12
8
8
4
0
4
0
0
1
2
3
4
5
0
10
20
30
40
I
50
(µA)
V
(V)
GG
G1
VDS = 5 V; VG2-S = 4 V.
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 62 kΩ (connected to VGG); see Fig.21.
Tj = 25 °C.
Fig.9 Drain current as a function of gate 1 current;
typical values.
Fig.10 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD941
MCD942
25
20
handbook, halfpage
68 kΩ
82 kΩ
handbook, halfpage
R
= 39 kΩ
I
G1
47 kΩ
56 kΩ
62 kΩ
I
D
(mA)
20
D
(mA)
V
= 5 V
GG
16
12
8
100 kΩ
4.5 V
15
10
4 V
3.5 V
3 V
5
4
0
0
0
2
4
6
8
10
(V)
0
2
4
6
V
(V)
V
= V
DS
G2-S
GG
VG2-S = 4 V; Tj = 25 °C.
RG1 connected to VGG; see Fig.21.
VDS = 5 V; Tj = 25 °C.
RG1 = 62 kΩ (connected to VGG); see Fig.21.
Fig.11 Drain current as a function of gate 1 (= VGG
and drain supply voltage; typical values.
)
Fig.12 Drain current as a function of gate 2
voltage; typical values.
2000 Mar 29
6
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
MCD943
MCD944
60
0
handbook, halfpage
V
= 5 V
handbook, halfpage
gain
GG
reduction
(dB)
I
G1
(µA)
−10
4.5 V
4 V
40
−20
−30
3.5 V
3 V
20
−40
0
−50
0
2
4
6
0
1
2
3
4
V
(V)
V
(V)
G2-S
AGC
VDS = 5 V; Tj = 25 °C.
RG1 = 62 kΩ (connected to VGG); see Fig.21.
VDS = 5 V; VGG = 5 V; RG1 = 62 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.14 Typical gain reduction as a function of the
AGC voltage; see Fig.21.
MCD945
120
MCD946
handbook, halfpage
20
handbook, halfpage
V
unw
(dBµV)
I
D
(mA)
16
110
12
8
100
90
4
0
80
0
10
20
30
40
50
0
10
20
30
40
50
gain reduction (dB)
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 62 kΩ; f = 50 MHz;
funw = 60 MHz; Tamb = 25 °C.
VDS = 5 V; VGG = 5 V; RG1 = 62 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.15 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.21.
Fig.16 Drain current as a function of gain
reduction; typical values; see Fig.21.
2000 Mar 29
7
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
MCD947
2
10
MCD948
3
3
handbook, halfpage
10
−10
handbook, halfpage
Y
is
(mS)
ϕ
y
rs
rs
(deg)
(µS)
10
ϕ
rs
2
2
−10
−10
−1
10
b
is
y
rs
g
is
1
10
−1
10
2
3
10
10
10
1
2
3
f (MHz)
10
10
10
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
ID = 15 mA; Tamb = 25 °C.
Fig.17 Input admittance as a function of frequency;
typical values.
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
MCD949
MCD950
2
2
10
−10
10
handbook, halfpage
handbook, halfpage
ϕ
y
Y
fs
fs
os
(deg)
(mS)
(mS)
y
fs
b
os
1
ϕ
fs
10
−10
−1
10
g
os
−2
−1
1
10
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 °C.
ID = 15 mA; Tamb = 25 °C.
Fig.19 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.20 Output admittance as a function of
frequency; typical values.
2000 Mar 29
8
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
V
AGC
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
R
L
50 Ω
L1
≈2.2 µH
C2
DUT
C4
4.7 nF
R
GEN
50 Ω
R2
50 Ω
R
G1
4.7 nF
V
V
V
I
GG
DS
MGS315
Fig.21 Cross-modulation test set-up.
Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 °C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.987
0.985
0.978
0.976
0.949
0.928
0.905
0.882
0.860
0.838
0.818
−4.72
−9.39
2.775
2.774
2.731
2.671
2.599
2.501
2.400
2.297
2.199
2.096
1.997
174.6
169.5
159.1
148.8
138.8
129.1
119.8
110.9
102.4
94.2
0.0006
0.0010
0.0019
0.0026
0.0032
0.0035
0.0035
0.0033
0.0029
0.0024
0.0021
88.8
86.7
79.7
74.2
69.9
65.9
64.6
65.7
69.1
83.3
103.8
0.997
0.997
0.996
0.994
0.992
0.989
0.986
0.982
0.979
0.975
0.971
−1.84
−3.37
−18.59
−27.74
−36.59
−45.08
−53.26
−61.07
−68.48
−75.55
−82.23
−6.72
−10.02
−13.33
−16.55
−19.64
−22.63
−25.54
−28.44
−31.42
86.3
Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 °C
Γopt
f
Fmin
(dB)
Rn
(Ω)
(MHz)
(ratio)
(deg)
400
800
1
0.825
0.753
38.93
70.65
50
1.9
38.75
2000 Mar 29
9
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
PACKAGE OUTLINES
Plastic surface mounted package; 4 leads
SOT143B
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
4
3
Q
A
A
1
c
1
2
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT143B
2000 Mar 29
10
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
3
4
Q
A
A
1
c
2
1
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.55
0.25
0.45
0.25
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-03-10
99-09-13
SOT143R
SC-61B
2000 Mar 29
11
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
Plastic surface mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
H
v
M
A
y
E
e
3
4
Q
A
A
1
c
2
1
L
p
w
M
B
b
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
A
UNIT
b
b
c
D
E
e
e
H
E
L
Q
v
w
y
p
p
1
1
0.4
0.3
1.1
0.8
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.23
0.13
mm
0.1
1.15
0.2
0.2
0.1
1.3
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT343R
97-05-21
2000 Mar 29
12
Philips Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Mar 29
13
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
NOTES
2000 Mar 29
14
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
NOTES
2000 Mar 29
15
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
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603504/02/pp16
Date of release: 2000 Mar 29
Document order number: 9397 750 06901
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