BF904A,215 [NXP]
N-channel dual-gate MOSFET SOT-143 4-Pin;
| 型号： | BF904A,215 |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate MOSFET SOT-143 4-Pin |
| 文件： | 总15页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BF904A; BF904AR; BF904AWR
N-channel dual gate MOS-FETs
Rev. 04 — 13 November 2007
Product data sheet
IMPORTANT NOTICE
Dear customer,
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- NXP Semiconductors, which will be used in future data sheets together with new contact
details.
In data sheets where the previous Philips references remain, please use the new links as
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(email)
The copyright notice at the bottom of each page (or elsewhere in the document,
depending on the version)
- © Koninklijke Philips Electronics N.V. (year). All rights reserved -
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If you have any questions related to the data sheet, please contact our nearest sales
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NXP Semiconductors
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
FEATURES
PINNING
PIN
• Specially designed for use at 5 V
supply voltage
DESCRIPTION
source
4
3
1
2
3
4
• Short channel transistor with high
transfer admittance to input
capacitance ratio
drain
gate 2
gate 1
1
2
• Low noise gain controlled amplifier
up to 1 GHz
Top view
MSB014
• Superior cross-modulation
performance during AGC.
BF904A marking code: %M7.
Fig.1 Simplified outline
(SOT143B).
APPLICATIONS
•
VHF and UHF applications with
3 to 7 V supply voltage such as
television tuners and professional
communications equipment.
3
4
3
4
halfpage
DESCRIPTION
2
1
Enhancement type field-effect
transistors. The transistors consist of
an amplifier MOS-FET with source
and substrate interconnected and an
internal bias circuit to ensure good
cross-modulationperformanceduring
AGC.
2
1
Top view
MSB842
Top view
MSB035
BF904AR marking code: %M8.
BF904AWR marking code: MH.
Fig.2 Simplified outline
(SOT143R).
Fig.3 Simplified outline
(SOT343R).
The BF904A, BF904AR and
BF904AWR are encapsulated in the
SOT143B, SOT143R and SOT343R
plastic packages respectively.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN.
TYP. MAX. UNIT
VDS
ID
−
−
7
V
drain current
−
−
30
200
30
2.6
35
−
mA
mW
mS
pF
fF
Ptot
yfs
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
Ts ≤ 110 °C
−
−
22
−
25
2.2
25
2
Cig1-ss
Crss
F
f = 1 MHz
−
f = 800 MHz
−
dB
°C
Tj
operating junction temperature
−
−
150
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
Rev. 04 - 13 November 2007
2 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDS
PARAMETER
drain-source voltage
CONDITIONS
MIN.
MAX.
UNIT
−
−
−
−
−
7
V
ID
drain current
30
mA
mA
mA
mW
°C
IG1
IG2
Ptot
Tstg
Tj
gate 1 current
±10
±10
200
+150
150
gate 2 current
total power dissipation
storage temperature
operating junction temperature
Ts ≤ 110 °C; note 1; see Fig.4
−65
−
°C
Note
1. Ts is the temperature of the soldering point of the source lead.
MGL615
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
50
100
150
200
T
(°C)
s
Fig.4 Power derating curve.
Rev. 04 - 13 November 2007
3 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
note 1
VALUE
UNIT
Rth j-s
thermal resistance from junction to soldering point
200
K/W
Note
1. Soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
15
UNIT
V(BR)G1-SS
V(BR)G2-SS
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
gate 1-source breakdown voltage
gate 2-source breakdown voltage
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
VG2-S = VDS = 0; IG1-S = 10 mA
VG1-S = VDS = 0; IG2-S = 10 mA
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VG2-S = 4 V; VDS = 5 V; ID = 20 µA
VG1-S = VDS = 5 V; ID = 20 µA
6
V
6
15
1.5
1.5
1
V
0.5
0.5
0.3
0.3
8
V
V
V
1.2
13
V
VG2-S = 4 V; VDS = 5 V;
mA
RG1 = 120 kΩ; note 1
IG1-SS
IG2-SS
gate 1 cut-off current
gate 2 cut-off current
VG2-S = VDS = 0; VG1-S = 5 V
VG1-S = VDS = 0; VG2-S = 5 V
−
−
50
50
nA
nA
Note
1. RG1 connects gate 1 to VGG = 5 V; see Fig.21.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
22
TYP.
25
MAX.
UNIT
yfs
Cig1-s
Cig2-s
Cos
Crs
forward transfer admittance pulsed; Tj = 25 °C
30
2.6
2
mS
pF
pF
pF
fF
input capacitance at gate 1
input capacitance at gate 2
drain-source capacitance
f = 1 MHz
f = 1 MHz
f = 1 MHz
−
1
1
−
−
−
2.2
1.5
1.4
25
1
1.7
35
1.5
2.8
reverse transfer capacitance f = 1 MHz
noise figure f = 200 MHz; GS = 2 mS; BS = BSopt
F
dB
dB
f = 800 MHz; GS = GSopt; BS = BSopt
2
Rev. 04 - 13 November 2007
4 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
MLD268
MRA769
40
0
handbook, halfpage
gain
Y
reduction
fs
(dB)
(mS)
30
10
20
30
40
50
20
10
0
50
0
50
100
150
( C)
0
1
2
3
4
o
T
V
(V)
j
AGC
f = 50 MHz.
Fig.5 Transfer admittance as a function of the
junction temperature; typical values.
Fig.6 Typical gain reduction as a function of
the AGC voltage; see Fig.21.
MRA771
MLD270
120
20
handbook, halfpage
V
V
= 4 V
S
3 V 2.5 V
2 V
unw
(dB µV)
110
G2
I
D
(mA)
15
100
90
10
5
1.5 V
1 V
80
0
0
10
20
30
40
50
0
0.4
0.8
1.2
1.6
V
2.0
(V)
gain reduction (dB)
G1
S
VDS = 5 V; VGG = 5 V; fw = 50 MHz.
funw = 60 MHz; Tamb = 25 °C; RG1 = 120 kΩ.
VDS = 5 V.
Fig.7 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.21.
Tj = 25 °C.
Fig.8 Transfer characteristics; typical values.
Rev. 04 - 13 November 2007
5 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
MLD269
MLD271
20
150
handbook, halfpage
handbook, halfpage
V
= 1.4 V
S
V
= 4 V
G2 S
I
G1
D
I
3.5 V
(mA)
G1
16
(µA)
1.3 V
3 V
100
1.2 V
1.1 V
12
8
2.5 V
2 V
1.0 V
0.9 V
50
4
0
0
0
0
2
4
6
8
10
(V)
0.5
1.0
1.5
2.0
2.5
(V)
V
V
G1
DS
S
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 °C.
Tj = 25 °C.
Fig.10 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.9 Output characteristics; typical values.
MLD272
MLD273
16
40
handbook, halfpage
handbook, halfpage
I
y
D
fs
(mS)
(mA)
V
= 4 V
S
G2
12
30
3.5 V
3 V
8
4
0
20
2.5 V
10
0
2 V
0
10
20
30
40
50
(µA)
0
4
8
12
16
20
(mA)
I
I
G1
D
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 °C.
VDS = 5 V.
Tj = 25 °C.
Fig.11 Forward transfer admittance as a
function of drain current; typical values.
Fig.12 Drain current as a function of gate 1 current;
typical values.
Rev. 04 - 13 November 2007
6 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
MLD274
MLD275
20
12
handbook, halfpage
handbook, halfpage
R
= 47 kΩ 68 kΩ
G1
I
D
I
D
82 kΩ
(mA)
(mA)
15
100 kΩ
120 kΩ
150 kΩ
8
10
5
180 kΩ
220 kΩ
4
0
0
0
2
4
6
8
0
1
2
3
4
5
V
(V)
V
= V
(V)
DS
GG
GG
VG2-S = 4 V; Tj = 25 °C.
G1 connected to VGG; see Fig.21.
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.21.
R
Fig.14 Drain current as a function of gate 1
(= VGG) and drain supply voltage;
typical values.
Fig.13 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MLD276
MLB945
12
40
handbook, halfpage
handbook, halfpage
V
= 5 V
4.5 V
GG
I
G1
(µA)
I
D
V
= 5 V
GG
4 V
(mA)
30
3.5 V
3 V
4.5 V
8
4 V
3.5 V
3 V
20
10
4
0
0
0
0
2
4
6
2
4
6
V
(V)
S
V
(V)
S
G2
G2
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.21.
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.21.
Fig.15 Drain current as a function of gate 2 voltage;
typical values.
Fig.16 Gate 1 current as a function of gate 2
voltage; typical values.
Rev. 04 - 13 November 2007
7 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
MLD277
MLD278
2
10
3
2
3
10
rs
10
handbook, halfpage
y
y
ϕ
is
(mS)
rs
(deg)
(µS)
ϕ
rs
2
10
10
10
y
rs
b
is
1
10
10
g
is
1
1
10
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 °C.
ID = 10 mA; Tamb = 25 °C.
Fig.17 Input admittance as a function of frequency;
typical values.
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
MGL614
MLD279
2
2
10
10
fs
10
handbook, halfpage
y
os
(mS)
ϕ
y
fs
y
fs
fs
b
g
(deg)
(mS)
os
1
ϕ
10
10
os
−1
10
10
−2
1
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 °C.
ID = 10 mA; Tamb = 25 °C.
Fig.19 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.20 Output admittance as a function of
frequency; typical values.
Rev. 04 - 13 November 2007
8 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
V
AGC
R1
10 kΩ
C1
4.7 nF
C3 12 pF
R
L
L1
C2
DUT
50 Ω
≈
450 nH
C4
4.7 nF
R
R2
GEN
R
G1
50 Ω
50Ω
4.7 nF
V
I
V
MLD171
GG
V
DS
Fig.21 Cross-modulation test set-up.
Rev. 04 - 13 November 2007
9 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C
S11
S21
S12
S22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
40
100
0.989
0.987
0.976
0.972
0.947
0.925
0.905
0.883
0.861
0.841
0.822
0.787
0.752
0.723
0.685
0.665
0.659
0.670
0.700
0.729
0.726
−3.2
−7.9
2.52
2.52
2.47
2.43
2.36
2.26
2.19
2.10
2.01
1.93
1.85
1.71
1.59
1.47
1.36
1.31
1.30
1.26
1.10
0.82
0.52
175.9
169.4
159.2
150.5
139.6
130.3
121.1
112.3
103.6
95.5
0.001
0.001
0.003
0.004
0.005
0.005
0.005
0.006
0.006
0.006
0.006
0.007
0.011
0.019
0.021
0.026
0.035
0.050
0.076
0.106
0.128
87.9
86.1
0.989
0.988
0.984
0.985
0.975
0.968
0.961
0.954
0.946
0.934
0.931
0.923
0.926
0.935
0.931
0.930
0.944
0.941
0.849
0.642
0.480
−1.7
−4.3
200
−15.7
−23.3
−30.6
−37.6
−44.4
−50.9
−57.0
−63.0
−68.4
−78.9
−88.1
−97.3
−106.3
−114.0
−119.8
−124.2
−129.3
−138.7
−150.1
81.4
−8.6
300
80.5
−12.7
−16.9
−20.8
−24.7
−28.4
−32.0
−35.6
−39.3
−46.7
−54.2
−62.2
−69.3
−77.7
−89.1
−103.5
−119.7
−130.9
−130.6
400
76.9
500
75.6
600
75.5
700
78.0
800
85.3
900
90.7
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
87.8
102.6
127.1
143.7
150.0
149.4
151.5
158.2
163.4
162.2
150.5
137.4
72.3
57.3
40.1
25.0
7.7
−14.0
−42.2
−78.2
−120.8
−162.8
Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C
Γopt
f
Fmin
(dB)
Rn
(Ω)
(MHz)
(ratio)
(deg)
49.6
800
2.0
0.686
50.4
Rev. 04 - 13 November 2007
10 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
PACKAGE OUTLINES
Plastic surface mounted package; 4 leads
SOT143B
D
B
E
A
X
y
H
v
M
A
E
e
b
p
w
M
B
4
3
Q
A
A
1
c
1
2
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT143B
Rev. 04 - 13 November 2007
11 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
3
4
Q
A
A
1
c
2
1
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.55
0.25
0.45
0.25
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-03-10
SOT143R
Rev. 04 - 13 November 2007
12 of 15
NXP Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
Plastic surface mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
H
v
M
A
y
E
e
3
4
Q
A
A
1
c
2
1
L
p
w
M
B
b
b
1
p
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
A
UNIT
b
b
c
D
E
e
e
H
E
L
Q
v
w
y
p
p
1
1
0.4
0.3
1.1
0.8
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.23
0.13
mm
0.1
1.15
0.2
0.2
0.1
1.3
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT343R
97-05-21
Rev. 04 - 13 November 2007
13 of 15
BF904A; BF904AR; BF904AWR
NXP Semiconductors
N-channel dual gate MOS-FETs
Legal information
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Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
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information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
Definitions
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specified use without further testing or modification.
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
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General — Information in this document is believed to be accurate and
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Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Rev. 04 - 13 November 2007
14 of 15
BF904A; BF904AR; BF904AWR
NXP Semiconductors
N-channel dual gate MOS-FETs
Revision history
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BF904A_AR_AWR_N_4 20071113
Product data sheet
-
BF904A_AR_AWR_3
Modifications:
• Fig. 1 and 2 on page 2; Figure note changed
BF904A_AR_AWR_3
(9397 750 05271)
19990514
Product specification
-
-
-
BF904A_AR_AWR_N_2
BF904A_AR_AWR_N_2 19990201
(9397 750 05234)
Preliminary specification
Preliminary specification
BF904A_AR_AWR_N_1
-
BF904A_AR_AWR_N_1 19981130
(9397 750 04748)
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 November 2007
Document identifier: BF904A_AR_AWR_N_4
相关型号：
BF904AWRT/R
TRANSISTOR 2 CHANNEL, UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, PLASTIC PACKAGE-4, FET RF Small Signal
NXP
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