BF904WR,135 [NXP]
N-channel dual-gate MOSFET;
| 型号： | BF904WR,135 |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate MOSFET |
| 文件： | 总14页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF904WR
N-channel dual-gate MOS-FET
Product specification
2010 Sep 15
Supersedes data of 1995 Apr 25
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
FEATURES
PINNING
Specially designed for use at 5 V supply voltage
PIN
1
SYMBOL
DESCRIPTION
Short channel transistor with high forward transfer
admittance to input capacitance ratio
s, b
d
source
drain
2
Low noise gain controlled amplifier up to 1 GHz
3
g2
g1
gate 2
gate 1
Superior cross-modulation performance during AGC.
4
APPLICATIONS
d
handbook, halfpage
VHF and UHF applications with 3 to 7 V supply voltage
such as television tuners and professional
communications equipment.
3
4
DESCRIPTION
g
2
g
Enhancement type field-effect transistor in a plastic
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and
substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.
1
2
1
s,b
Top view
MAM192
Marking code: MC*
* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA
SYMBOL
VDS
PARAMETER
drain-source voltage
CONDITIONS
MIN.
TYP.
MAX.
UNIT
7
V
ID
drain current
30
mA
mW
C
Ptot
Tj
total power dissipation
operating junction temperature
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
280
150
30
yfs
Cig1-s
Crs
F
22
25
2.2
25
2
mS
pF
2.6
35
f = 1 MHz
fF
f = 800 MHz
dB
2010 Sep 15
2
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDS
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
drain-source voltage
drain current
7
V
ID
30
mA
mA
mA
mW
IG1
IG2
Ptot
gate 1 current
10
10
280
gate 2 current
total power dissipation
up to Tamb = 50 C; see Fig.2;
note 1
Tstg
Tj
storage temperature
65
+150
+150
C
C
operating junction temperature
Note
1. Device mounted on a printed-circuit board.
MLD150
300
handbook, halfpage
P
tot
(mW)
200
100
0
0
50
100
150
200
o
T
( C)
amb
Fig.2 Power derating curve.
2010 Sep 15
3
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
note 1
Ts = 91 C; note 2
VALUE
UNIT
K/W
K/W
thermal resistance from junction to ambient
thermal resistance from junction to soldering point
350
210
Rth j-s
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
15
UNIT
V(BR)G1-SS
V(BR)G2-SS
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA
gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA
6
6
V
15
1.5
1.5
1
V
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VG2-S = 4V; VDS = 5 V; ID = 20 A
VG1-S = VDS = 5 V; ID = 20 A
0.5
0.5
0.3
0.3
8
V
V
V
1.2
13
V
VG2-S = 4 V; VDS = 5 V; RG1 = 120 k;
mA
note 1
IG1-SS
IG2-SS
gate 1 cut-off current
gate 2 cut-off current
VG2-S = VDS = 0; VG1-S = 5 V
VG1-S = VDS = 0; VG2-S = 5 V
50
50
nA
nA
Note
1. RG connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified.
SYMBOL
yfs
Cig1-s
Cig2-s
Cos
PARAMETER
CONDITIONS
MIN.
22
TYP.
25
MAX.
UNIT
forward transfer admittance pulsed; Tj = 25 C
30
2.6
2
mS
pF
pF
pF
fF
input capacitance at gate 1
input capacitance at gate 2
drain-source capacitance
f = 1 MHz
f = 1 MHz
f = 1 MHz
1
1
2.2
1.5
1.3
25
1
1.6
35
1.5
2.8
Crs
reverse transfer capacitance f = 1 MHz
noise figure f = 200 MHz; GS = 2 mS; BS = BSopt
f = 800 MHz; GS = GSopt; BS = BSopt
F
dB
dB
2
2010 Sep 15
4
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
MRA769
MLD268
40
0
handbook, halfpage
gain
reduction
Y
fs
(dB)
10
(mS)
30
20
30
40
20
10
0
50
0
1
2
3
4
50
0
50
100
150
( C)
o
V
(V)
T
AGC
j
f = 50 MHz.
Tj = 25 C.
Fig.3 Forward transfer admittance as a function
of junction temperature; typical values.
Fig.4 Typical gain reduction as a function of
AGC voltage.
MLD270
MRA771
120
20
handbook, halfpage
V
= 4 V
G2 S
3 V 2.5 V
2 V
V
unw
(dB μV)
110
I
D
(mA)
15
100
90
10
5
1.5 V
1 V
0
80
0
10
20
30
40
50
0
0.4
0.8
1.2
1.6
V
2.0
(V)
gain reduction (dB)
G1
S
VGG = 5 V; fw = 50 MHz.
funw = 60 MHz; Tamb = 25 C; RG1 = 120 k
VDS = 5 V.
Tj = 25 C.
Fig.5 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.19.
Fig.6 Transfer characteristics; typical values.
2010 Sep 15
5
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
MLD269
MLD271
20
150
handbook, halfpage
handbook, halfpage
V
= 1.4 V
S
V
= 4 V
G2 S
I
G1
D
I
3.5 V
(mA)
G1
16
(μA)
1.3 V
3 V
100
1.2 V
1.1 V
12
8
2.5 V
2 V
1.0 V
0.9 V
50
4
0
0
0
0
2
4
6
8
10
(V)
0.5
1.0
1.5
2.0
2.5
(V)
V
V
G1
DS
S
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 C.
Tj = 25 C.
Fig.8 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.7 Output characteristics; typical values.
MLD272
MLD273
16
40
handbook, halfpage
handbook, halfpage
I
y
D
fs
(mS)
(mA)
V
= 4 V
S
G2
12
30
3.5 V
3 V
8
4
0
20
2.5 V
10
0
2 V
0
10
20
30
40
50
(μA)
0
4
8
12
16
20
(mA)
I
I
G1
D
VDS = 5 V.
VDS = 5 V; VG2-S = 4 V.
Tj = 25 C.
Tj = 25 C.
Fig.9 Forward transfer admittance as a
function of drain current; typical values.
Fig.10 Drain current as a function of gate 1 current;
typical values.
2010 Sep 15
6
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
MLD275
MLD274
12
20
handbook, halfpage
handbook, halfpage
R
= 47 kΩ 68 kΩ
G1
I
D
I
D
82 kΩ
(mA)
(mA)
15
100 kΩ
120 kΩ
150 kΩ
8
10
5
180 kΩ
220 kΩ
4
0
0
0
0
1
2
3
4
5
2
4
6
8
V
(V)
V
= V
(V)
DS
GG
GG
VDS = 5 V; VG2-S = 4 V.
RG1 = 120 k (connected to VGG); Tj = 25 C.
VG2-S = 4 V.
RG1 connected to VGG; Tj = 25 C.
Fig.11 Drain current as a function of gate 1
supply voltage (= VGG); typical values;
see Fig.19.
Fig.12 Drain current as a function of gate 1
(= VGG) and drain supply voltage;
typical values; see Fig.19.
MLD276
MLB945
12
40
handbook, halfpage
handbook, halfpage
V
= 5 V
4.5 V
GG
I
G1
(μA)
I
D
V
= 5 V
GG
4 V
(mA)
30
3.5 V
3 V
4.5 V
8
4 V
3.5 V
3 V
20
10
0
4
0
0
2
4
6
0
2
4
6
V
(V)
S
V
(V)
S
G2
G2
VDS = 5 V; Tj = 25 C.
VDS = 5 V; Tj = 25 C.
RG = 120 k (connected to VGG).
RG = 120 k (connected to VGG).
Fig.13 Drain current as a function of gate 2 voltage;
typical values; see Fig.19.
Fig.14 Gate 1 current as a function of gate 2
voltage; typical values; see Fig.19.
2010 Sep 15
7
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
MLD277
MLD278
2
10
3
2
3
10
rs
10
handbook, halfpage
y
y
ϕ
is
(mS)
rs
(deg)
(μS)
ϕ
rs
2
10
10
10
y
rs
b
is
1
10
10
g
is
1
1
3
10
1
2
3
2
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID =10 mA; Tamb = 25 C.
ID = 10 mA; Tamb = 25 C.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MLD280
MLD279
2
2
10
fs
10
10
handbook, halfpage
y
os
(mS)
ϕ
(deg)
y
fs
y
fs
fs
b
g
(mS)
os
os
1
ϕ
10
10
1
2
10
10
1
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C.
ID = 10 mA; Tamb = 25 C.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2010 Sep 15
8
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
V
AGC
R1
10 kΩ
C1
4.7 nF
C3 12 pF
R
L
L1
C2
DUT
50 Ω
≈450 nH
C4
4.7 nF
R
R2
GEN
R
G1
50 Ω
50Ω
4.7 nF
V
I
V
MLD171
GG
V
DS
Fig.19 Cross-modulation test set-up.
2010 Sep 15
9
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
Table 1 Scattering parameters: VDS =5 V; VG2-S = 4 V; ID = 10 mA
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
40
100
0.989
0.985
0.976
0.958
0.942
0.918
0.899
0.876
0.852
0.823
0.800
0.750
0.719
0.682
0.642
0.602
0.547
0.596
0.682
0.771
0.793
3.4
8.3
2.420
2.414
2.368
2.301
2.251
2.170
2.080
2.001
1.924
1.829
1.747
1.621
1.535
1.424
1.349
1.283
1.130
1.018
0.979
0.804
0.541
175.7
169.1
158.8
148.5
138.8
129.5
120.7
112.1
103.2
94.7
0.000
0.001
0.003
0.004
0.005
0.005
0.005
0.005
0.005
0.005
0.005
0.005
0.008
0.010
0.013
0.018
0.014
0.040
0.077
0.120
0.149
79.9
78.3
0.993
0.992
0.987
0.980
0.974
0.966
0.958
0.951
0.944
0.937
0.933
0.928
0.930
0.924
0.928
0.928
0.887
0.837
0.778
0.629
0.479
1.6
3.9
200
16.4
24.1
32.0
39.3
46.0
52.6
58.8
64.9
70.9
82.4
92.7
102.5
109.8
116.5
124.9
128.7
132.6
142.5
157.5
80.3
7.8
300
73.7
11.4
15.2
18.7
22.2
25.5
28.9
32.1
35.2
41.7
48.4
54.9
62.9
73.1
81.0
95.8
109.6
119.5
119.9
400
70.7
500
67.2
600
67.8
700
68.6
800
72.9
900
78.7
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
86.5
88.3
70.7
120.5
139.8
137.8
156.8
175.1
172.6
163.9
164.0
178.8
158.3
54.6
39.4
22.5
1.1
15.1
49.1
79.4
116.2
153.5
Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA
opt
f
Fmin
(dB)
rn
50.40
(MHz)
(ratio)
(deg)
49.6
800
2.00
.686
2010 Sep 15
10
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
PACKAGE OUTLINE
Plastic surface-mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
H
v
M
A
y
E
e
3
4
Q
A
A
1
c
2
1
L
w
M
B
b
b
1
p
p
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
A
UNIT
b
b
c
D
E
e
e
H
E
L
Q
v
w
y
p
p
1
1
0.4
0.3
1.1
0.8
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.23
0.13
mm
0.1
1.15
0.2
0.2
0.1
1.3
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-05-21
06-03-16
SOT343R
2010 Sep 15
11
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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shall have no liability for the consequences of use of such
information.
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2010 Sep 15
12
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FET
BF904WR
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
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sheet expressly states that this specific NXP
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qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
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qualified products in automotive equipment or
applications.
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Semiconductors’ product specifications.
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national authorities.
2010 Sep 15
13
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and the package outline drawings which were updated to the latest version.
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Printed in The Netherlands
R77/02/pp14
Date of release: 2010 Sep 15
相关型号：
BF904WR-T
TRANSISTOR 2 CHANNEL, UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, MICROMINIATURE, PLASTIC PACKAGE-4, FET RF Small Signal
NXP
BF904WR-TAPE-13
TRANSISTOR UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, FET RF Small Signal
NXP
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