BF998,235 [NXP]
N-channel dual-gate MOSFET SOT-143 4-Pin;
| 型号： | BF998,235 |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate MOSFET SOT-143 4-Pin |
| 文件： | 总15页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
Product specification
1996 Aug 01
Supersedes data of April 1991
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
FEATURES
Short channel transistor with high forward transfer
admittance to input capacitance ratio
handbook, halfpage
d
4
3
2
Low noise gain controlled amplifier up to 1 GHz.
g
2
g
1
APPLICATIONS
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
1
s,b
Top view
Marking code: MOp.
MAM039
DESCRIPTION
Depletion type field effect transistor in a plastic
microminiature SOT143B or SOT143R package with
source and substrate interconnected. The transistors are
protected against excessive input voltage surges by
integrated back-to-back diodes between gates and
source.
Fig.1 Simplified outline (SOT143B)
and symbol; BF998.
d
handbook, page
CAUTION
3
4
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
g
2
g
1
PINNING
2
1
s,b
PIN
1
SYMBOL
DESCRIPTION
MAM040
Top view
s, b
d
source
drain
Marking code: MOp.
2
3
g2
g1
gate 2
gate 1
Fig.2 Simplified outline (SOT143R)
and symbol; BF998R.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
12
UNIT
VDS
ID
drain-source voltage
drain current
V
30
200
mA
mW
mS
pF
Ptot
yfs
Cig1-s
Crs
F
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
24
2.1
25
1
f = 1 MHz
f = 800 MHz
fF
dB
C
Tj
operating junction temperature
150
1996 Aug 01
2
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDS
PARAMETER
CONDITIONS
MIN.
MAX.
12
UNIT
drain-source voltage
drain current
V
ID
30
mA
mA
mA
mW
mW
mW
C
IG1
IG2
Ptot
gate 1 current
10
gate 2 current
10
total power dissipation; BF998
up to Tamb = 60 C; see Fig.3; note 1
up to Tamb = 50 C; see Fig.3; note 2
200
200
200
+150
150
Ptot
Tstg
Tj
total power dissipation; BF998R up to Tamb = 50 C; see Fig.4; note 1
storage temperature
65
operating junction temperature
C
Notes
1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm.
2. Device mounted on a printed-circuit board.
MLA198
MGA002
handbook, halfpage
handbook, halfpage
200
200
(2)
(1)
P
P
tot max
(mW)
tot max
(mW)
100
100
0
0
0
0
100
200
100
200
o
T
(°C)
T
( C)
amb
amb
(1) Ceramic substrate.
(2) Printed-circuit board.
Fig.3 Power derating curves; BF998.
Fig.4 Power derating curve; BF998R.
1996 Aug 01
3
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
460
UNIT
K/W
K/W
K/W
Rth j-a
thermal resistance from junction to ambient in free air; BF998 note 1
note 2
500
Rth j-a
thermal resistance from junction to ambient in free air; BF998R note 1
500
Notes
1. Device mounted on a ceramic substrate, 8 mm 10 mm 0.7 mm.
2. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
V(BR)G1-SS gate 1-source breakdown voltage
V(BR)G2-SS gate 2-source breakdown voltage
VG2-S = VDS = 0; IG1-SS = 10 mA
VG1-S = VDS = 0; IG2-SS = 10 mA
VG2-S = 4 V; VDS = 8 V; ID = 20 A
VG1-S = 0; VDS = 8 V; ID = 20 A
VG2-S = 4 V; VDS = 8 V; VG1-S = 0; note 1
VG2-S = VDS = 0; VG1-S = 5 V
6
6
2
20
20
2.0
1.5
18
50
50
V
V
V(P)G1-S
V(P)G2-S
IDSS
gate 1-source cut-off voltage
gate 2-source cut-off voltage
drain-source current
V
V
mA
nA
nA
IG1-SS
IG2-SS
gate 1 cut-off current
gate 2 cut-off current
VG1-S = VDS = 0; VG2-S = 5 V
Note
1. Measured under pulse condition.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VDS = 8 V; VG2-S = 4 V; ID = 10 mA.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
yfs
Cig1-s
Cig2-s
Cos
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
f = 1 kHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
21
24
mS
pF
pF
pF
fF
2.1
1.2
1.05
25
2.5
Crs
reverse transfer capacitance
noise figure
F
f = 200 MHz; GS = 2 mS; BS = BSopt
f = 800 MHz; GS = 3.3 mS; BS = BSopt
0.6
1.0
dB
dB
1996 Aug 01
4
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGE815
MGE813
24
24
handbook, halfpage
handbook, halfpage
I
I
D
D
3 V
V
=
G1-S
(mA)
(mA)
V
= 4 V
2 V
G2-S
0.4 V
20
20
16
12
8
1 V
0.3 V
0.2 V
16
12
8
0.1 V
0 V
−0.1 V
−0.2 V
−0.3 V
0 V
4
4
−0.4 V
−0.5 V
0
0
−1
0
1
0
2
4
6
8
10
V
(V)
G1
V
(V)
DS
VG2-S = 4 V; Tamb = 25 C.
VDS = 8 V; Tamb = 25 C.
Fig.5 Output characteristics; typical values.
Fig.6 Transfer characteristics; typical values.
MGE814
MGE811
24
30
handbook, halfpage
handbook, halfpage
I
D
4 V
3 V
2 V
|y
|
fs
(mS)
24
(mA)
max
typ
20
16
12
8
1 V
18
12
6
min
4
V
= 0 V
0.5 V
G2-S
4
0
0
−1600
−1200
−800
−400
0
(mV)
400
0
8
12
16
(mA)
20
V
G1
I
D
VDS = 8 V; VG2-S = 4 V; Tamb = 25 C.
VDS = 8 V; Tamb = 25 C.
Fig.7 Drain current as a function of gate 1
voltage; typical values.
Fig.8 Forward transfer admittance as a function of
drain current; typical values.
1996 Aug 01
5
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGE812
MGE810
30
1.5
handbook, halfpage
handbook, halfpage
V
= 4 V
G2-S
C
|y
|
os
(pF)
fs
(mS)
24
1.4
3 V
2 V
18
12
6
1.3
1.2
1.1
12 mA
1 V
0 V
10 mA
8 mA
0
−1
1.0
4
0
1
6
8
10
12
(V)
14
V
(V)
G1
V
DS
VDS = 8 V; Tamb = 25 C.
VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.
Fig.9 Forward transfer admittance as a function of
gate 1 voltage; typical values.
Fig.10 Output capacitance as a function of
drain-source voltage; typical values.
MGE809
MBH479
2.3
2.4
handbook, halfpage
handbook, halfpage
C
is
C
is
(pF)
(pF)
2.1
2.3
1.9
1.7
1.5
1.3
2.2
2.1
2.0
−2.4
−1.6
−0.8
0
0.8
(V)
6
4
2
0
−2
(V)
V
V
G2−S
G1-S
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.
VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C.
Fig.11 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values.
Fig.12 Gate 1 input capacitance as a function of
gate 2-source voltage; typical values.
1996 Aug 01
6
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGC466
MGC467
3
2
3
10
10
rs
10
y
y
ϕ
is
rs
(deg)
(mS)
(μS)
b
is
ϕ
rs
2
1
10
10
y
rs
1
10
10
10
1
g
is
2
10
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.
Fig.13 Input admittance as a function of the
frequency; typical values.
Fig.14 Reverse transfer admittance and phase as a
function of frequency; typical values.
MGC468
MGC469
2
2
10
fs
10
10
y
os
y
ϕ
(deg)
b
os
os
(mS)
fs
y
fs
(mS)
1
10
10
ϕ
fs
g
1
2
10
10
1
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.
VDS = 8 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 C.
Fig.15 Forward transfer admittance and phase as a
function of frequency; typical values.
Fig.16 Output admittance as a function of the
frequency; typical values.
1996 Aug 01
7
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
V
DD
47 μF
1 nF
1 nF
V
agc
1 nF
20 μH
1 nF
50 Ω
output
1.8 kΩ
47 kΩ
L2
1 nF
C1
5.5 pF
50 Ω
1 nF
360 Ω
input
15 pF
L1
10 pF
140 kΩ
1 nF
D1
BB405
D2
BB405
V
DD
330 kΩ
330 kΩ
100 kΩ
1 nF
1 nF
V
V
tun
tun
input
MGE802
output
VDD = 12 V; GS = 2 mS; GL = 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.17 Gain control test circuit at f = 200 MHz.
1996 Aug 01
8
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
V
V
DD
V
agc
DD
1 nF
1 nF
140 kΩ
1 nF
100 kΩ
L4
270 kΩ
L3
1 nF
1 nF
50 Ω
output
L1
L2
1 nF
50 Ω
input
C3
0.5 to
3.5 pF
C4
4 to 40 pF
1 nF
C1
2 to 18 pF
C2
0.5 to 3.5 pF
MGE801
1.8 kΩ
360 Ω
V
DD
VDD = 12 V; GS = 3.3 mS; GL = 1 mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.18 Gain control test circuit at f = 800 MHz.
1996 Aug 01
9
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
MGE807
MGE808
0
0
handbook, halfpage
handbook, halfpage
ΔG
ΔG
tr
tr
(dB)
(dB)
I
=
DSS
−10
−20
−30
−40
−50
−10
max
typ
min
−20
−30
I
=
DSS
−40
−50
max
typ
min
0
2
4
6
8
10
0
2
4
6
8
10
V
(V)
V
(V)
agc
agc
VDD = 12 V; f = 200 MHz; Tamb = 25 C.
VDD = 12 V; f = 800 MHz; Tamb = 25 C.
Fig.19 Automaticgaincontrolcharacteristics
measured in circuit of Fig.17.
Fig.20 Automatic gain control characteristics
measured in circuit of Fig.18.
1996 Aug 01
10
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
PACKAGE OUTLINES
Plastic surface-mounted package; 4 leads
SOT143B
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
4
3
Q
A
A
1
c
1
2
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-16
06-03-16
SOT143B
1996 Aug 01
11
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
Plastic surface-mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
3
4
Q
A
A
1
c
2
1
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.55
0.25
0.45
0.25
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-16
06-03-16
SOT143R
SC-61AA
1996 Aug 01
12
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
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provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
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DISCLAIMERS
Limited warranty and liability Information in this
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However, NXP Semiconductors does not give any
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the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
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Applications Applications that are described herein for
any of these products are for illustrative purposes only.
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Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
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responsibility to determine whether the NXP
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
1996 Aug 01
13
NXP Semiconductors
Product specification
Silicon N-channel dual-gate MOS-FETs
BF998; BF998R
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Export control This document as well as the item(s)
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regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
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specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
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NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
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Semiconductors’ product specifications.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
1996 Aug 01
14
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
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© NXP B.V. 2010
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/02/pp15
Date of release:1996 Aug 01
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