BLD6G21L-50,112 [NXP]
BLD6G21L-50;
NXP 
BLD6G21L-50; BLD6G21LS-50
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty
transistor
Rev. 2 — 17 August 2010
Product data sheet
1. Product profile
1.1 General description
The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution
using NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for
TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The
main and peak device, input splitter and output combiner are integrated in a single
package. This package consists of one gate and drain lead and two extra leads of which
one is used for biasing the peak amplifier and the other is not connected. It only requires
the proper input/output match and bias setting as with a normal class-AB transistor.
Table 1.
Typical performance
RF performance at Th = 25 °C.
Mode of operation
f
VDS PL(AV)
Gp
(dB) (%) (dBc)
14.5 43 −24
ηD
ACPR
PL(3dB)
(W)
(MHz)
(V)
(W)
TD-SCDMA [1][2]
2010 to 2025
28
8
53
[1] Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF.
[2] IDq = 170 mA (main); VGS(amp)peak = 0 V.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features and benefits
Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz:
Average output power = 8 W
Power gain = 14.5 dB
Efficiency = 43 %
Fully optimized integrated Doherty concept:
integrated asymmetrical power splitter at input
integrated power combiner
peak biasing down to 0 V
low junction temperature
high efficiency
100 % peak power tested for guaranteed output power capability
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
Integrated ESD protection
Good pair match (main and peak on the same chip)
Independent control of main and peak bias
Internally matched for ease of use
Excellent ruggedness
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
High efficiency RF power amplifiers with digital pre-distortion for TD-SCDMA multi
carrier applications in the 2010 MHz to 2025 MHz range.
2. Pinning information
Table 2.
Pin
BLD6G21L-50 (SOT1130A)
Pinning
Description
Simplified outline
Graphic symbol
1
2
3
4
5
drain
1
1
gate + bias main
source
[1]
2
5
n.c.
3
3
2
bias peak
001aak920
4
5
BLD6G21LS-50 (SOT1130B)
1
2
3
4
5
drain
1
3
1
2
gate + bias main
source
[1]
2
5
n.c.
3
bias peak
001aak920
4
5
[1] Connected to flange.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name Description
Version
BLD6G21L-50
-
-
flanged ceramic package; 2 mounting holes; 4 leads
earless flanged ceramic package; 4 leads
SOT1130A
SOT1130B
BLD6G21LS-50
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
2 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
4. Block diagram
main
amplifier
2
RF-input/bias main
90°
90°
1
RF-output/V
DS
peak
amplifier
5
bias peak
001aak932
Fig 1. Block diagram of BLD6G21L-50 and BLD6G21LS-50
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Valid for both main and peak device.
Symbol
Parameter
Conditions
Min Max
- 65
Unit
V
VDS
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
drain current
VGS(amp)main
−0.5 +13
−0.5 +13
V
VGS(amp)peak
V
ID
-
10.2
A
Tstg
Tj
storage temperature
junction temperature
−65
+150 °C
200 °C
-
6. Thermal characteristics
Table 5.
Thermal characteristics
Symbol Parameter
Conditions
Tcase = 80 °C; PL = 8 W
Typ
Unit
K/W
[1]
Rth(j-case) thermal resistance from junction to case
2.1
[1] When operated with a 6-carrier TD-SCDMA modulated signal with PAR = 10.8 dB at 0.01 % probability on
CCDF.
7. Characteristics
Table 6.
Characteristics
Valid for both main and peak device.
Symbol Parameter
Conditions
Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 0.62 mA
65
-
-
V
VGS(th)
VGSq
IDSS
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
VDS = 10 V; ID = 31 mA
VDS = 28 V; ID = 170 mA
VGS = 0 V; VDS = 28 V
1.4 1.8 2.4
1.55 2.05 2.55
V
V
-
-
1.4
-
μA
A
IDSX
drain cut-off current
VGS = VGS(th) + 3.75 V;
VDS = 10 V
4.95 5.5
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
3 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
Table 6.
Characteristics …continued
Valid for both main and peak device.
Symbol Parameter
Conditions
Min Typ Max Unit
IGSS
gfs
gate leakage current
VGS = 11 V; VDS = 0 V
VDS = 10 V; ID = 1.55 A
-
-
140
-
nA
S
forward transconductance
1.4 2.2
RDS(on) drain-source on-state resistance VGS = VGS(th) + 3.75 V;
ID = 1.085 A
-
0.52 0.736
Ω
8. Application information
Table 7.
Application information
Mode of operation: 6-carrier TD-SCDMA; PAR 10.8 dB at 0.01 % probability on CCDF;
f = 2017.5 MHz; RF performance at VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C;
unless otherwise specified; in a production circuit.
Symbol
PL(AV)
Gp
Parameter
Conditions
Min
-
Typ
8
Max
Unit
W
average output power
power gain
-
PL(AV) = 8 W
PL(AV) = 8 W
PL(AV) = 8 W
PL(AV) = 8 W
PL(AV) = 8 W
13
39
-
14.5
43
-
dB
%
ηD
drain efficiency
-
PARO
RLin
output peak-to-average ratio
input return loss
9.4
23
-
dB
dB
dBc
8
-
ACPR
adjacent channel power ratio
-
−24
−20
Table 8.
Application information
Mode of operation: Pulsed CW; δ = 10 %; tp = 100 μs; RF performance at VDS = 28 V; IDq = 170 mA;
VGS(amp)peak = 0 V; Tcase = 25 °C; unless otherwise specified; in a production circuit.
Symbol Parameter
Conditions Min
Typ
Max
Unit
PL(3dB)
output power at 3 dB gain compression
46
53
-
W
8.1 Ruggedness in Doherty operation
The BLD6G21L-50 and BLD6G21LS-50 are capable of withstanding a load mismatch
corresponding to VSWR = 10 : 1 through all phases under the following conditions:
V
DS = 28 V; IDq = 170 mA; PL = 8 W (TD-SCDMA); f = 2017.5 MHz.
8.2 Impedance information
Table 9.
Typical impedance
Measured Load Pull data; typical values unless otherwise specified.
f
ZS
ZL
MHz
1995
2010
2017.5
2025
2040
Ω
Ω
3.5 − 12.3j
3.6 − 12.7j
3.6 − 12.7j
3.7 − 12.7j
4.0 − 12.9j
6.7 − 6.1j
6.7 − 6.1j
6.7 − 5.7j
6.4 − 5.2j
5.7 − 4.8j
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
4 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 2. Definition of transistor impedance
8.3 Performance curves
Performance curves are measured in a BLD6G21L-50 application circuit.
8.3.1 CW pulsed
001aam428
001aam429
17
60
G
(dB)
η
D
(%)
p
(1)
(2)
(3)
(4)
(5)
(6)
15
40
(6)
(5)
(4)
(3)
(2)
(1)
13
11
20
0
30
35
40
45
50
30
35
40
45
50
P
L
(dBm)
P (dBm)
L
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
V
DS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
f = 2017.5 MHz; δ = 10 %; tp = 100 μs on 1 ms period.
f = 2017.5 MHz; δ = 10 %; tp = 100 μs on 1 ms period.
(1) VGS(amp)peak = 0 V
(2) VGS(amp)peak = 0.2 V
(3) VGS(amp)peak = 0.4 V
(4) VGS(amp)peak = 0.5 V
(5) VGS(amp)peak = 0.6 V
(6) VGS(amp)peak = 0.8 V
(1) VGS(amp)peak = 0 V
(2) VGS(amp)peak = 0.2 V
(3) VGS(amp)peak = 0.4 V
(4) VGS(amp)peak = 0.5 V
(5) VGS(amp)peak = 0.6 V
(6) VGS(amp)peak = 0.8 V
Fig 3. Power gain as a function of load power;
typical values
Fig 4. Drain efficiency as a function of load power;
typical values
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
5 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
001aam430
001aam431
16
60
G
(dB)
η
D
(%)
p
(3)
(2)
(1)
14
40
(1)
(2)
(3)
12
10
20
0
30
36
42
48
30
35
40
45
50
P
L
(dBm)
P (dBm)
L
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
GS(amp)peak = 0 V; δ = 10 %; tp = 100 μs on 1 ms period.
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
GS(amp)peak = 0 V; δ = 10 %; tp = 100 μs on 1 ms period.
V
V
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
Fig 5. Power gain as a function of load power;
typical values
Fig 6. Drain efficiency as a function of load power;
typical values
001aam432
50
RL
in
(dB)
40
30
20
10
0
(3)
(2)
(1)
30
36
42
48
P
L
(dBm)
VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; δ = 10 %; tp = 100 μs on 1 ms period.
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
Fig 7. Input return loss as a function of load power; typical values
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
6 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
8.3.2 TD-SCDMA
001aam433
001aam434
17
48
G
(dB)
η
D
(%)
p
(1)
(2)
(3)
(4)
(5)
(6)
15
32
(6)
(5)
(4)
(3)
(2)
(1)
13
11
16
0
22
30
38
46
22
30
38
46
P
L(AV)
(dBm)
P
L(AV)
(dBm)
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at
0.01 % probability on CCDF.
V
DS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at
0.01 % probability on CCDF.
(1)
V
GS(amp)peak = 0 V
(1) VGS(amp)peak = 0 V
(2) VGS(amp)peak = 0.2 V
(3) VGS(amp)peak = 0.4 V
(4) VGS(amp)peak = 0.5 V
(5) VGS(amp)peak = 0.6 V
(6) VGS(amp)peak = 0.8 V
(2) VGS(amp)peak = 0.2 V
(3) VGS(amp)peak = 0.4 V
(4) VGS(amp)peak = 0.5 V
(5) VGS(amp)peak = 0.6 V
(6) VGS(amp)peak = 0.8 V
Fig 8. Power gain as a function of average load
power; typical values
Fig 9. Drain efficiency as a function of average load
power; typical values
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
7 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
001aam435
16
43
η
D
(%)
η
D
G
(dB)
p
42
15.5
41
40
39
15
14.5
14
G
p
38
37
0.8
(V)
0
0.2
0.4
0.6
GS(amp)peak
V
VDS = 28 V; IDq = 170 mA; PL(AV) = 8 W; Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA;
PAR = 10.8 dB at 0.01 % probability on CCDF.
Fig 10. Power gain and drain efficiency as function of peak amplifier gate-source voltage;
typical values
001aam436
001aam437
16
48
G
(dB)
η
D
(%)
p
14
32
(1)
(2)
(3)
(1)
(2)
(3)
12
10
16
0
22
26
30
34
38
L(AV)
42
(dBm)
18
26
34
42
P
P
L(AV)
(dBm)
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
GS(amp)peak = 0 V; 6-carrier TD-SCDMA; PAR = 10.8 dB
at 0.01 % probability on CCDF.
VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C;
GS(amp)peak = 0 V; 6-carrier TD-SCDMA; PAR = 10.8 dB
at 0.01 % probability on CCDF.
V
V
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
(1) f = 2010 MHz
(2) f = 2018 MHz
(3) f = 2025 MHz
Fig 11. Power gain as a function of average load
power; typical values
Fig 12. Drain efficiency as a function of average load
power; typical values
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
8 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
9. Test information
V
GS(amp)main
V
DD
C2
R1
C6
C7
C11
C12
L1
V
GS(amp)peak
C3
C13
INPUT
BLD6G21-50-V2
C19
C20
C9
C1
C21
C10
C17
C18
C14
L2
C15
C16
C4
R2
C5
OUTPUT
C8
BLD6G21-50-V2
001aak944
The striplines are on a double copper-clad gold plated Rogers 4350B Printed-Circuit Board (PCB)
with εr = 3.5 and thickness = 0.76 mm.
See Table 10 for list of components.
Fig 13. Component layout
Table 10. List of components
See Figure 13 for component layout.
Component
C1, C3, C5, C18
C2, C4, C12, C15
C6
Description
Value
Dimensions
[1]
multilayer ceramic chip capacitor 9.1 pF
multilayer ceramic chip capacitor 100 nF
electrolytic capacitor
470 μF; 63 V
C7, C8
multilayer ceramic chip capacitor 10 μF
multilayer ceramic chip capacitor 1.5 pF
[1]
[1]
[1]
[1]
[1]
C9, C10
C11, C13, C14, C16 multilayer ceramic chip capacitor 8.2 pF
C17
multilayer ceramic chip capacitor 1.2 pF
multilayer ceramic chip capacitor 0.7 pF
multilayer ceramic chip capacitor 1.2 pF
C19, C20
C21
L1, L2
copper wire
-
diameter = 0.8 mm;
length = 8 mm
R1
R2
SMD resistor
SMD resistor
3.6 Ω
33 Ω
1206
1206
[1] American Technical Ceramics type 100B or capacitor of same quality.
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
9 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
10. Package outline
Flanged ceramic package; 2 mounting holes; 4 leads
SOT1130A
D
A
F
D
U
L
1
B
C
1
q
c
1
U
2
E
1
H
p
E
3
w
1
A
B
A
4
b
2
5
b
1
w
2
C
Q
0
5
10 mm
scale
Dimensions
(1)
(2)
Unit
A
b
b
c
D
D
1
E
E
1
F
H
L
p
Q
q
U
1
U
w
1
w
2
1
2
max 4.65 1.14 5.26 0.18 9.65 9.65 9.65 9.65 1.14 17.12 3.00 3.30 1.70
mm nom
20.45 9.91
15.24
0.6
0.25 0.51
0.01 0.02
min 3.76 0.89 5.00 0.10 9.40 9.40 9.40 9.40 0.89 16.10 2.69 2.92 1.45
20.19 9.65
0.805 0.39
max 0.183 0.045 0.207 0.007 0.38 0.38 0.38 0.38 0.045 0.674 0.118 0.130 0.067
inches nom
min 0.148 0.035 0.197 0.004 0.37 0.37 0.37 0.37 0.035 0.634 0.106 0.115 0.057
0.795 0.38
Note
1. millimeter dimensions are derived from the original inch dimensions.
2. dimension is measured 0.030 inch (0.76 mm) from the body.
sot1130a_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
09-10-12
10-02-02
SOT1130A
Fig 14. Package outline SOT1130A
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
10 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
Earless flanged ceramic package; 4 leads
SOT1130B
D
A
F
3
D
1
L
D
U
1
c
1
U
2
E
1
H
E
Z
Z
1
α
4
b
2
5
b
1
w
2
D
Q
0
5
10 mm
Q
scale
Dimensions
(1)
Unit
A
b
b
c
D
D
1
E
E
F
H
L
U
1
U
2
w
2
Z
Z
1
α
1
1
°
64
max 4.65 1.14 5.26 0.18 9.65 9.65 9.65 9.65 1.14 17.12 3.00 1.70 9.91 9.91
mm nom
min 3.76 0.89 5.00 0.10 9.40 9.40 9.40 9.40 0.89 16.10 2.69 1.45 9.65 9.65
max 0.183 0.045 0.207 0.007 0.38 0.38 0.38 0.38 0.045 0.674 0.118 0.069 0.39 0.39
inches nom
min 0.148 0.035 0.197 0.004 0.37 0.37 0.37 0.37 0.035 0.634 0.106 0.059 0.38 0.38
3.05 5.66
0.51
0.02
°
°
62
64
2.79 5.41
0.120 0.223
0.110 0.213
°
62
Note
1. millimeter dimensions are derived from the original inch dimensions.
2. dimension is measured 0.030 inch (0.76 mm) from the body.
sot1130b_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
09-10-12
09-12-14
SOT1130B
Fig 15. Package outline SOT1130B
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
11 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
11. Abbreviations
Table 11. Abbreviations
Acronym
Description
CCDF
CW
Complementary Cumulative Distribution Function
Continuous Wave
LDMOS
PAR
Laterally Diffused Metal-Oxide Semiconductor
Peak-to-Average power Ratio
Radio Frequency
RF
SMD
Surface Mounted Device
TD-SCDMA
VSWR
Time Division-Synchronous Code Division Multiple Access
Voltage Standing-Wave Ratio
12. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
20100817 Product data sheet
Change notice Supersedes
BLD6G21L-50_BLD6G21LS-50 v.2
-
BLD6G21L-50_
BLD6G21LS-50 v.1
Modifications:
• Figure 1 on page 3: Some corrections have been made.
• Table 5 on page 3: The typical value of Rth(j-case) has been changed.
• Table 6 on page 3: The values of IDSX have been changed.
• Table 7 on page 4: Several values have been changed or added.
• Table 8 on page 4: Table has been added.
• Section 8.3 on page 5: Figures have been updated.
BLD6G21L-50_BLD6G21LS-50 v.1
20091028
Objective data sheet
-
-
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
12 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
13.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
13.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
13 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
BLD6G21L-50_BLD6G21LS-50
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 August 2010
14 of 15
BLD6G21L-50; BLD6G21LS-50
NXP Semiconductors
TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor
15. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits. . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1
1.2
1.3
2
3
4
5
6
7
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 3
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
8.1
8.2
8.3
8.3.1
8.3.2
Application information. . . . . . . . . . . . . . . . . . . 4
Ruggedness in Doherty operation . . . . . . . . . . 4
Impedance information. . . . . . . . . . . . . . . . . . . 4
Performance curves . . . . . . . . . . . . . . . . . . . . . 5
CW pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TD-SCDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
10
11
12
13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13.1
13.2
13.3
13.4
14
15
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 August 2010
Document identifier: BLD6G21L-50_BLD6G21LS-50
相关型号：
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