BSH207,135 [NXP]

BSH207 - P-channel vertical D-MOS logic level FET TSOP 6-Pin;
BSH207,135
型号: BSH207,135
厂家: NXP    NXP
描述:

BSH207 - P-channel vertical D-MOS logic level FET TSOP 6-Pin

开关 光电二极管 晶体管
文件: 总7页 (文件大小:114K)
中文:  中文翻译
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Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
FEATURES  
SYMBOL  
QUICK REFERENCE DATA  
s
• Very low threshold voltage  
• Fast switching  
VDS = -12 V  
• Logic level compatible  
• Subminiature surface mount  
package  
ID = -1.52 A  
g
R
DS(ON) 0.15 (VGS = -2.5 V)  
VGS(TO) 0.4 V  
d
GENERAL DESCRIPTION  
PINNING  
SOT457  
P-channel, enhancement mode,  
logic level, field-effect power  
transistor. This device has low  
threshold voltage and extremely  
fast switching making it ideal for  
battery powered applications and  
high speed digital interfacing.  
PIN  
DESCRIPTION  
6
5
4
1,2,5,6 drain  
Top view  
3
4
gate  
source  
1
2
3
The BSH207 is supplied in the  
SOT457 subminiature surface  
mounting package.  
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
VGS  
ID  
Drain-source voltage  
-
-
-
-
-
-
-
-
-12  
-12  
± 8  
-1.52  
-0.96  
-6.09  
0.417  
0.17  
150  
V
V
V
A
A
Drain-gate voltage  
Gate-source voltage  
Drain current (DC)  
RGS = 20 kΩ  
Ta = 25 ˚C  
Ta = 100 ˚C  
Ta = 25 ˚C  
Ta = 25 ˚C  
Ta = 100 ˚C  
IDM  
Ptot  
Drain current (pulse peak value)  
Total power dissipation  
A
W
W
˚C  
Tstg, Tj  
Storage & operating temperature  
- 55  
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-a  
Thermal resistance junction to  
ambient  
FR4 board, minimum  
footprint  
300  
-
K/W  
August 1998  
1
Rev 1.000  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
ELECTRICAL CHARACTERISTICS  
Tj= 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
V(BR)DSS  
VGS(TO)  
RDS(ON)  
Drain-source breakdown  
voltage  
Gate threshold voltage  
VGS = 0 V; ID = -10 µA  
-12  
-
-
V
VDS = VGS; ID = -1 mA  
-0.4  
-0.1  
-
-
-
-
-0.6  
-
80  
117  
140  
175  
4.5  
-
-
V
V
mΩ  
mΩ  
mΩ  
mΩ  
S
Tj = 150˚C  
Drain-source on-state  
resistance  
VGS = -4.5 V; ID = -1 A  
VGS = -2.5 V; ID = -1 A  
120  
150  
180  
230  
-
V
GS = -1.8 V; ID = -0.5 A  
VGS = -2.5 V; ID = -1 A; Tj = 150˚C  
gfs  
Forward transconductance  
VDS = -9.6 V; ID = -1 A  
1.5  
IGSS  
IDSS  
Gate source leakage current VGS = ±8 V; VDS = 0 V  
-
-
-
±10 ±100  
nA  
nA  
µA  
Zero gate voltage drain  
current  
VDS = -9.6 V; VGS = 0 V;  
-50  
-13  
-100  
-100  
Tj = 150˚C  
Qg(tot)  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain (Miller) charge  
ID = -1 A; VDD = -10 V; VGS = -4.5 V  
-
-
-
8.8  
0.7  
2.0  
-
-
-
nC  
nC  
nC  
td on  
tr  
td off  
tf  
Turn-on delay time  
Turn-on rise time  
Turn-off delay time  
Turn-off fall time  
VDD = -10 V; ID = -1 A;  
VGS = -8 V; RG = 6 Ω  
Resistive load  
-
-
-
-
2
-
-
-
-
ns  
ns  
ns  
ns  
4.5  
45  
20  
Ciss  
Coss  
Crss  
Input capacitance  
Output capacitance  
Feedback capacitance  
VGS = 0 V; VDS = -9.6 V; f = 1 MHz  
-
-
-
500  
210  
62  
-
-
-
pF  
pF  
pF  
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS  
Tj = 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
IDR  
Continuous reverse drain  
current  
Ta = 25 ˚C  
-
-
-1.52  
A
IDRM  
VSD  
Pulsed reverse drain current  
Diode forward voltage  
-
-
-
-6.09  
-1.3  
A
V
IF = -0.62 A; VGS = 0 V  
-0.62  
trr  
Qrr  
Reverse recovery time  
Reverse recovery charge  
IF = -0.5 A; -dIF/dt = 100 A/µs;  
VGS = 0 V; VR = -9.6 V  
-
-
75  
69  
-
-
ns  
nC  
August 1998  
2
Rev 1.000  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
Normalised Power Dissipation, PD (%)  
120  
Peak Pulsed Drain Current, IDM (A)  
D = 0.5  
BSH207  
1000  
100  
10  
100  
80  
60  
40  
20  
0
0.2  
0.1  
0.05  
0.02  
P
D = tp/T  
D
tp  
1
single pulse  
0.1  
0.01  
T
0
25  
50  
75  
100  
125  
150  
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01  
Pulse width, tp (s)  
Ambient Temperature, Ta (C)  
Fig.1. Normalised power dissipation.  
PD% = 100 PD/PD 25 ˚C = f(Ta)  
Fig.4. Transient thermal impedance.  
Zth j-a = f(t); parameter D = tp/T  
Drain current, ID (A)  
-4.5 V  
BSH207  
Tj = 25 C  
Normalised Drain Current, ID (%)  
-5  
-4.5  
-4  
120  
100  
80  
60  
40  
20  
0
-1.8 V  
-2.5 V  
-3.5  
-3  
-1.3 V  
-1.2 V  
-1.1 V  
-2.5  
-2  
-1.5  
-1  
-1 V  
-0.9 V  
VGS = -0.8 V  
-0.5  
0
0
25  
50  
75  
100  
125  
150  
0
-0.5  
-1  
-1.5  
-2  
Ambient Temperature, Ta (C)  
Drain-Source Voltage, VDS (V)  
Fig.2. Normalised continuous drain current.  
ID% = 100 ID/ID 25 ˚C = f(Ta); conditions: VGS -10 V  
Fig.5. Typical output characteristics, Tj = 25 ˚C.  
ID = f(VDS); parameter VGS  
BSH207  
Tj = 25 C  
Drain-Source On Resistance, RDS(on) (Ohms)  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
BSH207  
Peak Pulsed Drain Current, IDM (A)  
RDS(on) = VDS/ ID  
-1V  
-1.2 V  
-1.1 V  
-0.8 V  
-0.9 V  
100  
10  
-1.3 V  
tp = 1ms  
10 ms  
1
100 ms  
-1.8 V  
-2.5 V  
0.1  
0.01  
d.c.  
VGS = -4.5V  
0.1  
1
10  
100  
0
-0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5  
Drain Current, ID (A)  
Drain-Source Voltage, VDS (V)  
Fig.3. Safe operating area. Ta = 25 ˚C  
ID & IDM = f(VDS); IDM single pulse; parameter tp  
Fig.6. Typical on-state resistance, Tj = 25 ˚C.  
RDS(ON) = f(ID); parameter VGS  
August 1998  
3
Rev 1.000  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
Drain Current, ID (A)  
-5  
BSH207  
Threshold Voltage, VGS(to), (V)  
typical  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
-4.5  
-4  
VDS > ID X RDS(on)  
Tj = 25 C  
150 C  
-3.5  
-3  
-2.5  
-2  
minimum  
-1.5  
-1  
-0.5  
0
0
25  
50  
75  
100  
125  
150  
0
-0.5  
-1  
-1.5  
-2  
Junction Temperature, Tj (C)  
Gate-Source Voltage, VGS (V)  
Fig.7. Typical transfer characteristics.  
ID = f(VGS)  
Fig.10. Gate threshold voltage.  
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS  
V
Transconductance, gfs (S)  
VDS > ID X RDS(on)  
BSH207  
BSH207  
Drain Current, ID (A)  
8
7
6
5
4
3
2
1
0
1E-01  
1E-02  
1E-03  
1E-04  
1E-05  
1E-06  
1E-07  
VDS = -5 V  
Tj = 25 C  
Tj = 25 C  
150 C  
0
-0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6  
Drain Current, ID (A)  
-1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1  
Gate-Source Voltage, VGS (V)  
0
Fig.8. Typical transconductance, Tj = 25 ˚C.  
gfs = f(ID)  
Fig.11. Sub-threshold drain current.  
ID = f(VGS); conditions: Tj = 25 ˚C  
BSH207  
Capacitances, Ciss, Coss, Crss (pF)  
Normalised Drain-Source On Resistance  
1000  
100  
10  
1.5  
1.4  
1.3  
1.2  
1.1  
1
RDS(ON) @ Tj  
Ciss  
RDS(ON) @ 25C  
-2.5 V  
VGS = -4.5 V  
Coss  
-1.8 V  
0.9  
0.8  
0.7  
0.6  
0.5  
Crss  
0
25  
50  
75  
100  
125  
150  
-0.1  
-1.0  
-10.0  
-100.0  
Junction Temperature, Tj (C)  
Drain-Source Voltage, VDS (V)  
Fig.9. Normalised drain-source on-state resistance.  
RDS(ON)/RDS(ON)25 ˚C = f(Tj)  
Fig.12. Typical capacitances, Ciss, Coss, Crss.  
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz  
August 1998  
4
Rev 1.000  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
Gate-source voltage, VGS (V)  
BSH207  
BSH207  
Source-Drain Diode Current, IF (A)  
-5  
-4  
-3  
-2  
-1  
0
5
4.5  
4
VDD = 10 V  
RD = 10 Ohms  
Tj = 25 C  
3.5  
3
2.5  
2
150 C  
Tj = 25 C  
1.5  
1
0.5  
0
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
0
1
2
3
4
5
6
7
8
9
Drain-Source Voltage, VSDS (V)  
Gate charge, (nC)  
Fig.13. Typical turn-on gate-charge characteristics.  
VGS = f(QG)  
Fig.14. Typical reverse diode current.  
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj  
August 1998  
5
Rev 1.000  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
MECHANICAL DATA  
Plastic surface mounted package; 6 leads  
SOT457  
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1  
index  
A
A
1
c
1
2
3
L
p
e
b
p
w
M B  
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1  
0.013  
0.40  
0.25  
1.1  
0.9  
0.26  
0.10  
3.1  
2.7  
1.7  
1.3  
3.0  
2.5  
0.6  
0.2  
0.33  
0.23  
mm  
0.95  
0.2  
0.2  
0.1  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
SC-74  
97-02-28  
SOT457  
Fig.15. SOT457 surface mounting package.  
Notes  
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static  
discharge during transport or handling.  
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.  
3. Epoxy meets UL94 V0 at 1/8".  
August 1998  
6
Rev 1.000  
Philips Semiconductors  
Product specification  
P-channel enhancement mode  
MOS transistor  
BSH207  
DEFINITIONS  
Data sheet status  
Objective specification  
This data sheet contains target or goal specifications for product development.  
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.  
Product specification  
This data sheet contains final product specifications.  
Limiting values  
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and  
operation of the device at these or at any other conditions above those given in the Characteristics sections of  
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
Philips Electronics N.V. 1998  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the  
copyright owner.  
The information presented in this document does not form part of any quotation or contract, it is believed to be  
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under patent or other  
industrial or intellectual property rights.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices or systems where malfunction of these  
products can be reasonably expected to result in personal injury. Philips customers using or selling these products  
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting  
from such improper use or sale.  
August 1998  
7
Rev 1.000  

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