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BSN304,126 [NXP]

BSN304 - N-channel vertical D-MOS logic level FET TO-92 3-Pin;
BSN304,126
型号： BSN304,126
厂家： NXP    NXP
描述：

BSN304 - N-channel vertical D-MOS logic level FET TO-92 3-Pin
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DISCRETE SEMICONDUCTORS  
DATA SHEET  
age  
BSN304  
N-channel enhancement mode  
vertical D-MOS transistor  
Product specification  
2001 Dec 11  
Supersedes data of 1997 Jun 17  
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
FEATURES  
PINNING - TO-92 variant  
PIN  
• Direct interface to C-MOS, TTL, etc.  
• High-speed switching  
DESCRIPTION  
1
2
3
gate  
• No secondary breakdown.  
drain  
source  
APPLICATIONS  
• Line current interruptor in telephone sets  
d
s
handbook, halfpage  
• Relay, high-speed and line transformer drivers.  
1
2
3
DESCRIPTION  
g
N-channel enhancement mode vertical D-MOS transistor  
in a TO-92 variant package.  
MAM146  
Fig.1 Simplified outline and symbol.  
QUICK REFERENCE DATA  
SYMBOL  
VDS  
PARAMETER  
drain-source voltage (DC)  
drain current (DC)  
CONDITIONS  
MIN.  
MAX.  
300  
UNIT  
−
−
−
−
−
V
ID  
300  
1
mA  
W
V
Ptot  
total power dissipation  
gate-source voltage  
T
amb ≤ 25 °C  
VGSO  
RDSon  
VGSoff  
open drain  
±20  
6
drain-source on-state resistance  
gate-source cut-off voltage  
ID = 250 mA; VGS = 10 V  
ID = 1 mA; VGS = VDS  
Ω
0.8  
2
V
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
PARAMETER  
drain-source voltage (DC)  
gate-source voltage (DC)  
drain current (DC)  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VGSO  
ID  
−
300  
±20  
300  
1.2  
V
open drain  
−
V
−
mA  
A
IDM  
Ptot  
Tstg  
Tj  
peak drain current  
−
total power dissipation  
storage temperature  
T
amb ≤ 25 °C; note 1  
−
1
W
°C  
°C  
−55  
−
+150  
150  
operating junction temperature  
Note  
1. Device mounted on an epoxy printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead  
minimum 10 mm x 10 mm.  
2001 Dec 11  
2
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
THERMAL CHARACTERISTICS  
SYMBOL  
Rth j-a  
Note  
PARAMETER  
thermal resistance from junction to ambient; note 1  
VALUE  
125  
UNIT  
K/W  
1. Device mounted on an epoxy printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead  
minimum 10 mm x 10 mm.  
STATIC CHARACTERISTICS  
Tj = 25 °C unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
ID = 10 µA; VGS = 0  
MIN. TYP. MAX. UNIT  
V(BR)DSS  
IGSS  
drain-source breakdown voltage  
gate-source leakage current  
gate-source threshold voltage  
drain-source on-state resistance  
300  
−
−
−
V
VGS = ±20 V; VDS = 0  
−
±100 nA  
VGSth  
ID = 1 mA; VDS = VGS  
0.8  
−
−
2
V
RDSon  
ID = 250 mA; VGS = 10 V  
ID = 20 mA; VGS = 2.4 V  
VDS = 240 V; VGS = 0  
3.7  
4.8  
−
6
Ω
−
10  
100  
−
Ω
IDSS  
Yfs  
drain-source leakage current  
transfer admittance  
−
nA  
mS  
pF  
pF  
pF  
ID = 250 mA; VDS = 25 V  
VDS = 25 V; VGS = 0; f = 1 MHz  
VDS = 25 V; VGS = 0; f = 1 MHz  
200  
−
690  
100  
21  
10  
Ciss  
Coss  
Crss  
input capacitance  
120  
30  
15  
output capacitance  
−
feedback capacitance  
VDS = 25 V; VGS = 0;  
f = 1 MHz  
−
Switching times (see Figs 2 and 3)  
ton  
turn-on time  
ID = 250 mA; VDD = 50 V;  
VGS = 0 to 10 V  
−
−
6
10  
60  
ns  
ns  
toff  
turn-off time  
ID = 250 mA; VDD = 50 V;  
46  
VGS = 10 to 0 V  
2001 Dec 11  
3
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
handbook, halfpage  
INPUT  
90 %  
V
= 50 V  
handbook, halfpage  
DD  
10 %  
90 %  
10 V  
0 V  
OUTPUT  
I
D
50 Ω  
10 %  
MSA631  
t
t
off  
on  
MBB692  
Fig.2 Switching times test circuit.  
Fig.3 Input and output waveforms.  
MRC238  
MLD765  
1.2  
250  
handbook, halfpage  
handbook, halfpage  
C
(pF)  
P
tot  
(W)  
200  
0.8  
150  
C
iss  
100  
50  
0.4  
C
oss  
C
rss  
0
0
0
0
50  
100  
150  
200  
(°C)  
10  
20  
30  
V
(V)  
DS  
T
amb  
VGS = 0; f = 1 MHz; Tj = 25 °C.  
Fig.5 Capacitance as a function of drain-source  
voltage; typical values.  
Fig.4 Power derating curve.  
2001 Dec 11  
4
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
MLD766  
MLD767  
1.2  
1.2  
handbook, halfpage  
handbook, halfpage  
5 V  
V
= 10 V  
GS  
4 V  
I
I
D
D
(A)  
(A)  
3.5 V  
3 V  
0.8  
0.8  
0.4  
0.4  
2.5 V  
2 V  
(V)  
0
0
0
0
4
8
12  
2
4
6
8
10  
(V)  
V
DS  
V
GS  
Tj = 25 °C.  
VDS = 10 V; Tj = 25 °C.  
Fig.6 Typical output characteristics.  
Fig.7 Typical transfer characteristics.  
MLD769  
MLD768  
30  
20  
handbook, halfpage  
handbook, halfpage  
V
= 2 V  
GS  
R
2.5 V  
DSon  
(Ω)  
3 V  
3.5 V  
R
DSon  
(Ω)  
15  
20  
10  
5
10  
4 V  
5 V  
10 V  
0
10  
0
0
−1  
1
10  
2
4
6
8
10  
(V)  
I
(A)  
V
D
GS  
Tj = 25 °C.  
VDS = 100 mV; Tj = 25 °C.  
Fig.8 Drain-source on-state resistance as a  
function of drain current; typical values.  
Fig.9 Drain-source on-state resistance as a function  
of gate-source voltage; typical values.  
2001 Dec 11  
5
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
MRC241  
3
10  
Z
th j-a  
(K/W)  
2
10  
δ =  
0.5  
0.2  
0.1  
10  
0.05  
0.02  
0.01  
t
p
P
δ =  
T
1
0
t
t
p
T
−1  
10  
−5  
−4  
−3  
−2  
−1  
2
3
10  
10  
10  
10  
10  
1
10  
10  
10  
t
(s)  
p
Fig.10 Transient thermal resistance from junction to ambient as a function of pulse time.  
MLD770  
10  
handbook, halfpage  
I
D
(A)  
1
(1)  
t
=
p
10 µs  
100 µs  
1 ms  
−1  
10  
10 ms  
t
p
100 ms  
1 s  
P
=
δ
T
−
2
3
10  
10  
DC  
t
t
p
T
−
2
3
10  
10  
10  
1
V
(V)  
DS  
δ = 0.01; Tamb = 25 °C.  
(1) RDSon limitation.  
Fig.11 SOAR curve.  
2001 Dec 11  
6
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
MLD772  
MLD771  
1.25  
2
handbook, halfpage  
handbook, halfpage  
k
k
(1)  
1
1.5  
(2)  
0.75  
0.5  
1
0.5  
0
0.25  
0
-50  
0
50  
100  
150  
−50  
0
50  
100  
150  
T (°C)  
T (°C)  
j
j
RDS(on) at Tj  
--------------------------------------------  
RDS(on) at 25 °C  
k =  
.
Typical RDSon  
;
VGS(th) at Tj  
k =  
.
-------------------------------------------  
(1) ID = 250 mA; VGS = 10 V.  
(2) ID = 20 mA; VGS = 2.4 V.  
VGS(th) at 25 °C  
Fig.13 Temperature coefficient of gate-source  
threshold voltage; typical values.  
Fig.12 Temperature coefficient of drain-source  
on-state resistance; typical values.  
2001 Dec 11  
7
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
PACKAGE OUTLINES  
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)  
SOT54 variant  
c
L
2
E
d
A
L
b
1
2
e
1
e
D
3
b
1
L
1
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
L
L
2
1
UNIT  
mm  
A
b
b
c
D
d
E
e
e
L
1
1
max  
max  
5.2  
5.0  
0.48  
0.40  
0.66  
0.56  
0.45  
0.40  
4.8  
4.4  
1.7  
1.4  
4.2  
3.6  
14.5  
12.7  
2.54  
1.27  
2.5  
2.5  
Notes  
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
98-03-26  
SOT54 variant  
TO-92 variant  
SC-43  
2001 Dec 11  
8
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS(1)  
STATUS(2)  
DEFINITIONS  
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change  
Notification (CPCN) procedure SNW-SQ-650A.  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2001 Dec 11  
9
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
NOTES  
2001 Dec 11  
10  
Philips Semiconductors  
Product specification  
N-channel enhancement mode  
vertical D-MOS transistor  
BSN304  
NOTES  
2001 Dec 11  
11  
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2001  
SCA73  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
613510/03/pp12  
Date of release: 2001 Dec 11  
Document order number: 9397 750 09063  

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