BSP106 [NXP]
N-channel enhancement mode vertical D-MOS transistor; N沟道增强型垂直的D- MOS晶体管
| 型号： | BSP106 |
| 厂家： | 
NXP |
| 描述： | N-channel enhancement mode vertical D-MOS transistor |
| 文件： | 总12页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BSP106
N-channel enhancement mode
vertical D-MOS transistor
April 1995
Product specification
File under Discrete Semiconductors, SC13b
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
FEATURES
QUICK REFERENCE DATA
• Very low RDS(on)
SYMBOL
VDS
PARAMETER
CONDITIONS MAX. UNIT
• Direct interface to C-MOS, TTL,
etc.
drain-source voltage
drain current
−
60
425
4
V
ID
DC value
mA
Ω
• High-speed switching
RDS(on)
drain-source on-resistance
ID = 200 mA
VGS = 10 V
• No secondary breakdown.
VGS(th)
gate-source threshold
voltage
ID = 1 mA
3
V
V
GS = VDS
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
miniature SOT223 envelope and
intended for use in relay, high-speed
and line transformer drivers.
PIN CONFIGURATION
PINNING - SOT223
d
s
4
handbook, halfpage
PIN
DESCRIPTION
1
2
3
4
gate
g
drain
source
drain
1
2
3
Top view
MAM054
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN. MAX. UNIT
VDS
VDG
±VGSO
ID
−
−
−
−
−
−
60
V
drain-gate voltage
gate-source voltage
drain current
60
V
20
V
DC value
425
850
1.5
mA
mA
W
IDM
drain current
peak value
Ptot
total power dissipation
up to Tamb = 25 °C
(note 1)
Tstg
Tj
storage temperature range
junction temperature
−55
150
150
°C
°C
−
THERMAL RESISTANCE
SYMBOL
PARAMETER
VALUE
83.3
UNIT
Rth j-a
from junction to ambient
(note 1)
K/W
Note
1. Device mounted on an epoxy printed-circuit board 40 x 40 x 1.5 mm;
mounting pad for the drain lead minimum 6 cm2.
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
ID = 10 µA
GS = 0
MIN. TYP. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
60
90
−
V
V
IDSS
drain-source leakage current
VDS = 48 V
VGS = 0
−
−
1
µA
µA
nA
V
VDS = 25 V
VGS = 0
−
−
0.5
10
3
±IGSS
VGS(th)
RDS(on)
Yfs
gate-source leakage current
gate-source threshold voltage
drain-source on-resistance
transfer admittance
VDS = 0
±VGS = 15 V
−
−
ID = 1 mA
VGS = VDS
0.8
−
−
ID = 200 mA
2.5
4
Ω
VGS = 10 V
ID = 200 mA
VDS = 10 V
100 200
−
mS
pF
Ciss
input capacitance
VDS = 10 V
VGS = 0
f = 1 MHz
−
−
−
25
22
6
40
Coss
output capacitance
VDS = 10 V
30
10
pF
pF
VGS = 0
f = 1 MHz
Crss
feedback capacitance
VDS = 10 V
VGS = 0
f = 1 MHz
Switching times (see Figs 2 and 3)
ton
turn-on time
ID = 200 mA
VDD = 50 V
VGS = 0 to 10 V
−
−
2
5
ns
ns
toff
turn-off time
ID = 200 mA
VDD = 50 V
VGS = 0 to 10
10
15
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
handbook, halfpage
INPUT
V
= 50 V
90 %
handbook, halfpage
DD
10 %
90 %
10 V
0 V
OUTPUT
I
D
50 Ω
10 %
MBB691
t
t
off
on
MBB692
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
MBB693
MDA718
2
1.6
handbook,
P
handbook, halfpage
tot
(W)
I
D
(A)
V
= 10 V
GS
1.6
1.2
1.2
0.8
0.8
0.4
5 V
4 V
3 V
0.4
0
0
0
0
50
100
150
200
(°C)
4
8
12
16
V
(V)
T
DS
amb
Fig.4 Power derating curve.
Fig.5 Typical output characteristics; Tj = 25 °C.
April 1995
5
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
MDA719
MDA720
20
1.2
handbook, halfpage
handbook, halfpage
V
= 3 V
GS
R
DSon
I
(Ω)
D
5 V
4 V
(A)
16
0.8
12
8
0.4
10 V
4
0
0
1
2
3
4
10
10
10
10
0
2
4
6
8
I
(mA)
V
(V)
D
GS
Fig.6 Typical transfer characteristic; VDS = 10 V;
Fig.7 Typical on-resistance as a function of drain
Tj = 25 °C.
current; Tj = 25 °C.
MDA721
MDA722
80
2.4
handbook, halfpage
handbook, halfpage
C
k
(pF)
2
60
40
1.6
1.2
C
iss
20
C
oss
0.8
0.4
C
rss
0
0
5
10
15
20
V
25
(V)
−50
0
50
100
150
T (°C)
j
DS
Fig.9 Temperature coefficient of drain-source
on-resistance;
RDS (on) at Tj
Fig.8 Typical capacitances as a function of
drain-source voltage; VGS = 0; f = 1 MHz;
Tj = 25 °C.
----------------------------------------------
;
k =
RDS (on) at 25 °C
typical RDS(on) at 200 mA/10 V.
April 1995
6
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
MDA723
1.2
handbook, halfpage
k
1.1
1
0.9
0.8
0.7
−50
0
50
100
150
T (°C)
j
Fig.10 Temperature coefficient of gate-source
threshold voltage;
VGS (th) at Tj
--------------------------------------------
k =
;
VGS (th) at 25 °C
VGS(th) at 1 mA.
April 1995
7
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
PACKAGE OUTLINES
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-247
SOT429
α
E
P
A
A
1
β
q
S
R
D
Y
(1)
L
1
Q
b
2
L
1
2
3
c
b
1
w
M
b
e
e
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
β
A
A
b
c
D
E
e
L
L
1
P
Q
q
R
S
w
Y
α
b
b
UNIT
mm
1
1
2
1.9
1.7
1.2
0.9
3.7
3.3
2.6
2.4
7.5
7.1
15.7
15.3
6°
4°
17°
13°
5.3
4.7
2.2
1.8
3.2
2.8
0.9
0.6
21
20
16
15
16
15
4.0
3.6
3.5
3.3
5.45
5.3
0.4
Note
1. Tinning of terminals are uncontrolled within zone L .
1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT429
TO-247
98-03-24
April 1995
8
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1995
9
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
NOTES
April 1995
10
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP106
NOTES
April 1995
11
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SCA54
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Date of release: April 1995
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