BT16841ADL [NXP]
20-bit bus interface latch 3-State; 20位总线接口锁存三态
| 型号： | BT16841ADL |
| 厂家： | 
NXP |
| 描述： | 20-bit bus interface latch 3-State |
| 文件： | 总10页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
Product specification
1998 Feb 27
Supersedes data of 1995 Sep 28
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
FEATURES
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
• High speed parallel latches
• Live insertion/extraction permitted
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
• Extra data width for wide address/data paths or buses carrying
parity
• Power-up 3-State
• 74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
• Power-up reset
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL UNIT
T
amb
t
t
Propagation delay
nDx to nQx
3.1
2.2
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
C
Input capacitance
Output capacitance
V = 0V or V
CC
4
7
pF
pF
IN
I
C
V
= 0V or V ; 3-State
O CC
OUT
CCZ
I
Outputs disabled; V = 5.5V
500
10
µA
mA
CC
Quiescent supply current
I
Outputs LOW; V = 5.5V
CC
CCL
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT16841A DL
74ABT16841A DGG
74ABTH16841A DL
74ABTH16841A DGG
BT16841A DL
BT16841A DGG
BH16841A DL
BH16841A DGG
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1D0 – 1D9
2D0 – 2D9
Data inputs
Data outputs
Output enable inputs (active-Low)
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Q0 – 1Q9
2Q0 – 2Q9
1, 28
56, 29
1OE, 2OE
1LE, 2LE
GND
Latch enable inputs (active rising edge)
Ground (0V)
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
V
CC
Positive supply voltage
2
1998 Feb 27
853-1797 19025
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
56 1LE
55 1D0
54 1D1
53 GND
52 1D2
51 1D3
1OE
1Q0
1Q1
GND
1Q2
1Q3
1
2
3
4
5
6
7
8
9
1
1OE
1LE
2OE
2LE
EN2
C1
56
28
29
EN4
C3
55
54
52
51
49
48
47
45
44
2
1D
2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
3
5
50
V
V
CC
CC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
1Q4
1Q5
6
8
1Q6 10
GND 11
9
10
12
13
1Q7
1Q8
12
13
1Q9 14
2Q0 15
43
42
41
40
38
37
36
34
33
31
30
14
15
16
17
19
20
21
23
24
26
27
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
3D
4
16
2Q1
2Q2 17
GND 18
2Q3
19
2Q4 20
2Q5 21
22
V
35
34
V
CC
CC
2D6
2Q6 23
2Q7 24
GND 25
2Q8 26
33 2D7
32 GND
31 2D8
SH00081
2Q9 27
2OE 28
30
2D9
FUNCTION TABLE
29 2LE
SA00076
INPUTS
OUTPUTS
OPERATING MODE
nOE nLE
nDx
nQ0 – nQ9
L
L
H
H
L
H
L
H
Transparent
Latched
LOGIC SYMBOL
L
L
↓
↓
l
h
L
H
55
54
52
51
49
48
47
45
44
43
H
L
X
L
X
X
Z
High impedance
Hold
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
NC
56
1
1LE
H
h
= High voltage level
=
1OE
High voltage level one set-up time prior to the High-to-Low LE
transition
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
L
l
=
=
Low voltage level
Low voltage level one set-up time prior to the High-to-Low LE
transition
High-to-Low LE transition
2
3
5
6
8
9
10
34
12
33
13
31
14
30
↓
=
42
41
40
38
37
36
NC= No change
X
Z
=
=
Don’t care
High impedance “off” state
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29
28
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
3
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00024
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +5.5
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
Min
4.5
0
Max
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
4
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= -40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
–0.9
2.9
Max
Min
Max
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = -18mA
–1.2
–1.2
V
V
V
V
V
V
IK
IK
= 4.5V; I = -3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
= 5.0V; I = -3mA; V = V or V
3.4
V
OH
High-level output voltage
Low-level output voltage
OH
I
IL
= 4.5V; I = -32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output voltage
= 5.5V; I = 1mA; V = GND or V
O I CC
Input leakage current
74ABT16841A
I
I
V
CC
= 5.5V; V = V or GND
±0.01
±1
±1.0
µA
I
CC
V
V
V
V
V
V
V
= 5.5V; V = V or GND
Control pins
±0.01
0.01
–2
±1
1
±1
1
µA
µA
µA
CC
CC
CC
CC
CC
CC
CC
I
CC
Input leakage current
= 5.5V; V = V
I
I
CC
I
5
Data pins
= 5.5V; V = 0
–3
–5
I
= 4.5V; V = 0.8V
35
35
I
6
Bus Hold current inputs
74ABTH16841A
= 4.5V; V = 2.0V
–75
–75
I
µA
I
HOLD
= 5.5V; V = 0 to 5.5V
±800
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V ≤ 4.5V
±5.0
±5.0
±100
±50
±100
±50
µA
µA
OFF
O
I
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
;
O
I
CC
CC
I
PU/PD
4
output current
= Don’t care
I
3-State output High current
3-State output Low current
Output High leakage current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
–70
0.5
10
10
–10
50
10
–10
50
µA
µA
OZH
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
OZL
CEX
I
= 5.5V; V = 5.5V; V = GND or V
µA
O
I
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–180
1
–50
–180
1
mA
mA
mA
mA
O
I
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
= 5.5V; Outputs Low, V = GND or V
CC
19
19
Quiescent supply current
CCL
CCZ
I
= 5.5V; Outputs 3-State; V = GND or V
0.5
1
1
I
CC
Additional supply current per
input pin
V
CC
V
CC
= 5.5V; one input at 3.4V, other inputs at
or GND
∆I
CC
0.2
1
1
mA
2
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
5. Unused pins at V or GND.
CC
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
MAX
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
MIN
TYP
MIN
MAX
t
t
Propagation delay
nDx to nQx
1.1
1.5
3.1
2.2
4.1
3.1
1.1
1.5
4.9
3.6
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
nLE to nQx
1.5
1.0
2.5
2.1
3.3
2.8
1.5
1.0
3.7
3.1
PLH
PHL
t
t
Output enable time
to High and Low level
4
5
1.2
1.2
2.4
2.2
3.2
2.9
1.2
1.2
4.0
3.6
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
1.8
1.5
3.0
2.5
4.0
3.2
1.8
1.5
4.9
3.7
PHZ
PLZ
5
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
Max
t (H)
t (L)
s
Setup time, High or Low
nDx to nLE
2.0
1.0
1.0
0.4
2.0
1.0
s
3
ns
t (H)
t (L)
h
Hold time, High or Low
nDx to nLE
2.0
2.0
–0.3
–0.7
2.0
2.0
h
3
1
ns
ns
t (H)
w
nLE pulse width High
2.9
1.9
2.9
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
3.0V or V
whichever
is less
CC
3.0V or V
whichever
is less
CC
nOE
V
V
V
nLE
M
M
M
V
V
M
M
0V
0V
t
t
PHZ
PZH
t
w
(H)
t
t
V
V
PHL
PLH
OH
V
V
OH
Y
V
M
V
V
M
nQx
M
nQx
0V
OL
SH00007
SA00078
Waveform 4. 3–State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 1. Propagation Delay, Latch Enable Input to
Output, and Enable Pulse Width
3.0V or V
CC
nOE
nQx
whichever
is less
3.0V or V
whichever
is less
V
V
M
CC
M
t
0V
V
V
M
M
nDx INPUT
t
PZL
PLZ
0V
3.0V or V
CC
t
t
PHL
PLH
V
M
V
X
3.0V or V
CC
0V
whichever
is less
V
OL
nQx OUTPUT
V
V
M
M
SH00008
0V
Waveform 5. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
SA00079
Waveform 2. Propagation Delay for Data to Outputs
3.0V or V
CC
whichever
is less
V
V
V
V
M
nDx
M
M
M
0V
t (H)
t (L)
s
t
(H)
t (L)
h
s
h
3.0V or V
CC
whichever
is less
nLE
V
V
M
M
0V
NOTE: The shaded areas indicate when the input is
permitted to change for predictable output performance.
SA00080
Waveform 3. Data Setup and Hold Times
6
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
TEST CIRCUIT AND WAVEFORM
t
W
V
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
10%
M
10%
R
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t
)
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Input Pulse Definition
t
closed
PLZ
PZL
t
closed
open
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT/H16
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00018
7
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
8
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
9
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03506
Document order number:
Philips
Semiconductors
相关型号：
BT16841ADL-T
IC ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, SOT-371-1, SSOP3-56, Bus Driver/Transceiver
NXP
BT16899DGG-T
IC ABT SERIES, 16-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, SOT-364-1, TSSOP2-56, Bus Driver/Transceiver
NXP
BT16899DL-T
IC ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, MO-118AB, SOT-371-1, SSOP-56, Bus Driver/Transceiver
NXP
BT168DT/R
Silicon Controlled Rectifier, 0.8 A, 400 V, SCR, TO-92, PLASTIC, SC-43, SOT-54 (TO-92) VARIANT, 3 PIN
NXP
©2020 ICPDF网 联系我们和版权申明