BUK107-50DLTRL [NXP]
IC BUF OR INV BASED PRPHL DRVR, Peripheral Driver;
| 型号： | BUK107-50DLTRL |
| 厂家： | 
NXP |
| 描述： | IC BUF OR INV BASED PRPHL DRVR, Peripheral Driver 晶体 晶体管 |
| 文件： | 总9页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
DESCRIPTION
QUICK REFERENCE DATA
Monolithic overload protected logic
level power MOSFET in a surface
mount plastic envelope, intended as
a general purpose switch for
automotive systems and other
applications.
SYMBOL
PARAMETER
MAX.
50
UNIT
V
VDS
ID
Continuous drain source voltage
Continuous drain current
Total power dissipation
0.7
A
PD
1.8
W
APPLICATIONS
Tj
Continuous junction temperature
Drain-source on-state resistance
150
200
˚C
General controller for driving
lamps
RDS(ON)
mΩ
small motors
solenoids
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Overload protected up to
85˚C ambient
DRAIN
Overload protection by current
limiting and overtemperature
sensing
O/V
CLAMP
Latched overload protection
reset by input
POWER
INPUT
MOSFET
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
RIG
LOGIC AND
derived from input
PROTECTION
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
4
D
S
TOPFET
input
drain
2
I
P
3
source
4
drain (tab)
2
3
1
March 1997
1
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
ID
II
IIRM
PD
Tstg
Tj
Continuous drain source voltage1
-
-
-
-
-
-
-
50
V
A
mA
mA
W
Continuous drain current2
Continuous input current
Non-repetitive peak input current
Total power dissipation
self limiting
clamping
tp ≤ 1 ms
3
10
1.8
150
150
Tamb = 25 ˚C
-
Storage temperature
Continuous junction temperature
-55
-
˚C
˚C
normal operation3
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
-
2
kV
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
EDSM
Non-repetitive clamping energy
Tb ≤ 25 ˚C; IDM < ID(lim)
;
-
100
mJ
inductive load
EDRM
Repetitive clamping energy
Tb ≤ 75 ˚C; IDM = 50 mA;
-
4
mJ
f = 250 Hz
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.
Overload protection operates by means of drain current limiting and activating the overtemperature protection.
SYMBOL PARAMETER
VDDP
CONDITIONS
MIN.
MAX.
UNIT
Protected drain source supply voltage VIS = 5 V
-
-
35
16
V
V
VIS = 4 V
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when there is an overload fault condition.
It remains latched off until reset by the input.
SYMBOL PARAMETER
Overload protection
CONDITIONS
MIN. TYP. MAX. UNIT
ID(lim)
Drain current limiting
VIS = 5 V
0.7
1.1
1.5
A
Overtemperature protection
only in drain current limiting
Tj(TO)
Threshold junction temperature VIS = 5 V
100
130
160
˚C
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not in an overload condition with drain current limiting.
March 1997
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
THERMAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Thermal resistance
Rth j-sp
Rth j-b
Rth j-a
Junction to solder point
Junction to board1
Junction to ambient
-
-
-
12
40
-
18
-
70
K/W
K/W
K/W
Mounted on any PCB
Mounted on PCB of fig. 19
STATIC CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(CL)DSS
V(CL)DSS
Drain-source clamping voltage VIS = 0 V; ID = 10 mA
Drain-source clamping voltage VIS = 0 V; IDM = 200 mA;
50
-
55
56
-
70
V
V
tp ≤ 300 µs; δ ≤ 0.01
IDSS
IDSS
IDSS
RDS(ON)
Off-state drain current
Off-state drain current
Off-state drain current
Drain-source on-state
resistance2
VDS = 45 V; VIS = 0 V
VDS = 50 V; VIS = 0 V
VDS = 40 V; VIS = 0 V; Tj = 100 ˚C
VIS = 5 V; IDM = 100 mA;
tp ≤ 300 µs; δ ≤ 0.01
-
-
-
-
0.5
1
10
150
2
20
100
200
µA
µA
µA
mΩ
INPUT CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER
VIS(TO) Input threshold voltage
IIS
CONDITIONS
MIN. TYP. MAX. UNIT
VDS = 5 V; ID = 1 mA
normal operation;
1.7
2.2
330
170
500
250
2.2
7.5
33
2.7
450
270
650
400
3.5
-
V
Input supply current
Input supply current
VIS = 5 V
VIS = 4 V
VIS = 5 V
VIS = 3.5 V
-
-
-
µA
µA
µA
µA
V
IISL
protection latched;
-
VISR
V(CL)IS
RIG
Protection latch reset voltage3
Input clamping voltage
Input series resistance
1
6
-
II = 1.5 mA
to gate of power MOSFET
V
kΩ
-
SWITCHING CHARACTERISTICS
Tamb = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
td on
tr
td off
tf
Turn-on delay time
Rise time
VIS = 0 V to VIS = 5 V
-
-
-
-
8
30
3
-
-
-
-
µs
µs
µs
µs
Turn-off delay time
Fall time
VIS = 5 V to VIS = 0 V
6
1 Temperature measured 1.3 mm from tab.
2 Continuous input voltage. The specified pulse width is for the drain current.
3 The input voltage below which the overload protection circuits will be reset.
March 1997
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
Normalised Power Derating
PD%
120
a
Normalised RDS(ON) = f(Tj)
110
100
90
80
70
60
50
40
30
20
10
0
1.5
1.0
0.5
0
0
20
40
60
80
Tmb /
100
120
140
-60 -40 -20
0
20 40 60 80 100 120 140
C
Tj /
C
Fig.2. Normalised limiting power dissipation.
PD% = 100 PD/PD(25 ˚C) = f(Tmb)
Fig.5. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 100 mA; VIS = 5 V
ID / A
BUK107-50DL
RDS(ON) / mOhm
BUK107-50DL
2.0
1.5
1.0
0.5
0
240
200
160
120
80
CURRENT LIMITING OCCURS
WITHIN THE SHADED REGION
MAX.
TYP.
TYP.
40
0
0
20
40
60
80
Tamb / C
100
120
140
0
2
4
6
8
10
VIS / V
Fig.3. Continuous drain current.
ID = f(Tamb); condition: VIS = 5 V
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VIS); conditions: ID = 100 mA, tp = 300 µs
ID / A
BUK107-50DL
7
ID / A
BUK107-50DL
1.5
1
1.5
1
VIS / V =
6
5
4
0.5
0.5
0
0
0
4
8
12
16
20
24
28
32
0
2
4
6
8
10
VDS / V
VIS / V
Fig.4. Typical on-state characteristics, Tj = 25 ˚C.
Fig.7. Typical transfer characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 300 µs
ID = f(VIS); conditions: VDS = 10 V, tp = 300 µs
March 1997
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
VIS(TO) / V
BUK107-50DL
Tj(TO) / C
200
BUK107-50DL
180
160
140
120
100
80
3
2
1
MAX.
TYP.
MIN.
TYP.
60
0
2
4
6
8
10
0
100
-50
50
150
VIS / V
Tj / C
Fig.8. Typical overtemperature protection threshold.
Tj(TO) = f(VIS); condition: VDS = 10 V
Fig.11. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
II / mA
BUK107-50DL
IIS & IISL / mA
BUK107-50DL
10
9
8
7
6
5
4
3
2
1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LATCHED
NORMAL
IISL
RESET
IIS
0
2
4
6
8
0
2
4
6
8
10
VIS / V
VIS / V
Fig.9. Typical DC input characteristics, Tj = 25 ˚C.
IIS & IISL = f(VIS); normal operation & protection latched
Fig.12. Typical input clamping characteristic.
II = f(VIS); normal operation, Tj = 25 ˚C.
IIS / uA
BUK107-50DL
ID / mA
BUK107-50DL
500
400
300
200
100
0
200
150
100
50
VIS / V =
5 V
4 V
TYP.
0
-50
50
Tj / C
150
50
52
54
56
58
60
0
100
VDS / V
Fig.10. Typical DC input current.
IIS = f(Tj); parameter VIS; normal operation
Fig.13. Overvoltage clamping characteristic, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs
March 1997
5
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
IDSS
BUK107-50DL
VDD
10 uA
1 uA
RL
VDS
measure
D
TOPFET
100 nA
I
P
D.U.T.
VIS
S
10 nA
-50
0
50
100
150
0V
Tj / C
Fig.14. Test circuit for resistive load switching times.
VIS = 5 V
Fig.16. Typical drain source leakage current
IDSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V.
VIS & VDS / V
BUK107-50DL
15
10
5
VDS
VIS
0
-20
0
20
40
60
80 100 120 140 160 180
time / us
Fig.15. Typical switching waveforms, resistive load .
RL = 50 Ω; adjust VDD to obtain ID = 250 mA; Tj = 25˚C
Zth j-amb / (K/W)
BUK107-50DL
1E+02
D =
0.5
0.2
1E+01
0.1
0.05
0.02
1E+00
t
T
p
t
p
P
D =
D
1E-01
t
T
0
1E-02
1E-07
1E-05
1E-03
1E-01
1E+01
1E+03
t / s
Fig.17. Transient thermal impedance, TOPFET mounted on PCB of fig 19.
Zth j-amb = f(t); parameter D = tp/T
March 1997
6
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
MOUNTING INSTRUCTIONS
PRINTED CIRCUIT BOARD
Dimensions in mm.
Dimensions in mm.
3.8
36
min
1.5
min
18
60
4.5
4.6
9
2.3
6.3
1.5
min
10
(3x)
1.5
min
7
15
4.6
50
Fig.19. PCB for thermal resistance and power rating.
PCB: FR4 epoxy glass (1.6 mm thick),
copper laminate (35 µm thick).
Fig.18. Soldering pattern for surface mounting.
March 1997
7
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
0.95
0.85
0.1 S
S
seating plane
6.7
6.3
0.32
0.24
B
3.1
2.9
M
0.2
A
4
A
0.10
0.01
3.7
3.3
7.3
6.7
o
o
16
16
max
1
2
3
o
10
max
1.80
max
0.80
0.60
M
2.3
0.1
B
(4x)
MSA035 - 1
4.6
Fig.20. SOT223 surface mounting package1.
1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8".
March 1997
8
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK107-50DL
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
March 1997
9
Rev 1.200
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