BUK754R0-55B,127 [NXP]
N-channel TrenchMOS standard level FET TO-220 3-Pin;
| 型号： | BUK754R0-55B,127 |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS standard level FET TO-220 3-Pin 局域网 开关 脉冲 晶体管 |
| 文件： | 总14页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUK754R0-55B; BUK764R0-55B
N-channel TrenchMOS standard level FET
Rev. 04 — 4 October 2007
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package
using NXP High-Performance Automotive (HPA) TrenchMOS technology.
1.2 Features
I Very low on-state resistance
I Q101 compliant
I 175 °C rated
I Standard level compatible
1.3 Applications
I Automotive systems
I General purpose power switching
I 12 V and 24 V loads
I Motors, lamps and solenoids
1.4 Quick reference data
I EDS(AL)S ≤ 1.2 J
I ID ≤ 75 A
I RDSon = 3.4 mΩ (typ)
I Ptot ≤ 300 W
2. Pinning information
Table 1.
Pinning
Pin
1
Description
gate (G)
Simplified outline
Symbol
D
S
mb
mb
2
drain (D)
3
source (S)
G
mb
mounting base; connected to
drain (D)
mbb076
2
1
3
1 2 3
03ab54
SOT404 (D2PAK)
SOT78A (TO-220AB)
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
BUK754R0-55B
BUK764R0-55B
SC-46
plastic single-ended package; heatsink mounted; 1 mounting hole; SOT78A
3-lead TO-220AB
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads
(one lead cropped)
SOT404
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min Max Unit
VDS
VDGR
VGS
ID
drain-source voltage
-
-
-
-
-
-
-
-
55
V
V
V
A
A
A
A
W
drain-gate voltage (DC)
gate-source voltage
drain current
RGS = 20 kΩ
55
±20
193
75
[1][3]
[2]
Tmb = 25 °C; VGS = 10 V;
see Figure 2 and 3
[2]
Tmb = 100 °C; VGS = 10 V; see Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
Tmb = 25 °C; see Figure 1
75
IDM
Ptot
Tstg
Tj
peak drain current
774
300
total power dissipation
storage temperature
junction temperature
−55 +175 °C
−55 +175 °C
Source-drain diode
[1][2]
[2]
IDR
reverse drain current
Tmb = 25 °C
-
-
-
193
75
A
A
A
IDRM
peak reverse drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
774
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 75 A;
-
-
1.2
-
J
J
energy
VDS ≤ 55 V; RGS = 50 Ω; VGS = 10 V; starting
at Tj = 25 °C
[4]
EDS(AL)R repetitive drain-source avalanche
energy
[1] Current is limited by chip power dissipation rating.
[2] Continuous current is limited by package.
[3] Refer to document 9397 750 12572 for further information.
[4] Conditions:
a) Maximum value not quoted. Repetitive rating defined in Figure 16.
b) Single-pulse avalanche rating limited by Tj(max) of 175 °C.
c) Repetitive avalanche rating limited by an average junction temperature of 170 °C.
d) Refer to application note AN10273 for further information.
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
2 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
03na19
001aaf871
120
200
I
D
P
(%)
der
(A)
150
80
100
50
0
(1)
40
0
0
50
100
150
200
25
75
125
175
T
(°C)
T
(°C)
mb
mb
V
GS ≥ 10 V
Ptot
Pder
=
× 100 %
-----------------------
Ptot(25°C)
(1) Capped at 75 A due to package.
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Continuous drain current as a function of
mounting base temperature
03ng55
103
tp = 10 µs
ID
Limit RDSon = VDS / ID
(A)
102
100 µs
(1)
1 ms
DC
10 ms
10
100 ms
1
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse
(1) Capped at 75 A due to package.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
3 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 4.
Symbol Parameter
Rth(j-mb) thermal resistance from junction to
Thermal characteristics
Conditions
Min
Typ
Max Unit
-
-
0.5
K/W
mounting base
Rth(j-a)
thermal resistance from junction to ambient
SOT78A (TO-220AB)
vertical in free air
-
-
60
50
-
-
K/W
K/W
SOT404 (D2PAK)
mounted on a printed-circuit board;
minimum footprint
03ng56
1
Zth(j-mb)
(K/W)
δ
= 0.5
0.2
0.1
10-1
10-2
10-3
0.05
tp
T
P
δ =
0.02
single shot
t
tp
T
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
4 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
6. Characteristics
Table 5.
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
55
50
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain leakage current
ID = 1 mA; VDS = VGS; see Figure 9
Tj = 25 °C
2
1
-
3
-
4
V
V
V
Tj = 175 °C
-
Tj = −55 °C
-
4.4
IDSS
VDS = 55 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.02
1
µA
µA
nA
Tj = 175 °C
-
500
100
IGSS
gate leakage current
VGS = ±20 V; VDS = 0 V
2
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 25 A;
see Figure 6 and 8
Tj = 25 °C
-
-
3.4
-
4.0
8
mΩ
mΩ
Tj = 175 °C
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 25 A; VDD = 44 V; VGS = 10 V;
see Figure 14
-
-
-
-
-
-
-
-
-
-
-
86
18
25
-
-
-
nC
nC
nC
pF
pF
pF
ns
VGS = 0 V; VDS = 25 V; f = 1 MHz;
see Figure 12
5082 6776
1054 1265
450
23
617
VDS = 30 V; RL = 1.2 Ω;
-
-
-
-
-
V
GS = 10 V; RG = 10 Ω
51
ns
td(off)
tf
turn-off delay time
fall time
71
ns
41
ns
LD
internal drain inductance
from drain lead 6 mm from package to
center of die
4.5
nH
from contact screw on mounting base to
center of die SOT78A
-
-
-
3.5
2.5
7.5
-
-
-
nH
nH
nH
from upper edge of drain mounting base
to center of die SOT404
LS
internal source inductance
from source lead to source bonding pad
Source-drain diode
VSD
trr
source-drain voltage
IS = 40 A; VGS = 0 V; see Figure 15
-
-
-
0.85 1.2
V
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs;
95
-
-
ns
nC
V
GS = −10 V; VR = 30 V
Qr
251
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
5 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
03nh22
03nh21
300
7
6
5
4
3
7
ID
20
10
6.5
RDSon
(A)
250
6
(mΩ)
5.5
200
150
100
50
5
4.5
VGS (V) = 4
0
0
2
4
6
8
10
5
10
15
20
V
GS (V)
V
DS (V)
Tj = 25 °C
Tj = 25 °C; ID = 25 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values
03ne89
03nh23
2
7
RDSon
a
(mΩ)
VGS (V) = 6
1.5
6
6.5
7
1
0.5
0
5
8
10
4
3
-60
0
60
120
180
0
50
100
150
200
250
300
ID (A)
T ( C)
°
j
Tj = 25 °C
RDSon
a =
-----------------------------
RDSon(25°C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
6 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
03aa32
03aa35
−1
−2
−3
−4
−5
−6
5
10
V
I
GS(th)
(V)
D
(A)
min
typ
max
4
3
2
1
0
10
10
10
10
10
max
typ
min
−60
0
60
120
180
0
2
4
6
T (°C)
V
(V)
j
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
03nh19
03nh24
120
gfs
7000
C
(pF)
6000
Ciss
(S)
100
5000
4000
3000
80
60
40
20
0
Coss
2000
1000
0
Crss
0
20
40
60
10-1
1
10
102
ID (A)
VDS (V)
Tj = 25 °C; VDS = 25 V
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
7 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
03nh20
03nh18
100
ID
10
VGS
(V)
(A)
80
60
40
8
6
4
2
0
VDS (V) = 14
VDS (V) = 44
Tj = 175 °C
20
0
Tj = 25 °C
0
2
4
6
0
20
40
60
80
100
QG (nC)
VGS (V)
VDS = 25 V
Tj = 25 °C; ID = 25 A
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 14. Gate-source voltage as a function of gate
charge; typical values
03nh17
003aab677
100
102
ID
IAL
(1)
(A)
80
(A)
10
60
40
(2)
(3)
1
Tj = 175 °C
20
Tj = 25 °C
0
0.0
10-1
0.2
0.4
0.6
0.8
1.0
10-3
10-2
10-1
1
10
tAL (ms)
VSD (V)
VGS = 0 V
See Table note 4 of Table 3 Limiting values.
(1) Single-pulse; Tj = 25 °C.
(2) Single-pulse; Tj = 150 °C.
(3) Repetitive.
Fig 15. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
Fig 16. Single-pulse and repetitive avalanche rating;
avalanche current as a function of avalanche
time
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
8 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
7. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
SOT78A
E
p
A
A
1
q
mounting
base
D
1
D
(1)
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
b
L
max.
(1)
2
e
A
b
D
E
L
D
L
1
A
1
c
UNIT
p
q
Q
1
1
4.5
4.1
1.39
1.27
0.9
0.6
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
15.0
13.5
3.30
2.79
3.8
3.6
3.0
2.7
2.6
2.2
mm
3.0
2.54
Note
1. Terminals in this zone are not tinned.
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
03-01-22
05-03-14
SOT78A
3-lead TO-220AB
SC-46
Fig 17. Package outline SOT78A (TO-220AB)
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
9 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 18. Package outline SOT404 (D2PAK)
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
10 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
8. Soldering
10.85
10.60
10.50
1.50
7.50
7.40
1.70
2.15
1.50
2.25
8.275
8.35
8.15
4.60
0.30
4.85
5.40
7.95
8.075
3.00
0.20
1.20
1.30
1.55
solder lands
solder resist
occupied area
solder paste
5.08
msd057
Fig 19. Reflow soldering footprint for SOT404
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
11 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
9. Revision history
Table 6.
Revision history
Document ID
Release date
20071004
Data sheet status
Change notice
Supersedes
BUK75_764R0-55B_4
Modifications:
Product data sheet
-
BUK75_764R0-55B_3
• Figure 7 updated.
20070124
BUK75_764R0-55B_3
Modifications:
Product data sheet
-
BUK75_764R0_55B-02
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Crss (typ) and (max) value in Section 6 “Characteristics” changed from 289 (typ) and 396
(max) to 450 (typ) and 617 (max).
BUK75_764R0_55B-02 20020930
BUK75_764R0_55B-01 20020328
Product data sheet
Product data sheet
-
-
BUK75_764R0_55B-01
-
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
12 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
10. Legal information
10.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
result in personal injury, death or severe property or environmental damage.
10.2 Definitions
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
10.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
10.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
TrenchMOS — is a trademark of NXP B.V.
11. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
BUK75_764R0-55B_4
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 04 — 4 October 2007
13 of 14
BUK754R0-55B; BUK764R0-55B
NXP Semiconductors
N-channel TrenchMOS standard level FET
12. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.1
10.2
10.3
10.4
11
12
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 October 2007
Document identifier: BUK75_764R0-55B_4
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