BUK9606-75B,118_技术文档

BUK9606-75B

AK

D2P

N-channel TrenchMOS logic level FET

Rev. 4 — 20 July 2011

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product has been designed and qualified to

the appropriate AEC standard for use in automotive critical applications.

1.2 Features and benefits

 AEC Q101 compliant

 Suitable for logic level gate drive

sources

 Low conduction losses due to low

on-state resistance

 Suitable for thermally demanding

environments due to 175 °C rating

1.3 Applications

 12 V, 24 V and 42 V loads

 Automotive systems

 General purpose power switching

 Motors, lamps and solenoids

1.4 Quick reference data

Table 1.

Symbol

V_DS

Quick reference data

Parameter

Conditions

Min Typ Max Unit

drain-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

-

75

V

A

[1]

I_D

V_GS= 5 V; T_mb= 25 °C;

see Figure 1; see Figure 3

P_tot

total power dissipation T_mb= 25 °C; see Figure 2

-

300

W

Static characteristics

R_DSondrain-source on-state

resistance

V_GS= 10 V; I_D= 25 A;

T_j= 25 °C

-

4.7

5.2

5.5

6.1

mΩ

V_GS= 5 V; I_D= 25 A;

T_j= 25 °C;

see Figure 11; see Figure 12

BUK9606-75B

NXP Semiconductors

N-channel TrenchMOS logic level FET

Table 1.

Symbol

Avalanche ruggedness

Quick reference data …continued

Parameter Conditions

Min Typ Max Unit

E_DS(AL)S

non-repetitive

drain-source

avalanche energy

I_D= 75 A; V_sup≤ 75 V;

R_GS= 50 Ω; V_GS= 5 V;

T_j(init)= 25 °C; unclamped

-

852 mJ

Dynamic characteristics

Q_GDgate-drain charge

V_GS= 5 V; I_D= 25 A;

-

37

-

nC

V

_DS= 60 V; T_j= 25 °C;

see Figure 13

[1] Continuous current is limited by package.

2. Pinning information

Table 2.

Pinning information

Symbol Description

1

Simplified outline

Graphic symbol

G

D

S

D

gate

drain^[1]

mb

D

S

2

3

source

G

mb

mounting base;

connected to drain

mbb076

2

1

3

SOT404 (D2PAK)

[1] It is not possible to make a connection to pin 2.

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

BUK9606-75B

D2PAK

plastic single-ended surface-mounted package (D2PAK);

3 leads (one lead cropped)

SOT404

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4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

75

Unit

V

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

R_GS= 20 kΩ

-

V_DGR

V_GS

-

75

V

-15

15

V

[1]

[2]

[1]

I_D

T_mb= 100 °C; V_GS= 5 V; see Figure 1

-

75

A

T_mb= 25 °C; V_GS= 5 V; see Figure 1;

see Figure 3

153

75

A

I_DM

peak drain current

T_mb= 25 °C; pulsed; t_p≤ 10 µs;

612

A

see Figure 3

P_tot

T_stg

T_j

total power dissipation

storage temperature

junction temperature

T_mb= 25 °C; see Figure 2

-

300

175

W

-55

°C

Source-drain diode

[2]

[1]

I_S

source current

T_mb= 25 °C

-

153

75

A

I_SM

peak source current

pulsed; t_p≤ 10 µs; T_mb= 25 °C

612

Avalanche ruggedness

E_DS(AL)Snon-repetitive drain-source

avalanche energy

I_D= 75 A; V_sup≤ 75 V; R_GS= 50 Ω;

V_GS= 5 V; T_j(init)= 25 °C; unclamped

-

852

mJ

[1] Continuous current is limited by package.

[2] Current is limited by power dissipation chip rating.

03na19

03nh76

120

200

I

D

P

der

(A)

(%)

150

80

100

50

0

40

Capped at 75 A due to package

0

50

100

150

200

25

50

75

100

125

150

175

T

200

(°C)

T

(°C)

mb

Fig 1. Continuous drain current as a function of

mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

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N-channel TrenchMOS logic level FET

03ng87

10³

I_D

(A)

Limit R_DSon= V_DS/ I_D

t =10

p

s

μ

10²

10

1

100

s

μ

DC

1 ms

10 ms

100 ms

10^-1

1

10

10²

10³

V _DS(V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

5. Thermal characteristics

Table 5.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from

junction to mounting base

see Figure 4

-

0.5

K/W

R_th(j-a)

thermal resistance from

junction to ambient

mounted on a printed circuit

board; minimum footprint

-

50

-

K/W

03ng88

1

Z

th(j-mb)

(K/W)

δ = 0.5

−1

0.2

10

0.1

0.05

0.02

t

p

−2

−3

P

δ =

T

single shot

t

p

T

−6

−5

−4

−3

−2

−1

10

1

t

p

(s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

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Product data sheet

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N-channel TrenchMOS logic level FET

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSSdrain-source

breakdown voltage

I_D= 0.25 mA; V_GS= 0 V; T_j= 25 °C

I_D= 0.25 mA; V_GS= 0 V; T_j= -55 °C

75

70

1.1

-

V

-

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

1.5

2

voltage

see Figure 10

I_D= 1 mA; V_DS= V_GS; T_j= 175 °C;

see Figure 10

0.5

-

V

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 10

2.3

I_DSS

drain leakage current

gate leakage current

V_DS= 75 V; V_GS= 0 V; T_j= 175 °C

V_DS= 75 V; V_GS= 0 V; T_j= 25 °C

V_GS= 15 V; V_DS= 0 V; T_j= 25 °C

V_GS= -15 V; V_DS= 0 V; T_j= 25 °C

V_GS= 4.5 V; I_D= 25 A; T_j= 25 °C

-

500

1

µA

nA

0.02

I_GSS

2

-

100

6.6

12.8

nA

R_DSon

drain-source on-state

resistance

mΩ

V_GS= 5 V; I_D= 25 A; T_j= 175 °C;

see Figure 11; see Figure 12

-

V_GS= 10 V; I_D= 25 A; T_j= 25 °C

-

4.7

5.2

5.5

6.1

mΩ

V_GS= 5 V; I_D= 25 A; T_j= 25 °C;

see Figure 11; see Figure 12

Dynamic characteristics

Q_G(tot)

Q_GS

Q_GD

C_iss

total gate charge

I_D= 25 A; V_DS= 60 V; V_GS= 5 V;

T_j= 25 °C; see Figure 13

-

95

17

37

-

nC

gate-source charge

gate-drain charge

input capacitance

output capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz;

T_j= 25 °C; see Figure 14

8770 11693 pF

C_oss

C_rss

842

336

1010 pF

reverse transfer

capacitance

460

pF

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 30 V; R_L= 1.2 Ω; V_GS= 5 V;

R_G(ext)= 10 Ω; T_j= 25 °C

-

68

-

ns

nH

144

273

116

4.5

turn-off delay time

fall time

L_D

internal drain

inductance

from drain lead 6 mm from package to

centre of die; T_j= 25 °C

from upper edge of drain mounting base

to centre of die; T_j= 25 °C

-

2.5

7.5

-

nH

L_S

internal source

inductance

from source lead to source bond pad;

T_j= 25 °C

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N-channel TrenchMOS logic level FET

Table 6.

Symbol

Characteristics …continued

Parameter

Conditions

Min

Typ

Max

Unit

Source-drain diode

V_SD

source-drain voltage

I_S= 40 A; V_GS= 0 V; T_j= 25 °C;

see Figure 15

-

0.85

1.2

V

t_rr

reverse recovery time I_S= 20 A; dI_S/dt = -100 A/µs;

-

68

-

ns

V_GS= -10 V; V_DS= 25 V; T_j= 25 °C

Q_r

recovered charge

176

nC

03ng84

03ng83

350

8

I

D

5

R

(mΩ)

(A)

4

DSon

300

10

7

250

200

150

100

50

6

5

4

V

= 3 V

GS

2.4

8

0

2

4

6

10

0

5

10

15

V

(V)

V

GS

(V)

DS

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Drain-source on-state resistance as a function

of gate-source voltages; typical values

03ng53

03ng81

−1

10

200

I

D

g

(S)

fs

(A)

−2

−3

−4

−5

−6

10

150

min

typ

max

10

100

50

0

20

40

60

0

1

2

3

V

(V)

I (A)

D

GS

Fig 7. Sub-threshold drain current as a function of

gate-source voltage

Fig 8. Forward transconductance as a function of

drain current; typical values

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N-channel TrenchMOS logic level FET

03ng52

03ng82

2.5

100

I

V

D

GS(th)

(V)

(A)

2.0

1.5

1.0

0.5

0

80

max

60

40

20

typ

min

T = 175 °C

j

T = 25 °C

j

0

0.0

0.5

1.0

1.5

2.0

2.5

V

3.0

(V)

−60

0

60

120

180

T (°C)

j

GS

Fig 9. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

Fig 10. Gate-source threshold voltage as a function of

junction temperature

03nb25

03ng85

2.4

12

V

GS

= 3 V

R

DSon

(mΩ)

a

3.2

10

3.4

1.6

8

6

4

3.6

3.8

4

0.8

5

10

0

−60

0

100

200

300

0

60

120

180

T (°C)

j

I

(A)

D

Fig 11. Drain-source on-state resistance as a function

of drain current; typical values

Fig 12. Normalized drain-source on-state resistance

factor as a function of junction temperature

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N-channel TrenchMOS logic level FET

03ng80

03ng86

5

14000

C

V

(V)

GS

(pF)

12000

C

iss

4

3

2

1

0

10000

8000

6000

4000

2000

0

V

= 14 V

V

= 60 V

DD

C

oss

rss

−1

2

0

20

40

60

80

100

(nC)

10

1

10

Q

G

V

(V)

DS

Fig 13. Gate-source voltage as a function of turn-on

gate charge; typical values

Fig 14. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

03ng79

100

I

S

(A)

80

60

40

20

0

T = 175 °C

j

T = 25 °C

j

0.0

0.2

0.4

0.6

0.8

1.0

(V)

V

SD

Fig 15. Reverse diode current as a function of reverse diode voltage; typical values

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N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)

SOT404

A

E

1

mounting

base

D

1

D

H

D

2

L

p

1

3

c

b

e

Q

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

D

E

A

b

UNIT

c

D

e

L

H

Q

1

p

D

max.

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

1.60

1.20

10.30

9.70

2.90 15.80 2.60

2.10 14.80 2.20

mm

11

2.54

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

05-02-11

06-03-16

SOT404

Fig 16. Package outline SOT404 (D2PAK)

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N-channel TrenchMOS logic level FET

8. Revision history

Table 7.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

BUK9606-75B v.4

Modifications:

20110720

Product data sheet

-

BUK9606-75B v.3

• Various changes to content.

20110207 Product data sheet

BUK9606-75B v.3

-

BUK95_9606_75B v.2

BUK9606-75B

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9. Legal information

9.1 Data sheet status

Document status ^{[1] [2]}

Product status ^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

Right to make changes — NXP Semiconductors reserves the right to make

9.2 Definitions

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Preview — The document is a preview version only. The document is still

subject to formal approval, which may result in modifications or additions.

NXP Semiconductors does not give any representations or warranties as to

the accuracy or completeness of information included herein and shall have

no liability for the consequences of use of such information.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

suitable for use in medical, military, aircraft, space or life support equipment,

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

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BUK9606-75B

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N-channel TrenchMOS logic level FET

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,

FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,

ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,

QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,

TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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N-channel TrenchMOS logic level FET

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .12

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 July 2011

Document identifier: BUK9606-75B


型号：	BUK9606-75B,118
厂家：	NXP
描述：	N-channel TrenchMOS logic level FET D2PAK 3-Pin 开关脉冲晶体管
文件：	总13页 (文件大小：186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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