BUK9607-30B_技术文档

BUK95/9607-30B

TrenchMOS™ logic level FET

Rev. 01 — 25 April 2003

Product data

1. Product proﬁle

1.1 Description

N-channel enhancement mode ﬁeld-effect power transistor in a plastic package using

Philips High-Performance Automotive (HPA) TrenchMOS™ technology.

Product availability:

BUK9507-30B in SOT78 (TO-220AB)

BUK9607-30B in SOT404 (D²-PAK).

1.2 Features

■ Low on-state resistance

■ 175 °C rated

■ Q101 compliant

■ Logic level compatible.

1.3 Applications

■ Automotive systems

■ 12 V loads

■ Motors, lamps and solenoids

■ General purpose power switching.

1.4 Quick reference data

■ E_DS(AL)S≤ 327 mJ

■ I_D≤ 75 A

■ R_DSon= 5.9 mΩ (typ)

■ P_tot≤ 157 W.

2. Pinning information

Table 1:

Pinning - SOT78 and SOT404, simpliﬁed outline and symbol

Description

Simpliﬁed outline

Symbol

1

gate (g)

mb

d

s

[1]

2

drain (d)

source (s)

3

g

mb

mounting base;

connected to drain (d)

MBB076

2

1

3

MBK116

MBK106

1

2 3

SOT78 (TO-220AB)

SOT404 (D²-PAK)

[1] It is not possible to make connection to pin 2 of the SOT404 package.

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

3. Limiting values

Table 2:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

30

Unit

V

drain-source voltage (DC)

drain-gate voltage (DC)

gate-source voltage (DC)

drain current (DC)

-

V_DGR

V_GS

R_GS= 20 kΩ

30

V

±15

108

75

V

[1]

[2]

[1]

I_D

T_mb= 25 °C; V_GS= 5 V;

Figure 2 and 3

A

T_mb= 100 °C; V_GS= 5 V; Figure 2

75

A

I_DM

peak drain current

T_mb= 25 °C; pulsed; t_p≤ 10 µs;

435

A

Figure 3

P_tot

T_stg

T_j

total power dissipation

storage temperature

junction temperature

T_mb= 25 °C; Figure 1

-

157

W

−55

+175

°C

Source-drain diode

[1]

[2]

I_DR

reverse drain current (DC)

T_mb= 25 °C

-

108

75

A

I_DRM

peak reverse drain current

T_mb= 25 °C; pulsed; t_p≤ 10 µs

unclamped inductive load; I_D= 75 A;

435

Avalanche ruggedness

E_DS(AL)Snon-repetitive drain-source

avalanche energy

-

327

mJ

V_DS≤ 30 V; V_GS= 5 V; R_GS= 50 Ω;

starting T_j= 25 °C

[1] Current is limited by power dissipation chip rating.

[2] Continuous current is limited by package.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

2 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

03na19

03nn21

120

I

D

P

der

(%)

(A)

90

80

40

0

60

30

0

Capped at 75 A due to package

0

50

100

150

200

(°C)

0

50

100

150

200

T

mb

T

( C)

°

mb

V_GS≥ 5 V

P_tot

P_der

=

× 100%

-----------------------

P

°

tot(25 C)

Fig 1. Normalized total power dissipation as a

function of mounting base temperature.

Fig 2. Continuous drain current as a function of

mounting base temperature.

03nn19

3

10

Limit R

DSon

= V /I

DS D

I

D

(A)

t

= 10 s

µ

p

2

10

100

s

µ

Capped at 75 A due to package

1 ms

DC

10 ms

10

100 ms

1

10

-1

2

10

1

10

V

(V)

DS

T_mb= 25 °C; I_DMsingle pulse.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

3 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

4. Thermal characteristics

Table 3:

Symbol Parameter

R_th(j-a)thermal resistance from junction to ambient

Thermal characteristics

Conditions

Min

Typ Max Unit

SOT78 package

SOT404 package

vertical in still air

-

60

50

-

K/W

minimum footprint; mounted on a PCB -

R_th(j-mb)thermal resistance from junction to mounting Figure 4

base

-

0.95 K/W

4.1 Transient thermal impedance

03nn20

1

δ = 0.5

Z

th(j-mb)

(K/W)

0.2

0.1

-1

10

0.05

0.02

-2

10

t

p

P

δ =

single shot

T

t

p

T

t

-3

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1

10

1

(s)

p

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

4 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

5. Characteristics

Table 4:

T_j= 25 °C unless otherwise speciﬁed.

Symbol Parameter

Static characteristics

V_(BR)DSSdrain-source breakdown

voltage

Characteristics

Conditions

Min

Typ

Max

Unit

I_D= 0.25 mA; V_GS= 0 V

T_j= 25 °C

30

27

-

V

T_j= −55 °C

V_GS(th)

gate-source threshold voltage I_D= 1 mA; V_DS= V_GS

Figure 9

T_j= 25 °C

;

1.1

0.5

-

1.5

2

V

T_j= 175 °C

T_j= −55 °C

-

2.3

I_DSS

drain-source leakage current V_DS= 30 V; V_GS= 0 V

T_j= 25 °C

T_j= 175 °C

-

0.02

1

µA

nA

-

500

100

I_GSS

gate-source leakage current V_GS= ±15 V; V_DS= 0 V

2

R_DSon

drain-source on-state

resistance

V_GS= 5 V; I_D= 25 A;

Figure 7 and 8

T_j= 25 °C

-

5.9

-

7

mΩ

T_j= 175 °C

13.3

9

V_GS= 4.5 V; I_D= 25 A

V_GS= 10 V; I_D= 25 A

-

4.4

5

Dynamic characteristics

Q_g(tot)

Q_gs

Q_gd

C_iss

C_oss

C_rss

t_d(on)

t_r

total gate charge

gate-source charge

gate-drain (Miller) charge

input capacitance

output capacitance

reverse transfer capacitance

turn-on delay time

rise time

V_GS= 5 V; V_DS= 24 V;

I_D= 25 A; Figure 14

-

32

-

nC

pF

nS

nH

7.6

13

-

V_GS= 0 V; V_DS= 25 V;

f = 1 MHz; Figure 12

2530

635

268

30

3373

762

367

V_DS= 25 V; R_L= 1.2 Ω;

V_GS= 5 V; R_G= 10 Ω

-

135

99

t_d(off)

t_f

turn-off delay time

fall time

98

L_d

internal drain inductance

from drain lead 6 mm from

package to centre of die

4.5

from contact screw on

mounting base to centre of

die SOT78

-

3.5

2.5

7.5

-

nH

from upper edge of drain

mounting base to centre of

die SOT404

L_s

internal source inductance

from source lead 6 mm from

package to source bond pad

9397 750 11239

Product data

Rev. 01 — 25 April 2003

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BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

Table 4:

T_j= 25 °C unless otherwise speciﬁed.

Symbol Parameter

Source-drain diode

Characteristics…continued

Conditions

Min

Typ

Max

Unit

V_SD

source-drain (diode forward) I_S= 25 A; V_GS= 0 V;

-

0.85

1.2

V

voltage

Figure 15

t_rr

reverse recovery time

recovered charge

I_S= 20 A; dI_S/dt = −100 A/µs

V_GS= −10 V; V_DS= 25 V

-

52

35

-

ns

Q_r

nC

9397 750 11239

Product data

Rev. 01 — 25 April 2003

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BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

03nn16

03nn15

300

20

6

Label is V

(V)

R

GS

DSon

I

D

(mΩ)

(A)

10

5

15

10

5

4.8

200

4.6

4.4

4.2

4

100

3.8

3.6

3.4

3.2

3

2.8

2.6

0

2

4

6

8

10

(V)

0

5

10

15

V

(V)

GS

V

DS

T_j= 25 °C; t_p= 300 µs

T_j= 25 °C; I_D= 25 A

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values.

Fig 6. Drain-source on-state resistance as a function

of gate-source voltage; typical values.

03nn17

03aa27

20

2

Label is V

(V)

R

GS

DSon

a

(mΩ)

3.2

3.4

15

1.5

3.6

3.8

4

10

5

1

0.5

0

5

10

0

40

80

120

160

-60

0

60

120

180

I

(A)

°

T ( C)

D

j

T_j= 25 °C; t_p= 300 µs

R_DSon

a =

----------------------------

R_{DSon(25 C)}

°

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values.

Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

7 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

03ng52

03ng53

-1

2.5

10

V

I

GS(th)

(V)

D

(A)

max

-2

2.0

1.5

1.0

0.5

0.0

10

min

typ

max

-3

typ

10

min

-4

-5

-6

10

-60

0

60

120

180

0

0.5

1

1.5

2

2.5

3

(V)

T (°C)

j

V

GS

I_D= 1 mA; V_DS= V_GS

T_j= 25 °C; V_DS= V_GS

Fig 9. Gate-source threshold voltage as a function of

junction temperature.

Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

03nn13

03nn18

80

4500

g

fs

(S)

C

(pF)

60

C

iss

3000

40

20

0

C

oss

1500

C

rss

0

-2

-1

10

2

10

0

25

50

75

100

10

1

10

I

(A)

D

V

(V)

DS

T_j= 25 °C; V_DS= 25 V

V_GS= 0 V; f = 1 MHz

Fig 11. Forward transconductance as a function of

drain current; typical values.

Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

8 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

03nn12

03nn14

5

100

V

GS

I

D

(V)

4

(A)

V

= 14 V

75

DD

V

= 24 V

DD

3

2

1

0

50

25

T = 175 C

T = 25 C

°

j

°

j

0

1

2

3

4

0

10

20

30

40

Q

(nC)

V

(V)

G

GS

V_DS= 25 V

T_j= 25 °C; I_D= 25 A

Fig 13. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

Fig 14. Gate-source voltage as a function of gate

charge; typical values.

03nn11

100

I

S

(A)

75

50

25

T = 175 C

°

j

T = 25 C

°

j

0

0.0

0.3

0.6

0.9

1.2

V

(V)

SD

V_GS= 0 V

Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

9 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

6. Package outline

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB

SOT78

E

p

A

1

q

mounting

base

D

1

D

(1)

L

2

1

Q

b

1

L

1

2

3

b

c

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

b

L

max.

(1)

2

e

A

b

D

E

L

D

L

1

A

c

UNIT

p

q

Q

1

4.5

4.1

1.39

1.27

0.9

0.7

1.3

1.0

0.7

0.4

15.8

15.2

6.4

5.9

10.3

9.7

15.0

13.5

3.30

2.79

3.8

3.6

3.0

2.7

2.6

2.2

mm

3.0

2.54

Note

1. Terminals in this zone are not tinned.

REFERENCES

JEDEC

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

EIAJ

SC-46

00-09-07

01-02-16

SOT78

3-lead TO-220AB

Fig 16. SOT78 (TO-220AB).

9397 750 11239

Product data

Rev. 01 — 25 April 2003

10 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

2

Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads

(one lead cropped)

SOT404

A

E

1

mounting

base

D

1

D

H

D

2

L

p

1

3

c

b

e

Q

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

D

E

A

b

UNIT

c

D

e

L

H

Q

1

p

D

max.

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

1.60

1.20

10.30

9.70

2.90 15.80 2.60

2.10 14.80 2.20

mm

11

2.54

REFERENCES

JEDEC

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

EIAJ

99-06-25

01-02-12

SOT404

Fig 17. SOT404 (D²-PAK).

9397 750 11239

Product data

Rev. 01 — 25 April 2003

11 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

7. Soldering

10.85

10.60

10.50

handbook, full pagewidth

1.50

7.50

7.40

1.70

2.15

1.50

2.25

8.275

8.35

8.15

4.60

0.30

4.85

5.40

7.95

8.075

3.00

0.20

1.20

1.30

1.55

solder lands

solder resist

occupied area

solder paste

5.08

MSD057

Dimensions in mm.

Fig 18. Reﬂow soldering footprint for SOT404.

9397 750 11239

Product data

Rev. 01 — 25 April 2003

12 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

8. Revision history

Table 5:

Revision history

CPCN

Rev Date

Description

01 20030425

-

Product data (9397 750 11239)

9397 750 11239

Product data

Rev. 01 — 25 April 2003

13 of 15

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

9. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

10. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

12. Trademarks

— TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.

11. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

14 of 15

9397 750 11239

Product data

Rev. 01 — 25 April 2003

BUK95/9607-30B

Philips Semiconductors

TrenchMOS™ logic level FET

Contents

1

Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

Transient thermal impedance . . . . . . . . . . . . . . 4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3

4

4.1

5

6

7

8

9

10

11

12

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 25 April 2003

Document order number: 9397 750 11239


型号：	BUK9607-30B
厂家：	NXP
描述：	TrenchMOS logic level FET 的TrenchMOS逻辑电平FET
文件：	总15页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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