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BUK9612-55B [NXP]

TrenchMOS⑩ logic level FET; 的TrenchMOS ™逻辑电平FET
BUK9612-55B
型号： BUK9612-55B
厂家： NXP    NXP
描述：

TrenchMOS⑩ logic level FET
的TrenchMOS ™逻辑电平FET

晶体 晶体管 开关 脉冲
文件： 总15页 (文件大小：281K)
中文：  中文翻译
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BUK95/9612-55B  
TrenchMOS™ logic level FET  
Rev. 01 — 28 April 2003  
Product data  
1. Product profile  
1.1 Description  
N-channel enhancement mode field-effect power transistor in a plastic package using  
Philips High-Performance Automotive (HPA) TrenchMOS™ technology.  
Product availability:  
BUK9512-55B in SOT78 (TO-220AB)  
BUK9612-55B in SOT404 (D2-PAK).  
1.2 Features  
■ Low on-state resistance  
■ 175 °C rated  
■ Q101 compliant  
■ Logic level compatible.  
1.3 Applications  
■ Automotive systems  
■ 12 V and 24 V loads  
■ Motors, lamps and solenoids  
■ General purpose power switching.  
1.4 Quick reference data  
■ EDS(AL)S ≤ 172 mJ  
■ ID ≤ 75 A  
■ RDSon = 10.2 mΩ (typ)  
■ Ptot ≤ 157 W.  
2. Pinning information  
Table 1:  
Pin  
Pinning - SOT78 and SOT404, simplified outline and symbol  
Description  
Simplified outline  
Symbol  
1
gate (g)  
mb  
mb  
d
s
[1]  
2
drain (d)  
source (s)  
3
g
mb  
mounting base;  
connected to drain (d)  
MBB076  
2
1
3
MBK116  
MBK106  
1
2 3  
SOT78 (TO-220AB)  
SOT404 (D2-PAK)  
[1] It is not possible to make connection to pin 2 of the SOT404 package.  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
3. Limiting values  
Table 2:  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDS  
Parameter  
Conditions  
Min  
Max  
55  
Unit  
V
drain-source voltage (DC)  
drain-gate voltage (DC)  
gate-source voltage (DC)  
drain current (DC)  
-
-
-
-
-
-
-
VDGR  
VGS  
RGS = 20 kΩ  
55  
V
±15  
79  
V
[1]  
[2]  
[1]  
ID  
Tmb = 25 °C; VGS = 5 V;  
Figure 2 and 3  
A
75  
A
Tmb = 100 °C; VGS = 5 V; Figure 2  
56  
A
IDM  
peak drain current  
Tmb = 25 °C; pulsed; tp ≤ 10 µs;  
322  
A
Figure 3  
Ptot  
Tstg  
Tj  
total power dissipation  
storage temperature  
junction temperature  
Tmb = 25 °C; Figure 1  
-
157  
W
−55  
−55  
+175  
+175  
°C  
°C  
Source-drain diode  
[1]  
[2]  
IDR  
reverse drain current (DC)  
Tmb = 25 °C  
-
-
-
79  
A
A
A
75  
IDRM  
peak reverse drain current  
Tmb = 25 °C; pulsed; tp ≤ 10 µs  
unclamped inductive load; ID = 75 A;  
322  
Avalanche ruggedness  
EDS(AL)S non-repetitive drain-source  
avalanche energy  
-
172  
mJ  
VDS ≤ 55 V; VGS = 5 V; RGS = 50 Ω;  
starting Tj = 25 °C  
[1] Current is limited by power dissipation chip rating.  
[2] Continuous current is limited by package.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
2 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03na19  
03nn10  
120  
80  
I
D
P
der  
(%)  
(A)  
60  
80  
40  
0
40  
20  
0
Capped at 75 A due to package  
0
50  
100  
150  
200  
(°C)  
0
50  
100  
150  
200  
T
mb  
T
( C)  
°
mb  
VGS ≥ 5 V  
Ptot  
Pder  
=
× 100%  
-----------------------  
P
°
tot(25 C)  
Fig 1. Normalized total power dissipation as a  
function of mounting base temperature.  
Fig 2. Continuous drain current as a function of  
mounting base temperature.  
03nn08  
3
10  
Limit R  
DSon  
= V /I  
DS D  
I
D
(A)  
t
= 10 s  
µ
p
2
10  
100  
s
µ
Capped at 75 A due to package  
DC  
1 ms  
10  
10 ms  
100 ms  
1
2
10  
1
10  
V
(V)  
DS  
Tmb = 25 °C; IDM single pulse.  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
3 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
4. Thermal characteristics  
Table 3:  
Symbol  
Rth(j-a)  
Thermal characteristics  
Parameter  
Conditions  
Min  
Typ Max Unit  
thermal resistance from junction to ambient  
SOT78 package  
vertical in still air;  
-
60  
50  
-
-
-
K/W  
K/W  
SOT404 package  
minimum footprint; mounted on PCB -  
Rth(j-mb)  
thermal resistance from junction to mounting Figure 4  
base  
-
0.95 K/W  
4.1 Transient thermal impedance  
03nn09  
1
δ = 0.5  
Z
th(j-mb)  
(K/W)  
0.2  
0.1  
-1  
10  
0.05  
0.02  
-2  
10  
t
p
P
δ =  
single shot  
T
t
t
p
T
-3  
10  
-6  
10  
-5  
10  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
1
t
(s)  
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
4 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
5. Characteristics  
Table 4:  
Tj = 25 °C unless otherwise specified.  
Symbol Parameter  
Static characteristics  
V(BR)DSS drain-source breakdown  
voltage  
Characteristics  
Conditions  
Min  
Typ  
Max  
Unit  
ID = 0.25 mA; VGS = 0 V  
Tj = 25 °C  
55  
50  
-
-
-
-
V
V
Tj = −55 °C  
VGS(th)  
gate-source threshold voltage ID = 1 mA; VDS = VGS  
Figure 9  
Tj = 25 °C  
;
1.1  
0.5  
-
1.5  
2
V
V
V
Tj = 175 °C  
Tj = −55 °C  
-
-
-
2.3  
IDSS  
drain-source leakage current VDS = 55 V; VGS = 0 V  
Tj = 25 °C  
Tj = 175 °C  
-
-
-
0.02  
1
µA  
µA  
nA  
-
500  
100  
IGSS  
gate-source leakage current VGS = ±15 V; VDS = 0 V  
2
RDSon  
drain-source on-state  
resistance  
VGS = 5 V; ID = 25 A;  
Figure 7 and 8  
Tj = 25 °C  
-
-
-
-
10.2  
12  
mΩ  
mΩ  
mΩ  
mΩ  
Tj = 175 °C  
-
24  
VGS = 4.5 V; ID = 25 A  
VGS = 10 V; ID = 25 A  
-
13.3  
10  
9
Dynamic characteristics  
Qg(tot)  
Qgs  
Qgd  
Ciss  
Coss  
Crss  
td(on)  
tr  
total gate charge  
gate-source charge  
gate-drain (Miller) charge  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
VGS = 5 V; VDS = 44 V;  
ID = 25 A; Figure 14  
-
-
-
-
-
-
-
-
-
-
−
31  
-
nC  
nC  
nC  
pF  
pF  
pF  
nS  
nS  
nS  
nS  
nH  
6
-
12  
-
VGS = 0 V; VDS = 25 V;  
f = 1 MHz; Figure 12  
2770  
360  
160  
19  
3693  
431  
220  
VDS = 30 V; RL = 1.2 Ω;  
VGS = 5 V; RG = 10 Ω  
-
-
-
-
-
101  
96  
td(off)  
tf  
turn-off delay time  
fall time  
75  
Ld  
internal drain inductance  
from drain lead 6 mm from  
package to centre of die  
4.5  
from contact screw on  
mounting base to centre of  
die SOT78  
−
−
-
3.5  
2.5  
7.5  
-
-
-
nH  
nH  
nH  
from upper edge of drain  
mounting base to centre of  
die SOT404  
Ls  
internal source inductance  
from source lead 6 mm from  
package to source bond pad  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
5 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
Table 4:  
Tj = 25 °C unless otherwise specified.  
Symbol Parameter  
Source-drain diode  
Characteristics…continued  
Conditions  
Min  
Typ  
Max  
Unit  
VSD  
source-drain (diode forward) IS = 25 A; VGS = 0 V;  
-
0.85  
1.2  
V
voltage  
Figure 15  
trr  
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = −100 A/µs  
VGS = −10 V; VDS = 30 V  
-
-
55  
53  
-
-
ns  
Qr  
nC  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
6 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03nn05  
03nn04  
250  
20  
Label is V  
(V)  
GS  
I
D
(A)  
R
DSon  
10  
8
(mΩ)  
200  
5
4.8  
6
15  
10  
5
4.6  
4.4  
4.2  
150  
100  
50  
4
3.8  
3.6  
3.4  
3.2  
3
2.8  
2.6  
2.4  
2.2  
0
0
2
4
6
8
10  
(V)  
3
7
11  
15  
V
(V)  
GS  
V
DS  
Tj = 25 °C; tp = 300 µs  
Tj = 25 °C; ID = 25 A  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values.  
Fig 6. Drain-source on-state resistance as a function  
of gate-source voltage; typical values.  
03ne89  
03nn06  
25  
2
3.8 4  
5
10  
3
R
DSon  
(mΩ)  
a
3.2  
3.4  
3.6  
20  
1.5  
15  
10  
5
1
0.5  
0
Label is V  
(V)  
GS  
0
50  
100  
150  
200  
250  
-60  
0
60  
120  
180  
I
(A)  
T ( C)  
°
D
j
Tj = 25 °C; tp = 300µs  
RDSon  
a =  
----------------------------  
RDSon(25 C)  
°
Fig 7. Drain-source on-state resistance as a function  
of drain current; typical values.  
Fig 8. Normalized drain-source on-state resistance  
factor as a function of junction temperature.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
7 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03ng52  
03ng53  
-1  
2.5  
10  
V
I
GS(th)  
(V)  
D
(A)  
max  
-2  
2.0  
1.5  
1.0  
0.5  
0.0  
10  
min  
typ  
max  
-3  
typ  
10  
min  
-4  
-5  
-6  
10  
10  
10  
-60  
0
60  
120  
180  
0
0.5  
1
1.5  
2
2.5  
3
(V)  
T (°C)  
j
V
GS  
ID = 1 mA; VDS = VGS  
Tj = 25 °C; VDS = VGS  
Fig 9. Gate-source threshold voltage as a function of  
junction temperature.  
Fig 10. Sub-threshold drain current as a function of  
gate-source voltage.  
03nn07  
03nn02  
80  
6000  
g
(S)  
fs  
C
(pF)  
60  
C
iss  
4000  
40  
20  
0
C
oss  
2000  
C
rss  
0
-2  
-1  
10  
2
10  
0
20  
40  
60  
10  
1
10  
I
(A)  
V
(V)  
D
DS  
Tj = 25 °C; VDS = 25 V  
VGS = 0 V; f = 1 MHz  
Fig 11. Forward transconductance as a function of  
drain current; typical values.  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
8 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03nn03  
03nn01  
100  
5
V
GS  
I
D
(V)  
(A)  
4
V
= 14 V  
75  
V
= 44 V  
DD  
DD  
3
2
1
0
50  
25  
T = 175 C  
°
j
T = 25 C  
°
j
0
0
1
2
3
4
5
0
10  
20  
30  
40  
Q
(nC)  
G
V
(V)  
GS  
VDS = 25 V  
Tj = 25 °C; ID = 25 A  
Fig 13. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values.  
Fig 14. Gate-source voltage as a function of gate  
charge; typical values.  
03nn00  
100  
I
S
(A)  
75  
50  
T = 175 C  
°
j
25  
0
T = 25 C  
°
j
0.0  
0.3  
0.6  
0.9  
1.2  
V
(V)  
SD  
VGS = 0 V  
Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
9 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
6. Package outline  
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB  
SOT78  
E
p
A
A
1
q
mounting  
base  
D
1
D
(1)  
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
b
L
max.  
(1)  
2
e
A
b
D
E
L
D
L
1
A
c
UNIT  
p
q
Q
1
1
1
4.5  
4.1  
1.39  
1.27  
0.9  
0.7  
1.3  
1.0  
0.7  
0.4  
15.8  
15.2  
6.4  
5.9  
10.3  
9.7  
15.0  
13.5  
3.30  
2.79  
3.8  
3.6  
3.0  
2.7  
2.6  
2.2  
mm  
3.0  
2.54  
Note  
1. Terminals in this zone are not tinned.  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
SC-46  
00-09-07  
01-02-16  
SOT78  
3-lead TO-220AB  
Fig 16. SOT78 (TO-220AB).  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
10 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads  
(one lead cropped)  
SOT404  
A
A
E
1
mounting  
base  
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
D
E
A
A
b
UNIT  
c
D
e
L
H
Q
1
1
p
D
max.  
4.50  
4.10  
1.40  
1.27  
0.85  
0.60  
0.64  
0.46  
1.60  
1.20  
10.30  
9.70  
2.90 15.80 2.60  
2.10 14.80 2.20  
mm  
11  
2.54  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
99-06-25  
01-02-12  
SOT404  
Fig 17. SOT404 (D2-PAK).  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
11 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
7. Soldering  
10.85  
10.60  
10.50  
1.50  
7.50  
7.40  
1.70  
2.15  
1.50  
2.25  
8.275  
8.35  
8.15  
4.60  
0.30  
4.85  
5.40  
7.95  
8.075  
3.00  
0.20  
1.20  
1.30  
1.55  
solder lands  
solder resist  
occupied area  
solder paste  
5.08  
MSD057  
Dimensions in mm.  
Fig 18. Reflow soldering footprint for SOT404.  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
12 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
8. Revision history  
Table 5:  
Revision history  
CPCN  
Rev Date  
Description  
01 20030428  
-
Product data (9397 750 11247)  
9397 750 11247  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 01 — 28 April 2003  
13 of 15  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
9. Data sheet status  
Level Data sheet status[1]  
Product status[2][3]  
Definition  
I
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips  
Semiconductors reserves the right to change the specification in any manner without notice.  
II  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification. Supplementary data will be published  
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in  
order to improve the design and supply the best possible product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant  
changes will be communicated via a Customer Product/Process Change Notification (CPCN).  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
[3]  
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
10. Definitions  
Short-form specification — The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes in the products - including circuits, standard cells, and/or  
software - described or contained herein in order to improve design and/or  
performance. When the product is in full production (status ‘Production’),  
relevant changes will be communicated via a Customer Product/Process  
Change Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
Limiting values definition — Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Application information — Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
12. Trademarks  
— TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.  
11. Disclaimers  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
Contact information  
For additional information, please visit http://www.semiconductors.philips.com.  
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
14 of 15  
9397 750 11247  
Product data  
Rev. 01 — 28 April 2003  
BUK95/9612-55B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Transient thermal impedance . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
3
4
4.1  
5
6
7
8
9
10  
11  
12  
© Koninklijke Philips Electronics N.V. 2003.  
Printed in The Netherlands  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 28 April 2003  
Document order number: 9397 750 11247  

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