BUK9635-100A [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | BUK9635-100A |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总7页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technology
the device features very low on-state
resistance. It is intended for use in
automotive and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
100
40
150
175
V
A
W
˚C
RDS(ON)
resistance
VGS = 5 V
VGS = 10 V
35
34
mΩ
mΩ
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
mb
gate
2
drain
(no connection possible)
g
2
3
source
s
1
3
mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non Repetive gate-source voltage
Drain current (DC)
-
-
-
-
-
-
-
-
-
100
100
10
15
40
V
V
V
V
A
A
A
W
˚C
VDGR
±VGS
±VGSM
ID
ID
IDM
RGS = 20 kΩ
-
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
Drain current (DC)
29
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
133
150
175
Ptot
Tstg, Tj
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Rth j-a
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
-
1.01
K/W
Minimum footprint, FR4
board
50
-
K/W
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
100
89
1
0.5
-
-
-
-
-
-
-
-
-
-
-
-
2
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
Tj = -55˚C
VDS = VGS; ID = 1 mA
1.5
-
Tj = 175˚C
Tj = -55˚C
-
2.3
10
500
100
35
95
34
38
IDSS
Zero gate voltage drain current VDS = 100 V; VGS = 0 V;
0.05
-
2
26
-
24.1
26.1
Tj = 175˚C
Tj = 175˚C
IGSS
RDS(ON)
Gate source leakage current
Drain-source on-state
resistance
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A
VGS = 10 V; ID = 25 A
VGS = 4.5 V; ID = 25 A
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
2700 3500
pF
pF
pF
260
160
314
220
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; Rload =1.2Ω;
VGS = 10 V; RG = 10 Ω
-
-
-
-
10
62
194
108
15
87
291
162
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from upper edge of drain
tab to centre of die
Measured from source lead
soldering point to source bond pad
-
-
2.5
7.5
-
-
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
40
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
133
1.2
-
A
V
V
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
0.85
1.1
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 40 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
-
60
0.3
-
-
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 40 A; VDD ≤ 25 V;
VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
-
-
125
mJ
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
Normalised Power Derating
Zth/(K/W)
D=
PD%
10
1
120
110
100
90
80
70
60
50
40
30
20
10
0
0.5
0.2
0.1
0.1
0.05
0.02
tp
T
tp
P
0.01
D =
D
0
t
T
0.001
0
20
40
60
80
Tmb /
100 120 140 160 180
C
1E-07
1E-05
1E-3
t/S
1E-01
1E+01
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
150
ID/A
VGS/V=
120
110
100
90
80
70
60
50
40
30
20
10
0
10.0
5.0
4.0
3.8
3.6
100
50
0
3.4
3.2
3.0
2.8
2.6
2.4
2.2
0
20
40
60
80
100 120 140 160 180
C
0
2
4
6
10
8
Tmb /
VDS/V
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
1000
RDS(ON)/mOhm
40
ID/A
tp=
RDS(ON)=VDS/ID
35
100
10
1
1uS
VGS/V=
10uS
30
3.0
100uS
1mS
3.2
3.4
3.6
4.0
5.0
DC
25
10mS
100mS
20
0
10
20
30
40
50
60
70
1
10
100
1000
VDS/V
ID/A
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
Rds(on) normalised to 25degC
RDS(ON)/mOhm
33
a
3
2.5
2
32
31
30
29
28
27
26
25
24
23
22
1.5
1
0.5
-100
-50
0
50
100
150
200
3
4
5
6
7
8
9
10
Tmb / degC
ID/A
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(VGS); conditions: ID = 25 A;
Fig.10. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
90
ID/A
VGS(TO) / V
max.
2.5
2
80
70
60
50
40
30
20
10
0
typ.
1.5
1
min.
0.5
Tj/C=
25
175
0
-100
-50
0
50
Tj / C
100
150
200
0.0
1.0
2.0
3.0
4.0
5.0
VGS/V
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
70
Sub-Threshold Conduction
1E-01
gfs/S
60
50
40
30
20
10
0
1E-02
1E-03
1E-04
1E-05
1E-05
2%
typ
98%
0
20
40
60
80
100
0
0.5
1
1.5
2
2.5
3
ID/A
Fig.9. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
7
6
5
4
3
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
ThouandspF
Ciss
2
1
Coss
Crss
0
20
40
60
80
100
120
140
160
180
0.01
0.1
1
10
100
Tmb /
C
VDS/V
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
VDD
6
+
VGS / V
L
5
VDS = 14V
VDS
4
VDS = 44V
-
3
2
1
0
VGS
-ID/100
T.U.T.
0
R 01
RGS
shunt
0
10 QG / nC 20
30
40
Fig.17. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 25 A; parameter VDS
)
100
80
VDD
+
-
RD
VDS
60
Tj/C=
25
175
VGS
0
40
20
0
RG
T.U.T.
0.0
0.5
1.0
1.5
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.18. Switching test circuit.
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
MECHANICAL DATA
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.40 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
98-12-14
99-06-25
SOT404
Fig.19. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9635-100A
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.20. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
7
Rev 1.000
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