BUK9840-55 [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | BUK9840-55 |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总9页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
automotive and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
55
10.7
1.8
150
40
V
A
W
˚C
mΩ
RDS(ON)
resistance
VGS = 5 V
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
4
gate
2
drain
g
3
source
4
drain (tab)
s
2
3
1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
Drain-source voltage
-
-
-
-
-
-
55
55
10
10.7
5
V
V
V
A
A
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
RGS = 20 kΩ
-
Tsp = 25 ˚C
On PCB in Fig.19
Tamb = 25 ˚C
On PCB in Fig.19
Tamb = 100 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
On PCB in Fig.19
Tamb = 25 ˚C
-
ID
ID
Drain current (DC)
-
3.1
A
IDM
Ptot
Ptot
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
-
-
-
40
8.3
1.8
A
W
W
Tstg, Tj
Storage & operating temperature
- 55
150
˚C
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model
(100 pF, 1.5 kΩ)
-
2
kV
January 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-sp
Rth j-amb
From junction to solder point
From junction to ambient
Mounted on any PCB
Mounted on PCB of Fig.18
12
-
15
70
K/W
K/W
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA
55
50
1.0
0.6
-
-
-
-
-
10
-
-
-
-
V
V
V
V
V
µA
µA
µA
µA
V
Tj = -55˚C
VGS(TO)
VDS = VGS; ID = 1 mA
1.5
-
-
0.05
-
0.02
-
-
2.0
-
2.3
10
100
1
Tj = 150˚C
Tj = -55˚C
IDSS
IGSS
Zero gate voltage drain current VDS = 55 V; VGS = 0 V;
Gate source leakage current VGS = ±5 V
Gate source breakdown voltage IG = ±1 mA
Tj = 150˚C
Tj = 150˚C
5
-
±V(BR)GSS
RDS(ON)
Drain-source on-state
resistance
VGS = 5 V; ID = 5 A
-
-
30
-
40
74
mΩ
mΩ
Tj = 150˚C
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 5 A; Tj = 25˚C
VGS = 0 V; VDS = 25 V; f = 1 MHz
11
19
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
1050 1400
205
110
pF
pF
pF
245
150
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 9 A;
VGS = 5 V; RG = 10 Ω;
-
-
-
-
17
65
70
70
25
ns
ns
ns
ns
100
105
105
Tj = 25˚C
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = -55 to 175˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
Tsp = 25˚C
-
-
10.7
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
Tsp = 25˚C
IF = 5 A; VGS = 0 V
-
-
-
40
1.1
A
V
0.85
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 5 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
-
45
.3
-
-
ns
µC
January 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 3.6 A; VDD ≤ 25 V;
-
-
60
mJ
VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C
Normalised Power Derating
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
100
ID/A
tp =
RDS(ON) = VDS/ID
1 us
10 us
100 us
10
1
1 ms
DC
10 ms
100 ms
0
20
40
60
80
Tmb /
100
120
140
0.1
0.1
1
10
55
C
VDS/V
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tsp)
Fig.3. Safe operating area. Tsp = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
Zth / (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
1E+02
3E+01
1E+01
0.5
3E+00
1E+00
3E-01
1E-01
3E-02
1E-02
0.2
0.1
0.05
0.02
p
t
t
p
P
D =
D
T
t
T
0
0
20
40
60
80
Tmb /
100
120
140
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T
January 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
25
gfs/S
20
10
5
4
VGS/V =
3.4
ID/A
3.6
20
15
10
5
15
3.2
3.0
10
5
2.8
2.6
2.4
2.2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
ID/A
0
0
2
4
6
8
10
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
RDS(ON)/mOhm
80
Rds(on) normalised to 25degC
a
2.5
2
3
VGS/V =
70
60
50
40
30
20
3.2
1.5
1
3.4
3.6
4
5
0.5
-100
-50
0
50
100
150
200
0
5
10
15
20
25
ID/A
Tmb / degC
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5 A; VGS = 5 V
20
VGS(TO) / V
max.
B
2.5
2
ID/A
15
10
5
typ.
1.5
1
min.
150
25
Tj/C =
0.5
0
-100
-50
0
50
Tj / C
100
150
200
0
0
1
2
3
4
VGS/V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
January 1998
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
20
IF/A
Sub-Threshold Conduction
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
15
10
5
Tj/C =
150
25
2%
typ
98%
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
0.5
1
1.5
2
2.5
3
VSDS/V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
2.5
2.0
1.5
1.0
0.5
0
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
Ciss
ThouandspF
Coss
Crss
20
40
60
80
Tmb /
100
C
120
140
0.01
0.1
1
10
100
VDS/V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tsp); conditions: ID = 3.6 A
6
VGS/V
VDD
+
5
L
4
3
2
1
0
VDS
VDS = 14V
VDS = 44V
-
VGS
-ID/100
T.U.T.
0
R 01
RGS
shunt
0
5
10
15
20
QG/nC
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 9 A; parameter VDS
)
January 1998
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
VDD
+
-
RD
VDS
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
January 1998
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
18
60
4.5
4.6
9
10
7
15
50
Fig.18. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick).
January 1998
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
6.7
6.3
B
3.1
2.9
0.32
0.24
0.2
M
A
A
4
0.10
0.02
7.3
6.7
3.7
3.3
16
max
13
2
3
1
10
max
1.05
0.85
0.80
0.60
2.3
1.8
max
M
0.1
(4x)
B
4.6
Fig.19. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
January 1998
8
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9840-55
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1998
9
Rev 1.000
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