首页 |元器件品牌

BUK9E4R4-40B [NXP]

TrenchMOS logic level FET; 的TrenchMOS逻辑电平FET
BUK9E4R4-40B
型号： BUK9E4R4-40B
厂家： NXP    NXP
描述：

TrenchMOS logic level FET
的TrenchMOS逻辑电平FET
文件： 总16页 (文件大小：297K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
BUK95/96/9E4R4-40B  
TrenchMOS™ logic level FET  
Rev. 02 — 13 October 2003  
Product data  
1. Product profile  
1.1 Description  
N-channel enhancement mode field-effect power transistor in a plastic package using  
Philips High-Performance Automotive (HPA) TrenchMOS™ technology.  
1.2 Features  
■ Very low on-state resistance  
■ 175 °C rated  
■ Q101 compliant  
■ Logic level compatible.  
1.3 Applications  
■ Automotive systems  
■ 12 V loads  
■ Motors, lamps and solenoids  
■ General purpose power switching.  
1.4 Quick reference data  
■ EDS(AL)S ≤ 961 mJ  
■ ID ≤ 75 A  
■ RDSon = 3.9 mΩ (typ)  
■ Ptot ≤ 254 W.  
2. Pinning information  
Table 1:  
Pinning - SOT78, SOT404, and SOT226 simplified outlines and symbol  
Pin  
1
Description  
gate (g)  
Simplified outline  
Symbol  
mb  
d
s
mb  
mb  
[1]  
2
drain (d)  
3
source (s)  
g
mb  
mounting base,  
connected to  
drain (d)  
MBB076  
2
1
3
MBK116  
1
2 3  
MBK112  
MBK106  
1
2 3  
SOT404 (D2-PAK)  
SOT226 (I2-PAK)  
SOT78 (TO-220AB)  
[1] It is not possible to make connection to pin 2 of the SOT404 package.  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
3. Ordering information  
Table 2:  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
BUK954R4-40B  
BUK964R4-40B  
BUK9E4R4-40B  
TO-220AB Plastic single-ended heat-sink mounted package  
SOT78  
D2-PAK  
I2-PAK  
Plastic single-ended surface mounted package  
Plastic single-ended low-profile package  
SOT404  
SOT226  
4. Limiting values  
Table 3:  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
40  
Unit  
V
VDS  
VDGR  
VGS  
ID  
drain-source voltage (DC)  
-
-
-
-
-
-
-
drain-gate voltage (DC)  
gate-source voltage (DC)  
drain current (DC)  
RGS = 20 kΩ  
40  
V
±15  
174  
75  
V
[1]  
[2]  
[2]  
Tmb = 25 °C; VGS = 5 V;  
Figure 2 and 3  
A
A
Tmb = 100 °C; VGS = 5 V; Figure 2  
75  
A
IDM  
peak drain current  
Tmb = 25 °C; pulsed; tp ≤ 10 µs;  
697  
A
Figure 3  
Ptot  
Tstg  
Tj  
total power dissipation  
storage temperature  
junction temperature  
Tmb = 25 °C; Figure 1  
-
254  
W
−55  
−55  
+175  
+175  
°C  
°C  
Source-drain diode  
[1]  
[2]  
IDR  
reverse drain current (DC)  
Tmb = 25 °C  
-
-
-
174  
75  
A
A
A
IDRM  
peak reverse drain current  
Tmb = 25 °C; pulsed; tp ≤ 10 µs  
697  
Avalanche ruggedness  
EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 75 A;  
-
961  
mJ  
energy  
VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω;  
starting Tmb = 25 °C  
[1] Current is limited by power dissipation chip rating  
[2] Continuous current is limited by package.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
2 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03na19  
03nl57  
120  
200  
I
D
P
der  
(%)  
(A)  
150  
100  
50  
80  
40  
0
Capped at 75 A due to package  
0
0
50  
100  
150  
200  
(°C)  
0
50  
100  
150  
200  
( C)  
T
T
mb  
°
mb  
VGS ≥ 5 V  
Ptot  
Pder  
=
× 100%  
-----------------------  
P
°
tot(25 C)  
Fig 1. Normalized total power dissipation as a  
function of mounting base temperature.  
Fig 2. Continuous drain current as a function of  
mounting base temperature.  
03nl58  
3
10  
Limit R  
DSon  
= V /I  
DS D  
I
D
t
= 10 s  
µ
(A)  
p
2
100 s  
µ
10  
1 ms  
Capped at 75 A due to package  
10 ms  
DC  
10  
100 ms  
1
-1  
2
10  
10  
1
10  
V
(V)  
DS  
Tmb = 25 °C; IDM single pulse.  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
3 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
5. Thermal characteristics  
Table 4:  
Thermal characteristics  
Symbol Parameter  
Conditions  
Min Typ Max Unit  
Rth(j-mb) thermal resistance from junction to mounting Figure 4  
base  
-
-
0.59 K/W  
Rth(j-a)  
thermal resistance from junction to ambient  
SOT78 (TO-220AB)  
SOT226 (I2-PAK)  
SOT404 (D2-PAK)  
vertical in still air  
-
-
-
60  
60  
50  
-
-
-
K/W  
K/W  
K/W  
vertical in still air  
minimum footprint; mounted on a PCB  
5.1 Transient thermal impedance  
03nl59  
1
Z
th(j-mb)  
(K/W)  
δ = 0.5  
0.2  
0.1  
-1  
10  
0.05  
0.02  
-2  
10  
t
p
P
δ =  
T
single shot  
t
t
p
T
-3  
10  
-6  
10  
-5  
10  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
1
t
(s)  
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
4 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
6. Characteristics  
Table 5:  
Tj = 25 °C unless otherwise specified  
Symbol Parameter  
Static characteristics  
V(BR)DSS drain-source breakdown  
voltage  
Characteristics  
Conditions  
Min  
Typ  
Max  
Unit  
ID = 0.25 mA; VGS = 0 V  
Tj = 25 °C  
40  
36  
-
-
-
-
V
V
Tj = −55 °C  
VGS(th)  
gate-source threshold voltage ID = 1 mA; VDS = VGS  
Figure 9  
Tj = 25 °C  
;
1.1  
0.5  
-
1.5  
2
V
V
V
Tj = 175 °C  
Tj = −55 °C  
-
-
-
2.3  
IDSS  
drain-source leakage current VDS = 40 V; VGS = 0 V  
Tj = 25 °C  
Tj = 175 °C  
-
-
-
0.02  
1
µA  
µA  
nA  
-
500  
100  
IGSS  
gate-source leakage current VGS = ±15 V; VDS = 0 V  
2
RDSon  
drain-source on-state  
resistance  
VGS = 5 V; ID = 25 A;  
Figure 7 and 8  
Tj = 25 °C  
-
-
-
-
3.9  
-
4.4  
8.3  
4.8  
4
mΩ  
mΩ  
mΩ  
mΩ  
Tj = 175 °C  
VGS = 4.5 V; ID = 25 A  
VGS = 10 V; ID = 25 A  
-
3.6  
Dynamic characteristics  
Qg(tot)  
Qgs  
Qgd  
Ciss  
Coss  
Crss  
td(on)  
tr  
total gate charge  
VGS = 5 V; VDD = 32 V;  
ID = 25 A; Figure 14  
-
-
-
-
-
-
-
-
-
-
-
64  
-
nC  
nC  
nC  
pF  
pF  
pF  
ns  
gate-to-source charge  
gate-to-drain (Miller) charge  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
11  
-
24  
-
VGS = 0 V; VDS = 25 V;  
f = 1 MHz; Figure 12  
5343  
943  
408  
44  
7124  
1131  
558  
VDD = 30 V; RL = 1.2 Ω;  
VGS = 5 V; RG = 10 Ω  
-
-
-
-
-
118  
197  
132  
4.5  
ns  
td(off)  
tf  
turn-off delay time  
fall time  
ns  
ns  
Ld  
internal drain inductance  
from drain lead 6 mm from  
package to center of die  
nH  
from contact screw on  
mounting base to center of  
die SOT78  
-
-
-
3.5  
2.5  
7.5  
-
-
-
nH  
nH  
nH  
from upper edge of drain  
mounting base to center of  
die SOT404/SOT226  
Ls  
internal source inductance  
from source lead to source  
bond pad  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
5 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
Table 5:  
Tj = 25 °C unless otherwise specified  
Symbol Parameter  
Source-drain diode  
Characteristics…continued  
Conditions  
Min  
Typ  
Max  
Unit  
VSD  
source-drain (diode forward) IS = 25 A; VGS = 0 V;  
-
0.85  
1.2  
V
voltage  
Figure 15  
trr  
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = −100 A/µs  
VGS = −10 V; VDS = 30 V  
-
-
70  
67  
-
-
ns  
Qr  
nC  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
6 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03nl86  
03nl85  
350  
5
10  
5
Label is V  
(V)  
4
3.8  
GS  
I
D
(A)  
280  
R
DSon  
(mΩ)  
3.6  
3.4  
210  
140  
70  
3.2  
3
4
2.8  
2.6  
2.4  
2.2  
0
3
0
2
4
6
8
10  
(V)  
3
7
11  
15  
V
(V)  
V
GS  
DS  
Tj = 25 °C; tp = 300 µs  
Tj = 25 °C; ID = 25 A  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values.  
Fig 6. Drain-source on-state resistance as a function  
of gate-source voltage; typical values.  
03aa27  
03nl87  
8
2
3
3.2  
Label V  
(V)  
GS  
R
DSon  
(mΩ)  
3.4  
a
7
6
5
4
3
1.5  
4
1
0.5  
0
5
10  
0
70  
140  
210  
280  
350  
-60  
0
60  
120  
180  
I
(A)  
°
T ( C)  
D
j
Tj = 25 °C  
RDSon  
a =  
----------------------------  
RDSon(25 C)  
°
Fig 7. Drain-source on-state resistance as a function  
of drain current; typical values.  
Fig 8. Normalized drain-source on-state resistance  
factor as a function of junction temperature.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
7 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03ng52  
03ng53  
-1  
2.5  
10  
V
I
GS(th)  
(V)  
D
(A)  
max  
-2  
2.0  
1.5  
1.0  
0.5  
0.0  
10  
min  
typ  
max  
-3  
typ  
10  
min  
-4  
-5  
-6  
10  
10  
10  
-60  
0
60  
120  
180  
0
0.5  
1
1.5  
2
2.5  
3
(V)  
T (°C)  
j
V
GS  
ID = 1 mA; VDS = VGS  
Tj = 25 °C; VDS = VGS  
Fig 9. Gate-source threshold voltage as a function of  
junction temperature.  
Fig 10. Sub-threshold drain current as a function of  
gate-source voltage.  
03nl83  
03nl60  
180  
10000  
C
(pF)  
C
iss  
g
(S)  
fs  
7500  
C
oss  
120  
5000  
C
rss  
60  
2500  
0
0
-2  
-1  
10  
2
0
14  
28  
42  
56  
70  
10  
1
10  
10  
(V)  
I
(A)  
V
D
DS  
Tj = 25 °C; VDS = 25 V  
VGS = 0 V; f = 1 MHz  
Fig 11. Forward transconductance as a function of  
drain current; typical values.  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
8 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
03nl84  
03nl82  
100  
5
V
GS  
I
D
(V)  
(A)  
4
75  
V
= 14 V  
V
= 32 V  
DD  
DD  
3
2
1
0
50  
25  
T = 175 C  
T = 25 C  
°
°
j
j
0
0
1
2
3
0
20  
40  
60  
80  
Q
(nC)  
V
(V)  
GS  
G
VDS = 25 V  
Tj = 25 °C; ID = 25 A  
Fig 13. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values.  
Fig 14. Gate-source voltage as a function of gate  
charge; typical values.  
03nl81  
100  
I
S
(A)  
75  
50  
T = 175 C  
°
j
T = 25 C  
°
j
25  
0
0.0  
0.3  
0.6  
0.9  
1.2  
V
(V)  
SD  
VGS = 0 V  
Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
9 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
7. Package outline  
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB  
SOT78  
E
p
A
A
1
q
mounting  
base  
D
1
D
(1)  
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
b
L
max.  
(1)  
2
e
A
b
D
E
L
D
L
1
A
c
UNIT  
p
q
Q
1
1
1
4.5  
4.1  
1.39  
1.27  
0.9  
0.7  
1.3  
1.0  
0.7  
0.4  
15.8  
15.2  
6.4  
5.9  
10.3  
9.7  
15.0  
13.5  
3.30  
2.79  
3.8  
3.6  
3.0  
2.7  
2.6  
2.2  
mm  
3.0  
2.54  
Note  
1. Terminals in this zone are not tinned.  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
SC-46  
00-09-07  
01-02-16  
SOT78  
3-lead TO-220AB  
Fig 16. SOT78 (TO-220AB).  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
10 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
Plastic single-ended package; low-profile 3 lead TO-220AB  
SOT226  
A
A
1
E
D
1
mounting  
base  
D
L
1
L
2
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
2
max  
L
L
D
D
1
A
1
b
c
E
UNIT  
A
b
e
L
Q
1
1
4.5  
4.1  
1.40  
1.27  
0.9  
0.7  
1.3  
1.0  
0.7  
0.4  
9.65  
8.65  
1.5  
1.1  
10.3  
9.7  
15.0  
13.5  
3.30  
2.79  
2.6  
2.2  
mm  
2.54  
3.0  
Note  
1. Terminals in this zone are not tinned.  
REFERENCES  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
JEDEC  
EIAJ  
low-profile  
3-lead TO-220AB  
99-05-27  
99-09-13  
SOT226  
Fig 17. SOT226 (I2-PAK).  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
11 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads  
(one lead cropped)  
SOT404  
A
A
E
1
mounting  
base  
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
D
E
A
A
b
UNIT  
c
D
e
L
H
Q
1
1
p
D
max.  
4.50  
4.10  
1.40  
1.27  
0.85  
0.60  
0.64  
0.46  
1.60  
1.20  
10.30  
9.70  
2.90 15.80 2.60  
2.10 14.80 2.20  
mm  
11  
2.54  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
99-06-25  
01-02-12  
SOT404  
Fig 18. SOT404 (D2-PAK).  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
12 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
8. Soldering  
10.85  
10.60  
10.50  
1.50  
7.50  
7.40  
1.70  
2.15  
1.50  
2.25  
8.275  
8.35  
8.15  
4.60  
0.30  
4.85  
5.40  
7.95  
8.075  
3.00  
0.20  
1.20  
1.30  
1.55  
solder lands  
solder resist  
occupied area  
solder paste  
5.08  
MSD057  
Dimensions in mm.  
Fig 19. Reflow soldering footprint for SOT404.  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
13 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
9. Revision history  
Table 6:  
Revision history  
CPCN  
Rev Date  
Description  
02 20031013  
-
Product data (9397 750 12051)  
Modifications:  
• Addition of BUK9E4R4-40B part to data sheet.  
01 20030402  
-
Product data (9397 750 11134)  
9397 750 12051  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 02 — 13 October 2003  
14 of 16  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
10. Data sheet status  
Level Data sheet status[1]  
Product status[2][3]  
Definition  
I
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips  
Semiconductors reserves the right to change the specification in any manner without notice.  
II  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification. Supplementary data will be published  
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in  
order to improve the design and supply the best possible product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant  
changes will be communicated via a Customer Product/Process Change Notification (CPCN).  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
[3]  
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
11. Definitions  
Short-form specification — The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes in the products - including circuits, standard cells, and/or  
software - described or contained herein in order to improve design and/or  
performance. When the product is in full production (status ‘Production’),  
relevant changes will be communicated via a Customer Product/Process  
Change Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
Limiting values definition — Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Application information — Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
13. Trademarks  
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.  
12. Disclaimers  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
Contact information  
For additional information, please visit http://www.semiconductors.philips.com.  
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
15 of 16  
9397 750 12051  
Product data  
Rev. 02 — 13 October 2003  
BUK95/96/9E4R4-40B  
Philips Semiconductors  
TrenchMOS™ logic level FET  
Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Transient thermal impedance . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 15  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
3
4
5
5.1  
6
7
8
9
10  
11  
12  
13  
© Koninklijke Philips Electronics N.V. 2003.  
Printed in The Netherlands  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 13 October 2003  
Document order number: 9397 750 12051  

相关型号：

BUK9E4R4-80E

 TRANSISTOR 120 A, 80 V, 0.0044 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-262AA, PLASTIC, TO-262, I2PAK-3, FET General Purpose Power
NXP

BUK9E4R4-80E,127

 N-channel TrenchMOS logic level FET TO-262 3-Pin
NXP

BUK9E4R9-60E

 TRANSISTOR 100 A, 60 V, 0.0049 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-262AA, PLASTIC, TO-262, I2PAK-3, FET General Purpose Power
NXP

BUK9E4R9-60E,127

 N-channel TrenchMOS logic level FET TO-262 3-Pin
NXP

BUK9J0R9-40H

 N-channel 40 V, 0.9 mΩ logic level MOSFET in LFPAK56EProduction
NEXPERIA

BUK9K12-60E

 Dual N-channel 60 V, 11.5 mΩ logic level MOSFETProduction
NEXPERIA

BUK9K13-40H

 Dual N-channel 40 V, 13 mOhm logic level MOSFET in LFPAK56DProduction
NEXPERIA

BUK9K13-60E

 Dual N-channel 60 V, 12.5 mΩ logic level MOSFETProduction
NEXPERIA

BUK9K13-60EX

 MOSFET 2N-CH 60V 40A LFPAK56
ETC

BUK9K13-60RA

 Dual N-channel 60 V, 12.5 mOhm logic level MOSFET in LFPAK56D using Repetitive Avalanche technologyProduction
NEXPERIA

BUK9K134-100E

 Dual N-channel 100 V, 159 mΩ logic level MOSFETProduction
NEXPERIA

BUK9K17-60E

 Dual N-channel 60 V, 17 mΩ logic level MOSFETProduction
NEXPERIA
©2020 ICPDF网 联系我们和版权申明