BUK9Y14-40B [NXP]
N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET![BUK9Y14-40B](http://pdffile.icpdf.com/pdf1/p00130/img/icpdf/BUK9Y_715807_icpdf.jpg)
型号: | BUK9Y14-40B |
厂家: | ![]() |
描述: | N-channel TrenchMOS logic level FET |
文件: | 总12页 (文件大小:190K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
BUK9Y14-40B
N-channel TrenchMOS logic level FET
Rev. 03 — 2 June 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using NXP High Performance Automotive (HPA) TrenchMOS technology. This
product has been designed and qualified to the appropriate AEC standard for use in
automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
Q101 compliant
on-state resistance
Suitable for logic level gate drive
Suitable for thermally demanding
environments due to 175 °C rating
sources
1.3 Applications
Air bag
Automotive ABS systems
Diesel injection systems
Motors, lamps and solenoids
Automotive transmission control
Fuel pump and injection
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS
ID
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
-
-
40
56
V
A
VGS = 5 V; Tmb = 25 °C;
see Figure 4 and 1
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
-
-
-
85
-
W
Dynamic characteristics
QGD gate-drain charge
VGS = 5 V; ID = 10 A;
9
nC
VDS = 32 V; see Figure 14
Static characteristics
RDSon drain-source on-state
resistance
VGS = 5 V; ID = 20 A;
Tj = 25 °C; see Figure 12 and
13
-
-
12
-
14
89
mΩ
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
ID = 56 A; Vsup ≤ 40 V;
RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
mJ
avalanche energy
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
Pinning
Symbol Description
Simplified outline
Graphic symbol
1, 2, 3
4
S
G
D
source
gate
D
mb
mb
mounting base;
connected to drain
G
mbb076
S
1
2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
BUK9Y14-40B
LFPAK
SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
40
Unit
V
VDS
VGS
ID
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
gate-source voltage
drain current
15
15
V
Tmb = 25 °C; VGS = 5 V; see Figure 4 and 1
Tmb = 100 °C; VGS = 5 V; see Figure 1
Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4
Tmb = 25 °C; see Figure 2
-
56
A
-
40
A
IDM
Ptot
Tstg
Tj
peak drain current
-
226
85
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
-55
-55
175
175
Avalanche ruggedness
EDS(AL)S non-repetitive
ID = 56 A; Vsup ≤ 40 V; RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
-
-
89
-
mJ
J
drain-source avalanche
energy
[1][2]
[3]
EDS(AL)R repetitive drain-source
avalanche energy
see Figure 3
Source-drain diode
IS
source current
Tmb = 25 °C
-
-
56
A
A
ISM
peak source current
tp ≤ 10 μs; pulsed; Tmb = 25 °C
226
[1] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[2] Repetitive avalanche rating limited by average junction temperature of 170 °C.
[3] Refer to application note AN10273 for further information.
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
2 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03na19
003aab217
120
60
ID
P
der
(A)
(%)
80
40
20
0
40
0
0
50
100
150
200
0
50
100
150
200
T
mb (°C)
T
mb
(°C)
P
tot
V
5V
GS
P
=
× 100 %
der
P
(
)
tot 25°C
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aab220
102
(1)
IAL
(A)
10
(2)
(3)
1
10-1
10-3
10-2
10-1
1
10
tAL (ms)
(1) Singleípulse;T = 25 °C.
j
(2) Singleípulse;T = 150 °C.
j
(3) Repetitive.
Fig 3. Single-shot and repetitive avalanche rating; avalanche current as a function of avalanche period
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
3 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab218
3
10
Limit R
= V / I
DS D
I
D
DSon
(A)
2
10
t
p
= 10 μs
100 μs
10
1 ms
DC
10 ms
1
100 ms
−1
10
2
1
10
10
V
DS
(V)
T
= 25 °C; I
is single pulse
mb
DM
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance
from junction to
mounting base
see Figure 5
-
-
1.8
K/W
03nm01
10
Zth (j-mb)
(K/W)
1
10-1
10-2
δ = 0.5
0.2
0.1
tp
T
P
δ =
0.05
0.02
t
tp
T
single shot
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
4 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 μA; VGS = 0 V;
Tj = 25 °C
40
36
-
-
-
V
ID = 250 μA; VGS = 0 V;
Tj = -55 °C
-
-
V
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS
;
-
2.3
2
V
voltage Tj = -55 °C; see Figure 10
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11 and 10
1.1
0.5
-
1.5
V
ID = 1 mA; VDS = VGS
;
-
-
-
V
Tj = 175 °C; see Figure 10
IDSS
drain leakage current VDS = 40 V; VGS = 0 V;
500
μA
Tj = 175 °C
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
-
-
0.02
2
1
μA
nA
nA
IGSS
gate leakage current VDS = 0 V; VGS = 20 V; Tj = 25 °C
100
100
VDS = 0 V; VGS = -20 V;
2
Tj = 25 °C
RDSon
drain-source on-state VGS = 5 V; ID = 20 A; Tj = 175 °C;
-
-
26
mΩ
resistance
see Figure 12
V
GS = 4.5 V; ID = 20 A; Tj = 25 °C
-
-
-
-
16
11
14
mΩ
mΩ
mΩ
VGS = 10 V; ID = 20 A; Tj = 25 °C
9
VGS = 5 V; ID = 20 A; Tj = 25 °C;
12
see Figure 12 and 13
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
-
0.85
1.2
V
see Figure 16
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/μs;
-
-
50
26
-
-
ns
VGS = 0 V; VDS = 30 V
Qr
recovered charge
nC
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
total gate charge
ID = 10 A; VDS = 32 V; VGS = 5 V;
see Figure 14
-
-
-
-
-
-
21
-
nC
nC
nC
pF
pF
pF
gate-source charge
gate-drain charge
input capacitance
output capacitance
3.7
9
-
-
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
1360
274
147
1800
330
200
Coss
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 30 V; RL = 2.5 Ω;
VGS = 5 V; RG(ext) = 10 Ω
-
-
-
-
15
34
68
42
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
5 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab413
003aab415
160
15
I
D
R
(A)
DSon
15
6
5
(mΩ)
120
12
4
3.8
80
40
0
3.6
3.4
3.2
3
9
6
2.8
2.6
2.4
(V) = 2.2
V
GS
0
2
4
6
8
10
(V)
3
7
11
15
V
DS
V
GS
(V)
T = 25 °C
T = 25 °C; I = 20 A
j D
j
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aab417
003aab416
50
50
I
D
g
(S)
fs
(A)
40
45
30
20
10
0
40
35
30
T = 175 °C
j
T = 25 °C
j
5
10
15
20
25
30
0
1
2
3
4
I
D
(A)
V
GS
(V)
T = 25 °C;V = 25V
V
= 25V
j
DS
DS
Fig 8. Forward transconductance as a function of
drain current; typical values
Fig 9. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
6 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ng53
03ng52
−1
10
2.5
I
V
GS(th)
(V)
D
(A)
−2
10
2.0
1.5
1.0
0.5
0
max
min
typ
max
−3
10
typ
−4
min
10
−5
10
−6
10
0
1
2
3
−60
0
60
120
180
T (°C)
j
V
GS
(V)
T = 25 °C;V = V
I
= 1 mA;V = V
GS
j
DS
GS
D
DS
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
Fig 11. Gate-source threshold voltage as a function of
junction temperature
003aab851
003aab414
2
30
a
V
GS
(V) = 3
3.4
3.8 4
R
DSon
5
(mΩ)
1.5
20
1
0.5
0
10
15
10
0
−60
0
60
120
180
0
30
60
90
120
150
T (°C)
j
I
D
(A)
R
DSon
T = 25 °C
j
a =
R
(
)
DSon 25°C
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 13. Drain-source on-state resistance as a function
of drain current; typical values
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
7 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab412
003aab410
5
2500
V
C
GS
(V)
(pF)
4
2000
1500
1000
500
0
C
iss
V
DS
= 14 V
3
2
1
0
V
DS
= 32 V
C
C
oss
rss
−1
2
0
5
10
15
20
25
(nC)
10
1
10
10
Q
G
V
DS
(V)
T = 25 °C; I = 10 A
V
= 0V; f = 1 MHz
j
D
GS
Fig 14. Gate-source voltage as a function of gate
charge; typical values
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aab411
50
I
S
(A)
40
30
20
10
0
T = 175 °C
j
T = 25 °C
j
0.0
0.2
0.4
0.6
0.8
V
1.0
(V)
SD
V
= 0V
GS
Fig 16. Source current as a function of source-drain voltage; typical values
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
8 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 17. Package outline SOT669 (LFPAK)
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
9 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK9Y14-40B_3
Modifications:
20080602
Product data sheet
BUK9Y14-40B_2
• Table 4 VDS temperature operating range corrected
BUK9Y14-40B_2
BUK9Y14-40B_1
20080523
Product data sheet
-
BUK9Y14-40B_1
-
20070903
Product data sheet
-
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
10 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
11 of 12
BUK9Y14-40B
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits. . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.1
9.2
9.3
9.4
10
11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 June 2008
Document identifier: BUK9Y14-40B_3
相关型号:
©2020 ICPDF网 联系我们和版权申明