BUK9Y19-55BT/R [NXP]
TRANSISTOR,MOSFET,N-CHANNEL,55V V(BR)DSS,46A I(D),SOT-669;
| 型号： | BUK9Y19-55BT/R |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR,MOSFET,N-CHANNEL,55V V(BR)DSS,46A I(D),SOT-669 晶体 晶体管 功率场效应晶体管 开关 脉冲 |
| 文件： | 总12页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
M3D748
Rev. 01 — 28 May 2004
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive (HPA) TrenchMOS™ technology.
1.2 Features
■ Very low on-state resistance
■ 175 °C rated
■ Q101 compliant
■ Logic level compatible.
1.3 Applications
■ Automotive systems
■ 12 V and 24 V loads
■ Motors, lamps and solenoids
■ General purpose power switching.
1.4 Quick reference data
■ EDS(AL)S ≤ 91 mJ
■ ID ≤ 40 A
■ RDSon = 16.3 mΩ (typ)
■ Ptot ≤ 75 W.
2. Pinning information
Table 1:
Pin
Pinning - SOT669 (LFPAK) simplified outline and symbol
Description
source (s)
gate (g)
Simplified outline
Symbol
1,2,3
4
mb
d
mb
mounting base,
connected to
drain (d)
g
MBL798
s1 s2 s3
1
2
3
4
Top view
MBL286
SOT669 (LFPAK)
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
BUK9Y19-55B
LFPAK
Plastic single-ended surface mounted package (Philips version LFPAK); 4 SOT669
leads
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
55
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
-
-
-
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
RGS = 20 kΩ
55
V
±15
40
V
Tmb = 25 °C; VGS = 5 V;
A
Figure 2 and 3
T
mb = 100 °C; VGS = 5 V; Figure 2
-
-
28
A
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
160
Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
Tmb = 25 °C; Figure 1
-
75
W
−55
−55
+175
+175
°C
°C
Source-drain diode
IDR
reverse drain current (DC)
peak reverse drain current
Tmb = 25 °C
-
-
40
A
A
IDRM
Tmb = 25 °C; pulsed; tp ≤ 10 µs
160
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 40 A;
-
-
91
mJ
-
energy
VDS ≤ 55 V; VGS = 5 V; RGS = 50 Ω;
starting Tmb = 25 °C
[1]
EDS(AL)R repetitive drain-source avalanche
energy
[1] Maximum value not quoted. Repetitive rating defined in Figure 16.
Single-shot avalanche rating limited by Tj(max) of 175 °C.
Repetitive avalanche rating limited by Tj(avg) of 170 °C.
Refer to http://www.semiconductors.philips.com/acrobat/applicationnotes/AN10273_1.pdf for further information.
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
2 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03na19
03nl99
120
50
I
D
P
(A)
der
(%)
40
80
40
0
30
20
10
0
0
50
100
150
200
0
50
100
150
200
T
(°C)
T ( C)
°
mb
mb
VGS ≥ 5 V
Ptot
Pder
=
× 100%
-----------------------
P
°
tot(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Continuous drain current as a function of
mounting base temperature.
03nm00
3
10
I
D
(A)
Limit R
DSon
= V
/ I
D
t = 10 s
µ
p
DS
2
10
100
s
µ
10
1 ms
DC
10 ms
100 ms
1
2
10
1
10
V
(V)
DS
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
3 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
Rth(j-mb) thermal resistance from junction to
mounting base
Figure 4
-
-
2
K/W
5.1 Transient thermal impedance
03nm01
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
-1
10
t
p
0.02
P
δ =
T
t
t
p
single shot
T
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
1
t
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
4 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
6. Characteristics
Table 5:
Tj = 25 °C unless otherwise specified
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown
voltage
Characteristics
Conditions
Min
Typ
Max
Unit
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
55
50
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS
Figure 9
Tj = 25 °C
;
1.1
0.5
-
1.5
2
V
V
V
Tj = 175 °C
Tj = −55 °C
-
-
-
2.3
IDSS
drain-source leakage current VDS = 55 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
-
-
-
0.02
1
µA
µA
nA
-
500
100
IGSS
gate-source leakage current VGS = ±15 V; VDS = 0 V
2
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 20 A;
Figure 7 and 8
Tj = 25 °C
-
-
-
-
16.3
19
mΩ
mΩ
mΩ
mΩ
Tj = 175 °C
-
40
VGS = 4.5 V; ID = 20 A
VGS = 10 V; ID = 20 A
-
21
14.3
17.3
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
VGS = 5 V; VDD = 44 V;
ID = 25 A; Figure 14
-
-
-
-
-
-
-
-
-
-
18
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
5
-
8
-
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
1494
217
86
1992
260
118
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
18
-
-
-
-
180
44
td(off)
tf
turn-off delay time
fall time
134
Source-drain diode
VSD
source-drain (diode forward) IS = 25 A; VGS = 0 V;
-
0.85
1.2
V
voltage
Figure 15
trr
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = −100 A/µs
VGS = −10 V; VDS = 30 V
-
-
52
38
-
-
ns
Qr
nC
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
5 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03np29
03np28
120
30
Label is V
(V)
GS
R
(mΩ)
10
6
DSon
I
D
(A)
5
4.6
25
4.4
4.2
4
80
20
15
10
3.8
3.6
3.4
40
3.2
3
2.8
2.6
0
0
2
4
6
8
10
(V)
3
7
11
15
V
(V)
GS
V
DS
Tj = 25 °C; tp = 300 µs
Tj = 25 °C; ID = 20 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
03nb25
03np30
2.4
50
R
(mΩ)
DSon
a
3.2 3.4 3.6 3.8
4
5
10
40
30
20
10
0
1.6
0.8
Label is V
(V)
GS
0
-60
0
60
120
180
T (°C)
0
40
80
I
120
j
(A)
D
Tj = 25 °C
RDSon
a =
----------------------------
RDSon(25 C)
°
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
6 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03ng52
03ng53
-1
2.5
10
V
I
GS(th)
(V)
D
(A)
max
-2
2.0
1.5
1.0
0.5
0.0
10
min
typ
max
-3
typ
10
min
-4
-5
-6
10
10
10
-60
0
60
120
180
0
0.5
1
1.5
2
2.5
3
(V)
T (°C)
j
V
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03np15
03np31
40
2500
C
(pF)
g
(S)
fs
C
iss
1875
30
C
C
oss
1250
625
0
20
10
rss
-1
2
10
0
10
20
30
10
1
10
I
(A)
D
V
(V)
DS
Tj = 25 °C; VDS = 25 V
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
7 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03np27
03np14
60
5
V
(V)
GS
I
D
V
= 14 V
DD
(A)
4
3
2
1
0
V
= 44 V
DD
40
T = 175 C
°
j
20
T = 25 C
°
j
0
0
1
2
3
4
0
5
10
15
20
V
(V)
Q
(nC)
GS
G
VDS = 25 V
Tj = 25 °C; ID = 25 A
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Fig 14. Gate-source voltage as a function of gate
charge; typical values.
03np79
03np13
2
100
10
I
S
I
(A)
Single-shot
AV
(A)
T = 25 C
°
j
75
T = 175 C
°
j
50
25
0
10
Single-shot
T = 25 C
°
j
T = 150 C
°
j
Repetitive
1
-3
-2
10
-1
0.0
0.3
0.6
0.9
1.2
10
10
1
10
V
(V)
t
(ms)
AV
SD
VGS = 0 V
See Table note [1] to Table 3 “Limiting values”
Fig 15. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 16. Single-shot and repetitive avalanche rating;
avalanche current as a function of avalanche
period.
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
8 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
7. Package outline
Plastic single-ended surface mounted package (Philips version LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
b
b
2
1
2
L
3
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-02-05
03-09-15
SOT669
MO-235
Fig 17. SOT669 (LFPAK).
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
9 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
8. Revision history
Table 6:
Revision history
CPCN
Rev Date
Description
01 20040528
-
Product data (9397 750 13188)
9397 750 13188
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 28 May 2004
10 of 12
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
9. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 12
9397 750 13188
Product data
Rev. 01 — 28 May 2004
BUK9Y19-55B
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
4
5
5.1
6
7
8
9
10
11
12
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 28 May 2004
Document order number: 9397 750 13188
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