BUK9Y40-55B,115 [NXP]
N-channel TrenchMOS logic level FET SOIC 4-Pin;型号: | BUK9Y40-55B,115 |
厂家: | NXP |
描述: | N-channel TrenchMOS logic level FET SOIC 4-Pin 开关 脉冲 晶体管 |
文件: | 总12页 (文件大小:178K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BUK9Y40-55B
N-channel TrenchMOS logic level FET
Rev. 03 — 22 February 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using NXP High-Performance Automotive (HPA) TrenchMOS technology. This
product has been designed and qualified to the appropriate AEC standard for use in
automotive critical applications.
1.2 Features
175 °C rated
Logic level compatible
Q101 compliant
Very low on-state resistance
1.3 Applications
12 V and 24 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
ID
drain current
VGS = 5 V; Tmb = 25 °C;
-
-
26
A
see Figure 1 and 4
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
-
-
59
W
Static characteristics
RDSon drain-source on-state
resistance
VGS = 5 V; ID = 15 A;
Tj = 25 °C; see Figure 12 and
13
-
-
34
-
40
36
mΩ
Avalanche ruggedness
EDS(AL)S non-repetitive
ID = 26 A; Vsup ≤ 55 V;
mJ
drain-sourceavalanche RGS = 50 Ω; VGS = 5 V;
energy Tj(init) = 25 °C; unclamped
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning
Pin
1
Symbol Description
Simplified outline
Graphic symbol
S
S
S
G
D
source
source
source
gate
D
mb
2
3
G
4
mbb076
S
mb
mounting base;
1
2 3 4
connected to drain
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
BUK9Y40-55B
LFPAK
SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
55
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
RGS = 20 kΩ
-
drain-gate voltage
gate-source voltage
drain current
-
55
V
-15
15
V
Tmb = 100 °C; VGS = 5 V; see Figure 1
Tmb = 25 °C; VGS = 5 V; see Figure 1 and 4
Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4
Tmb = 25 °C; see Figure 2
-
18
A
-
26
A
IDM
Ptot
Tstg
Tj
peak drain current
-
106
59
A
total power dissipation
storage temperature
junction temperature
-
W
°C
°C
-55
-55
175
175
Avalanche ruggedness
EDS(AL)S non-repetitive
ID = 26 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
-
-
36
-
mJ
J
drain-source avalanche
energy
[1][2]
[3]
EDS(AL)R repetitive drain-source
avalanche energy
see Figure 3
Source-drain diode
IS
source current
Tmb = 25 °C
-
-
26
A
A
ISM
peak source current
tp ≤ 10 μs; pulsed; Tmb = 25 °C
106
[1] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[2] Repetitive avalanche rating limited by average junction temperature of 170 °C.
[3] Refer to application note AN10273 for further information.
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
2 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03na19
03nn93
120
30
ID
P
der
(%)
(A)
80
20
10
0
40
0
0
50
100
150
200
0
50
100
150
200
T
mb (°C)
T
mb
(°C)
P
tot
V
5V
GS
P
=
× 100 %
der
P
(
)
tot 25°C
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
03np80
2
10
I
AV
(A)
(1)
10
(2)
(3)
1
−1
10
−2
10
10
−3
−2
−1
10
10
1
10
t
(ms)
AV
(1) Singleípulse;T = 25 °C.
j
(2) Singleípulse;T = 150 °C.
j
(3) Repetitive.
Fig 3. Single-shot and repetitive avalanche rating; avalanche current as a function of avalanche period
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
3 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03nn94
103
ID
(A)
Limit RDSon = VDS / ID
102
10
tp = 10 μs
100 μs
1 ms
1
10 ms
100 ms
DC
10-1
1
10
102
VDS (V)
T
= 25 °C; I
is single pulse
mb
DM
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance
from junction to
mounting base
see Figure 5
-
-
2.5
K/W
03nn95
10
Zth (j-mb)
(K/W)
δ = 0.5
1
10-1
10-2
0.2
0.1
tp
T
P
δ =
0.05
0.02
single shot
t
tp
T
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
4 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 0.25 mA; VGS = 0 V;
Tj = 25 °C
55
50
0.5
1.1
-
-
-
V
V
V
V
V
ID = 0.25 mA; VGS = 0 V;
Tj = -55 °C
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS
;
-
-
voltage Tj = 175 °C; see Figure 11
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11
1.5
-
2
ID = 1 mA; VDS = VGS
;
2.3
Tj = -55 °C; see Figure 11
IDSS
drain leakage current VDS = 55 V; VGS = 0 V; Tj = 25 °C
-
-
0.02
-
1
μA
μA
VDS = 55 V; VGS = 0 V;
500
Tj = 175 °C
IGSS
gate leakage current VDS = 0 V; VGS = 15 V; Tj = 25 °C
-
-
2
2
100
100
nA
nA
VDS = 0 V; VGS = -15 V;
Tj = 25 °C
RDSon
drain-source on-state VGS = 5 V; ID = 15 A; Tj = 175 °C;
-
-
84
mΩ
resistance
see Figure 12 and 13
V
GS = 10 V; ID = 15 A; Tj = 25 °C
-
-
-
32
-
36
45
40
mΩ
mΩ
mΩ
VGS = 4.5 V; ID = 15 A; Tj = 25 °C
VGS = 5 V; ID = 15 A; Tj = 25 °C;
34
see Figure 12 and 13
Source-drain diode
VSD
source-drain voltage
IS = 20 A; VGS = 0 V; Tj = 25 °C;
-
0.85
1.2
V
see Figure 16
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/μs;
-
-
45
25
-
-
ns
VGS = -10 V; VDS = 30 V;
Qr
recovered charge
nC
Tj = 25 °C
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
total gate charge
ID = 15 A; VDS = 44 V; VGS = 5 V;
Tj = 25 °C; see Figure 14
-
-
-
-
-
-
11
2
-
nC
nC
nC
pF
pF
pF
gate-source charge
gate-drain charge
input capacitance
output capacitance
-
5
-
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
765
123
71
1020
148
97
Coss
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 30 V; RL = 2.2 Ω;
VGS = 5 V; RG(ext) = 10 Ω;
Tj = 25 °C
-
-
-
-
17
93
35
72
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
5 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03np10
03np09
60
50
V
GS
(V) = 10
6.0
5.0
I
R
DSon
(mΩ)
D
(A)
4.4
4.2
4.0
3.8
40
40
3.6
3.4
3.2
3.0
20
30
20
2.8
2.6
0
0
2
4
6
8
10
(V)
0
5
10
15
V
DS
V
GS
(V)
T = 25 °C; t = 300 ȝs
T = 25 °C; I = 15 A
j D
j
p
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
03ng53
03np07
−1
10
30
I
D
g
(S)
fs
(A)
−2
−3
−4
−5
−6
10
25
min
typ
max
10
10
10
10
20
15
10
0
1
2
3
0
4
8
12
16
V
GS
(V)
I (A)
D
T = 25 °C;V = V
T = 25 °C;V = 25V
j DS
j
DS
GS
Fig 8. Sub-threshold drain current as a function of
gate-source voltage
Fig 9. Forward transconductance as a function of
drain current; typical values
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
6 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03np08
03ng52
20
2.5
V
GS(th)
(V)
I
D
(A)
2.0
1.5
1.0
0.5
0
max
15
typ
10
5
min
T = 175 °C
T = 25 °C
j
j
0
0
1
2
3
4
−60
0
60
120
180
T (°C)
j
V
(V)
GS
V
= 25V
I
= 1 mA;V = V
GS
DS
D
DS
Fig 10. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 11. Gate-source threshold voltage as a function of
junction temperature
03np11
03nb25
90
2.4
3.0 3.2 3.4 3.6 3.8
5.0
R
DSon
a
(mΩ)
60
1.6
V
GS
(V) = 10
30
0.8
0
0
−60
0
20
40
60
0
60
120
180
T (°C)
j
I
D
(A)
R
DSon
T = 25 °C
j
a =
R
(
)
DSon 25°C
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
7 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03np06
03np12
5
1400
V
(V)
GS
C
(pF)
V
DS
= 14 V
4
3
2
1
0
V
= 44 V
1050
700
350
0
DS
C
iss
C
oss
C
rss
−1
2
0
5
10
15
10
1
10
10
Q
G
(nC)
V
DS
(V)
T = 25 °C; I = 15 A
V
= 0V; f = 1 MHz
j
D
GS
Fig 14. Gate-source voltage as a function of gate
charge; typical values
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
03np05
80
I
S
(A)
60
40
20
0
T = 175 °C
j
T = 25 °C
j
0
0.5
1.0
1.5
V
(V)
SD
V
= 0V
GS
Fig 16. Source current as a function of source-drain voltage; typical values
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
8 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 17. Package outline SOT669 (LFPAK)
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
9 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
BUK9Y40-55B_3
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20080222
Product data sheet
-
BUK9Y40-55B_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
BUK9Y40-55B_2
BUK9Y40_55B-01
20060411
Product data sheet
-
BUK9Y40_55B-01
20040528
Product data sheet
-
-
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
10 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
BUK9Y40-55B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 22 February 2008
11 of 12
BUK9Y40-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.1
9.2
9.3
9.4
10
11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 February 2008
Document identifier: BUK9Y40-55B_3
相关型号:
©2020 ICPDF网 联系我们和版权申明