BUK9Y53-100B [NXP]

N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET
BUK9Y53-100B
型号: BUK9Y53-100B
厂家: NXP    NXP
描述:

N-channel TrenchMOS logic level FET
N沟道的TrenchMOS逻辑电平FET

文件: 总12页 (文件大小:90K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
BUK9Y53-100B  
N-channel TrenchMOS logic level FET  
Rev. 01 — 30 August 2007  
Product data sheet  
1. Product profile  
1.1 General description  
N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package  
using NXP High-Performance Automotive (HPA) TrenchMOS technology.  
1.2 Features  
I Very low on-state resistance  
I Q101 compliant  
I 175 °C rated  
I Logic level compatible  
1.3 Applications  
I Automotive systems  
I General purpose power switching  
I 12 V, 24 V and 42 V loads  
I Motors, lamps and solenoids  
1.4 Quick reference data  
I EDS(AL)S 85 mJ  
I ID 23 A  
I RDSon = 45 m(typ)  
I Ptot 75 W  
2. Pinning information  
Table 1.  
Pin  
Pinning  
Description  
Simplified outline  
Symbol  
1, 2, 3 source (S)  
D
mb  
4
gate (G)  
mb  
mounting base; connected to drain (D)  
G
1
2 3 4  
mbl798  
S1 S2 S3  
SOT669 (LFPAK)  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
3. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
plastic single-ended surface-mounted package (LFPAK); 4 leads  
Version  
BUK9Y53-100B  
LFPAK  
SOT669  
4. Limiting values  
Table 3.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min Max Unit  
VDS  
VDGR  
VGS  
ID  
drain-source voltage  
-
-
-
-
-
-
-
100  
100  
±15  
23  
V
V
V
A
A
A
W
drain-gate voltage (DC)  
gate-source voltage  
drain current  
RGS = 20 kΩ  
Tmb = 25 °C; VGS = 5 V; see Figure 2 and 3  
Tmb = 100 °C; VGS = 5 V; see Figure 2  
Tmb = 25 °C; pulsed; tp 10 µs; see Figure 3  
Tmb = 25 °C; see Figure 1  
16  
IDM  
Ptot  
Tstg  
Tj  
peak drain current  
94  
total power dissipation  
storage temperature  
junction temperature  
75  
55 +175 °C  
55 +175 °C  
Source-drain diode  
IDR  
reverse drain current  
peak reverse drain current  
Tmb = 25 °C  
-
-
23  
94  
A
A
IDRM  
Tmb = 25 °C; pulsed; tp 10 µs  
Avalanche ruggedness  
EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 23 A;  
-
-
85  
mJ  
-
energy  
VDS 100 V; VGS = 5 V; RGS = 50 Ω; starting at  
Tj = 25 °C  
[1]  
EDS(AL)R repetitive drain-source avalanche  
energy  
[1] Conditions:  
a) Maximum value not quoted. Repetitive rating defined in Figure 16.  
b) Single-pulse avalanche rating limited by Tj(max) of 175 °C.  
c) Repetitive avalanche rating limited by Tj(avg) of 170 °C.  
d) Refer to application note AN10273 for further information.  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
2 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aab844  
003aab225  
120  
30  
P
I
D
der  
(%)  
(A)  
80  
20  
40  
10  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
(°C)  
T
(°C)  
mb  
mb  
VGS 5 V  
Ptot  
Pder  
=
× 100 %  
-----------------------  
Ptot(25°C)  
Fig 1. Normalized total power dissipation as a  
function of mounting base temperature  
Fig 2. Continuous drain current as a function of  
mounting base temperature  
003aab226  
3
10  
I
D
(A)  
Limit R  
= V / I  
DS D  
DSon  
2
10  
t
= 10 µs  
p
100 µs  
10  
DC  
1
1 ms  
10 ms  
100 ms  
1  
10  
2
3
1
10  
10  
10  
V
(V)  
DS  
Tmb = 25 °C; IDM is single pulse.  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
3 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
5. Thermal characteristics  
Table 4:  
Symbol  
Rth(j-mb)  
Thermal characteristics  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
2 K/W  
thermal resistance from junction to mounting base see Figure 4  
-
-
003aab219  
1
Z
th(jmb)  
(K/W)  
δ = 0.5  
1
0.2  
0.1  
t
p
0.05  
P
δ =  
−1  
10  
T
0.02  
t
t
p
single pulse  
T
2  
10  
6  
5  
4  
3  
2  
1  
10  
10  
10  
10  
10  
10  
1
t
(s)  
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
4 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
6. Characteristics  
Table 5:  
Characteristics  
Tj = 25 °C unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
Static characteristics  
V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V  
Tj = 25 °C  
100  
89  
-
-
-
-
V
V
Tj = 55 °C  
VGS(th)  
gate-source threshold voltage  
ID = 1 mA; VDS = VGS; see Figure 9 and 10  
Tj = 25 °C  
1.1  
0.5  
-
1.5  
2
V
V
V
Tj = 175 °C  
-
-
-
Tj = 55 °C  
2.3  
IDSS  
drain leakage current  
gate leakage current  
VDS = 100 V; VGS = 0 V  
Tj = 25 °C  
-
-
-
0.02  
1
µA  
µA  
nA  
Tj = 175 °C  
-
500  
100  
IGSS  
VGS = ±15 V; VDS = 0 V  
2
RDSon  
drain-source on-state resistance VGS = 5 V; ID = 10 A; see Figure 6 and 8  
Tj = 25 °C  
-
-
-
-
45  
-
53  
mΩ  
mΩ  
mΩ  
mΩ  
Tj = 175 °C  
132  
59  
VGS = 4.5 V; ID = 10 A  
VGS = 10 V; ID = 10 A  
-
41  
49  
Dynamic characteristics  
QG(tot)  
QGS  
QGD  
Ciss  
Coss  
Crss  
td(on)  
tr  
total gate charge  
gate-source charge  
gate-drain charge  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
ID = 15 A; VDS = 80 V; VGS = 5 V;  
see Figure 14  
-
-
-
-
-
-
-
-
-
-
18  
4.1  
8
-
-
-
nC  
nC  
nC  
VGS = 0 V; VDS = 25 V; f = 1 MHz;  
see Figure 12  
1600 2130 pF  
141  
60  
18  
26  
52  
16  
170  
pF  
pF  
ns  
ns  
ns  
ns  
82  
-
VDS = 30 V; RL = 2.5 ;  
VGS = 5 V; RG = 10 Ω  
-
td(off)  
tf  
turn-off delay time  
fall time  
-
-
Source-drain diode  
VSD  
trr  
source-drain voltage  
IS = 25 A; VGS = 0 V; see Figure 15  
-
-
-
0.85 1.2  
V
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = 100 A/µs;  
71  
83  
-
-
ns  
nC  
VGS = 0 V; VR = 30 V  
Qr  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
5 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aab421  
003aab423  
60  
56  
V
(V) = 15  
GS  
5
4
R
DSon  
(m)  
I
D
(A)  
3.4  
52  
40  
3.2  
3
48  
44  
40  
20  
2.8  
2.6  
2.4  
2.2  
0
0
2
4
6
8
10  
(V)  
3
6
9
12  
15  
V
V
(V)  
DS  
GS  
Tj = 25 °C  
Tj = 25 °C; ID = 20 A  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values  
Fig 6. Drain-source on-state resistance as a function  
of gate-source voltage; typical values  
03aa29  
003aab422  
3
100  
R
(m)  
3.8  
4
5
DSon  
a
V
(V) = 3  
3.4  
GS  
15  
80  
2
60  
40  
20  
1
0
-60  
0
60  
120  
180  
0
10  
20  
30  
40  
50  
T ( C)  
°
j
I
(A)  
D
Tj = 25 °C  
RDSon  
a =  
-----------------------------  
RDSon(25°C )  
Fig 7. Drain-source on-state resistance as a function  
of drain current; typical values  
Fig 8. Normalized drain-source on-state resistance  
factor as a function of junction temperature  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
6 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aab986  
003aab987  
1  
2  
3  
4  
5  
6  
2.5  
10  
I
V
D
GS(th)  
(V)  
(A)  
2.0  
10  
10  
10  
10  
10  
max  
min  
typ  
max  
1.5  
1.0  
0.5  
0.0  
typ  
min  
60  
0
60  
120  
180  
0
1
2
3
T (°C)  
V
(V)  
j
GS  
ID = 1 mA; VDS = VGS  
Tj = 25 °C; VDS = VGS  
Fig 9. Gate-source threshold voltage as a function of  
junction temperature  
Fig 10. Sub-threshold drain current as a function of  
gate-source voltage  
003aab418  
003aab425  
2500  
50  
C
(pF)  
g
fs  
(S)  
2000  
C
iss  
40  
15000  
1000  
500  
0
30  
20  
C
oss  
C
rss  
1  
2
10  
1
10  
10  
5
10  
15  
20  
25  
30  
V
(V)  
I
(A)  
DS  
D
Tj = 25 °C; VDS = 25 V  
VGS = 0 V; f = 1 MHz  
Fig 11. Forward transconductance as a function of  
drain current; typical values  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
7 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aab424  
003aab420  
50  
5
4
3
2
1
0
I
D
V
GS  
(V)  
(A)  
40  
V
= 14 V  
DS  
V
= 80 V  
DS  
30  
20  
10  
0
T = 175 °C  
T = 25 °C  
j
j
0
1
2
3
4
0
5
10  
15  
20  
V
(V)  
GS  
Q (nC)  
G
VDS = 25 V  
Tj = 25 °C; ID = 10 A  
Fig 13. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values  
Fig 14. Gate-source voltage as a function of gate  
charge; typical values  
003aab419  
003aab224  
2
50  
10  
I
S
(A)  
40  
I
AL  
(1)  
(2)  
(A)  
30  
20  
10  
0
10  
T = 175 °C  
j
T = 25 °C  
j
(3)  
1
10  
3  
2  
1  
0.0  
0.2  
0.4  
0.6  
0.8  
V
1.0  
(V)  
10  
10  
1
10  
t
(ms)  
AL  
SD  
VGS = 0 V  
See Table note 1 of Table 3 Limiting values.  
(1) Single-pulse; Tj = 25 °C.  
(2) Single-pulse; Tj = 150 °C.  
(3) Repetitive.  
Fig 15. Source (diode forward) current as a function of  
source-drain (diode forward) voltage; typical  
values  
Fig 16. Single-pulse and repetitive avalanche rating;  
avalanche current as a function of avalanche  
time  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
8 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
7. Package outline  
Plastic single-ended surface-mounted package (LFPAK); 4 leads  
SOT669  
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting  
base  
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e  
A
(A )  
3
C
A
1
θ
L
detail X  
y
C
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
D
(1)  
D
(1)  
(1)  
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT  
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max  
1.20 0.15 1.10  
1.01 0.00 0.95  
0.50 4.41 2.2 0.9 0.25 0.30 4.10  
0.35 3.62 2.0 0.7 0.19 0.24 3.80  
5.0 3.3  
4.8 3.1  
6.2 0.85 1.3 1.3  
5.8 0.40 0.8 0.8  
8°  
0°  
mm  
0.25  
4.20  
1.27  
0.25 0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
04-10-13  
06-03-16  
SOT669  
MO-235  
Fig 17. Package outline SOT669 (LFPAK)  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
9 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
8. Revision history  
Table 6.  
Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
BUK9Y53-100B_01  
20070830  
Product data sheet  
-
-
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
10 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
9. Legal information  
9.1  
Data sheet status  
Document status[1][2]  
Product status[3]  
Definition  
Objective [short] data sheet  
Development  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
result in personal injury, death or severe property or environmental damage.  
NXP Semiconductors accepts no liability for inclusion and/or use of NXP  
Semiconductors products in such equipment or applications and therefore  
9.2  
Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
such inclusion and/or use is at the customer’s own risk.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
9.3  
Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
9.4  
Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of a NXP Semiconductors product can reasonably be expected to  
TrenchMOS — is a trademark of NXP B.V.  
10. Contact information  
For additional information, please visit: http://www.nxp.com  
For sales office addresses, send an email to: salesaddresses@nxp.com  
BUK9Y53-100B_1  
© NXP B.V. 2007. All rights reserved.  
Product data sheet  
Rev. 01 — 30 August 2007  
11 of 12  
BUK9Y53-100B  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
11. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1  
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10  
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
9.1  
9.2  
9.3  
9.4  
10  
11  
Contact information. . . . . . . . . . . . . . . . . . . . . 11  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2007.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 30 August 2007  
Document identifier: BUK9Y53-100B_1  

相关型号:

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