CBTL04DP211BS [NXP]
DisplayPort 2 : 1 multiplexer; DisplayPort的2 ： 1多路复用器
| 型号： | CBTL04DP211BS |
| 厂家： | 
NXP |
| 描述： | DisplayPort 2 : 1 multiplexer |
| 文件： | 总17页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBTL04DP211
DisplayPort 2 : 1 multiplexer
Rev. 1 — 30 March 2011
Product data sheet
1. General description
CBTL04DP211 is an (Embedded) DisplayPort multiplexer for DisplayPort v1.1a switching
and multiplexing applications on PC platforms. It is capable of 1 : 2 switching or
2 : 1 multiplexing of 2-lane DisplayPort Main Link signals, using high-bandwidth pass-gate
technology. Also, it can switch/multiplex Hot Plug Detect (HPD) signal and AUX signals,
for a total of four channels on the display side.
To facilitate DisplayPort switching/multiplexing scheme on PC platforms suitably,
CBTL04DP211 provides two separate selection pins (GPU_SEL, AUX_SEL). The
selection pin GPU_SEL performs switching from one Main Link to another Main Link. HPD
signals will also be switched using the same selection pin. A separate select pin
(AUX_SEL) provides additional selection between two AUX channels such that the AUX
channel selection is independent of the Main Link and HPD signal selection.
A typical application of CBTL04DP211 is on motherboards where one of two GPU/CPU
display sources needs to be selected to connect to a DisplayPort sink device or connector.
A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to
the non-directional nature of the signal paths (which use high-bandwidth pass-gate
technology), the CBTL04DP211 can also be used in the reverse topology, e.g., to connect
one DisplayPort source device to one of two DisplayPort sink devices or connectors.
2. Features and benefits
Supports DisplayPort v1.1a: 1.62 Gbit/s, 2.7 Gbit/s
Supports Embedded DisplayPort v1.2: 1.62 Gbit/s, 2.7 Gbit/s
Supports 1-lane, 2-lane Main Link operation
1 : 2 switching or 2 : 1 multiplexing of DisplayPort Main Link signals
2 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
Main Link signals
1 channel with 2 : 1 multiplexing/switching for AUX signals
1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals
High-bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
Very low inter-pair skew (< 180 ps)
Switch/multiplexer position select CMOS input
Single 3.3 V power supply
Very low operation current of 0.2 mA typical
ESD 8 kV HBM, 1 kV CDM
ESD 2 kV HBM, 500 V CDM for control pins
Available in 3 mm 6 mm, 0.4 mm pitch HVQFN32 package
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
3. Applications
Motherboard applications requiring (embedded) DisplayPort switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of DisplayPort I/O pins to board connectors
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
CBTL04DP211BS
HVQFN32
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 3 6 0.85 mm[1]
SOT1185-1
[1] Total height after printed-circuit board mounting = 1 mm (maximum).
5. Marking
Table 2.
Package marking
Marking
04DP211[1]
Line
A
Description
basic type number
diffusion lot number
manufacturing code:
Z = diffusion site
P = assembly site
G = lead-free
B
xxxxxxx
C
ZPGyyww
yy = year code
ww = week code
[1] Industrial temperature range.
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
2 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
6. Functional diagram
IN1_0+
IN1_0-
OUT_0+
OUT_0-
2 : 1
MUX
IN2_0+
IN2_0-
IN1_1+
IN1_1-
OUT_1+
OUT_1-
2 : 1
MUX
IN2_1+
IN2_1-
HPD_1
HPD_2
2 : 1
MUX
HPD_IN
AUX1+
AUX1-
AUX+
AUX-
2 : 1
MUX
AUX2+
AUX2-
AUX_SEL GPU_SEL
002aag018
Fig 1. Functional diagram
CBTL04DP211
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Product data sheet
Rev. 1 — 30 March 2011
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
7. Pinning information
7.1 Pinning
OUT_0+
OUT_0-
1
2
3
4
5
6
7
8
9
27 IN1_1+
26 IN1_1-
25 IN2_0+
24 IN2_0-
23 IN2_1+
22 IN2_1-
21 GND
V
DD
OUT_1+
OUT_1-
AUX+
CBTL04DP211BS
AUX-
HPD_IN
20 V
DD
V
19 AUX1+
18 AUX1-
17 HPD_1
DD
GPU_SEL 10
n.c. 11
002aag019
Transparent top view
Fig 2. Pin configuration for HVQFN32
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Type
Description
Selection for Main Link and Hot Plug Detect
GPU_SEL
10
3.3 V CMOS
single-ended input signals between two multiplexer/switch paths.
When HIGH, path 2 is connected to its
corresponding I/O. When LOW, path 1 is
connected to its corresponding I/O.
AUX_SEL
32
3.3 V CMOS
Selects between AUX paths. When HIGH, AUX2
single-ended input (path 2) input is connected to AUX output. When
LOW, AUX1 (path 1) input is connected to AUX
output.
IN1_0+
IN1_0
IN1_1+
IN1_1
IN2_0+
IN2_0
IN2_1+
IN2_1
31
30
27
26
25
24
23
22
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals, path 1.
Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals, path 2.
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
4 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
Table 3.
Pin description …continued
Symbol
OUT_0+
OUT_0
OUT_1+
OUT_1
AUX1+
AUX1
AUX2+
AUX2
AUX+
Pin
1
Type
Description
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
single-ended I/O
single-ended I/O
Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals.
2
4
5
19
18
15
14
6
High-speed differential pair for AUX signals,
path 1.
High-speed differential pair for AUX signals,
path 2.
High-speed differential pair for AUX signals.
AUX
7
HPD_1
HPD_2
HPD_IN
VDD
17
13
8
Single-ended channel for the HPD signal, path 1.
Single-ended channel for the HPD signal, path 2.
Single-ended channel for the HPD signal.
3.3 V power supply.
3, 9, 12, 16, power supply
20, 29
GND[1]
n.c.
21, 28,
center pad
ground
Ground.
11
-
Not connected. This pin is not connected to any
signal internally.
[1] HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
5 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
8. Functional description
Refer to Figure 1 “Functional diagram”.
The CBTL04DP211 uses a 3.3 V power supply. All Main Link signal paths are
implemented using high-bandwidth pass-gate technology and are non-directional. No
clock or reset signal is needed for the multiplexer to function.
The switch position for the main link differential channels and Hot Plug Detect signals is
selected using the select signal GPU_SEL. Additionally, the signal AUX_SEL selects
between two AUX positions. The detailed operation is described in Section 8.1
“Multiplexer/switch select functions”.
8.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
AUX_SEL as described below.
Table 4.
Multiplexer/switch select control for IN and OUT channels
GPU_SEL
IN1_n
IN2_n
0
1
active; connected to OUT_n
high-impedance
high-impedance
active; connected to OUT_n
Table 5.
Multiplexer/switch select control for HPD channel
GPU_SEL
HPD_1
HPD_2
0
1
active; connected to HPD_IN
high-impedance
high-impedance
active; connected to HPD_IN
Table 6.
Multiplexer/switch select control for AUX channels
AUX_SEL
AUX1
AUX2
0
1
active; connected to AUX
high-impedance
high-impedance
active; connected to AUX
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Min
Max
+5
Unit
V
VDD
supply voltage
0.3
Tcase
VESD
case temperature
40
+85
C
V
[1]
[1]
[2]
[2]
electrostatic discharge HBM
voltage
-
-
-
8000
2000
1000
500
HBM; CMOS inputs
V
CDM
V
CDM; CMOS inputs
V
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol Parameter
Conditions
Min
3.0
Typ
Max
Unit
V
VDD
VI
supply voltage
input voltage
3.3
3.6
CMOS inputs
Main Link
HPD inputs
AUX
0.3
0.3
0.3
0.3
40
-
-
-
-
-
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
+85
V
V
[1]
[2]
V
V
Tamb
ambient temperature operating in free air
C
[1] HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is
placed in series. See Section 12.1 “Special considerations”.
[2] AUX input is tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and the pin
is placed in series. See Section 12.1 “Special considerations”.
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
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CBTL04DP211
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DisplayPort 2 : 1 multiplexer
11. Characteristics
11.1 General characteristics
Table 9.
General characteristics
Symbol Parameter
Conditions
VDD = 3.3 V
VDD = 3.3 V
Min
Typ
Max
500
4
Unit
A
IDD
supply current
power consumption
start-up time
-
-
-
200
Pcons
tstartup
-
-
mW
s
supply voltage valid to channel specified
operating characteristics
10
trcfg
reconfiguration time
GPU_SEL or AUX_SEL state change to
channel specified operating characteristics
-
-
1
s
11.2 DisplayPort Main Link channel characteristics
Table 10. DisplayPort Main Link channel characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
VI
input voltage
0.3
-
+3.3
VIC
VID
DDIL
common-mode input voltage
differential input voltage
differential insertion loss
0
-
-
2.0
V
peak-to-peak
-
+1.2
V
channel is on; f = 100 MHz
channel is on; f = 1.5 GHz
channel is off; 0 Hz f 1.5 GHz
channel is on; 0 Hz f 1.5 GHz
-
1.6
2.7
35
10
40
-
-
-
-
-
dB
dB
dB
dB
dB
-
-
DDRL
differential return loss
-
DDNEXT differential near-end crosstalk adjacent channels are on;
-
0 Hz f 1.5 GHz
B
bandwidth
3.0 dB intercept
-
-
2.0
-
-
GHz
ps
tPD
propagation delay
from INx_n+/INx_n port to
100
OUT_n+/OUT_n port or vice versa
tsk(dif)
tsk
differential skew time
skew time
intra-pair
inter-pair
-
-
5
-
-
ps
ps
180
CBTL04DP211
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Product data sheet
Rev. 1 — 30 March 2011
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
11.3 AUX ports
Table 11. AUX port characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
VI
input voltage
0.3
-
VDD + 0.3
VO
output voltage
bias voltage
50 load
-
0
-
-
VDD + 0.3
V
Vbias
Ron
AUX
-
VDD
V
ON-state resistance
Vbias 2.0 V
2.0 V < Vbias < VDD
peak-to-peak
15
30
-
-
-
-
VID
tPD
differential input voltage
propagation delay
-
+1.4
-
V
[1]
from AUXn port to AUX port or
vice versa
-
100
ps
[1] Time from AUX input changing state to AUX output changing state. Includes AUX rise/fall time.
11.4 HPD_IN input, HPD_x outputs
Table 12. HPD input and output characteristics
Symbol
VI
Parameter
Conditions
Min
Typ
Max
Unit
V
input voltage
output voltage
propagation delay
0.3
-
VDD + 0.3
VDD + 0.3
-
VO
-
-
-
V
[1]
tPD
from HPD_IN to HPD_x or vice versa
100
ps
[1] Time from HPD_IN changing state to HPD_x changing state. Includes HPD rise/fall time.
11.5 GPU_SEL and AUX_SEL inputs
Table 13. GPU_SEL and AUX_SEL input characteristics
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
-
Unit
V
HIGH-level input voltage
LOW-level input voltage
input leakage current
2.0
-
-
-
VIL
-
-
0.8
10
V
ILI
VDD = 3.6 V; 0.3 V VI 3.9 V
A
CBTL04DP211
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Product data sheet
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
12. Application information
12.1 Special considerations
Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to
occur on pins AUX+ and AUX, as well as HPD_IN. When AUX+ and AUX are
connected through a minimum of 2.2 k each, the CBTL04DP211 will sink current but will
not be damaged. Similarly, HPD_IN may be connected to 5 V via at least a 1 k resistor.
(Correct functional operation to specification is not expected in these scenarios.) The
latter also prevents the HPD_OUT output from loading down the system HPD signal when
power to the CBTL04DP211 is off.
GPU A
CBTL04DP211
OUT_0+
OUT_0-
MUX
2 : 1
OUT_1+
OUT_1-
MUX
2 : 1
HPD_IN
2 : 1
MUX
GND
100 kΩ
AUX+
AUX-
2 : 1
MUX
100 kΩ
V
DD
GPU B
002aag022
Fig 3. Application diagram
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
13. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; 3 x 6 x 0.85 mm
SOT1185-1
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
e
C
v
C
A
B
b
y
C
1
y
w
C
12
16
L
11
17
27
E
e
E
h
e
2
1
terminal 1
index area
32
28
X
D
h
0
2.5
5 mm
v
scale
Dimensions
Unit
(1)
(1)
(1)
A
A
b
c
D
D
E
e
e
1
e
2
L
w
y
y
1
1
h
h
max 1.00 0.05 0.25
mm nom 0.85 0.02 0.20 0.2 3.0 1.8 6.0 4.8 0.4 1.6
min 0.80 0.00 0.15 2.9 1.7 5.9 4.7
3.1 1.9 6.1 4.9
0.4
4
0.3 0.07 0.05 0.08 0.1
0.2
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1185-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
10-07-26
10-08-09
SOT1185-1
Fig 4. Package outline SOT1185-1 (HVQFN32)
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
11 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 15. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 5.
CBTL04DP211
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Product data sheet
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CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 16. Abbreviations
Acronym
AUX
Description
Auxiliary channel (in DisplayPort definition)
Charged-Device Model
Complementary Metal-Oxide Semiconductor
Central Processing Unit
ElectroStatic Discharge
Graphics Processor Unit
Human Body Model
CDM
CMOS
CPU
ESD
GPU
HBM
HPD
I/O
Hot Plug Detect
Input/Output
PC
Personal Computer
16. Revision history
Table 17. Revision history
Document ID
Release date
20110330
Data sheet status
Change notice
Supersedes
CBTL04DP211 v.1
Product data sheet
-
-
CBTL04DP211
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
14 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
CBTL04DP211
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
15 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL04DP211
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 30 March 2011
16 of 17
CBTL04DP211
NXP Semiconductors
DisplayPort 2 : 1 multiplexer
19. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
9
Functional description . . . . . . . . . . . . . . . . . . . 6
Multiplexer/switch select functions . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
10
11
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
General characteristics. . . . . . . . . . . . . . . . . . . 8
DisplayPort Main Link channel characteristics . 8
AUX ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
HPD_IN input, HPD_x outputs . . . . . . . . . . . . . 9
GPU_SEL and AUX_SEL inputs . . . . . . . . . . . 9
11.1
11.2
11.3
11.4
11.5
12
12.1
13
Application information. . . . . . . . . . . . . . . . . . 10
Special considerations . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
14
Soldering of SMD packages . . . . . . . . . . . . . . 12
Introduction to soldering . . . . . . . . . . . . . . . . . 12
Wave and reflow soldering . . . . . . . . . . . . . . . 12
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 12
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 13
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 March 2011
Document identifier: CBTL04DP211
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