CBTL05024BS [NXP]
DIFFERENTIAL MULTIPLEXER;
| 型号： | CBTL05024BS |
| 厂家： | 
NXP |
| 描述： | DIFFERENTIAL MULTIPLEXER |
| 文件： | 总3页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBTL05024
Multiplexer/de-multiplexer switch chip
Rev. 1 — 1 August 2012
Product brief
1. General description
The CBTL05024 is a custom multiplexer/demultiplexer switch chip optimized to interface
the Thunderbolt/MiniDP connector for Thunderbolt systems. It supports 10.3125 Gbit/s
Thunderbolt or DisplayPort v1.2 channels.
The TB MUX is a 3 : 1 switch that selects between Thunderbolt data path and
DisplayPort v1.2 control signals — either DDC or AUX.
The DP MUX is a 2 : 1 switch that selects between DP ML (DisplayPort Main Link) and
LS TX/RX signals. Both LSTX and LSRX are the control signals for Thunderbolt channel.
This chip also includes HPDOUT and CA_DETOUT buffers for HPD_IN and CA_DET
control signals.
CBTL05024 is powered by a 3.3 V supply and it is available in a 3 mm × 3 mm HVQFN24
package with 0.4 mm pitch.
2. Features and benefits
The input of the HPDOUT (Hug Plug Detect) buffer must be 5 V tolerant
HPDOUT and CA_DETOUT buffers
CA_DET input leakage current < 0.1 μA to prevent driving the 1 MΩ pull-down to a
HIGH level
Integrated LSRX buffer with 1 MΩ pull-down resistor (R1) on the LSRX buffer input to
improve signal integrity
Integrated 8.75 kΩ pull-up resistor (R4) on the LSTX pin
When AUXIO_EN = 1, TB_ENA = 0 and DP_PD = 1, the CBTL05024 is in
Detect mode
AUXIO+ and AUXIO− of the TB MUX are disabled
LS path is selected in DP MUX
CA_DETOUT and HPDOUT buffers are on
When the CBTL05024 is in Detect mode, this chip will consume < 1 mW
Patent-pending high bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
Back current protection on connector pins (AUXIO+/−, DPMLO+/−, CA_DET and HPD
pins)
All channels support rail-to-rail input voltage
All CMOS input buffer with hysteresis
Single 3.3 V 10 % power supply
CBTL05024
NXP Semiconductors
Multiplexer/de-multiplexer switch chip
HVQFN24 3 mm × 3 mm package, 0.4 mm pitch, exposed center pad for thermal relief
and electrical ground
ESD: 1500 V HBM, 500 V CDM
Operating temperature range −20 °C to 85 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
CBTL05024BS
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3 × 3 × 0.85 mm[1]
SOT905-1
[1] Maximum package height is 1 mm.
4. Block diagram
TB_ENA
CBTL05024
CONTROL
LOGIC
AUXIO_EN
DP_PD
3.3 V
TB−
TB+
R3
85 kΩ
AUXIO−
AUXIO+
10G
MUX
2 : 1
AUX−
AUX+
AUX
MUX
2 : 1
R2
85 kΩ
DDC_DAT
DDC_CLK
CA_DETOUT
CA_DET
DP+
DP−
3.3 V
DP
MUX
2 : 1
DPMLO+
DPMLO−
R4
8.75 kΩ
LSTX
LSRX
R1
1 MΩ
LSRX buffer
HPDOUT
HPD
002aag997
Fig 1. Block diagram of CBTL05024
CBTL05024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product brief
Rev. 1 — 1 August 2012
2 of 3
CBTL05024
NXP Semiconductors
Multiplexer/de-multiplexer switch chip
5. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3 x 3 x 0.85 mm
SOT905-1
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
C
e
b
1
e
y
1
y
M
v
C
C
A
B
C
1
b
M
w
6
7
11
12
L
13
5
e
e
b
1
E
2
h
17
1
LC
terminal 1
index area
24
23
19
18
X
D
h
L
1
LC
0
1.5
scale
3 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
b
c
D
D
E
E
e
e
1
e
2
L
L
LC
v
w
y
y
1
1
1
h
h
1
max
0.05 0.25 0.45
0.00 0.15 0.35
3.1
2.9
2.05
1.75
3.1
2.9
2.05
1.75
0.35
0.15
0.1
0.0
0.3
0.2
mm
1
0.2
0.4
1.8
1.8
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
- - -
JEITA
06-03-13
06-03-31
SOT905-1
- - -
- - -
Fig 2. Package outline SOT905-1 (HVQFN24)
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 August 2012
Document identifier: CBTL05024
CBTL05024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product brief
Rev. 1 — 1 August 2012
3 of 3
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