CX24109-11Z [NXP]
Digital Satellite Tuner; 数字卫星调谐器
| 型号： | CX24109-11Z |
| 厂家： | 
NXP |
| 描述： | Digital Satellite Tuner |
| 文件： | 总40页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CX24109
Digital Satellite Tuner
Rev. 01 — 13 November 2008
Product data sheet
Document information
Info
Content
Keywords
Abstract
CX24109
NXP Semiconductors
Digital Satellite Tuner
Ordering information
Type number
Description
Package
CX24109-11
Digital Satellite Tuner
48-pin eTQFP
CX24109-11Z
Revision history
Revision
Date
Description
First NXP version based on the Conexant 102031A data sheet.
01
20081113
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
2
CX24109
NXP Semiconductors
General description
Digital Satellite Tuner
The CX24109 is a highly integrated, direct down-conversion satellite tuner intended for
high-volume digital video, audio, and data receivers. When combined with the CX24121
QPSK demodulator/FEC decoder, the chip set provides a complete broadband satellite
front-end solution capable of operating from 1–45 MSps in the most demanding satellite
environments. It is compatible with international standards such as DVB and DSS. The
highly integrated CX24109 reduces the tuner BOM cost and simplifies the RF layout.
Features
Zero-IF architecture eliminates the need for image reject filtering
Integrated LNA
Integrated LO with onboard VCO and synthesizer
Single +5 V supply
Reference oscillator output for demodulator
Applications
DBS set-top boxes
Commercial digital video, audio, and data receivers
Digital VCRs
Block diagram
Variable Low
Pass Filter
VGA1
VGA2
I Channel
Output
VCA
90
RF
Input
0
Variable Low
Pass Filter
VGA1
VGA2
Q Channel
Output
VCO
Reference
Oscillator
PLL
Dividers, Phase Detector,
and Charge Pump
Reference Programming Lock
to DEMOD and Control Detect
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
3
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
4
CX24109
NXP Semiconductors
Digital Satellite Tuner
Contents
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AGC and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Local Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Gain Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Frequency Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7.1
1.7.2
1.7.3
2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AGC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VCO Power Pin Ripple Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1
2.2
2.3
2.4
2.5
3
Parametric Data and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Standard Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1
3.1.1
3.2
Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
5
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
6
CX24109
NXP Semiconductors
Digital Satellite Tuner
Figures
Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
CX24109 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
QPSK Demodulation Typical Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Interface Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programming Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Simplified Application Schematic (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Simplified Application Schematic (Page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reflection Coefficient at Input of CX24109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Baseband Filter Gain vs. Frequency and FILTUNE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Filter –3 dB Bandwidth vs. FILTUNE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Gain and IIP3 vs. AGC Voltage at 950 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Gain and IIP3 vs. AGC Voltage at 2150 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Gain and NF vs. AGC Voltage at 950 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Gain and NF vs. AGC Voltage at 2150 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Serial Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
48-pin eTQFP Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
48-pin eTQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
7
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
8
CX24109
NXP Semiconductors
Digital Satellite Tuner
Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Programming Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Band Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VGA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VCA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PLL Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Recommended AGC Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended VCO Frequency vs. Charge Pump Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended Charge Pump Polarity and Reference Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
RF Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Baseband Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
9
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
10
CX24109
Chapter 1: Functional Description
Rev. 01 — 13 November 2008
Product data sheet
1.1
Figure 1.
Pinout Information
CX24109 Pin Diagram
VCC
GND
1
36
35
34
33
32
31
30
29
28
27
26
25
FILTUNE
2
IOUTN
IOUTP
GND
GND
3
RFIN
4
RFGND
GND
5
QOUTN
QOUTP
GND
6
CX24109
GND
7
DCIP
8
VCC
DCIN
9
CLK
DCQP
DCQN
TUNERES
10
11
12
DATA
EN
LD
102031_002
1.2
Pin Description
Table 1.
Pin Description
Pin Name
Pin No.
I/O
Description
RFIN
AGC
4
I
I
RF input signal pin.
37
AGC control input from the demodulator/FEC IC. It controls the gain of the RF attenuator
and both baseband amplifiers. Minimum gain occurs at minimum voltage. Input impedance
zin = 1 MΩ//20 pF..
FILTUNE
36
I
Baseband filter control input from the demodulator/FEC IC.
Minimum BW occurs at minimum voltage. Zin = 17 kΩ//20 pF.
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
11
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 1.
Pin Description
Pin Name
Pin No.
I/O
Description
TUNERES
12
—
Filter reference. A resistor to ground from this pin sets the reference current for the tunable
filter. See Figure 6 and Figure 7.
IOUTP, IOUTN
QOUTP, QOUTN
DCIP, DCIN
DCQP, DCQN
LPFILT
34, 35
31, 32
8, 9
O
O
I channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout
= 1 kΩ//10 pF.
Q channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout
= 1 kΩ//10 pF.
—
—
—
I channel DC offset cancellation. A capacitor must be placed between these pins. See
Figure 6 and Figure 7.
10, 11
20
Q channel DC offset cancellation. A capacitor must be placed between these pins. See
Figure 6 and Figure 7.
Loop filter. A network with a capacitor in parallel with a series resistor and capacitor
connected from this pin to ground determines the loop filter bandwidth. See Figure 6 and
Figure 7.
CLKREFOUT
XTAL1, XTAL2
24
O
Clock reference output. This pin provides the reference clock for the demodulator/FEC IC.
The maximum load allowed at this node is ZLOAD = 10 kΩ//20 pF.
16, 17
—
Crystal inputs. A 10.111 MHz, series-resonant, fundamental crystal is placed between
these two pins to create the system clock. See Figure 6 and Figure 7.
CLK
EN
28
26
27
25
I
I
Serial bus clock signal.
Serial bus latch enable.
DATA
LD
I
Serial bus data pin.
O
The lock detect signal to the demodulator/FEC IC.
ZLOAD = 10 kΩ//20 pF. High is the locked state.
Table 2.
Power Supply and Ground Pins
Pin Name
Pin No.
I/O
Description
VCC
GND
1, 13, 18, 22,
29, 38, 40,
42, 44, 47
P
+5 V power supply
Ground
2, 3, 5, 6, 7,
14, 15, 19,
P
21, 23, 30,
33, 39, 41,
43, 45, 46, 48
1.3
Application Overview
Several million Satellite Set-Top Boxes (STBs) are deployed in many different entertainment
networks around the world today. The standards for each network may vary a little but the
requirements for the tuner in the STB are essentially the same. Each receiver system in the
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
12
CX24109
NXP Semiconductors
Chapter 1: Functional Description
network requires an antenna, a Low Noise Block (LNB) downconverter, a drop cable, and an
STB. The LNB converts the satellite downlink frequency to an intermediate L-band frequency
where it is passed to the STB via the drop cable. The STB front end consists of a tuner and a
demodulator/FEC IC. The satellite tuner must tune to the L-band frequency, downconvert the
carrier, and separate it to baseband I and Q signals. The demodulator/FEC IC includes
QPSK Demodulation, carrier tracking, AGC control, bit timing, and the required FEC for a
given network service. Figure 2 illustrates a typical application block diagram for the
CX24109/CX24121 chip set in an STB front end.
Figure 2.
QPSK Demodulation Typical Application Block Diagram
LNB
CX24109
RF Tuner IC
CX24121
Demod/FEC IC
Dish
Antenna
IOUTP
8
IOUTN
QOUTN
QOUTP
AGC
I_N
RS_DATA[7:0]
Drop
Cable
Q_N
To
MPEG
Processor
RS_CLK
RSCntl1
RSCntl2
RFIN
XTAL1
AGCV
FILTERV
LD
XTAL2
FILTUNE
CLKREFOUT
LD
TUNERES
Tuner Control
3
102031_003
1.4
Signal Path
The CX24109 is a highly integrated, direct-down conversion satellite tuner. It consists of an
LNA, variable RF attenuator, quadrature downconverter, variable IF gain amplifiers, variable
low-pass filters, VCO, and synthesizer. A detailed block diagram of the IC is illustrated in
Figure 3.
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
13
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Figure 3.
Detailed Functional Block Diagram
Variable Low
Pass Filter
VGA1
VGA2
IOUTP
IOUTN
VCA
TUNERES
90 Degree
Splitter and
Divide by
2 or 4
RFIN
QOUTP
QOUTN
FILTUNE
AGC
AGC
Control
LPFILT
Crystal
Cell
XTAL1
XTAL2
Divide by
10, 20, 40
Phase
Detector
Charge
Pump
Voltage
Controlled
Oscillator
CLKREFOUT
9 Bit
Counter
32/33
Prescaler
Divide
by 2
CLK
DATA
EN
Control
Interface
Lock
Detect
5 Bit
LD
Counter
102031_004
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
14
CX24109
NXP Semiconductors
Chapter 1: Functional Description
The L-band output from the LNB enters the IC through the RFIN pin and is immediately
amplified by the Voltage Controlled Attenuator block (VCA). The VCA functions as a variable
gain LNA. The noise figure and gain of the VCA are the dominant factors for the tuner’s noise
figure. The signal is then quadrature downconverted to I and Q baseband channels.
Additional amplifiers at baseband provide more variable gain for the AGC loop. Also at
baseband, variable low-pass filters provide anti-alias filtering and eliminate noise power from
adjacent carriers and spurious signals before they can impact the A/Ds in the demodulator
IC.
1.5
1.6
AGC and Control
The AGC functionality for the CX24109 is split between the RF and baseband sections, and
provides 80 dB of variable gain. The primary control for the AGC is an analog voltage from
the demodulator IC. Programmable adjustments to the slope and offset of each variable gain
component in the tuner are available through the AGC control registers. Programming
information for the VGA and VCA is provided in Tables 4 and 5, respectively. The
recommended default values for the programmable control bits versus symbol rate are listed
in Table 8.
Local Oscillator
The local oscillator consists of a synthesizer and a VCO block, and is contained entirely
within the CX24109. The VCO block uses an innovative architecture that requires only a 5 V
source, eliminating the need for a 28 V power supply. It includes the required tank circuit.
The VCO block consists of a bank of eight oscillators operating at twice and four times the
input frequency with a continuous range from 2200 MHz to 4400 MHz. The VCOs overlap to
cover the frequency range from 950 MHz to 2150 MHz under all voltage, temperature, and
process variations. The VCO tuning range, combined with programmable ÷2 or ÷4 frequency
dividers, creates the continuous frequencies from 950 MHz to 2150 MHz for the local
oscillator. A simple tuning algorithm must be run by the host processor one time at power-up
to calibrate the VCO block. Conexant provides this program.
The synthesizer is also contained within the CX24109. It uses a 10.111 MHz reference
frequency and a reference divider, ÷R, to set the phase comparison frequency. Two
programming bits are used to configure the reference divider to divide by 10, 20, or 40, which
in turn sets the comparison frequency to 1.0111 MHz, 505 kHz, or 253 kHz, respectively. A
reference divider of 10 is recommended. The comparison frequency also determines the
frequency step size of the local oscillator. Another programmable divider is provided for the
VCO output. It consists of a 32/33 prescaler, a 9-bit N-counter (N-divider), a 5-bit A-counter
(A-divider), and a fixed ÷ 2 block. The programmable divider divides the VCO output from its
highest frequency to the minimum phase comparison frequency. The programmable charge
pump includes output currents of 1 mA, 2 mA, 3 mA, and 4 mA. Programming information for
the synthesizer can be found in Table 7. The recommended values for charge pump current,
polarity, and referenced dividers are listed in Tables 9 and 10.
The typical loop filter bandwidth is set with external passive components and should be set
between 8 kHz and 15 kHz.
1.7
Programming Interface
A three-wire serial interface with Clock, Data, and Enable lines is used to program the
CX24109. All digital signals are CMOS-compatible. The serial data carries the binary settings
for the programmable dividers, the VCO band select, the voltage-controlled attenuator, and
the voltage-controlled amplifiers. When the Enable line is low, data is shifted into an internal
shift register on the rising edge of the clock, and when the Enable line goes high, the stored
data is latched. The clock signal should be kept low when inactive. The maximum clock rate
is 1 MHz. Figure 4 illustrates the relationship between the Clock, Data, and Enable signals.
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
15
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Figure 4.
Serial Interface Programming Example
. . .
. . .
Clock
Data
Enable
102031_005
The internal shift register in the CX24109 is 21 bits long. When the data is latched into the IC,
the two MSBs act as control bits, and the lower 19 bits are the data bits as illustrated in
Figure 5. Data must be entered MSB first.
Figure 5.
Programming Word Configuration
MSB
LSB
d20 d19
d18 d17 d16 d15 d14 d13 d12 d11 d10 d9
d8
d7 d6
d5
d4 d3
d2
d1 d0
Control
Bits
Data Bits
102031_006
The control bits determine the functional block that is being programmed, while the data bits
contain the specific control information. Table 3 provides a detail mapping of the control and
data bits.
Table 3.
Programming Bit Mapping (Sheet 1 of 2)
Programming Bit Mapping
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Band Select
(1)
(1)
0
0
1
0
1
0
R
R
R
R
R
R
R
R
R
R
R
V
R
Band Select
VGA Programming
VCA Programming
PLL Programming
VGA2 Offset
VCA Offset
VGA1 Offset
VCA Slope
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
16
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 3.
Programming Bit Mapping (Sheet 2 of 2)
Programming Bit Mapping
(2)
(2)
1
1
÷R Divider
P
Charge
Pump
MSB
÷ N Divider
LSB MSB ÷A Divider
LSB
Current
GENERAL NOTES:
1. R means Reserved except for ÷R which means reference divider.
P means Charge Pump Polarity
V means VCO Divide Select
FOOTNOTES:
(1)
These Reserved locations must be set to zero. All other Reserved location values do not matter.
These Divide ratios are binary coded.
(2)
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
17
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 4.
Band Select Programming
Band Select
Typical Receive
Frequency Range
(MHz)
VCO
Number
VCO
Divider
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
950–1019
1019–1075
1075–1178
1178–1296
1296–1432
1432–1576
1576–1718
1718–1856
1856–2036
2036–2150
7
8
1
2
3
4
5
6
7
8
4
4
2
2
2
2
2
2
2
2
VCO Divide Select
Bit 9
Function
0
1
÷4
÷2
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
18
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 5.
VGA Programming
VGA1 Offset
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset in dB
–27.0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–28.5
–30.0
–31.5
–33.0
–34.5
–36.0
–37.5
–39.0
VGA2 Offset
Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Offset in dB
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
35
32
29
26
23
20
17
14
11
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
19
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 6.
VCA Programming
VCA Slope
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slope in dB/V
47.0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
49.5
1
52.0
1
54.5
1
57.0
1
59.5
1
62.0
1
1
64.5
67.0
VCA Offset
Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Offset in dB
90.00
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
94.25
98.50
102.75
107.00
111.25
115.50
119.75
124.00
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
20
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 7.
PLL Programming
Charge Pump Current
Bit 15
Bit 14
Current (mA)
0
0
1
1
0
1
0
1
1
2
3
4
Charge Pump Polarity
Reference Dividers
Bit 16
Function
Positive
0
1
Negative
Bit 18
Bit 17
Function
—
0
0
1
1
0
1
0
1
Reserved
Reserved
÷10
1.7.1
Gain Equations
The RF block voltage gain (GRF) is equal to the VCA gain + the mixer gain.
GRF = VAGC × VCA Slope – VCA Offset (in dB) + 23
where the maximum value of GRF is 23 dB, regardless of voltage
VGA1 voltage gain (GVGA1) is equal to
GVGA1 = VAGC × 26 + VGA1 Offset (in dB)
VGA2 voltage gain (GVGA2) is equal to
GVGA2 = VGA2 Offset (in dB)
The total baseband voltage gain (GBaseband) is equal to
GBaseband = GVGA1 + GFilter + GVGA2
= GVGA1 + 3 + GVGA2
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
21
CX24109
NXP Semiconductors
Chapter 1: Functional Description
1.7.2
Frequency Equations
The VCO frequency is determined by
FVCO = (FCrystal ÷ R) × (N + (A ÷ 32)) × 32 × 2
= (10.111 ÷ R) × (N + (A ÷ 32)) × 32 × 2
NOTE:
If A = 0, then N = N + 1
Remember, the incoming receive frequency is always lower than the VCO frequency, such
that:
FReceive = FVCO ÷ 2 or FVCO ÷ 4
1.7.3
Recommended Default Values
Table 8.
Recommended AGC Programming Values
VCA and VGA Slope and Offset vs. Symbol Rate
Condition
VGA2
Slope (dB/
V)(2)
FILTUNE
Voltage
(V)
VCA Slope
(dB/V)
VCA Offset
(dB)(1)
VGA1 Slope VGA1 Offset
VGA2 Offset
(dB)
Symbol Rate
(dB/V)(2)
(dB)
1 to 5 MSps
5 to 15 MSps
15 to 45 MSps
52
57
98.5
(102.75)
26
–30
0
0
0
29
17
14
0.41
0.90
2.70
98.5
(107)
26
26
–33
–36
59.5
98.5
(111.25)
FOOTNOTES:
(1)
There is an interaction between the offset and slope settings in the RF block, so the actual settings will be different from the theoretical
setting. Theoretical settings are given in parentheses.
These values are for reference only. They are not programmable.
(2)
Table 9.
Recommended VCO Frequency vs. Charge Pump Current
VCO Frequency
Charge Pump Current
Lower 50% VCO Frequency Range
Upper 50% of VCO Frequency Range
2 mA
3 mA
Table 10. Recommended Charge Pump Polarity and Reference Divider Values
Feature Specification
Charge Pump Polarity
Reference Divider
Negative
÷10
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
22
CX24109
Chapter 2: Applications
Rev. 01 — 13 November 2008
Product data sheet
2.1
2.2
AGC Input
To prevent excessive current draw, a 10 kΩ resistor on the AGC pin is recommended. See
Figure 6.
VCO Power Pin Ripple Requirement
Care must be taken to reduce the power supply ripple on pin 13 (VCO power supply) in order
to reduce phase noise. The power supply conditioning circuitry given in Figure 6 is suitable
for most circumstances.
2.3
2.4
Transmission Lines
Though the CX24109’s RF layout is simple, there are two transmission lines that must be
designed. The first transmission line is the LNB power line, which is located at the connector.
The second transmission line is between the connector and the RF IN pin. The input
transmission line must have a characteristic impedance of 75 Ω. The schematic gives
recommended dimensions assuming a two-layer FR-4 board.
Example Schematic
Figure 6 provides a simplified version of the CX24109/CX24121 reference design. For
complete and current reference design information, contact your local Conexant sales office.
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
23
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 6.
Simplified Application Schematic (Page 1 of 2)
5 V_RF
C106
33 p
C104
47 p
LNB_POWER
C107
0.01 µF
C105
33 p
C108
33 p
L103
BEAD
C109
1 n
C110
1 n
W = 0.5 mm, L = 27 mm, H = 1.6 mm FR-4
AGC
FILTUNE
C103
33 p
W = 1.4 mm
L = 1.6 mm
H < 10 mm FR-4
75 Ω
C111
0.047 µF
36
35
34
FILTUNE
I_OUTN
I_OUTP
Q_OUTN
Q_OUTP
3
2
1
ATTEN_VCC2
RF_IN
C101
I_OUT
1
4
5
C112
0.047 µF
Q_OUT
J1
3.3 pF
22 pF
32
31
29
RF_GND
DC_IP
8
C113
0.047 µF
C121
0.047 µF
9
CX24109
DC_IN
AGC2_VCC
CLK
10
28
DC_QP
CLK
C120
0.047 µF
11
27
26
DC_QP
DATA
LE
DATA
EN
R101
1.2 k
TUNERES
25
LD
LD
C119
10 n
CLKREF
_OUT
C114
1 n
C117
10 n
10.111
Series
C116
6.8 n
C118
100 u
Y1
R105
8.2
R102
1.0 k
L102
BEAD
C115
33 n
5 V_RF
FOOTNOTE:
(1)
Ground pins include: 2, 3, 5, 6, 7, 14, 15, 19, 21, 23, 30, 33, 39, 41, 43, 45, 46, and 48
102031_007
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
24
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 7.
Simplified Application Schematic (Page 2 of 2)
+3.3 V
R515
30.9 KΩ
1%
C602
0.047 uF
C535
0.047 uF
C536
0.01 uF
C534
0.01 uF
C532
0.01 uF
C533
0.01 uF
AGC
2
1
FILTUNE
72
3
5
AD_VAA
AD_VAA
AD_VDD
I_OUT
Q_OUT
CX24121
CLK
R203 300
68
LD
DATA
LE
C204
0.1 u
R204 300
R205 300
R206
67
66
65
TUNER_EN
TUNER_DATA
TUNER_CLK
LD
C205
100 p
C206
100 p
300
R207 10 K
R208
300
55
56
63
64
LNB
Control
GPIO_1 (LNB_DC)
LNB_22K
AGCV
FILTERV
CLKREF
_OUT
C207
100 p
C209
0.1 u
C208
0.1 u
(3)
41
11
RS_DATA
TEST_MODE
XTAL_IN
32
37
47
38
RS_CLK
RSCntl1
Interrupt (RSSYNC)
RSCntl2
To MPEG
Processor
79
77
I_N
Q_N
80
78
I_P
Q_P
C861
0.01 µF
C863
0.01 µF
R306
33
45
46
SER_CLK
SER_DATA
SER_CLK
SER_DATA
R307
33
FOOTNOTE:
(1)
(2)
Ground Pins include: 4, 6, 8, 10, 15, 26, 30, 34, 50, 52, 62, 70, and 71.
Core (1.8 V) power pins include: 7, 9, 14, 29, 49, and 69.
3.3 V power pins include: 25, 33, 51, and 61.
RS_DATA includes RS_DATA0–RS_DATA7 pins 35, 31, 28, 27, 24, 23, 22, and 21.
(3)
102031_008
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
25
CX24109
NXP Semiconductors
Chapter 2: Applications
2.5
Figure 8.
Typical Performance Curves
Reflection Coefficient at Input of CX24109
CX24109 S11
m1
Freq = 950 MHz
plot_vs(S(1,1), freq) = –0.19 + j0.21
Impedance = 31.629 + j14.373
m2
Freq = 1.20 GHz
plot_vs(S(1,1), freq) = 0.39/65.79
Impedance = 51.055 + j42.441
m3
Freq = 2.15 GHz
plot_vs(S(1,1), freq) = 0.29/–2.11
Impedance = 89.855 – j2.055
Frequency (950.0 MHz to 2.200 GHz)
102031_020
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
26
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 9.
Baseband Filter Gain vs. Frequency and FILTUNE Voltage
10
0
FILTUNE = 0.5 V
FILTUNE = 1.0 V
FILTUNE = 1.5 V
FILTUNE = 2.0 V
FILTUNE = 2.5 V
FILTUNE = 3.0 V
–10
–20
–30
–40
–50
–60
–70
0
5
10
15
20
25
30
35
40
45
Frequency (MHz)
Figure 10. Filter –3 dB Bandwidth vs. FILTUNE Voltage
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
FILTUNE Voltage (V)
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
27
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 11. Gain and IIP3 vs. AGC Voltage at 950 MHz
85
80
75
70
65
60
55
50
IIIP3
Gain
45
40
35
30
25
20
15
10
5
0
–5
–10
1
1.5
2
2.5
3
AGC Voltage (V)
Figure 12. Gain and IIP3 vs. AGC Voltage at 2150 MHz
85
80
75
70
65
60
55
50
45
40
35
IIIP3
Gain
30
25
20
15
10
5
0
–5
–10
1.2
1.7
2.2
2.7
3.2
AGC Voltage (V)
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
28
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 13. Gain and NF vs. AGC Voltage at 950 MHz
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Gain
Noise Figure
0
–5
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2
AGC Voltage (V)
Figure 14. Gain and NF vs. AGC Voltage at 2150 MHz
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Gain
Noise Figure
0
–5
–10
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2
AGC Voltage (V)
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
29
CX24109
NXP Semiconductors
Chapter 2: Applications
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
30
CX24109
Chapter 3: Parametric Data and Specifications
Rev. 01 — 13 November 2008
Product data sheet
3.1
Electrical Specifications
Table 11.
Absolute Maximum Ratings
Parameter
Supply Voltage
Minimum
–0.3
Maximum
6
Units
V
Input Voltage Range
Storage Temperature
Junction Temperature
–0.3
Vcc +0.3
+150
V
–65
°C
°C
—
+150
3.1.1
Standard Operating Conditions
All specifications are valid under the operating conditions indicated in Tables 8, 9, 10, and
12.
Table 12. Operating Conditions
Parameter
Conditions
Min
0
Typ
+25
—
Max
+70
125
5.25
—
Units
°C
Ambient Operating Temperature
Maximum Operating Junction Temperature
Supply Voltage
—
—
—
°C
—
Series resonant, fundamental
Including temperature drift
—
4.75
—
5.0
V
Reference Oscillator Frequency
Reference Oscillator Frequency Stability
Loop Filter Bandwidth
10.111
—
MHz
ppm
kHz
—
+100
—
—
10
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
31
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 13. DC Electrical Characteristics
Parameter
Conditions
Min
—
1.3
—
—
0
Typ
244
—
Max
262
2.80
—
Units
mA
Supply Current(1)
—
—
Usable AGC Voltage Range, VAGC
Impedance of AGC Input
V
at DC
—
1
MΩ
mA
AGC Current, IAGC
—
0.4
3.0
—
Usable Filtune Voltage Range, VFiltune
Impedance of Filtune Input
Thermal Resistance of Package
—
—
V
at DC
θja(2)
θjc
—
—
—
17
42
8.7
kΩ
—
°C/W
°C/W
—
FOOTNOTES:
(1)
Using 15–45 MSps programming values (see Table 8), Vcc = 5.0 V, VAGC = 1.45 V, VFiltune = 2.7 V.
(2)
Using a 2-layer CX24109/CX24121 reference design, where the package’s exposed paddle is connected to the printed circuit board ground plane
using thermal vias. The ground plane on the reference design is approximately 2-7/8 inches x 1-1/4 inches. Better thermal performance can be
obtained by increasing ground plane coverage or increasing the number of attached printed circuit board layers.
Table 14. AC Electrical Characteristics
Parameter
Conditions
—
Min
—
—
—
1
Typ
—
Max
1
Units
MHz
ns
Programming Clock Frequency
Bus Timing
Data Setup, tSU
See Figure 15.
10
10
—
—
Data Hold, tHD
—
ns
Enable Pulse
Width, tEW
—
μs
Clock to Enable,
tCE
—
1
—
μs
Programming Lines:
Clock, Data, Enable
VIH
VIL
IIH
—
—
—
—
—
—
2.1
—
—
—
—
0.8
V
V
—
—
0.5
mA
mA
V
IIL
—
—
–0.5
—
LD and CLKREFOUT
VOH
VOL
2.3
—
2.65
0.9
1.125
V
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
32
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Figure 15. Serial Programming Example
. . .
. . .
Clock
Data
t
HD
t
su
Enable
t
t
ew
ce
102031_016
Table 15. RF Electrical Characteristics (Sheet 1 of 3)
Parameter
Conditions
Min
950
–81
Typ
—
Max Units
Tuning Frequency
—
2150
–23
MHz
dBm
Input Power, Single Tone(1)
Depends on bandwidth of incoming signal
and C/I
—
Aggregate Input Power(1)(2)
Input Impedance, Balanced(1)
Input VSWR(1)
—
—
—
—
—
76
8
—
75
10
0.5
86
18
36
–7
—
—
—
91
23
42
dBm
Ω
ZSOURCE = 75 Ω
—
dB
Iout and Qout Output Voltage
Maximum Conversion (Voltage) Gain
Minimum Conversion (Voltage) Gain
Noise Figure (NF)(1) (3)
R
Load = 1 kΩ
VAGC=2.4 V, 1 MSps gain coefficients(1)
AGC=1.45 V, 45 MSps gain coefficients(1)
VP-P
dB
V
dB
Pin = –43 dBm,
—
dB
1–5 MSps gain coefficients(4)
Pin = –81 dBm,
—
—
—
—
—
10.5
35
14
42
14
45
14
dB
dB
dB
dB
dB
1–5 MSps gain coefficients(5)
Pin = –34.5 dBm,
5–15 MSps gain coefficients(6)
Pin = –72 dBm,
5–15 MSps gain coefficients(7)
10.5
35
Pin = –30 dBm,
15–45 MSps gain coefficients(8)
Pin = –70 dBm,
15–45 MSps gain coefficients(9)
10.5
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
33
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 15. RF Electrical Characteristics (Sheet 2 of 3)
Parameter
Conditions
Min
Typ
Max Units
IIP3 (Out-of-band)(1) (4)
+(31 and 60) MHz, Pin = –42 dBm,
1–5 MSps gain coefficients(4)
–2
4.0
—
—
—
—
—
—
—
—
—
—
—
—
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
+(91 and 180) MHz, Pin = –42 dBm,
1–5 MSps gain coefficients(4)
5.5
–35
–39
0
9.4
–25.0
–7.2
5.0
+(31 and 60) MHz, Pin = –81 dBm,
1–5 MSps gain coefficients
+(91 and 180) MHz, Pin = –81 dBm,
1–5 MSps gain coefficients(5)
+(31 and 60) MHz, Pin = –34.5 dBm,
5–15 MSps gain coefficients(6)
+(91 and 180) MHz, Pin = –34.5 dBm,
5–15 MSps gain coefficients(6)
5.5
–35
–30
–2
9.8
+(31 and 60) MHz, Pin = –72 dBm,
5–15 MSps gain coefficients(7)
–25.5
–6.5
5.5
+(91 and 180) MHz, Pin = –72 dBm,
5–15 MSps gain coefficients(7)
+(31 and 60) MHz, Pin = –30 dBm,
15–45 MSps gain coefficients(8)
+(91 and 180) MHz, Pin = –30 dBm,
15–45 MSps gain coefficients(8)
5.7
–35
–28
10.5
–24.5
–6.5
+(31 and 60) MHz, Pin = –70 dBm,
15–45 MSps gain coefficients(9)
+(91 and 180) MHz, Pin = –70 dBm,
15–45 MSps gain coefficients(9)
IIP3I (Inband)
1 MSps coefficients and VAGC = 1. 5 V(1)
—
—
–30
–65
3
—
—
13
3
dBm
dBm
+deg
+dB
dBm
dB
1 MSps coefficients and VAGC = 2.4 V(1)
I/Q Phase Difference
I/Q Amplitude Ratio
LO Leakage
—
—
—
—
1
950 to 2150 MHz(1)
C/I = 10 dB VAGC = 1.5 V(1)
C/I = 10 dB(1)
—
–80
–45
–50
–70
—
—
2LO-RF Rejection
2RF-LO Rejection
–30
–30
dB
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
34
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 15. RF Electrical Characteristics (Sheet 3 of 3)
Parameter
Conditions
VCO and Synthesizer
Measured at 400 Hz
Min
Typ
Max Units
Reference Oscillator Phase Noise
Spurious
—
–130
–45
—
—
dBc/Hz
dBc
At 1, 10.111, and 30 MHz offsets
with 2 mA charge pump and
10 kHz loop BW
–30
VCO Tuning Sensitivity
—
100
—
—
—
—
—
—
—
–75
–97
–69
–94
—
330
—
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
LO Phase Noise at 950 MHz–1450 MHz
10 kHz offset
100 kHz offset
—
LO Phase Noise at 1450 MHz–2150 MHz
LO Phase Noise at 950 MHz–2150 MHz
10 kHz offset
—
100 kHz offset
—
10 kHz offset +100 kHz offset
All frequencies, VCOs and modes
–158 dBc/Hz
ms
Local Oscillator Settling Time
1
—
GENERAL NOTES:
1. Values in this table are valid under the operating conditions listed in Tables 8, 9, and 10, using a reference divider of 10, unless otherwise
stated.
FOOTNOTES:
(1)
This measurement is made at RFIN of CX24109.
Aggregate average power of 40 QPSK modulated carriers.
All NF and IIP3 measurements/specifications are made by setting a specific input level for the desired symbol rate and adjusting the AGC
(2)
(3)
level to obtain the desired output level of 0.5 Vpp.
This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 1 MSps.
(4)
Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 1 MHz), thus, Pin = –23 dBm – 7 dB – 10 log (20 / 1) = –43 dBm.
(5)
This level is derived from Pin = PTransponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 1 MSps and
PTransponder is at a minimum. PTransponder = 10 log ((1E6 / 45E6) 10 (82 – 4) /10) = +61 dBm. Therefore, Pin = + 61 dBm – 205 dB + 38 dB +
45 dB – 20 dB = –81 dBm.
(6)
This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 7 MSps.
Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 7 MHz), thus, Pin = –23 dBm – 7 dB – 10 log 20 / 7 = –34.5 dBm.
(7)
This level is derived from Pin = PTransponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 7 MSps and
P
Transponder = 10 log ((7E6 / 45E6) 10 (82–4)/10) = +70 dBm. Therefore, Pin = +70 dB – 205 dB + 38 dB + 45 dB – 20 dB = –72 dBm
(8)
(9)
This level is derived assuming –23 dBm is the maximum level of all other transponders, an operating symbol rate of 20 MSps and a C/I of
7 dB.
Assume a symbol rate of 20 MSps.
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
35
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 16. Baseband Frequency Response
Parameter
Conditions
Measured at minimum VFiltune
Measured at maximum VFiltune
0 V < VFiltune < 3.0 V
0 < Freq < F1 dB
Min
1.4
27
—
Typ
—
Max Units
Minimum Cutoff Frequency, F1 dB
Minimum Cutoff Frequency, F1 dB
Tuning Voltage Transfer Function
Passband Ripple
2.6
—
MHz
MHz
MHz/V
dB
—
10.5
—
—
—
1.0
—
Stopband Attenuation
F > 2.6 × F1 dB
35
45
—
dB
Stopband Attenuation
5 × F1 dB < F < 2 GHz
—
—
dB
3.2
Mechanical Specifications
Figure 16. 48-pin eTQFP Land Pattern
LAND PATTERN - 48 ETQFP
0.965 REF.
PWB Exposed Pad
5.070 REF.
1.215 REF.
4.570 REF.
3x3 Array of
Mask Opening
Thermal Vias Should be
Thermal Vias
0.330 mm Dia.
Spacing TBD
Tinted Using 0.430 mm Dia.
Solder Mask
4.570 REF.
0.250
5.070 REF.
0.965 REF.
0.250
1.215 REF.
0.500
1.000
8.400 REF.
9.400 REF.
11 EQ SP @ 0.50 = 5.50
TYP
PWB METALIZATION PATTERN
PWB SOLDER MASK PATTERN
102031_017
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
36
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Figure 17. 48-pin eTQFP Package Diagram
D
D
1
Pin #1
D
2
Ref. Mark
D
2
D
1
D
D
1
e
b
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Millimeters
Min Max
Inches
Dimension
A
Min
Max
1.20 MAX
0.047 MAX
See Detail A
0.05
0.15 0.002
0.006
0.041
A
A
1
0.95
1.05 0.037
2
9.00 BSC
7.00 BSC
4.50 REF
0.354 BSC
0.275 BSC
0.177 REF
D
D
D
L
1
2
A
2
A
c
0.45
0.75 0.018
0.030
1.00 REF
0.50 BSC
0.039 REF
0.020 BSC
L
e
b
c
1
0.17
0.09
0.27 0.007
0.20 0.004
0.011
0.008
A
1
L
DETAIL A
L
1
0.08 MAX
0.003 MAX
Coplanarity
102031_018
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
37
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
38
CX24109
NXP Semiconductors
Digital Satellite Tuner
Legal information
Data sheet status
[1][2]
[3]
Document status
Product status
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
CX24109_N_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
39
CX24109
NXP Semiconductors
Digital Satellite Tuner
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
40
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 November 2008
Document identifier: CX24109_N_1
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