DAC1003D160HW_技术文档

DAC1003D160

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Rev. 02 — 13 August 2008

Product data sheet

1. General description

The DAC1003D160 is optimized to reduce architecture complexity and overall system

cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier

support because of its direct IF conversion capabilities. With an internal sampling rate up

to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband

wireless systems transmitters, as well as a wide range of applications.

2. Features

I Dual 10-bit resolution

I Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz

I Input data rate up to 80 MHz

I 2 × interpolation ﬁlter

I Output data rate up to 160 Mhz

I Single 3.3 V power supply

I Low noise capacitor free integrated Phase-Locked Loop (PLL)

I Low power dissipation

I HTQFP80 package

I Ambient temperature from −40 °C to +85 °C

3. Applications

I Broadband wireless systems

I Digital radio links

I Cellular base stations

I Instrumentation

I Cable modems

I Cable Modem Termination System (CMTS)/Data Over Cable Service Interface

Speciﬁcation (DOCSIS)

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

DAC1003D160HW HTQFP80

plastic thermal enhanced thin quad ﬂat package; 80 leads;

SOT841-1

body 12 × 12 × 1 mm; exposed die pad

5. Block diagram

V

CCA

U/I

DAC1003D160

60

IVIRES

11 to 16,

19 to 22

73

72

IOUT

I9 to I0

LATCH

DAC

10

IOUTN

FIR

(CLK × 2)

PLL

5

6

CLK

CLOCK

DRIVER

INTERNAL 58

BAND GAP

(CLK × 2)

GAPOUT

GAPD

CLKN

(CLK × 2)

57

31 to 34,

37 to 42

69

68

QOUT

Q9 to Q0

LATCH

DAC

10

QOUTN

FIR

U/I

59

2, 8

i.c.

QVIRES

10, 51

(1)

V

CCA

CCD

(2)

(3)

(4)

014aaa532

V

AGND DGND DEC

CCA

(1) Pins 1, 3, 61, 65, 76 and 80.

(2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79.

(3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56.

(4) Pins 18, 26, 36, 43, 63 and 78.

Fig 1. Block diagram

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

2 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

6. Pinning information

6.1 Pinning

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

V

IVIRES

QVIRES

GAPOUT

GAPD

CCA

2

3

i.c.

CCA

4

AGND

CLK

5

DGND

6

CLKN

AGND

i.c.

7

8

9

DGND

10

11

12

13

14

15

16

17

18

19

20

V

CCD

V

CCD

DAC1003D160

I9

DGND

n.c.

I8

I7

I6

I5

I4

n.c.

DGND

n.c.

DGND

DEC

I3

DGND

DEC

Q0

I2

Q1

014aaa533

Fig 2. Pin conﬁguration

6.2 Pin description

Table 2.

Symbol

V_CCA

Pin description

Type^[1]Description

1

S analog supply voltage

i.c.

2

3

4

5

6

7

8

9

I/O

S

G

I

internally connected; leave open

analog supply voltage

analog ground

V_CCA

AGND

CLK

clock input

CLKN

AGND

i.c.

I

complementary clock input

analog ground

G

O

G

internally connected; leave open

digital ground

DGND

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

3 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Table 2.

Pin description …continued

Type^[1]Description

Symbol

V_CCD

I9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

S

I

digital supply voltage

I data input bit 9 (Most Signiﬁcant Bit (MSB))

I data input bit 8

I data input bit 7

I data input bit 6

I data input bit 5

I data input bit 4

digital ground

I8

I

I7

I

I6

I

I5

I

I4

I

DGND

DEC

I3

G

O

I

decoupling node

I data input bit 3

I data input bit 2

I data input bit 1

I data input bit 0 (Least Signiﬁcant Bit (LSB))

not connected

I2

I

I1

I

I0

I

n.c.

DGND

DEC

n.c.

DGND

Q9

I

not connected

G

O

I

digital ground

decoupling node

not connected

I

not connected

G

I

digital ground

Q data input bit 9 (MSB)

Q data input bit 8

Q data input bit 7

Q data input bit 6

digital ground

Q8

I

Q7

I

Q6

I

DGND

DEC

Q5

G

O

I

decoupling node

Q data input bit 5

Q data input bit 4

Q data input bit 3

Q data input bit 2

Q data input bit 1

Q data input bit 0 (LSB)

decoupling node

digital ground

Q4

I

Q3

I

Q2

I

Q1

I

Q0

I

DEC

DGND

n.c.

DGND

O

G

I

not connected

I

not connected

I

not connected

I

not connected

G

digital ground

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

4 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Table 2.

Pin description …continued

Type^[1]Description

Symbol

V_CCD

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

S

G

I

digital supply voltage

digital ground

DGND

GAPD

GAPOUT

QVIRES

IVIRES

V_CCA

digital ground

internal band gap power disable input

band gap output voltage

Q DAC biasing resistor

I DAC biasing resistor

analog supply voltage

analog ground

I/O

I

S

G

O

G

S

G

O

G

O

G

S

G

O

G

S

AGND

DEC

decoupling node

AGND

V_CCA

analog ground

analog supply voltage

analog ground

AGND

QOUTN

QOUT

AGND

IOUTN

IOUT

analog ground

complementary Q DAC output current

Q DAC output current

analog ground

complementary I DAC output current

I DAC output current

analog ground

AGND

V_CCA

analog ground

analog supply voltage

analog ground

AGND

DEC

decoupling node

AGND

V_CCA

analog ground

analog supply voltage

[1] Type description: S: Supply; G: Ground; I: Input; O: Output.

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

5 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

7. Functional description

The DAC1003D160 is a segmented architecture composed of a 7-bit thermometer

sub-DAC and the remaining 3-bit in a binary weighted sub-DAC.

The device produces two complementary current outputs on both channels, respectively

pins IOUT/IOUTN and QOUT/QOUTN which need to be connected via a load resistor to

the ground.

Figure 3 shows the equivalent analog output circuit of one DAC, which consists of a

parallel combination of PMOS current sources and associated switches for each segment.

The cascade source conﬁguration enables the increase of the output impedance of the

source and the improvement of the dynamic performance of the DAC by introducing less

distortion.

Figure 4 shows the internal reference conﬁguration. In this case the bias current is given

by the output of the internal regulator connected to the inverting input of the internal

operational ampliﬁers, while external resistors R_Iand R_Qare connected respectively to

pins IVIRES and QVIRES. Thus the output current of the two DACs is typically ﬁxed to

20 mA with an appropriate choice of these resistors. This conﬁguration is optimal for

temperature drift compensation because the band gap can be matched with the voltage

on the feedback resistors.

The relation between full-scale output current I_O(fs)and the R_I(R_Q) is:

2048 × V

R_I=

^GAPOUTΩ

-----------------------------------------

82 × I_O(FS)

The output current can also be adjusted by imposing an external reference voltage to the

inverting input pin GAPOUT and disabling the internal band gap with pin GAPD set to

HIGH. At a voltage lower than 1.2 V the current can be set at values lower than 20 mA.

The input references at pins IVIRES and QVIRES may also be driven by separate

reference voltages to adjust independently the two DAC currents.

DAC1003D160

GAPD

INTERNAL

BAND GAP

AGND

GAPOUT

R

I

I DAC current

sources array

IVIRES

DAC1003D160

IOUT/QOUT

IOUTN/QOUTN

R

L

R

L

R

Q

Q DAC current

sources array

QVIRES

AGND AGND

014aaa537

014aaa538

Fig 3. Equivalent analog output circuit

Fig 4. Internal reference conﬁguration

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

6 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

8. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CCD

Parameter

Conditions

Min

Max

+3.9

+150

Unit

V

[1]

digital supply voltage

analog supply voltage

supply voltage difference

−0.3

−150

V_CCA

V

∆V_CC

between the

mV

analog and digital

supply voltages

V_I

input voltage

pins Qn and In

referenced to

DGND

−0.3

V_CCD+ 0.3 V

pins IVIRES,

QVIRES, GAPD,

CLK and CLKN

referenced to

AGND

V

_CCA+ 0.3 V

V_O

output voltage

pins IOUT,

−0.3

_CCA+ 0.3 V

IOUTN, QOUT

and QOUTN

referenced to

DAGND

T_stg

T_amb

T_j

storage temperature

ambient temperature

junction temperature

−55

−40

-

+150

+85

°C

125

[1] All supplies are connected together.

9. Thermal characteristics

Table 4.

Thermal characteristics

Parameter

Symbol

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction in free air

to ambient

27.1

K/W

R_th(c-a)

thermal resistance from case to

ambient

in free air

11.8

K/W

10. Characteristics

Table 5.

V_CCD= V_CCA= 3.0 V to 3.6 V; AGND and DGND connected together; T_amb= −40 °C to +85 °C; typical values measured at

_CCD= V_CCA= 3.3 V, I_O(fs)= 20 mA and T_amb= 25 °C; dynamic parameters measured using output schematic given in

Figure 10; unless otherwise speciﬁed.

Characteristics

V

Symbol

Supplies

V_CCD

Parameter

Conditions

Min

Typ

Max

Unit

digital supply voltage

analog supply voltage

digital supply current

3.0

-

3.3

55

3.6

65

V

V_CCA

V

I_CCD

mA

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

7 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Table 5.

V_CCD= V_CCA= 3.0 V to 3.6 V; AGND and DGND connected together; T_amb= −40 °C to +85 °C; typical values measured at

_CCD= V_CCA= 3.3 V, I_O(fs)= 20 mA and T_amb= 25 °C; dynamic parameters measured using output schematic given in

Figure 10; unless otherwise speciﬁed.

Characteristics …continued

V

Symbol

I_CCA

Parameter

Conditions

Min

Typ

73

Max

85

Unit

mA

analog supply current

total power dissipation

-

P_tot

f_clk= 80 MHz;

422

540

mW

f_IOUT= f_QOUT= 5 MHz

Clock inputs (CLK and CLKN)

V_I(cm)

common-mode input

voltage

-

1.65

1.0

-

V

V_i(dif)(p-p)

peak-to-peak differential

input voltage

Analog outputs (IOUT, IOUTN, QOUT and QOUTN)

I_O(fs)

R_o

full-scale output current

output resistance

differential outputs

4

-

20

-

mA

kΩ

pF

[1]

150

3

C_o

output capacitance

-

Digital inputs (I0 to I9, Q0 to Q9 and GAPD)

V_IL

V_IH

I_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level input current

HIGH-level input current

DGND

-

0.3 V_CCD

V

0.7 V_CCD

-

V_CCD

V

V_IL= 0.3 V_CCD

V_IH= 0.7 V_CCD

-

5

-

µA

I_IH

Reference voltage output (GAPOUT)

V_GAPOUT

I_GAPOUT

voltage on pin GAPOUT

current on pin GAPOUT

-

1.31

1

-

V

external voltage

µA

∆V_GAPOUTvoltage variation on pin

±133

ppm/°C

GAPOUT

Clock timing inputs (CLK and CLKN)

f_clk

clock frequency

-

80

-

MHz

ns

t_w(clk)H

t_w(clk)L

HIGH clock pulse width

LOW clock pulse width

5

-

ns

Input timing (I0 to I9 and Q0 to Q9); see Figure 5

t_h(i)

input hold time

1.1

-

3.4

ns

t_su(i)

input set-up time

−1.5

+0.7

Output timing (IOUT, IOUTN, QOUT, QOUTN)

t_ssettling time t_{o ±}0.5 LSB

[1]

-

16

-

ns

Digital ﬁlter speciﬁcation (FIR); order N = 42 see Figure 6 and 7 and Table 7

f_data

data rate

-

80

-

MHz

α_ripple(pb)

B_p

α_stpb

t_d(grp)

pass-band ripple

power bandwidth

stop-band attenuation

group delay time

f_data/f_clk; 0.005 dB attenuation

f_data/f_clk; 3 dB attenuation

f_data/f_clk= 0.6 dB to 1 dB

0.405

0.479

69

-

dB

ns

11 T_clk

-

Analog signal processing

INL

integral non-linearity

differential non-linearity

-

±0.2

±0.1

-

LSB

DNL

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

8 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Table 5.

V_CCD= V_CCA= 3.0 V to 3.6 V; AGND and DGND connected together; T_amb= −40 °C to +85 °C; typical values measured at

_CCD= V_CCA= 3.3 V, I_O(fs)= 20 mA and T_amb= 25 °C; dynamic parameters measured using output schematic given in

Figure 10; unless otherwise speciﬁed.

Characteristics …continued

V

Symbol

I_n(o)

Parameter

Conditions

Min

Typ

120

−0.3

-

Max

Unit

pA/√Hz

%

output noise current

offset error

-

E_offset

E_G

relative to full-scale

-

gain error

−5.4

+5.4

-

%

∆G_IQ

IQ gain mismatch

between I and Q, relative to

full-scale

-

±0.2

%

SFDR

spurious free dynamic

range

f_clk= 80 MHz; B = Nyquist

f_o= 2.5 MHz at 0 dBFS

f_o= 5 MHz at 0 dBFS

f_o= 13 MHz at 0 dBFS

f_o= 5 MHz

-

80

72

64

73

65

88

86

65

-

dBc

α_2H

second harmonic level

third harmonic level

second-order

f_o= 13 MHz

α_3H

f_o= 5 MHz

f_o= 13 MHz

IMD2

IMD3

THD

f_clk= 80 MHZ; f_o1 = 10 MHz;

intermodulation distortion f_o2 = 12 MHz; B = Nyquist

third-order intermodulation f_clk= 80 MHz; f_o1 = 10 MHz;

distortion

-

84

-

dBc

f_o2 = 12 MHz

total harmonic distortion

f_clk= 80 MHz; B = Nyquist; T_amb= 25 °C

f_o= 2.5 MHz

-

75

71

-

dBc

f_o= 5 MHz

68

NSD

S/N

noise spectral density

signal-to-noise ratio

f_clk= 80 MHz

f_o= 2.5 MHz

-

−155

−153

-

dBm/Hz

f_o= 5 MHz

f_o= 19 MHz

f_clk= 80 Msample/s; B = Nyquist

f_o= 2.5 MHz

-

80

78

-

dBc

f_o= 5 MHz

70

-

f_o= 19 MHz

ACPR

adjacent channel power

ratio

baseband; 5 MHz channel spacing; B = 3.84 MHz

f_o= 2.5 MHz

f_o= 20 MHz

-

60

61

-

dBc

[1] Guaranteed by design.

Table 6.

Band gap

Band gap disable (GAPD)

Band gap input/output (GAPOUT)

output (V_GAPOUT= 1.2 V)

input

Internal band gap

enable

LOW

HIGH

disable

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

9 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

t

su(i)

I0 to I9,

Q0 to Q9

CLKN

CLK

50 %

t

h(i)

IOUT/IOUTN,

QOUT/QOUTN

014aaa534

Fig 5. Input timing diagram

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

10 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

014aaa535

014aaa536

20

0.6

output

(dB)

normalized output

−20

−60

0.4

0.2

0

−100

−140

−180

−0.2

0

0.2

0.4

0.6

0.8

o/ clk

1.0

0

10

20

30

40

normalized frequency f

f

t (sample)

Fig 6. FIR ﬁlter frequency response

Fig 7. FIR ﬁlter impulse response

Table 7.

Coefﬁcient

H(1)

Interpolation FIR ﬁlter coefﬁcient

Coefﬁcient

H(43)

H(42)

H(41)

H(40)

H(39)

H(38)

H(37)

H(36)

H(35)

H(34)

H(33)

H(32)

H(31)

H(30)

H(29)

H(28)

H(27)

H(26)

H(25)

H(24)

H(23)

-

Value

10

H(2)

0

H(3)

−31

0

H(4)

H(5)

69

H(6)

0

H(7)

−138

0

H(8)

H(9)

248

0

H(10)

H(11)

H(12)

H(13)

H(14)

H(15)

H(16)

H(17)

H(18)

H(19)

H(20)

H(21)

H(22)

−419

0

678

0

−1083

0

1776

0

−3282

0

10364

16384

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

11 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

11. Application information

AGND

DAC1003D160

1 kΩ

CLK

100 nF

DAC1003D160

1 kΩ

R

s

CLK

V

CCA

V

CCA

100 nF

AGND

1 kΩ

CLKN

V

th

CLKN

100 nF

AGND

014aaa539

014aaa540

Fig 8. Single-ended clock schematic

Fig 9. Differential clock schematic

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

12 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

50 Ω

(RLOAD)

1:1

(RLOAD)

1:1

AGND

50 Ω

C

AGND

AGND AGND AGND

AGND

AGND AGND AGND

3.3 V

C

3.3 V

C

3.3 V

C

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1.5 kΩ

V

CCA

IVIRES

QVIRES

GAPOUT

GAPD

1

2

3

4

5

6

7

8

9

3.3 V

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

i.c.

C

CCA

3.3 V

C

AGND

CLK

C

AGND

DGND

CLKN

AGND

i.c.

AGND

DGND

3.3 V

DGND

3.3 V

C

V

CCD

V

CCD

10

11

12

13

14

15

16

17

18

19

20

DAC1003D160

I9

I8

DGND

n.c.

C

DGND

I7

I6

n.c.

I5

n.c.

I4

n.c.

DGND

DEC

I3

DGND

DEC

Q0

DGND

C

I2

Q1

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

C

014aaa541

DGND

All resistors are 1 % precision resistors.

C = 100 nF.

Fig 10. Application diagram

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

13 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

11.1 Alternative parts

The following alternative parts are also available:

Table 8.

Alternative parts

Type number

Description

Sampling frequency

[1]

DAC1403D160

Dual 14 bits DAC,

with 2 × interpolating

160 MHz

DAC1203D160

Dual 12 bits DAC,

160 MHz

with 2 × interpolating

[1] Pin to pin compatible

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

14 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

12. Package outline

HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad

SOT841-1

c

y

exposed die pad

X

D

h

A

60

41

Z

61

40

E

e

(A )

3

A

2

E

H

E

h

M

w

θ

b

p

A

1

L

p

L

detail X

pin 1 index

80

21

1

20

M

v

A

M

w

Z

D

b

p

e

D

B

M

H

D

B

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

1

A

2

A

3

b

c

D

E

e

H

D

H

E

L

v

w

y

Z

θ

p

h

p

D

E

max

°

0.15 1.05

0.05 0.95

0.27 0.20 12.1 6.05 12.1 6.05

0.17 0.09 11.9 5.95 11.9 5.95

14.15 14.15

13.85 13.85

0.75

0.45

1.45 1.45

1.05 1.05

7

0

mm

1.2

0.25

0.5

1

0.2 0.08 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

SOT841-1

04-01-15

MS-026

Fig 11. Package outline SOT841-1 (HTQFP80)

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

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DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

13. Abbreviations

Table 9.

Abbreviations

Description

Acronym

FIR

Finite Impulse Response

Intermediate Frequency

Least Signiﬁcant Bit

IF

LSB

MSB

PLL

Most Signiﬁcant Bit

Phase-Locked Loop

PMOS

Positive-Metal Oxide Semiconductor

14. Glossary

14.1 Static parameters

DNL — Differential Non-Linearity. The difference between the ideal and the measured

output value between successive DAC codes.

INL — Integral Non-Linearity. The deviation of the transfer function from a best-ﬁt straight

line (linear regression computation).

14.2 Dynamic parameters

IMD2 — Second-order intermodulation distortion. From a dual-tone digital input sine wave

(these two frequencies are close together), the intermodulation distortion product IMD2 is

the ratio of the RMS value of either tone and the RMS value of the worst 2nd-order

intermodulation product.

IMD3 — Third-order intermodulation distortion. From a dual-tone digital input sine wave

(these two frequencies are close together), the intermodulation distortion product IMD3 is

the ratio of the RMS value of either tone and the RMS value of the worst 3rd-order

intermodulation product.

SFDR — Spurious Free Dynamic Range. The ratio between the RMS value of the

reconstructed output sine wave and the RMS value of the largest spurious observed

(harmonic and non-harmonic, excluding DC component) in the frequency domain.

S/N — Signal-to-Noise ratio. The ratio of the RMS value of the reconstructed output sine

wave to the RMS value of the noise excluding the harmonics and the DC component.

THD — Total Harmonic Distortion. The ratio of the RMS value of the harmonics of the

output frequency to the RMS value of the output sine wave. Usually, the calculation of

THD is done on the ﬁrst 5 harmonics.

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

16 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

15. Revision history

Table 10. Revision history

Document ID

DAC1003D160_2

Modiﬁcations:

Release date

20080813

Data sheet status

Change notice

Supersedes

Product data sheet

-

DAC1003D160_1

• Added condition to t_sin Table 5.

• Correction to Figure 10.

DAC1003D160_1

20080612

Product data sheet

-

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

17 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

16.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

DAC1003D160_2

Product data sheet

Rev. 02 — 13 August 2008

18 of 19

DAC1003D160

NXP Semiconductors

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

18. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

Functional description . . . . . . . . . . . . . . . . . . . 6

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal characteristics. . . . . . . . . . . . . . . . . . . 7

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Application information. . . . . . . . . . . . . . . . . . 12

Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

8

9

10

11

11.1

12

13

14

14.1

14.2

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Static parameters . . . . . . . . . . . . . . . . . . . . . . 16

Dynamic parameters. . . . . . . . . . . . . . . . . . . . 16

15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 August 2008

Document identifier: DAC1003D160_2


型号：	DAC1003D160HW
厂家：	NXP
描述：	Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 双10位DAC ，高达160兆赫， 2×插值转换器数模转换器
文件：	总19页 (文件大小：113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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