DAC1008D650 [NXP]
Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface; 双10位DAC高达650 Msps的; 2 × ， 4 ×或8 ×插值与JESD204A接口
| 型号： | DAC1008D650 |
| 厂家： | 
NXP |
| 描述： | Dual 10-bit DAC up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface |
| 文件： | 总98页 (文件大小：2645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC1008D650
Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
with JESD204A interface
Rev. 1 — 1 October 2010
Preliminary data sheet
1. General description
The DAC1008D650 is a high-speed 10-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1008D650 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1008D650 also includes a 2×, 4× or 8× clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1008D650 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
Dual 10-bit resolution
IMD3: 76 dBc; fs = 640 Msps;
fo = 140 MHz
650 Msps maximum update rate
ACPR: 64 dBc; two carriers WCDMA;
fs = 640 Msps; fo = 133 MHz
Selectable 2×, 4× or 8× interpolation
Typical 1.20 W power dissipation at
4× interpolation, PLL off and 640 Msps
filters
Input data rate up to 312.5 Msps
Power-down mode and Sleep modes
Very low noise cap free integrated PLL Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency
Four JESD204A serial input lanes
On-chip 1.25 V reference
External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
LVDS compatible clock inputs
Internal digital offset control
Inverse (sin x) / x function
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Two’s complement or binary offset data Fully compatible SPI port
format
LMF = 421 or LMF = 211 support
Industrial temperature range from
−40 °C to +85 °C
Differential CML receiver with
Integrated PLL can be bypassed
embedded termination
Synchronization of multiple DAC outputs Embedded complex modulator
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
DAC1008D650HN
HVQFN64
plastic thermal enhanced very thin quad flat package; no leads; SOT804-3
64 terminals; body 9 × 9 × 0.85 mm
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
2 of 98
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5. Block diagram
SDO
SDIO
SCS_N
SCLK
NCO
10-BIT
OFFSET
CONTROL
SPI CONTROL REGISTERS
AUXAP
AUXAN
32-bit frequency setting
16-bit phase adjustment
AUX.
DAC
cos
sin
10-BIT
GAIN
CONTROL
SYNC_OUTP
SYNC_OUTN
DIGITAL LAYER
PROCESSING
JESD204A
FIR 1
FIR 2
FIR 3
IOUTAP
IOUTAN
VIN_P0
L0
VIN_N0
I DAC
X
Sin X
LANE
PROC
Σ
+
2 ×
2 ×
2 ×
VIN_P1
L1
VIN_N1
LANE
PROC
SINGLE
SIDE
BAND
REF.
BANDGAP
AND
VIRES
OFFSET
CONTROL
DAC1008D650HN
GAPOUT
MODULATOR
BIASING
VIN_P2
L2
VIN_N2
LANE
PROC
FIR 1
FIR 2
FIR 3
+
X
Sin X
VIN_P3
L3
VIN_N3
Σ
IOUTBP
IOUTBN
LANE
PROC
Q DAC
2 ×
2 ×
2 ×
10-BIT
GAIN
CONTROL
CLOCK GENERATOR UNIT
10-BIT
OFFSET
CONTROL
AUXBP
AUXBN
MULTI-DAC
SYNCHRONIZATION
AUX.
DAC
CLKINP
CLKINN
RESET_N
MDS_P
MDS_N
005aaa160
Fig 1. Block diagram
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SDO
SDIO
SCLK
n.c.
V
DDD(1V8)
3
MDS_N
MDS_P
4
V
DDD(1V8)
5
SCS_N
V
DDA(1V8)
6
RESET_N
n.c.
AGND
7
CLKINN
CLKINP
AGND
8
VIRES
DAC1008D650HN
9
GAPOUT
10
11
12
13
14
15
16
V
V
V
DDA(1V8)
DDA(1V8)
DDA(1V8)
V
DDA(1V8)
AGND
AGND
AUXBN
AUXBP
AUXAN
AUXAP
V
V
DDA(3V3)
DDA(3V3)
AGND
AGND
005aaa155
Transparent top view
Fig 2. Pin configuration
6.2 Pin description
Table 2.
Symbol
SDO
Pin description
Pin
1
Type[1] Description
O
I/O
I
SPI data output
SDIO
2
SPI data input/output
SPI clock
SCLK
3
VDDD(1V8)
SCS_N
RESET_N
n.c.
4
P
I
digital supply voltage 1.8 V
SPI chip select (active LOW)
general reset (active LOW)
not connected
5
6
I
7
-
VIRES
8
I/O
I/O
P
P
DAC biasing resistor
GAPOUT
VDDA(1V8)
VDDA(1V8)
9
bandgap input/output voltage
analog supply voltage 1.8 V
analog supply voltage 1.8 V
10
11
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
4 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 2.
Pin description …continued
Type[1] Description
Symbol
AGND
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
G
O
O
P
G
P
G
P
P
G
O
O
G
G
O
O
G
P
P
G
P
G
P
O
O
G
P
P
G
I
analog ground
AUXBN
AUXBP
VDDA(3V3)
AGND
complementary auxiliary DAC B output
auxiliary DAC B output
analog supply voltage 3.3 V
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
IOUTBN
IOUTBP
AGND
complementary DAC B output current
DAC B output current
analog ground
AGND
analog ground
IOUTAP
IOUTAN
AGND
DAC A output current
complementary DAC A output current
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
VDDA(3V3)
AUXAP
AUXAN
AGND
analog supply voltage 3.3 V
auxiliary DAC A output current
complementary auxiliary DAC A output current
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
CLKINP
CLKINN
AGND
clock input
I
complementary clock input
analog ground
G
P
I/O
I/O
P
-
VDDA(1V8)
MDS_P
MDS_N
VDDD(1V8)
n.c.
analog supply voltage 1.8 V
multi-device synchronization
complementary multi-device synchronization
digital supply voltage 1.8 V
not connected
VDDD(1V8)
SYNC_OUTN
P
O
digital supply voltage 1.8 V
synchronization request to transmitter, complementary
output
SYNC_OUTP
51
O
synchronization request to transmitter
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
5 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 2.
Pin description …continued
Type[1] Description
Symbol
VIN_N0
VIN_P0
VDDD(1V8)
VIN_P1
VIN_N1
VIN_N2
VIN_P2
VDDD(1V8)
VIN_P3
VIN_N3
n.c.
Pin
52
53
54
55
56
57
58
59
60
61
62
63
64
H[2]
I
serial interface lane 0 negative input
serial interface lane 0 positive input
digital supply voltage 1.8 V
I
P
I
serial interface lane 1 positive input
serial interface lane 1 negative input
serial interface lane 2 negative input
serial interface lane 2 positive input
digital supply voltage 1.8 V
I
I
I
P
I
serial interface lane 3 positive input
serial interface lane 3 negative input
not connected
I
-
n.c.
-
not connected
JTAG
I
JTAG test mode select (must be grounded)
ground
GND
G
[1] P: power supply; G: ground; I: input; O: output.
[2] H = heatsink (exposed die pad to be soldered to GND. A minimum of 81 thermal vias are required)
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA(3V3)
VDDA(1V8)
VDDD
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−55
−40
−40
Max
+4.6
+2.5
+2.5
+150
+85
Unit
V
[1]
[2]
[2]
analog supply voltage (3.3 V)
analog supply voltage (1.8 V)
digital supply voltage
storage temperature
ambient temperature
junction temperature
V
V
Tstg
°C
°C
°C
Tamb
Tj
+125
[1] The supply voltage VDDA(3V3) may have any value between −0.5 V and +4.6 V provided that the supply voltage differences ΔVCC are
respected.
[2] The supply voltages VDDA(1V8) and VDDD may have any value between −0.5 V and +2.5 V provided that the supply voltage differences
ΔVCC are respected.
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
18.7
6.7
Unit
K/W
K/W
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
Rth(j-c)
[1] Complies with JEDEC test board, in free air.
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
6 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
9. Characteristics
Table 5.
Characteristics
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
VDDA(3V3)
analog supply voltage
(3.3 V)
I
3.0
3.3
3.6
V
VDDD(1V8)
VDDA(1V8)
IDDA(3V3)
IDDD(1V8)
IDDA(1V8)
ΔIDDD
digital supply voltage
(1.8 V)
I
1.7
1.8
1.8
43
1.9
V
analog supply voltage
(1.8 V)
I
1.7
1.9
V
analog supply current fo = 19 MHz; fs = 640 Msps;
(3.3 V)
I
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
W
4× interpolation; NCO on
digital supply current
(1.8 V)
fo = 19 MHz; fs = 640 Msps;
4× interpolation; NCO on
I
361
373
48
analog supply current fo = 19 MHz; fs = 640 Msps;
(1.8 V)
I
4× interpolation; NCO on
digital supply current
difference
x/sin x function on;
fs = 640 Msps
I
Ptot
total power dissipation fs = 640 Msps;
4× interpolation; NCO off;
C
0.75
DAC Q off
fs = 640 Msps;
4× interpolation; NCO off
C
C
C
C
-
-
-
-
1.20
1.45
1.29
1.46
-
-
-
-
W
W
W
W
fs = 640 Msps;
4× interpolation; NCO on
fs = 625 Msps;
2× interpolation; NCO off
fs = 625 Msps;
2× interpolation; NCO on
Power-down mode;
fo = 19 MHz; fs = 640 Msps;
4× interpolation; NCO on
complete device;
Power-down mode
I
I
I
-
-
-
0.04
0.58
0.75
-
-
-
W
W
W
DAC A and DAC B;
Power-down mode
DAC A and DAC B;
Sleep mode
Timing specifications
td(startup)
td(restart)
tlock
start-up delay time
from full Power-down mode
from Sleep mode
D
D
D
-
-
-
20
-
-
-
ms
ns
μs
restart delay time
300
11
[2]
lock time
maximum input rate
Clock inputs (CLKINN, CLKINP)[3]
Vi
input voltage
range: CLK+ or CLK−
|Vgpd| < 50 mV[4]
C
825
-
1575
mV
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
7 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
Vidth
input differential
threshold voltage
|Vgpd| < 50 mV[4]
C
−100
-
+100
mV
Ri
CI
input resistance
D
D
-
-
10
-
-
MΩ
input capacitance
0.5
pF
Digital inputs (SDO, SDIO, SCLK, SCS_N, RESET_N)
VIL
VIH
IIL
LOW-level input
voltage
C
C
I
GND
-
0.54
V
HIGH-level input
voltage
1.26
-
VDDD
V
LOW-level input
current
VIL = 0.54 V
VIH = 1.26 V
-
-
1
1
-
-
μA
μA
IIH
HIGH-level input
current
I
Digital inputs (Vin_p/Vin_n)[5]
VI(cm)
common-mode input
voltage
D
D
0.68
175
0.78
-
1.40
V
VI(dif)(p-p)
peak-to-peak
differential input
voltage
1000
mV
Ztt
Vtt source impedance
D
D
-
-
0.7
-
-
Ω
Ω
ΔZi
differential input
impedance
100
Digital outputs (SYNC_OUTN/SYNC_OUTP)[6]
Vo(cm)
common-mode output
voltage
I
I
0.79
0.12
1.17
0.48
1.46
0.96
V
V
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
Digital inputs/outputs (MDS_N/MDS_P)
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
D
-
600
-
mV
Co(L)
CI
Output load
capacitance
between pins GND and
MDS_N or MDS_P
D
D
-
-
-
10
-
pF
pF
Input capacitance
between pins GND and
MDS_N or MDS_P
0.3
Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
IO(fs)
full-scale output
current
register value = 00h
(see Table 14 and Table 15)
D
-
-
1.6
20
-
-
mA
mA
register = default value
(see Table 14 and Table 15)
VO
Ro
output voltage
compliance range
D
D
1.8
-
-
VDDA(3V3)
-
V
output resistance
250
kΩ
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
8 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Co
Parameter
Conditions
Test[1]
Min
Typ
3
Max
Unit
output capacitance
offset error variation
gain error variation
D
C
C
-
-
-
-
-
-
pF
ΔEO
6
ppm/°C
ppm/°C
ΔEG
18
Reference voltage output (GAPOUT)
VO(ref)
reference output
voltage
C
C
C
<tbd>
1.25
40
<tbd>
V
IO(ref)
reference output
current
external voltage 1.2 V
-
-
-
-
μA
ΔVO(ref)
reference output
voltage variation
117
ppm/°C
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
IO(aux)
auxiliary output current differential outputs
I
-
2.2
-
-
mA
V
VO(aux)
auxiliary output
voltage
compliance range
D
0
2
NDAC(aux)mono auxiliary DAC
monotonicity
guaranteed
D
-
10
-
bits
Input timing (Vin_p/Vin_n)
fdata
data rate
2× interpolation
4× interpolation
8× interpolation
serial input
D
D
D
D
-
-
-
-
-
312.5
162.5
81.25
3.125
Msps
Msps
Msps
Gbps
-
-
fbit
bit rate
0.5
Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
fs
ts
sampling rate
settling time
D
D
-
-
-
650
-
Msps
ns
up to 0.5 LSB
20
NCO frequency range; fs = 650 Msps
fNCO
NCO frequency
register value = 00000000h
(see Table 22 to Table 25)
D
D
D
-
-
-
0
-
-
-
MHz
MHz
MHz
register value = FFFFFFFFh
(see Table 22 to Table 25)
650
0.151
fstep
step frequency
Low power NCO frequency range; fs = 650 Msps
fNCO
NCO frequency
reg value = 00000000h
(see Table 22 to Table 25)
D
D
D
-
-
-
0
-
-
-
MHz
MHz
MHz
reg value = F8000000h
(see Table 22 to Table 25)
630
20.3
fstep
step frequency
Dynamic performances
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
9 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
dBc
dBc
SFDR
spurious-free dynamic fdata = 80 Msps;
range
fs = 640 Msps; ×8;
BW = fdata / 2; PLL on
fo = 4 MHz at −1 dBFS
C
C
-
-
76
-
-
fdata = 160 Msps;
fs = 640 Msps; ×4;
BW = fdata / 2
fo = 19 MHz at −1 dBFS
74
fdata = 312.5 Msps;
fs = 625 Msps; ×2;
BW = fdata / 2
fo = 19 MHz at −1 dBFS
I
I
-
-
74
80
-
-
dBc
dBc
SFDRRBW
restricted bandwidth
fs = 640 Msps;
spurious-free dynamic 4× interpolation;
range
fo = 133 MHz at −1 dBFS;
BW = 100 MHz
fs = 640 Msps;
C
-
84
-
dBc
4× interpolation;
fo = 133 MHz at −1 dBFS;
BW = 20 Mhz
[7]
[7]
IMD3
third-order
intermodulation
distortion
fo1 = 95 MHz; fo2 = 97 MHz;
fs = 640 Msps;
4× interpolation
C
I
-
-
79
76
dBc
dBc
fo1 = 153.1 MHz;
fo2 = 154.1 MHz;
fs = 640 Msps;
4× interpolation
-
-
[7]
f
o1 = 137 MHz;
C
-
76
dBc
fo2 = 143 MHz;
fs = 640 Msps;
4× interpolation
ACPR
adjacent channel
power ratio
NCO on; 4× interpolation;
fs = 640 Msps; fo = 96 MHz
1 carrier; BW = 5 MHz
2 carriers; BW = 10 MHz
4 carriers; BW = 20 MHz
C
C
C
-
-
-
67
64
60
-
-
-
dBc
dBc
dBc
NCO on; 4× interpolation;
fs = 640 Msps; fo = 133 MHz
1 carrier; BW = 5 MHz
2 carriers; BW = 10 MHz
4 carriers; BW = 20 MHz
C
C
C
-
-
-
67
64
59
-
-
-
dBc
dBc
dBc
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Table 5.
Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
NSD
noise spectral density fs = 640 Msps;
I
-
−145
-
dBm/Hz
4× interpolation;
fo = 133 MHz at 0 dBFS
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It
reflects the delay required by DAC1008D650 to lock to a JESD204A stream. It supposes that the TX is already transmitting
K28.5 characters in error-free conditions.
[3] CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 Ω and 120 Ω (see
Figure 16) should be connected across the pins.
[4] |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
and the inductance between the receiver and the driver circuit ground voltage.
[5] Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to Vtt via 50 Ω (see Figure 4).
[6] SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 Ω
and 120 Ω.
[7] IMD3 rejection with −6 dBFS/tone.
10. Application information
10.1 General description
The DAC1008D650 is a dual 10-bit DAC operating up to 650 Msps. With a maximum input
data rate of up to 312.5 Msps and a maximum output sampling rate of 650 Msps, the
DAC1008D650 allows more flexibility for wide bandwidth and multi-carrier systems.
Combined with its quadrature modulator and 32-bit NCO, the DAC1008D650 simplifies
the frequency selection of the system. This is also possible because of the 2×, 4× or 8×
interpolation filters which remove undesired images.
DAC1008D650 supports the following JESD204A key features:
• 10-bit/8-bit decoding
• Code group synchronization
• inter-lane alignment
• 1 + x14 + x15 scrambling polynomial
• Character replacement
• TX/RX synchronization management via SYNC signals
• Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device
DAC1008D650 can be interfaced with any logic device that features high-speed SERDES
functionality. This macro is now widely available in FPGA from different vendors.
Standalone SERDES ICs can also be used.
To enhance the intrinsic board layout simplification of the JESD204A standard, NXP
includes polarity swapping for each of the lanes and additionally offers lane swapping.
Each physical lane can be configured logically as lane0, lane1, lane2 or lane3.
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This device is MCDA-ML compliant and offers inter-lane alignment between several
devices. Samples alignment between devices is maintained up to output level because of
an NXP proprietary mechanism. One device is configured as the master and all the others
are configured as slaves. These will automatically align their output samples to the master
ones. Therefore, a system with several DAC1008D650s can produce data with a
guaranteed alignment of less than 1 DAC output clock period.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
The DAC1008D650 must be configured before operating. Therefore, it features an SPI
slave interface to access internal registers. Some of these registers also provide
information about the JESD204A interface status.
The DAC1008D650 requires supplies of both 3.3 V and 1.8 V. The 1.8 V supply has
separate digital and analog power supply pins. The clock input is LVDS compliant.
10.2 JESD204A receiver
internal
configuration
interface
RX CONTROLLER
8b
K-DETECT
SYNC_OUT
lane#
10b
SYNC
AND
WORD
ALIGN
8b
8b
8b
8b
10b
10b
8b
10b
10b
CLOCK
ALIGN
DES
DESCRAMBLER
10b/8b
frame
clock
005aaa157
The descrambler can be enabled/disabled
Fig 3. JESD204A receiver
The JEDEC204A defines the following parameters:
L is the number of lanes per link
M is the number of converters per device
F is the number of bytes per frame clock period
The DAC1008D650 supports both LMF = 421 and LMF = 211. The current setting is
configurable via the SPI registers interface.
The complete Digital Layer Processing (DLP) adds a variable delay on each lane path.
This is mainly because of the inter-lane alignment.
Table 6.
Digital Layer Processing Latency
Symbol Parameter Conditions
Test[1] Min
13
Typ
Max
Unit
cycle[2]
td
delay time
digital layer processing
delay
D
-
28
[1] D = guaranteed by design.
[2] Frame clock cycle.
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10.2.1 Lane input
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50 Ω
resistor.
Vin_p
50 Ω
50 Ω
Vin_n
Z
tt
V
tt
001aak166
Fig 4. Lane input termination
The common-mode voltage is programmable by the SET_VCM_VOLTAGE register as
shown in Table 76 on page 55.
DC coupling is only possible if both the DAC and the transmitter have the same
common-mode voltage. If this is not the case AC coupling is required.
V
DD1
V
DD2
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Z
= 100 Ω
diff
Z
= 100 Ω
diff
data in +
data in +
data in −
data in −
001aak162
001aak163
Fig 5. DC coupling
Fig 6. AC coupling
The deserializer performs the incoming data clock recovery and also the serial to parallel
conversion. Therefore, each lane includes its own PLL that must first lock.
The clock alignment module transfers the data from the regenerated clock to the frame
clock domain. The frequency of both clocks is the same but the phase relationship
between the clocks is unknown.
10.2.2 Sync and word align
As stated in JESD204A, the transmitter and the receiver first have to synchronize. This is
achieved through SYNC_OUT signals and a sync pattern (K28.5 symbol). The receiver
(i.e. DAC1008D650) first drives its SYNC_OUT outputs. The sync pattern is continuously
sent until the receiver deasserts the SYNC_OUT signal.
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The lane processing makes use of the sync patterns to synchronize the datastream,
determine the initial running disparity and extract the 10-bit word from the incoming
datastream (word-alignment).
The SYNC_OUT signal is also used during normal operation by the DAC1008D650 to
request a link reinitialization. This occurs when the 10b/8b module loses synchronization.
The SYNC_OUT signal conforms to LVDS signaling. Its common-mode voltage and its
single-ended peak amplitude can be programmed using SET_SYNC_LEVEL bits in the
SET_SYNC registers (see Table 78 on page 55).
SYNC_OUT is synchronous with the frame clock.
t
FS_R(max)
t
FS_R(min)
SYNC_OUT
CLK
001aak165
tFS_R(min) and tFS_R(max) are defined in the JEDEC standard No. 204A.
Fig 7. SYNC_OUT timing
Table 7.
Symbol Parameter Conditions
td delay time frame clock to sync
SYNC_OUT timing
Test[1] Min
<tbd>
Typ
Max
Unit
C
-
<tbd>
ns
[1] C = guaranteed by characterization.
10.2.3 Comma detection and word align
This stage monitors the datastream for code characters (comma detection), decodes the
words to bytes (octets) and performs optional character replacement as part of frame/lane
alignment monitoring and correction. This module provides the required control signals to
the RX controller and ILA.
This module decodes the 10-bit words into 8-bit words (octets). The decoding table is
specified in the IEEE 802.3-2005 specification. During decoding, the disparity is
calculated according to the disparity rules mentioned in the same specification
IEEE 802.3-2005. When the disparity counter is more than +2 or less than −2, an error will
be generated.
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The following comma symbols are detected during data transmission irrespective of the
running disparity:
/K/ = K28.5
/F/ = K28.7
/A/ = K28.3
/R/ = K28.0
/Q/ = K28.4
A flag is sent to the control interface to reflect detected commas in registers.
The following flags are also triggered according to the following definitions:
• VALID: a code group that is found in the column of the 10b/8b decoding tables
according to the current running disparity.
• DISPARITY ERROR: The received code group exists in the 10b/8b decoding table,
but is not found in the proper column according to the current running disparity.
• NOT-IN-TABLE (NIT) ERROR: The received code group is not found in the 10b/8b
decoding table for either disparity.
• INVALID: a code group that either shows a disparity error or that does not exist in the
10b/8b decoding table.
DAC1008D650 supports character replacement whatever the state of the descrambler.
When scrambling is not active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the
previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or
D28.7 (0xFC) will be used.
10.2.4 Descrambler
The descrambler is a 16-bit parallel self-synchronous descrambler based on the
polynomial 1 + x14 + x15. This processing can be turned off.
10.2.5 Inter-lane alignment
This feature removes strict PCB design skew compensation between the lanes.
10.2.5.1 Single device operation
This module handles the alignment of the four data streams. Because of inter-lane skew
and each PLL per lane concept, these alignment characters may be received at different
times by the receivers. After the synchronization period, the lock signal will be HIGH. This
enables the receipt of K28.3 /A/ characters.
The ILA_CNTRL register’s SEL_ILA[1:0] bits select which K28.3 /A/ symbol triggers the
initial lane alignment:“00” = 1st /A/ symbol, “01” = 2nd /A/ symbol, “10” = 3rd /A/ symbol,
“11” = 4th /A/ symbol; Table 87 on page 61. When all receivers have received their first
selected /A/, they start propagating the received data to the frame assembly module at the
same point in time.
This module can compensate up to ±7 frame clock period misalignments between the
lanes.
When initial lane alignment is not supported, the manual alignment mode can be used.
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After the initial ILA sequence, the lane alignment monitoring starts. When a K28.3 /A/
symbol is received among the user data:
• its position is compared to the value of the alignment monitor counter
• if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
• if the buffers are empty or overflow, this is indicated by the registers
ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3
10.2.5.2 Multi-device operation
DAC1008D650 implements a multi-device inter-lane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: master/slave and all slave. Both make use of the MDS_P and
MDS_N pins.
mds_A_out
MDS_A
ref_A
COMP
mds_A
I
LANES
SYNC~
DIG
BUFFER
Q
CLK
MGMT
DAC
CK
001aal073
Fig 8. Multi-Device Synchronization (MDS) implementation
Each DAC device of the system generates its own reference (ref_A in Figure 8).
If configured as a slave, an early-late comparator compares the internal reference with the
external reference provided by the MDS pins. The comparator controls an internal buffer
that is used to delay the samples.
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10.2.5.3 Master/slave mode
The external reference is provided by one of the DACs (the master DAC), which has to be
configured to do this. The others are set to slave mode.
mds_out
ref_A
COMP
mds_in
I
MASTER
DIG
BUFFER
DAC 0
Q
CLK
MGMT
SYNC_0
SYNC_1
SYNC_2
DAC
mds_out
ref_A
COMP
mds_in
I
SLAVE
DAC 1
DIG
BUFFER
Q
CLK
MGMT
TX
DAC
mds_out
ref_A
COMP
mds_in
I
SLAVE
DAC 2
DIG
BUFFER
Q
CLK
MGMT
DAC
CLOCK
DISTRIBUTION
REF_CLOCK
001aal070
Fig 9. Master-slave mode
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The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges will reach each of the
DACs at different times.
TDAC
ref clock
PH01
master clock
PH02
slave 1 clock
PH03
slave 2 clock
001aal072
Fig 10. Clock skew case 1: Master is the farthest
The worst case clock skew is given by δt1 = PH01 − PH03, where PH0x represents the
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by Δt = TDAC − δt1.
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TDAC
ref clock
master clock
slave 1 clock
slave 2 clock
PH01
PH02
PH03
001aal071
Fig 11. Clock skew case 2: Master is closest
The worst case clock skew is given by δt2 = PH03 − PH01.
The minimum allowable trace delay for the MDS signal is given by Δt = δt2.
In real applications, the master DAC can be anywhere and both conditions must be
satisfied: δt2 < Δtmds < TDAC − δt1.
Example:
• clock generator skew = ± 80 ps
• FR4 substrate ⇒ 15 cm/ns delay
• clock trace length difference = 3 cm and 4 cm
• Output sampling rate = 650 Msps
⇒ 200 ps + 80 ps < Δtmds < 1538 ps − (266 ps + 80 ps)
⇒ 280 ps < Δtmds < 1192 ps
⇒ 4.2 cm < Lmds < 17.8 cm
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10.2.5.4 All slave mode
The external reference is provided by the JESD204A transmitter. All DACs are configured
in slave mode.
mds_out
ref_A
COMP
JESD204A
mds_in
TX
I
SLAVE
DAC 0
DIG
BUFFER
Q
CLK
MGMT
SYNC_0
SYNC_1
SYNC_2
DAC
mds_out
ref_A
COMP
mds_in
I
SLAVE
DAC 1
DIG
BUFFER
Q
/A/
CLK
MGMT
INSERTION
DAC
mds_out
ref_A
COMP
mds_in
I
SLAVE
DAC 2
DIG
BUFFER
Q
CLK
MGMT
DAC
dT
MDS
CLOCK
DISTRIBUTION
REF_CLOCK
001aal069
Fig 12. All slave mode
The MDS signal is now driven from the transmitter. It is generated at the end of the
inter-lane alignment phase (see the JESD204A standard for details).
The transmitter must also compensate for the DAC latency. Although the DAC has an
internal samples delay line, it cannot handle large delays.
In this mode, PCB layout is also important. The following delay equation applies:
δt < Δtmds < TDAC − δt, where δt is the clock skew considered close to DAC pins.
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10.2.6 Frame assembly
DAC1008D650 supports only /F/ = 1, which means that every frame clock period carries
one byte per lane. Frame assembly combines the octet of lane_0 with the two MSB bits of
lane_1 and reassembles the original 10-bit sample. The same is done for lane_2 and
lane_3. Tail bits are dropped.
The frame assembler also handles previously triggered errors.
If scrambling is enabled:
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 10-bit sample is repeated twice for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
If scrambling is disabled:
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 10-bit sample will be repeated once for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
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CHARACTER CLOCK
312.5 MHz
FRAME CLOCK
312.5 MHz
SERIAL CLOCK
3.125 GHz
encoded
octet
/F
scrambled
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
octet
S7
S6
S5
S4
S3
S2
S1
S0
ON/OFF
ON/OFF
ON/OFF
ON/OFF
byte 0
/10
/10
/10
/10
D09
D08
D07
D06
D05
D04
D03
D02
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
lane 0
encoded
octet
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
scrambled
octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
byte 1
S7
S6
S5
S4
S3
S2
S1
S0
D01
D00
T
DAC0
M = 2 converters
DAC1
T
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
T
T
T
T
lane 1
F = 1 byte
encoded
octet
scrambled
octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
byte 2
D09
D08
D07
D06
D05
D04
D03
D02
S7
S6
S5
S4
S3
S2
S1
S0
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
lane 2
encoded
octet
scrambled
octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
byte 3
S7
S6
S5
S4
S3
S2
S1
S0
D01
D00
T
T
T
T
T
T
lane 3
005aaa153
Fig 13. Frame assembly
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10.3 Serial Peripheral Interface (SPI)
10.3.1 Protocol description
The DAC1008D650 serial interface is a synchronous serial communication port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that define the operating modes of the chip in both Write mode and Read mode.
This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pin, input and output port respectively). In both
configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with two bytes to five bytes, depending on the content of the
instruction byte (see Table 9).
RESET_N
SCS_N
SCLK
SDIO
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SDO
(optional)
001aaj812
R/W indicates the mode access, (see Table 8).
Fig 14. SPI protocol
Table 8.
Read or Write mode access description
Description
R/W
0
Write mode operation
1
Read mode operation
In Table 9 below, N1 and N0 indicate the number of bytes transferred after the instruction
byte.
Table 9.
Number of bytes to be transferred
N1
0
N0
0
Number of bytes transferred
1
2
3
4
0
1
1
0
1
1
A[4:0] indicates which register is being addressed. In the case of a multiple transfer, this
address points to the first registerto be accessed. The address is then internally
decreased after each following data phase.
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10.3.2 SPI timing description
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure 15.
t
w(RESET_N)
RESET_N
SCS_N
50 %
t
t
h(SCS_N)
su(SCS_N)
50 %
t
w(SCLK)
SCLK
SDIO
50 %
50 %
t
h(SDIO)
su(SDIO)
t
001aaj813
Fig 15. SPI timing diagram
The SPI timing characteristics are given in Table 10.
Table 10. SPI timing characteristics
Symbol
fSCLK
Parameter
Min
-
Typ
Max
Unit
MHz
ns
SCLK frequency
SCLK pulse width
SCS_N set-up time
SCS_N hold time
SDIO set-up time
SDIO hold time
-
-
-
-
-
-
-
15
-
tw(SCLK)
tsu(SCS_N)
th(SCS_N)
tsu(SDIO)
th(SDIO)
30
20
20
10
5
-
ns
-
ns
-
ns
-
ns
tw(RESET_N)
RESET_N pulse width
30
-
ns
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10.4 Clock input
The DAC1008D650 has one differential clock input, CLKINN/CLKINP.
CLKINP
LVDS
LVDS
Z
diff
= 100 Ω
100 Ω
CLKINN
001aah021
Fig 16. LVDS clock configuration
V
DDA(1V8)
1.1 kΩ
100 nF
CLKINP
55 Ω
LVDS
CML
Z
diff
= 100 Ω
100 Ω
55 Ω
100 nF
CLKINN
100 nF
2.2 kΩ
AGND
001aah020
Fig 17. Interfacing CML to LVDS
The DAC1008D650 can operate with a clock frequency up to 312.5 MHz or up to
650 MHz if the internal PLL is bypassed. The clock input can be LVDS (see Figure 16) but
it can also be interfaced with CML (see Figure 17).
During the reset phase (RESET_N asserted), the clock must be stable and running. This
ensures a proper reset of the complete device.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
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10.5 FIR filters
The three interpolation FIR filters have a stop band attenuation of at least 80 dBc and a
pass band ripple of less than 0,0005 dB.
Table 11. Interpolation filter coefficients
First interpolation filter
Second interpolation filter
Third interpolation filter
Lower
H(1)
Upper
H(55)
H(54)
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(47)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
-
Value
−4
Lower
Upper
Value
Lower
Upper
Value
H(1)
H(23)
−2
H(1)
H(15)
−39
H(2)
0
H(2)
H(22)
0
H(2)
H(14)
0
H(3)
13
H(3)
H(21)
17
H(3)
H(13)
273
H(4)
0
H(4)
H(20)
0
H(4)
H(12)
0
H(5)
−34
0
H(5)
H(19)
−75
H(5)
H(11)
−1102
H(6)
H(6)
H(18)
0
H(6)
H(10)
0
H(7)
72
H(7)
H(17)
238
H(7)
H(9)
4964
H(8)
0
H(8)
H(16)
0
H(8)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8192
H(9)
−138
0
H(9)
H(15)
−660
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
H(28)
H(10)
H(14)
0
245
0
H(11)
H(13)
2530
H(12)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4096
−408
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
650
0
−1003
0
1521
0
−2315
0
3671
0
−6642
0
20756
32768
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10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO)
The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier
signal generated by the NCO.
The frequency of the NCO is programmed over 32 bits and the sign of the sine component
can be inverted in order to operate positive or negative, lower or upper single sideband
up-conversion.
10.6.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB,
FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits.
The frequency for the NCO in 32-bit is calculated as follows:
M × fs
232
fNCO
=
(1)
--------------
where M is the decimal representation of FREQ_NCO[31:0].
The phase of the NCO can be set from 0° to 360° by both registers PHINCO_LSB and
PHINCO_MSB over 16 bits.
The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0°.
10.6.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the five MSBs of register
FREQNCO_MSB.
The frequency for the low-power NCO is calculated as follows:
M × fs
25
fNCO
=
(2)
--------------
where M is the decimal representation of FREQ_NCO[31:27].
The phase of the low-power NCO can be set by the five MSBs of the register
PHINCO_MSB.
10.6.3 Minus_3dB
During normal use, a full-scale pattern will also be full-scale at the output of the DAC.
Nevertheless, when the I and Q data are simultaneously close to full-scale, some clipping
can occur and the minus_3dB function can be used to reduce the gain in the modulator by
3 dB. This is to keep a full-scale range at the output of the DAC without added interferers.
10.7 x / (sin x)
The roll-off effect of the DAC causes a selectable FIR filter to be inserted to compensate
for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are
represented in Table 12.
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Table 12. Inversion filter coefficients
First interpolation filter
Lower
H(1)
H(2)
H(3)
H(4)
H(5)
Upper
H(9)
H(8)
H(7)
H(6)
-
Value
2
−4
10
−35
401
10.8 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
IO(fs) = IIOUTP + IIOUTN
(3)
The output current depends on the digital input data:
DATA
1023
⎛
⎝
⎞
⎠
---------------
IIOUTP = IO(fs)
×
×
(4)
(5)
1023 – DATA
⎛
⎝
⎞
⎠
---------------------------------
IIOUTN = IO(fs)
1023
The setting applied to register COMMON bit DF (register 00h[2]; see Table 18 “Page 0
register allocation map”) defines whether the DAC1008D650 operates with a binary input
or a two’s complement input.
Table 13 shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 13. DAC transfer function
Data
I9/Q9 to I0/Q0
Binary
IOUTnP
IOUTnN
Two’s complement
10 0000 0000
...
0
00 0000 0000
...
0 mA
...
20 mA
...
...
2048
...
10 0000 00 00
...
00 0000 0000
...
10 mA
...
10 mA
...
4095
11 1111 1111
01 1111 1111
20 mA
0 mA
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10.9 Full-scale current
10.9.1 Regulation
The DAC1008D650 reference circuitry integrates an internal bandgap reference voltage
which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin
GAPOUT using a 100 nF capacitor.
The reference current is generated via an external resistor of 909 Ω (1 %) connected to
pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs
(see Figure 18).
REF.
BANDGAP
100 nF
GAPOUT
AGND
909 Ω
(1 %)
DAC
VIRES
CURRENT
SOURCES
ARRAY
AGND
001aaj816
Fig 18. Internal reference configuration
This configuration is optimum for temperature drift compensation because the bandgap
reference voltage can be matched to the voltage across the feedback resistor.
10.9.1.1 External regulation
The DAC current can also be set by applying an external reference voltage to the
non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage
with bit GAP_PD (register 00h[0]; see Table 19 “COMMON register (address 00h) bit
description”).
10.9.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the
user to both DACs independently using the serial interface from 1.6 mA to 22 mA, ± 10 %.
The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 29
“DAC_A_CFG_2 register (address 0Ah) bit description” and register 0Bh; see Table 30
“DAC_A_CFG_3 register (address 0Bh) bit description”) and DAC_B_GAIN COARSE[3:0]
(register 0Dh; see Table 32 “DAC_B_CFG_2 register (address 0Dh) bit description” and
register 0Eh; see Table 33 “DAC_B_CFG_3 register (address 0Eh) bit description”) define
the coarse variation of the full-scale current (see Table 14).
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Table 14. IO(fs) coarse adjustment
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
IO(fs) (mA)
Decimal
Binary
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.6
1
3.0
2
4.4
3
5.8
4
7.2
5
8.6
6
10.0
11.4
12.8
14.2
15.6
17.0
18.5
20.0
21.0
22.0
7
8
9
10
11
12
13
14
15
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 29
“DAC_A_CFG_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0]
(register 0Dh; see Table 32 “DAC_B_CFG_2 register (address 0Dh) bit description”)
define the fine variation of the full-scale current (see Table 15).
Table 15. IO(fs) fine adjustment
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0]
Delta IO(fs)
Decimal
Two’s complement
−32
...
10 0000
...
−10 %
...
0
00 0000
...
0
...
...
31
01 1111
+10 %
The coding of the fine gain adjustment is two’s complement.
10.10 Digital offset correction
When the DAC1008D650 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common-mode level at the output of the DAC.
It adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (register 09h; see Table 28
“DAC_A_CFG_1 register (address 09h) bit description” and register 0Bh; see Table 30
“DAC_A_CFG_3 register (address 0Bh) bit description”) and to “DAC_B_OFFSET[11:0]”
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(register 0Ch; see Table 31 “DAC_B_CFG_1 register (address 0Ch) bit description” and
register 0Eh; see Table 33 “DAC_B_CFG_3 register (address 0Eh) bit description”) define
the range of variation of the digital offset (see Table 16).
Table 16. Digital offset adjustment
Default settings are shown highlighted.
DAC_OFFSET[11:0]
Offset applied
Decimal
−2048
−2047
...
Two’s complement
1000 0000 0000
1000 0000 0001
...
−4096
−4094
...
−1
1111 1111 1111
0000 0000 0000
0000 0000 0001
...
−2
0
0
+1
+2
...
...
2046
2047
0111 1111 1110
0111 1111 1111
+4092
+4094
10.11 Analog output
The DAC1008D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a
load resistor RL to the 3.3 V analog power supply (VDDA(3V3)).
The equivalent analog output circuit of one DAC is shown in Figure 19. This circuit
consists of a parallel combination of NMOS current sources and their associated switches
for each segment.
V
DDA(3V3)
R
R
L
L
IOUTAP/IOUTBP
IOUTAN/IOUTBN
001aah019
AGND
AGND
Fig 19. Equivalent analog output circuit (one DAC)
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level (Vo(p-p)) of up to 2 V, depending on the application,
the following stages and the targeted performances.
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10.12 Auxiliary DACs
The DAC1008D650 integrates two auxiliary DACs that can be used to compensate for
any offset between the DAC and the next stage in the transmission path.
Both auxiliary DACs have a 10-bit resolution and are current sources (referenced to
ground).
IO(AUX) = IAUXP + IAUXN
(6)
The output current depends on the auxiliary DAC data:
AUX[9:0]
⎛
⎝
⎞
⎠
------------------------
AUXP = IO(AUX)
AUXN = IO(AUX)
×
×
(7)
(8)
1023
(1023–AUX[9:0])
⎛
⎝
⎞
⎠
---------------------------------------------
1023
Table 17 shows the output current as a function of the auxiliary DAC data.
Table 17. Auxiliary DAC transfer function
Default settings are shown highlighted.
Data
0
AUX[9:0] (binary)
00 0000 0000
...
IAUXP
0 mA
...
IAUXN
2.2 mA
...
...
512
...
10 0000 0000
...
1.1 mA
...
1.1 mA
...
1023
11 1111 1111
2.2 mA
0 mA
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10.13 Output configuration
10.13.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion
performance (see Figure 20). In addition, it helps to match the impedance and provides
electrical isolation.
V
DDA(3V3)
50 Ω
0 mA to 20 mA
0 mA to 20 mA
2:1
IOUTnP
IOUTnN
50 Ω
50 Ω
V
DDA(3V3)
IOUTnP/IOUTnN; V
= 2.8 V; V
= 1 V
o(cm)
o(dif)(p-p)
001aaj817
Fig 20. 1 Vo(p-p) differential output with transformer
The DAC1008D650 can operate at a Vo(p-p) of 2 V differential outputs. In this
configuration, it is recommended to connect the center tap of the transformer to a 62 Ω
resistor connected to the 3.3 V analog power supply in order to adjust the DC
common-mode to approximately 2.7 V (see Figure 21).
V
V
DDA(3V3)
DDA(3V3)
100 Ω
62 Ω
0 mA to 20 mA
0 mA to 20 mA
4:1
IOUTnP
IOUTnN
50 Ω
100 Ω
V
DDA(3V3)
IOUTnP/IOUTnN; V
= 2.7 V; V
= 2 V
o(cm)
o(dif)(p-p)
001aaj818
Fig 21. 2 Vo(p-p) differential output with transformer
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10.13.2 DC interface to an Analog Quadrature Modulator (AQM)
When the system operation requires to keep the DC component of the spectrum, the
DAC1008D650 must use a DC interface to connect to an AQM. In this case, the offset
compensation for LO cancellation can be made with the use of the digital offset control in
the DAC.
Figure 22 is an example of a connection to an AQM with a common-mode input level
(Vi(cm)) of 1.7 V.
V
AQM (V = 1.7 V)
i(cm)
DDA(3V3)
(1)
(2)
51.1 Ω
51.1 Ω
442 Ω
442 Ω
IOUTnP
IOUTnN
BBP
BBN
0 mA to 20 mA
768 Ω
768 Ω
(1)
IOUTnP/IOUTnN; V
= 2.67 V; V
= 1.98 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 1.7 V; V
= 1.26 V
i(cm)
i(dif)(p-p)
001aaj541
Fig 22. Example of a DC interface to an AQM with a Vi(cm) of 1.7 V
Figure 23 is an example of a connection to an AQM with a common-mode input level
(Vi(cm)) of 3.3 V.
V
5 V
AQM (V = 3.3 V)
i(cm)
DDA(3V3)
(1)
(2)
54.9 Ω
54.9 Ω
750 Ω
750 Ω
237 Ω
237 Ω
IOUTnP
IOUTnN
BBP
BBN
1.27 kΩ
1.27 kΩ
(1)
(2)
IOUTnP/IOUTnN; V
= 2.75 V; V
= 1.97 V
o(cm)
o(dif)(p-p)
BBP/BBN; V
= 3.3 V; V
= 1.5 V
001aaj542
i(cm)
i(dif)(p-p)
Fig 23. Example of a DC interface to an AQM with a Vi(cm) of 3.3 V
The auxiliary DACs can be used to control the offset in a precise range or with precise
steps.
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Figure 24 is an example of a DC interface connected to an AQM with a common-mode
input level (Vi(cm)) of 1.7 V when using auxiliary DACs.
V
AQM (V = 1.7 V)
i(cm)
DDA(3V3)
(1)
(2)
51.1 Ω
51.1 Ω
442 Ω
442 Ω
IOUTnP
IOUTnN
BBP
BBN
0 mA to 20 mA
698 Ω
698 Ω
AUXnP
AUXnN
1.1 mA (typ.)
51.1 Ω
51.1 Ω
(1)
IOUTnP/IOUTnN; V
= 2.67 V; V
= 1.94 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 1.7 V; V
= 1.23 V; offset correction up to 36 mV
i(cm)
i(dif)(p-p)
001aaj543
Fig 24. Example of a DC interface to an AQM with a Vi(cm) of 1.7 V when using auxiliary
DACs
Figure 25 is an example of a DC interface connected to an to an AQM with a
common-mode input level (Vi(cm)) of 3.3 V when using auxiliary DACs.
AQM (V
= 3.3 V)
i(cm)
3.3 V
5 V
54.9 Ω
54.9 Ω
634 Ω
750 Ω
750 Ω
(1)
(2)
237 Ω
237 Ω
IOUTnP
BBP
BBN
IOUTnN
634 Ω
442 Ω
AUXnP
AUXnN
442 Ω
(1)
IOUTnP/IOUTnN; V
= 2.75 V; V
= 1.96 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 3.3 V; V
= 1.5 V; offset correction up to 36 mV
i(cm)
i(dif)(p-p)
001aaj544
Fig 25. Example of a DC interface to an AQM with a Vi(cm) of 3.3 V when using auxiliary
DACs
The constraints to adjusting the interface are the output compliance range of the DAC and
the auxiliary DACs, the input common-mode level of the AQM, and the range of offset
correction.
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10.13.3 AC interface to an Analog Quadrature Modulator (AQM)
When the AQM common-mode voltage is close to ground, the DAC1008D650 must be
AC-coupled and the auxiliary DACs are needed for offset correction.
Figure 26 is an example of a connection to an AQM with a common-mode input level
(Vi(cm)) of 0.5 V when using auxiliary DACs.
V
5 V
AQM (V = 0.5 V)
i(cm)
DDA(3V3)
(1)
(2)
66.5 Ω
66.5 Ω
2 kΩ
2 kΩ
10 nF
10 nF
IOUTnP
IOUTnN
BBP
BBN
0 mA to 20 mA
174 Ω
34 Ω
174 Ω
34 Ω
AUXnP
AUXnN
1.1 mA (typ.)
(1)
IOUTnP/IOUTnN; V
= 2.65 V; V
= 1.96 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 0.5 V; V
= 1.96 V; offset correction up to 70 mV
i(cm)
i(dif)(p-p)
001aaj589
Fig 26. Example of a DC interface to an AQM with a Vi(cm) of 0.5 V when using auxiliary
DACs
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10.13.4 Phase correction
The Analog Quadrature Modulator which follows the DACs may have a phase imbalance
which will result in undesired sidebands. By adjusting the phase between the I and Q
channels, the spur can be reduced.
Without compensation the I and Q have a phase difference of Π / 2 (90°). The registers
PHASECORR_CNTRL0 and PHASECORR_CNTRL1 located in register page 0 allow a
phase variation from 75,7° to 104,3°. The two registers define a signed value that ranges
from −512 to +511. The resulting phase compensation (in radians) is given by the
equation: PHASE_CORR[9:0] / 2048.
10.14 Power and grounding
The power supplies should be decoupled with the following ground pins to optimize the
decoupling:
• VDDA(1V8): pin 38 with pin 37; pin 44 with pin 43; pin 11 with pin 12; pin 17 with pin 18;
pin 32 with pin 31
10.15 Configuration interface
10.15.1 Register description
DAC1008D650 implements indirect addressing using a page access method. The
page-address is located at address 0x1F and is by default 0x00, which selects page 0 as
default page. For example, to access registers which configure the JESDRX, one must
first activate page 4 by writing 0x04 to the page-address 0x1F.
The DAC1008D650 contains six different pages.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
10.15.2 Detailed descriptions of registers
The register information has been provided in page form accompanied by a detailed
description for each bit in the tables following the register allocation map of each page.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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10.15.2.1 Page 0 allocation map description
Table 18. Page 0 register allocation map
Address Register name
R/W Bit definition
b7
Default
Bin
b6
b5
b4 b3
b2 b1
DF PD_ALL
INT_FIR[1:0]
b0
Hex
0
1
2
3
4
5
6
7
8
9
00h COMMON
01h TXCFG
R/W
R/W
R/W
R/W
SPI_3W
NCO_EN
PLL_PD
SPI_RST
NCO_LP_SEL INV_SINE_EN
-
-
-
PD_GAP
10000100 84h
00000001 01h
00000000 00h
01100110 66h
01100110 66h
01100110 66h
00100110 26h
00000000 00h
00000000 00h
00000000 00h
01000000 40h
11000000 C0h
00000000 00h
01000000 40h
11000000 C0h
00000000 00h
MODE[2:0]
02h PLLCFG
-
-
PLL_DIV[1:0]
FREQ_NCO[7:0]
PLL_PHASE[1:0]
PLL_POL
03h FREQNCO_LSB
04h FREQNCO_LISB R/W
05h FREQNCO_UISB R/W
06h FREQNCO_MSB R/W
FREQ_NCO[15:8]
FREQ_NCO[23:16]
FREQ_NCO[31:24]
PH_NCO[7:0]
07h PHINCO_LSB
08h PHINCO_MSB
09h DAC_A_CFG_1
R/W
R/W
PH_NCO[15:8]
R/W DAC_A_PD
DAC_A_SLEEP
DAC_A_OFFSET[5:0]
10 0Ah DAC_A_CFG_2
11 0Bh DAC_A_CFG_3
12 0Ch DAC_B_CFG_1
13 0Dh DAC_B_CFG_2
14 0Eh DAC_B_CFG_3
15 0Fh DAC_CFG
R/W
R/W
DAC_A_GAIN_COARSE[1:0]
DAC_A_GAIN_COARSE[3:2]
DAC_A_GAIN_FINE[5:0]
DAC_A_OFFSET[11:6]
DAC_B_OFFSET[5:0]
DAC_B_GAIN_FINE[5:0]
DAC_B_OFFSET[11:6]
R/W DAC_B_PD
DAC_B_SLEEP
R/W
R/W
R/W
DAC_B_GAIN_COARSE[1:0]
DAC_B_GAIN_COARSE[3:2]
-
-
-
-
-
-
-
MINUS_
3DB
NOISE_
SHAPER
17 11h DAC_CURRENT_0 R/W
18 12h DAC_CURRENT_1 R/W
19 13h DAC_CURRENT_2 R/W
20 14h DAC_CURRENT_3 R/W
-
-
-
-
-
-
-
DAC_DIG_BIAS[2:0]
DAC_MST_BIAS[2:0]
DAC_SLV_BIAS[2:0]
DAC_CAS_BIAS[2:0]
-
00000110 06h
00000110 06h
01100110 66h
01100110 66h
00000010 02h
-
DAC_DRV_BIAS[2:0]
-
DAC_CK_BIAS[2:0]
-
-
21 15h DAC_SEL_PH_
FINE
R/W
-
-
-
-
SEL_PH_FINE[1:0]
22 16h PHASECORR_
CNTRL0
R/W
PHASE_CORR[7:0]
00000000 00h
00000000 00h
23 17h PHASECORR_
CNTRL1
R/W PHASE_CORR_
ENABLE
-
-
-
-
-
-
-
-
-
PHASE_CORR[9:8]
AUX_A[1:0]
26 1Ah DAC_A_AUX_MSB R/W
27 1Bh DAC_A_AUX_LSB R/W
AUX_A[9:2]
-
10000000 80h
00000000 00h
AUX_A_PD
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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Table 18. Page 0 register allocation map …continued
Address Register name
R/W Bit definition
b7
Default
Bin
b6
b5
b4 b3
b2 b1
b0
Hex
28 1Ch DAC_B_AUX_MSB R/W
29 1Dh DAC_B_AUX_LSB R/W
31 1Fh PAGE_ADDRESS R/W
AUX_B[9:2]
10000000 80h
00000000 00h
00000000 00h
AUX_B_PD
-
-
-
-
-
-
-
-
-
-
AUX_B[1:0]
PAGE[2:0]
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.2 Page 0 bit definition detailed description
Please refer to Table 18 for a register overview for page 0. In the following tables, all the
values emphasized in bold are the default values.
Table 19. COMMON register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
SPI_3W
R/W
serial interface bus type
4 wire SPI
0
1
3 wire SPI
6
2
1
0
SPI_RST
DF
R/W
R/W
R/W
R/W
serial interface reset
no reset
0
1
performs a reset on all registers except 0x00
data format
0
signed (two’s compliment) format
unsigned format
1
PD_ALL
GAP_PD
power-down
0
no action
1
all circuits (digital and analog) are switched off
internal bandgap power-down
no action
0
1
internal bandgap references are switched off
Table 20. TXCFG register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
NCO_EN
R/W
NCO
0
disabled (the NCO phase is reset to 0)
enabled
1
6
NCO_LP_SEL
R/W
low-power NCO
0
NCO may use all 32 bits
1
NCO frequency and phase given by the five
MSBs of the registers 06h and 08h respectively
5
INV_SINE_EN
MODE[2:0]
R/W
R/W
x / (sin x) function
0
disabled
1
enabled
4 to 2
modulation
000
001
010
011
100
dual DAC: no modulation
positive upper single sideband up-conversion
positive lower single sideband up-conversion
negative upper single sideband up-conversion
negative lower single sideband up-conversion
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
40 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 20. TXCFG register (address 01h) bit description …continued
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
1 to 0
INT_FIR[1:0]
R/W
interpolation
00
01
10
11
no interpolation
2×
4×
8×
Table 21. PLLCFG register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
PLL_PD
R/W
PLL
0
1
0
0
switched on
switched off
6
-
R/W
R/W
R/W
undefined
5
-
must be written with ’0’
4 to 3
PLL_DIV[1:0]
PLL divider factor
00
01
10
2
4
8
2 to 1
PLL_PHASE[1:0]
R/W
R/W
PLL phase shift of fs
00
01
10
11
0°
120°
240°
undefined
clock edge of DAC (fs)
normal
0
PLL_POL
0
1
inverted
Table 22. FREQNCO_LSB register (address 03h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
FREQ_NCO[7:0]
R/W
66h
lower 8 bits for the NCO frequency setting
Table 23. FREQNCO_LISB register (address 04h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
FREQ_NCO[15:8]
R/W
66h
lower intermediate 8 bits for the NCO frequency
setting
Table 24. FREQNCO_UISB register (address 05h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
FREQ_NCO[23:16]
R/W
66h
upper intermediate 8 bits for the NCO frequency
setting
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
41 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 25. FREQNCO_MSB register (address 06h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
FREQ_NCO[31:24]
R/W
26h
most significant 8 bits for the NCO frequency setting
Table 26. PHINCO_LSB register (address 07h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
PH_NCO[7:0]
R/W
00h
lower 8 bits for the NCO phase setting
Table 27. PHINCO_MSB register (address 08h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
PH_NCO[15:8]
R/W
00h
most significant 8 bits for the NCO phase setting
Table 28. DAC_A_CFG_1 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
DAC_A_PD
R/W
DAC A power
0
on
1
off
6
DAC_A_SLEEP
R/W
R/W
DAC A Sleep mode
disabled
0
1
enabled
5 to 0
DAC_A_OFFSET[5:0]
00h
lower 6 bits for the DAC A offset
Table 29. DAC_A_CFG_2 register (address 0Ah) bit description
Bit
Symbol
Access
Value
Description
7 to 6
DAC_A_GAIN_COARSE[1:0]
R/W
1h
least significant 2 bits for the DAC A gain setting for
coarse adjustment
5 to 0
DAC_A_GAIN_FINE[5:0]
R/W
00h
the 6 bits for the DAC A gain setting for fine
adjustment
Table 30. DAC_A_CFG_3 register (address 0Bh) bit description
Bit
Symbol
Access
Value
Description
7 to 6
DAC_A_GAIN_COARSE[3:2]
R/W
3h
most significant 2 bits for the DAC A gain setting for
coarse adjustment
5 to 0
DAC_A_OFFSET[11:6]
R/W
00h
most significant 6 bits for the DAC A offset
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
42 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 31. DAC_B_CFG_1 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
DAC_B_PD
R/W
DAC B power
0
on
1
off
6
DAC_B_SLEEP
R/W
R/W
DAC B Sleep mode
disabled
0
1
enabled
5 to 0
DAC_B_OFFSET[5:0]
00h
lower 6 bits for the DAC B offset
Table 32. DAC_B_CFG_2 register (address 0Dh) bit description
Bit
Symbol
Access
Value
Description
7 to 6
DAC_B_GAIN_COARSE[1:0]
R/W
1h
least significant 2 bits for the DAC B gain setting for
coarse adjustment
5 to 0
DAC_B_GAIN_FINE[5:0]
R/W
00h
the 6 bits for the DAC B gain setting for fine
adjustment
Table 33. DAC_B_CFG_3 register (address 0Eh) bit description
Bit
Symbol
Access
Value
Description
7 to 6
DAC_B_GAIN_COARSE[3:2]
R/W
3h
most significant 2 bits for the DAC B gain setting for
coarse adjustment
5 to 0
DAC_B_OFFSET[11:6]
R/W
00h
most significant 6 bits for the DAC B offset
Table 34. DAC_CFG register (address 0Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
NCO gain
unity
1
MINUS_3DB
R/W
0
1
−3 dB
0
NOISE_SHAPER
R/W
noise shaper
disabled
enabled
0
1
Table 35. DAC_CURRENT_0 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 1
DAC_DIG_BIAS[2:0]
R/W
3h
bias current control (see Table 47)
Table 36. DAC_CURRENT_1 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 1
DAC_MST_BIAS[2:0]
R/W
3h
bias current control (see Table 47)
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
43 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 37. DAC_CURRENT_2 register (address 13h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
R/W
Value
3h
Description
7 to 5
3 to 1
DAC_DRV_BIAS[2:0]
DAC_SLV_BIAS[2:0]
bias current control (see Table 47)
bias current control (see Table 47)
R/W
3h
Table 38. DAC_CURRENT_3 register (address 14h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
R/W
Value
3h
Description
7 to 5
3 to 1
DAC_CK_BIAS[2:0]
DAC_CAS_BIAS[2:0]
bias current control (see Table 47)
bias current control (see Table 47)
R/W
3h
Table 39. DAC_SEL_PH_FINE register (address 15h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
1 to 0
SEL_PH_FINE[1:0]
R/W
2h
fine DAC phase selection
Table 40. PHASECORR_CNTRL0 register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
PHASE_CORR[7:0]
R/W
00h
LSB phase correction factor
Table 41. PHASECORR_CNTRL1 register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
PHASE_CORR_ENABLE
R/W
phase correction
disabled
0
1
enabled
1 to 0
PHASE_CORR[9:8]
R/W
0h
MSB phase correction factor
Table 42. DAC_A_AUX_MSB register (address 1Ah) bit description
Bit
Symbol
Access
Value
Description
7 to 0
AUX_A[9:2]
R/W
80h
most significant 8 bits for auxiliary DAC A
Table 43. DAC_A_AUX_LSB register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
AUX_A_PD
R/W
auxiliary DAC A power
0
on
1
off
1 to 0
AUX_A[1:0]
R/W
0h
lower 2 bits for auxiliary DAC A
Table 44. DAC_B_AUX_MSB register (address 1Ch) bit description
Bit
Symbol
Access
Value
Description
7 to 0
AUX_B[9:2]
R/W
80h
most significant 8 bits for auxiliary DAC B
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
44 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 45. DAC_B_AUX_LSB register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
AUX_B_PD
R/W
auxiliary DAC B power
0
on
1
off
1 to 0
AUX_B[1:0]
R/W
0h
lower 2 bits for auxiliary DAC B
Table 46. DAC_B_AUX_LSB register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
R/W 0h
Description
2 to 0
PAGE[2:0]
page address
Table 47. Bias current control table
Default settings are shown highlighted.
BIAS[2:0]
000
Deviation from nominal current
−30 %
...
001
010
...
011
0 %
...
100
101
...
110
...
111
+30 %
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
45 of 98
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
10.15.2.3 Page 1 allocation map description
Table 48. Page 1 register allocation map
Address Register name R/W Bit definition
b7 b6
R/W MDS_EQCHECK[1:0]
Default[1]
Bin Hex
b5
MDS_
b4
b3
b2
b1
b0
0
00h MDS_MAIN
MDS_NCO MDS_SEL_ MDS_32T_
MDS_
MASTER
MDS_
ENA
00000100 04h
RUN
LN23
ENA
1
2
3
01h MDS_WIN_PERIOD_A R/W
02h MDS_WIN_PERIOD_B R/W
MDS_WIN_PERIOD_A[7:0]
MDS_WIN_PERIOD_B[7:0]
10000000 80h
01000000 40h
00010000 10h
03h MDS_MISCCNTRL0
R/W
-
-
-
MDS_EVAL_
ENA
MDS_
PRERUN_
ENA
MDS_PULSEWIDTH[2:0]
4
04h MDS_MAN_ADJUSTD R/W
LY
MDS_
MAN
MDS_MAN_ADJUSTDLY[6:0]
01000000 40h
5
6
05h MDS_AUTO_CYCLES R/W
MDS_AUTO_CYCLES[7:0]
10000000 80h
00001111 0Fh
06h MDS_MISCCNTRL1
R/W MDS_SR_ MDS_SR_ MDS_
MDS_
MDS_LOCK_DELAY[3:0]
CKEN LOCKOUT
SR_
RELOCK
LOCK
8
9
08h MDS_ADJDELAY
09h MDS_STATUS0
R
R
-
MDS_ADJDELAY[6:0]
uuuuuuuu uuh
uuuuuuuu uuh
EARLY
LATE
EQUAL MDS_LOCK
EARLY_
ERROR
LATE_
EQUAL_
FOUND
MDS_
ACTIVE
ERROR
10 0Ah MDS_STATUS1
31 1Fh PAGE_ADDRESS
R
-
-
-
-
-
-
-
-
JD_ODD
MDS_
PRERUN
MDS_
LOCKOUT
MDS_
LOCK
uuuuuuuu uuh
00000000 00h
R/W
-
PAGE[2:0]
[1] u = undefined at power-up or after reset.
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.4 Page 1 bit definition detailed description
Please refer to Table 48 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 49. MDS_MAIN register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
MDS_EQCHECK[1:0]
R/W
lock mode
00
01
10
11
lock when (early = 1 and late = 1)
lock when (early = 1 and late = 1 and equal = 1)
lock when equal = 1
force_lock (equal-check = 1)
evaluation restart
5
4
3
MDS_RUN
R/W
R/W
R/W
0
no action
1
transition from 0 to 1 restarts evaluation_counter
NCO synchronization
MDS_NCO
0
no action
1
NCO synchronization enabled
synchronization reference
MDS_SEL_LN23
0
use lane 1 enable as reference for
synchronization
1
use lane 2/lane 3 enable as reference for
synchronization
2
1
0
MDS_32T_ENA
MDS_MASTER
MDS_ENA
R/W
R/W
R/W
maximum delay
0
maximum coarse delay is 16T_dclk
maximum coarse delay is 32T_dclk
MDS mode
1
0
slave mode
1
master mode
MDS function
0
disable MDS function
enable MDS function
1
Table 50. MDS_WIN_PERIOD_A register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MDS_WIN_PERIOD_A[7:0]
R/W
80h
determines MDS window LOW-time
Table 51. MDS_WIN_PERIOD_B register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MDS_WIN_PERIOD_B[7:0]
R/W
40h
determines MDS window HIGH-time
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
47 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 52. MDS_MISCCNTRL0 register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4
MDS_EVAL_ENA
R/W
MDS evaluation
0
disabled
1
enabled
3
MDS_PRERUN_ENA
R/W
R/W
automatic MDS start-up
0
no mds_win/mds_ref generation in advance
1
mds_win/mds_ref run-in before MDS evaluation
2 to 0
MDS_PULSEWIDTH[2:0]
width of MDS (in output clk-periods)
000
1T
001
2T
010 to
111
(MDS_pulsewidth −1) × 4T
Table 53. MDS_MAN_ADJUSTDLY register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
MDS_MAN
R/W
adjustment delay mode
auto-control adjustment delays
manual control adjustment delays
adjustment delay value
0
1
6 to 0
MDS_MAN_ADJUSTDLY[6:0]
R/W
40h
-
if MDS_MAN = 0 then initial value adjustment
delay
if MDS_MAN = 1 then controls adjustment delay
Table 54. MDS_AUTO_CYCLES register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MDS_AUTO_CYCLES[7:0]
R/W
80h
number of evaluation cycles applied for MDS
Table 55. MDS_MISCCNTRL1 register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
MDS_SR_CKEN
R/W
lock mode
0
free-running mds_cken
MDS_cken forced LOW
lockout detector soft reset
mds_lockout in use
MDS_lockout forced LOW
lock detector soft reset
MDS_lock in use
1
6
5
MDS_SR_LOCKOUT
MDS_SR_LOCK
R/W
R/W
0
1
0
1
MDS_lock forced LOW
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
48 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 55. MDS_MISCCNTRL1 register (address 06h) bit description …continued
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4
MDS_RELOCK
R/W
relock mode
0
no action
1
relock when lockout occurs
number of succeeding 'equal'-detections until lock
3 to 0
MDS_LOCK_DELAY[3:0]
R/W
Fh
Table 56. MDS_ADJDELAY register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
6 to 0
MDS_ADJDELAY[6:0]
R
-
actual value adjustment delay
Table 57. MDS_STATUS0 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
EARLY
R
early signal (sampled) from early-late detector
0
1
false
true
6
5
4
3
2
1
0
LATE
R
R
R
R
R
R
R
late signal (sampled) from early-late detector
0
1
false
true
EQUAL
equal signal (sampled) from early-late detector
0
1
false
true
MDS_LOCK
EARLY_ERROR
LATE_ERROR
EQUAL_FOUND
MDS_ACTIVE
result equal check
0
1
false
true
adjustment delay maximum value stops the search
0
1
false
true
adjustment delay minimum value stops the search
0
1
false
true
evaluation logic has detected equal condition
0
1
false
true
evaluation logic active
0
1
false
true
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
49 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 58. MDS_STATUS1 register (address 0Ah) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3
JD_ODD
R
MDS start mode
0
1
MDS start aligned to cdi-even sample
MDS start aligned to cdi-odd sample (only for ^2)
2
1
0
MDS_PRERUN
MDS_LOCKOUT
MDS_LOCK
R
R
R
MDS pre-run phase active flag
0
1
false
true
MDS lockout detected flag
0
1
false
true
MDS lock flag
false
0
1
true
Table 59. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
0h
page address
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
50 of 98
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10.15.2.5 Page 2 allocation map description
Table 60. Page 2 register allocation map
Address Register name R/W Bit definition
b7 b6
Default
Bin
b5
FULL_RE_ SYNC_INIT_
INIT LEVEL
b4
b3
b2
b1
b0
Hex
0
00h MAINCONTROL
R/W
-
-
-
0
-
0
FORCE_ FORCE_ 00000011 03h
RESET_ RESET_
DCLK
FCLK
3
4
5
6
7
8
9
03h JCLK_CNTRL
R/W
R/W
R/W
SR_CDI
CDI_MODE[1:0]
FCLK_POL
FCLK_SEL[1:0]
00000000 00h
00111111 3Fh
00100000 20h
00011110 1Eh
00110010 32h
00110010 32h
00000100 04h
00000010 02h
01000011 43h
11011111 DFh
00000001 01h
00000010 02h
00000010 02h
00000000 00h
04h RST_EXT_FCLK
05h RST_EXT_DCLK
RST_EXT_FCLK_TIME[7:0]
RST_EXT_DCLK_TIME[7:0]
DCSMU_PREDIVIDER[7:0]
PLL_CHARGE_TIME[7:0]
PLL_RUNIN_TIME[7:0]
CA_RUNIN_TIME[7:0]
-
06h DCSMU_PREDIVCNT R/W
07h PLL_CHARGETIME R/W
08h PLL_RUN_IN_TIME R/W
09h CA_RUN_IN_TIME
R/W
22 16h SET_VCM_VOLTAGE R/W
-
-
-
-
SET_SYNC_VCOM[2:0]
FRONTEND[1:0] DUAL
SET_VCM[3:0]
23 17h SET_SYNC
R/W
R
-
SET_SYNC_LEVEL[2:0]
BIT_RES[1:0]
27 1Bh TYPE_ID
DAC
DSP
28 1Ch DAC_VERSION
29 1Dh DIG_VERSION
30 1Eh JRX_ANA_VERSION
31 1Fh PAGE_ADDRESS
R
DAC_VERSION_ID[7:0]
DIG_VERSION_ID[7:0]
R
R
JRX_ANA_VERSION_ID[7:0]
R/W
-
-
-
-
-
PAGE[2:0]
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.6 Page 2 bit definition detailed description
Please refer to Table 60 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 61. MAINCONTROL register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
5
FULL_RE_INIT
R/W
initialization
0
quick reinitialization
full reinitialization
synchronization
1
4
SYNC_INIT_LEVEL
R/W
0
synchronization starts with '0'
synchronization starts with '1'
must be written with ’0’
must be written with ’0’
reset_dclk
1
3
2
1
-
R/W
R/W
R/W
-
FORCE_RESET_DCLK
0
release reset_dclk
force reset_dclk
reset_fclk
1
0
FORCE_RESET_FCLK
R/W
0
release reset_fclk
force reset_fclk
1
Table 62. JCLK_CNTRL register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
SR_CDI
R/W
cdi reset
0
no action
1
soft reset cdi
5 to 4
CDI_MODE[1:0]
R/W
cdi mode
00
01
10
11
cdi_mode 0 (^2 modes)
cdi_mode 1 (^4 modes)
cdi_mode 2 (^8 modes)
reserved
2
FCLK_POL
R/W
R/W
fclk polarity
0
no action
1
invert polarity
fclk clock source
dclk × 2
1 to 0
FCLK_SEL[1:0]
00
01
10
11
dclk
dclk_div2; running
dclk_div2; reset dclk_div2 divider
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
52 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 63. RST_EXT_FCLK register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
RST_EXT_FCLK_TIME[7:0]
R/W
3Fh
specifies extension time reset_fclk in fclk periods
Table 64. RST_EXT_DCLK register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
RST_EXT_DCLK_TIME[7:0]
R/W
20h
specifies extension time reset_dclk (in dclk-periods)
Table 65. DCSMU_PREDIVCNT register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
DCSMU_PREDIVIDER[7:0]
R/W
1Eh
value used by dcsmu predivider (at fclk)
Table 66. PLL_CHARGETIME register (address 07h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
PLL_CHARGE_TIME[7:0]
R/W
32h
PLL charge time
(at fclk/DCSMU_PREDIVIDER[7:0])
Table 67. PLL_RUN_IN_TIME register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
PLL_RUNIN_TIME[7:0]
R/W
32h
PLL run in time (at fclk/DCSMU_PREDIVIDER[7:0])
Table 68. CA_RUN_IN_TIME register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
CA_RUNIN_TIME[7:0]
R/W
04h
clock alignment run in time
(at fclk/DCSMU_PREDIVIDER[7:0])
Table 69. SET_VCM_VOLTAGE register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
SET_VCM[3:0]
R/W
02h
set lane common-mode voltage (see Table 76)
Table 70. SET_SYNC register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
6 to 4
SET_SYNC_VCOM[2:0]
R/W
4h
set synchronization transmitter common-mode level
(see Table 77)
2 to 0
SET_SYNC_LEVEL[2:0]
R/W
3h
set synchronization transmitter output level swing
(see Table 78)
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
53 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 71. TYPE_ID register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
part type
7
DAC
R
0
ADC
1
DAC
6 to 5
FRONTEND [1:0]
R
input format
CMOS
00
01
10
11
LVDS
JESD204A
reserved
4
DUAL
DSP
R
R
converter structure
single
0
1
dual
3 to 2
digital processing
none
00
01
10
11
upsampling filters
single sideband modulator
upsampling filters + single sideband
modulator
1 to 0
BIT_RES[1:0]
R
resolution
16 bits
00
01
10
11
14 bits
12 bits
10 bits
Table 72. DAC_VERSION register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
DAC_VERSION_ID[7:0]
R
01h
dual DAC core version
Table 73. DIG_VERSION register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
DIG_VERSION_ID[7:0]
R
02h
digital version
Table 74. JRX_ANA_VERSION register (address 1Eh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
JRX_ANA_VERSION_ID[7:0]
R
02h
analog deserializer version
Table 75. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
0h
page address
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
54 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 76. Lane common-mode voltage adjustment
Register 16h: SET_VCM_VOLTAGE
Decimal
SET_VCM_VOLTAGE
Vcom (V)
1.40
1.36
1.31
1.26
1.21
1.16
1.12
1.07
1.02
0.97
0.92
0.87
0.82
0.78
0.73
0.68
15
14
13
12
11
10
9
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
8
7
6
5
4
3
2
1
0
Table 77. SYNC common-mode voltage adjustment
Register 17h: SET_SYNC
Decimal
SET_SYNC_VCOM[2:0]
Vcom (V)
1.46
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
1.36
1.27
1.17
1.07
0.98
0.88
0.79
Table 78. SYNC swing voltage adjustment
Register 17h: SET_SYNC
Decimal
SET_SYNC_LEVEL[2:0]
Single-ended output voltage (V)
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
0.48
0.42
0.36
0.30
0.24
0.18
0.12
0.06
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
55 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
10.15.2.7 Page 4 allocation map description
Table 79. Page 4 register allocation map
Address Register name R/W Bit definition
b7 b6
Default
Bin
b5
b4
b3
b2
b1
b0
Hex
0
1
2
3
00h SR_DLP_0
01h SR_DLP_1
02h FORCE_LOCK
R/W SR_SWA_ SR_SWA_ SR_SWA_ SR_SWA_ SR_CA_LN3 SR_CA_LN2 SR_CA_LN1 SR_CA_LN0 00000000 00h
LN3 LN2 LN1 LN0
R/W SR_CNTRL SR_CNTRL SR_CNTRL_ SR_CNTRL_ SR_DEC_
SR_DEC_
LN2
SR_DEC_
LN1
SR_DEC_ 00000000 00h
LN0
_LN3
_LN2
LN1
LN0
LN3
R/W FORCE_
FORCE_
FORCE_
FORCE_
-
-
-
SR_ILA 00000000 00h
LOCK_LN3 LOCK_LN2 LOCK_LN1 LOCK_LN0
03h MAN_LOCK_
LN_1_0
R/W
MAN_LOCK_LN1[3:0]
MAN_LOCK_LN0[3:0]
MAN_LOCK_LN2[3:0]
00000000 00h
4
5
04h MAN_LOCK_2_0 R/W
MAN_LOCK_LN3[3:0]
00000000 00h
05h CA_CNTRL
06h SCR-CNTRL
07h ILA_CNTRL
R/W
WORD_
WORD_
WORD_
WORD_ SELECT_RF SELECT_RF SELECT_RF SELECT_RF 00000000 00h
SWAP_LN3 SWAP_LN2 SWAP_LN1 SWAP_LN0 _F10_LN3
_F10_LN2 _F10_LN1
_F10_LN0
6
7
8
9
R/W MAN_SCR MAN_SCR_ MAN_SCR_ MAN_SCR_ FORCE_
FORCE_
SCR_LN2
FORCE_
SCR_LN1
FORCE_ 00000000 00h
SCR_LN0
_LN3
LN2
LN1
LN0
SCR_LN3
R/W SEL_421_
211
SEL_ILA[1:0]
SEL_LOCK[2:0]
SUP_LANE_ EN_SCR 10000011 83h
SYN
08h FORCE_ALIGN R/W
-
-
-
-
-
-
DYN_ALIGN FORCE_ 00000000 00h
_ENA
ALIGN
09h MAN_ALIGN_
LN_0_1
R/W
R/W
R/W
R/W
R/W
MAN_ALIGN_LN1[3:0]
MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN0[3:0]
00000000 00h
00000000 00h
10 0Ah MAN_ALIGN_
LN_2_3
MAN_ALIGN_LN2[3:0]
11 0Bh FA_ERR_
HANDLING
SEL_KOUT_UNEXP_
LN23[1:0]
SEL_KOUT_UNEXP_
LN10[1:0]
SEL_NIT_ERR_LN23[1:0] SEL_NIT_ERR_LN10[1:0] 00000000 00h
12 0Ch SYNCOUT_
MODE
SEL_RE_INIT[2:0]
SYNC_POL
SEL_SYNC[3:0]
POL_LN2 POL_LN1
LANE_SEL_LN1[1:0]
00000000 00h
13 0Dh LANE_
POLARITY
-
-
-
-
POL_LN3
POL_LN0 00000000 00h
14 0Eh LANE_SELECT R/W
LANE_SEL_LN3[1:0]
LANE_SEL_LN2[1:0]
LANE_SEL_LN0[1:0]
11100100 E4h
16 10h SOFT_RESET_ R/W
SCRAMBLER
-
-
-
-
SR_SCR_
LN3
SR_SCR_
LN2
SR_SCR_
LN1
SR_SCR_ 00000000 00h
LN0
17 11h INIT_SCR_S15T8 R/W
_LN0
INIT_VALUE_S15_S8_LN0[7:0]
00000000 00h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 79. Page 4 register allocation map …continued
Address Register name R/W Bit definition
b7 b6
Default
Bin
b5
b4
b3
b2
b1
b0
Hex
18 12h INIT_SCR_
S7T1_LN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
INIT_VALUE_S7_S1_LN0[6:0]
00000000 00h
00000000 00h
00000000 00h
00000000 00h
00000000 00h
00000000 00h
00000000 00h
10001000 88h
10001000 88h
19 13h INIT_SCR_
S15T8_LN1
INIT_VALUE_S15_S8_LN1[7:0]
INIT_VALUE_S7_S1_LN1[6:0]
INIT_VALUE_S15_S8_LN2[7:0]
INIT_VALUE_S7_S1_LN2[6:0]
INIT_VALUE_S15_S8_LN3[7:0]
INIT_VALUE_S7_S1_LN3[6:0]
20 14h INIT_SCR_
S7T1_LN1
21 15h INIT_SCR_
S15T8_LN2
22 16h INIT_SCR_
S7T1_LN2
23 17h INIT_SCR_
S15T8_LN3
24 18h INIT_SCR_
S7T1_LN3
25 19h INIT_ILA_
BUFPTR_LN01
INIT_ILA_BUFPTR_LN1[3:0]
INIT_ILA_BUFPTR_LN3[3:0]
INIT_ILA_BUFPTR_LN0[3:0]
INIT_ILA_BUFPTR_LN2[3:0]
26 1Ah INIT_ILA_
BUFPTR_LN23
27 1Bh ERROR_
HANDLING
-
NAD_ERR_ KUX_CORR NAD_CORR
CORR
CORR_MODE[1:0]
IMPL_ALT
IGNORE_ 00000000 00h
ERR
28 1Ch REINIT_CNTRL R/W REINIT_ REINIT_ILA REINIT_ILA_ REINIT_ILA_ RESYNC_O RESYNC_O RESYNC_O RESYNC_O 00000000 00h
ILA_LN3
_LN2
LN1
LN0
_L_LN3
_L_LN2
_L_LN1
_L_LN0
31 1Fh PAGE_ADDRESS R/W
-
-
-
-
-
PAGE[2:0]
00000000 00h
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.8 Page 4 bit definition detailed description
Please refer to Table 79 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 80. SR_DLP_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
Description
SR_SWA_LN3
SR_SWA_LN2
SR_SWA_LN1
SR_SWA_LN0
SR_CA_LN3
SR_CA_LN2
SR_CA_LN1
SR_CA_LN0
0
0
0
0
0
0
0
0
soft reset sync_word_alignment lane 3
soft reset sync_word_alignment lane 2
soft reset sync_word_alignment lane 1
soft reset sync_word_alignment lane 0
soft reset clock_alignment lane 3
soft reset clock_alignment lane 2
soft reset clock_alignment lane 1
soft reset clock_alignment lane 0
6
5
4
3
2
1
0
Table 81. SR_DLP_1 register (address 01h) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
Description
SR_CNTRL_LN3
SR_CNTRL_LN2
SR_CNTRL_LN1
SR_CNTRL_LN0
SR_DEC_LN3
SR_DEC_LN2
SR_DEC_LN1
SR_DEC_LN0
0
0
0
0
0
0
0
0
soft reset controller lane 3
soft reset controller lane 2
soft reset controller lane 1
soft reset controller lane 0
soft reset decoder_10b8b lane 3
soft reset decoder_10b8b lane 2
soft reset decoder_10b8b lane 1
soft reset decoder_10b8b lane 0
6
5
4
3
2
1
0
Table 82. FORCE_LOCK register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
FORCE_LOCK_LN3
R/W
lane 3 lock mode
0
automatic lock sync_word_alignment lane 3
manual lock sync_word_alignment lane 3
lane 2 lock mode
1
6
5
4
FORCE_LOCK_LN2
FORCE_LOCK_LN1
FORCE_LOCK_LN0
R/W
R/W
R/W
0
automatic lock sync_word_alignment lane 2
manual lock sync_word_alignment lane 2
lane 1 lock mode
1
0
automatic lock sync_word_alignment lane 1
manual lock sync_word_alignment lane 1
lane 0 lock mode
1
0
automatic lock sync_word_alignment lane 0
manual lock sync_word_alignment lane 0
1
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
58 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 82. FORCE_LOCK register (address 02h) bit description …continued
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
0
SR_ILA
R/W
soft reset inter-lane alignment
no action
0
1
reset
Table 83. MAN_LOCK_LN_1_0 register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
MAN_LOCK_LN1[3:0]
R/W
0h
manual lock setting synchronization word alignment
lane 1
3 to 0
MAN_LOCK_LN0[3:0]
R/W
0h
manual lock setting synchronization word alignment
lane 0
Table 84. MAN_LOCK_2_0 register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
MAN_LOCK_LN3[3:0]
R/W
0h
manual lock setting synchronization word alignment
lane 3
3 to 0
MAN_LOCK_LN2[3:0]
R/W
0h
manual lock setting synchronization word alignment
lane 2
Table 85. CA_CNTRL register (address 05h) bit description
Bit
Symbol
Access
Value
Description
7
WORD_SWAP_LN3
R/W
lane 3 bit swapping
0
dout_ca_ln3[7:0] = din_ca_ln3[7:0]
dout_ca_ln3[7:0] = din_ca_ln3[0:7]
lane 2 bit swapping
1
6
5
4
3
2
WORD_SWAP_LN2
WORD_SWAP_LN1
WORD_SWAP_LN0
SELECT_RF_F10_LN3
SELECT_RF_F10_LN2
R/W
R/W
R/W
R/W
R/W
0
dout_ca_ln2[7:0] = din_ca_ln2[7:0]
dout_ca_ln2[7:0] = din_ca_ln2[0:7]
lane 1 bit swapping
1
0
dout_ca_ln1[7:0] = din_ca_ln1[7:0]
dout_ca_ln1[7:0] = din_ca_ln1[0:7]
lane 0 bit swapping
1
0
dout_ca_ln0[7:0] = din_ca_ln0[7:0]
dout_ca_ln0[7:0] = din_ca_ln0[0:7]
lane 3 sampling mode
1
0
din_ca_ln3 sampled at falling edge f10_ln3
din_ca_ln3 sampled at rising edge f10_ln3
lane 2 sampling mode
1
0
din_ca_ln2 sampled at falling edge f10_ln2
din_ca_ln2 sampled at rising edge f10_ln2
1
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
59 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 85. CA_CNTRL register (address 05h) bit description …continued
Bit
Symbol
Access
Value
Description
1
SELECT_RF_F10_LN1
R/W
lane 1 sampling mode
0
din_ca_ln1 sampled at falling edge f10_ln1
din_ca_ln1 sampled at rising edge f10_ln1
lane 0 sampling mode
1
0
SELECT_RF_F10_LN0
R/W
0
din_ca_ln0 sampled at falling edge f10_ln0
din_ca_ln0 sampled at rising edge f10_ln0
1
Table 86. SCR_CNTRL register (address 06h) bit description
Bit
Symbol
Access
Value
Description
7
MAN_SCR_LN3
R/W
lane 3 manual scrambling
0
scrambling lane 3 off (when force_scr_ln3 = 1)
scrambling lane 3 on (when force_scr_ln3 = 1)
lane 2 manual scrambling
1
6
5
4
3
MAN_SCR_LN2
MAN_SCR_LN1
MAN_SCR_LN0
FORCE_SCR_LN3
R/W
R/W
R/W
R/W
0
scrambling lane 2 off (when force_scr_ln2 = 1)
scrambling lane 2 on (when force_scr_ln2 = 1)
lane 1 manual scrambling
1
0
scrambling lane 1 off (when force_scr_ln1 = 1)
scrambling lane 1 on (when force_scr_ln1 = 1)
lane 0 manual scrambling
1
0
scrambling lane 0 off (when force_scr_ln0 = 1)
scrambling lane 0 on (when force_scr_ln0 = 1)
lane 3 scrambling mode
1
0
scrambling lane 3 depends on lock_ln3 and
en_scr
1
scrambling lane 3 depends on man_scr_ln3
lane 2 scrambling mode
2
1
0
FORCE_SCR_LN2
FORCE_SCR_LN1
FORCE_SCR_LN0
R/W
R/W
R/W
0
scrambling lane 2 depends on lock_ln2 and
en_scr
1
scrambling lane 2 depends on man_scr_ln2
lane 1 scrambling mode
0
scrambling lane 1 depends on lock_ln1 and
en_scr
1
scrambling lane 1 depends on man_scr_ln1
lane 0 scrambling mode
0
scrambling lane 0 depends on lock_ln0 and
en_scr
1
scrambling lane 0 depends on man_scr_ln0
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
60 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 87. ILA_CNTRL register (address 07h) bit description
Bit
Symbol
Access
Value
Description
7
SEL_421_211
R/W
inter-lane alignment mode
0
inter-lane alignment based on lane 3 : lane 2
and/or lane 1 : lane 0
1
inter-lane alignment based on ln3 : ln0
6 to 5
SEL_ILA[1:0]
R/W
inter-lane alignment trigger mode
00
01
10
11
inter-lane alignment is done after receiving
1 /A/-symbol
inter-lane alignment is done after receiving
2 /A/-symbols
inter-lane alignment is done after receiving
3 /A/-symbols
inter-lane alignment is done after receiving
4 /A/-symbols
4 to 2
SEL_LOCK[2:0]
R/W
inter-lane alignment start mode
000
inter-lane alignment may start only if all (4 or 2)
lanes are locked
001
inter-lane alignment may start if one of the (4 or 2)
lanes are locked
010
011
100
101
inter-lane alignment may start if lane 0 is locked
inter-lane alignment may start if lane 1 is locked
inter-lane alignment may start if lane 2 is locked
inter-lane alignment may start if lane 3 is locked
inter-lane alignment enable
1
0
SUP_LANE_SYN
EN_SCR
R/W
R/W
0
inter-lane alignment synchronization disabled
inter-lane alignment synchronization enabled
data descrambling
1
0
disabled
1
enabled
Table 88. FORCE_ALIGN register (address 08h) bit description
Bit
Symbol
Access
Value
Description
1
DYN_ALIGN_ENA
R/W
dynamic re-alignment mode
no dynamic re-alignment
dynamic re-alignment (and monitoring) enabled
lane alignment mode
0
1
0
FORCE_ALIGN
R/W
0
automatic lane alignment based on
/A/ symbols
1
manual lane alignment based on man_align_lnx
Table 89. MAN_ALIGN_LN_0_1 register (address 09h) bit description
Bit
Symbol
Access
R/W
Value
0h
Description
7 to 4
3 to 0
MAN_ALIGN_LN1[3:0]
MAN_ALIGN_LN0[3:0]
indicates alignment data-delay for lane 1 [1..15]
indicates alignment data-delay for lane 0 [1..15]
R/W
0h
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
61 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 90. MAN_ALIGN_LN_2_3 register (address 0Ah) bit description
Bit
Symbol
Access
R/W
Value
0h
Description
7 to 4
3 to 0
MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN2[3:0]
indicates alignment data-delay for lane 3 [1..15]
indicates alignment data-delay for lane 2 [1..15]
R/W
0h
Table 91. FA_ERR_HANDLING register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
00
Description
7 to 6
SEL_KOUT_ UNEXP_LN23[1:0]
R/W
lane 2/lane 3 unexpected /K/ error handling
unexpected /K/ in lane 2 or lane 3
error_handling
01
10
11
unexpected /K/ in lane 2 and lane 3 error_handling
unexpected /K/ in lane 2 error_handling
unexpected /K/ in lane 3 error_handling
5 to 4
3 to 2
1 to 0
SEL_KOUT_ UNEXP_LN10[1:0]
SEL_NIT_ERR_ LN23[1:0]
SEL_NIT_ERR_ LN10[1:0]
R/W
R/W
R/W
lane 0/lane 1 unexpected /K/ error handling
00
unexpected /K/ in lane 0 or lane 1
error_handling
01
10
11
unexpected /K/ in lane 0 and lane 1 error_handling
unexpected /K/ in lane 0 error_handling
unexpected /K/ in lane 1 error_handling
lane 2/lane 3 nit-error handling
00
nit-errors in lane 2 or lane 3 error_handling
01
not-in-table errors lane 2 and lane 3
error_handling
10
11
not-in-table errors in lane 2 error_handling
not-in-table errors in lane 3 error_handling
lane 0/lane 1 nit-error handling
00
nit-errors in lane 0 or lane 1 error_handling
01
not-in-table errors lane 0 and lane 1
error_handling
10
11
not-in-table errors in lane 0 error_handling
not-in-table errors in lane 1 error_handling
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
62 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 92. SYNCOUT_MODE register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
SEL_RE_INIT[2:0]
R/W
reinitialization mode
000
001
010
011
100
101
110
111
i_re_init when 1 of the lane_rst's is active
i_re_init when rst_ln0 or rst_ln1 is active
i_re_init when rst_ln2 or rst_ln3 is active
i_re_init when rst_ln0 is active
i_re_init when rst_ln1 is active
i_re_init when rst_ln2 is active
i_re_init when rst_ln3 is active
i_re_init remains '0'
4
SYNC_POL
R/W
R/W
synchronization polarity
0
sync_out is active when LOW
sync_out is active when HIGH
synchronization mode
1
3 to 0
SEL_SYNC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
other
sync when one of the four lane_syncs is active
sync when all four lane_syncs are active
sync when sync_ln0 or sync_ln1 is active
sync when both sync_ln0 and sync_ln1 are active
sync when sync_ln2 or sync_ln3 is active
sync when both sync_ln2 and sync_ln3 are active
sync when sync_ln0 is active
sync when sync_ln1 is active
sync when sync_ln2 is active
sync when sync_ln3 is active
sync remains fixed '1'
sync remains fixed '0'
Table 93. LANE_POLARITY register (address 0Dh) bit description
Bit
Symbol
Access
Value
Description
3
POL_LN3
R/W
lane 3 data polarity
no action
0
1
invert all data bits of lane 3
lane 2 data polarity
no action
2
1
0
POL_LN2
POL_LN1
POL_LN0
R/W
R/W
R/W
0
1
invert all data bits of lane 2
lane 1 data polarity
no action
0
1
invert all data bits of lane 1]
lane 0 data polarity
no action
0
1
invert all data bits of lane 0
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
63 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 94. LANE_SELECT register (address 0Eh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
LANE_SEL_LN3[1:0]
R/W
lane 3 data mapping
00
01
10
11
ila_in_ln3 = lane_ln0 (dout and controls)
ila_in_ln3 = lane_ln1 (dout and controls)
ila_in_ln3 = lane_ln2 (dout and controls)
ila_in_ln3 = lane_ln3 (dout and controls)
lane 2 data mapping
5 to 4
3 to 2
1 to 0
LANE_SEL_LN2[1:0]
LANE_SEL_LN1[1:0]
LANE_SEL_LN0[1:0]
R/W
R/W
R/W
00
01
10
11
ila_in_ln2 = lane_ln0 (dout and controls)
ila_in_ln2 = lane_ln1 (dout and controls)
ila_in_ln2 = lane_ln2 (dout and controls)
ila_in_ln2 = lane_ln3 (dout and controls)
lane 1 data mapping
00
01
10
11
ila_in_ln1 = lane_ln0 (dout and controls)
ila_in_ln1 = lane_ln1 (dout and controls)
ila_in_ln1 = lane_ln2 (dout and controls)
ila_in_ln1 = lane_ln3 (dout and controls
lane 0 data mapping
00
01
10
11
ila_in_ln0 = lane_ln0 (dout and controls)
ila_in_ln0 = lane_ln1 (dout and controls)
ila_in_ln0 = lane_ln2 (dout and controls)
ila_in_ln0 = lane_ln3 (dout and controls)
Table 95. SOFT_RESET_SCRAMBLER register (address 10h) bit description
Bit
Symbol
Access
Value
Description
3
SR_SCR_LN3
R/W
lane 3 scrambler reset
no action
0
1
soft_reset scrambler of lane 3
lane 2 scrambler reset
no action
2
1
0
SR_SCR_LN2
SR_SCR_LN1
SR_SCR_LN0
R/W
R/W
R/W
0
1
soft_reset scrambler of lane 2
lane 1 scrambler reset
no action
0
1
soft_reset scrambler of lane 1
lane 0 scrambler reset
no action
0
1
soft_reset scrambler of lane 0
Table 96. INIT_SCR_S15T8_LN0 register (address 11h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
INIT_VALUE_S15_S8_LN0[7:0]
R/W
00h
initialization value for lane 0 descrambler bits
s15 : s8
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
64 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 97. INIT_SCR_S7T1_LN0 (address 12h) bit description
Bit
Symbol
Access
Value
Description
6 to 0
INIT_VALUE_S7_S1_LN0[6:0]
R/W
00h
initialization value for lane 0 descrambler bits s7 : s1
Table 98. INIT_SCR_S15T8_LN1 register (address 13h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
INIT_VALUE_S15_S8_LN1[7:0]
R/W
00h
initialization value for lane 1 descrambler bits
s15 : s8
Table 99. INIT_SCR_S7T1_LN1 register (address 14h) bit description
Bit
Symbol
Access
Value
Description
6 to 0
INIT_VALUE_S7_S1_LN1[6:0]
R/W
00h
initialization value for lane 1 descrambler bits s7 : s1
Table 100. INIT_SCR_S15T8_LN2 register (address 15h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
INIT_VALUE_S15_S8_LN2[7:0]
R/W
00h
initialization value for lane 2 descrambler bits
s15 : s8
Table 101. INIT_SCR_S7T1_LN2 register (address 16h) bit description
Bit
Symbol
Access
Value
Description
6 to 0
INIT_VALUE_S7_S1_LN2[6:0]
R/W
00h
initialization value for lane 2 descrambler bits s7 : s1
Table 102. INIT_SCR_S15T8_LN3 register (address 17h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
INIT_VALUE_S15_S8_LN3[7:0]
R/W
00h
initialization value for lane 3 descrambler bits
s15 : s8
Table 103. INIT_SCR_S7T1_LN3 register (address 18h) bit description
Bit
Symbol
Access
Value
Description
6 to 0
INIT_VALUE_S7_S1_LN3[6:0]
R/W
00h
initialization value for lane 3 descrambler bits s7 : s1
Table 104. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description
Bit
Symbol
Access
R/W
Value
8h
Description
7 to 4
3 to 0
INIT_ILA_BUFPTR_LN1[3:0]
INIT_ILA_BUFPTR_LN0[3:0]
initialization value for lane 1 ILA buffer pointer
initialization value for lane 0 ILA buffer pointer
R/W
8h
Table 105. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description
Bit
Symbol
Access
R/W
Value
8h
Description
7 to 4
3 to 0
INIT_ILA_BUFPTR_LN3[3:0]
INIT_ILA_BUFPTR_LN2[3:0]
initialization value for lane 3 ILA buffer pointer
initialization value for lane 2 ILA buffer pointer
R/W
8h
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
65 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 106. ERROR_HANDLING register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
6
NAD_ERR_CORR
R/W
frame assembler (fa)
0
not-in-table errors passed to fa
nad (nit and disparity) errors passed to fa
K-character error mode
1
5
KUX_CORR
R/W
0
unexpected K-character errors ignored (at fa)
1
unexpected K-character errors concealment (at
fa)
4
NAD_CORR
R/W
R/W
nad error mode
0
nad-errors ignored (at fa)
nad-errors concealment (at fa)
conceal mode
1
3 to 2
CORR_MODE[1:0]
00
01
10
11
conceal 1 period at fa
conceal 2 periods at fa
conceal 3 periods at fa
conceal 4 periods at fa
1
0
IMPL_ALT
R/W
R/W
disparity error detection configuration
default disparity error detection (table mode)
alternative disparity error detection (cnt mode)
general error mode
0
1
IGNORE_ERR
0
no action
1
ignore disparity/nit-errors at lane-controller
Table 107. REINIT_CNTRL register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
REINIT_ILA_LN3
R/W
lane 3, ila-buffer out-of-range check
no action
0
1
lane 3 ila-buffer out-of-range_error will activate
reinitialization
6
5
4
REINIT_ILA_LN2
REINIT_ILA_LN1
REINIT_ILA_LN0
R/W
R/W
R/W
lane 2, ila-buffer out-of-range check
0
no action
1
lane 2 ila-buffer out-of-range_error will activate
reinitialization
lane 1, ila-buffer out-of-range check
0
no action
1
lane 1 ila-buffer out-of-range_error will activate
reinitialization
lane 0, ila-buffer out-of-range check
0
no action
1
lane 0 ila-buffer out-of-range_error will activate
reinitialization
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
66 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 107. REINIT_CNTRL register (address 1Ch) bit description …continued
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3
RESYNC_O_L_LN3
R/W
lane 3, resync over link
no action
0
1
lane 3 lane controller checks for
K28.5 /K/ symbols
2
1
0
RESYNC_O_L_LN2
RESYNC_O_L_LN1
RESYNC_O_L_LN0
R/W
R/W
R/W
lane 2, resync over link
0
no action
1
lane 2 lane controller checks for
K28.5 /K/ symbols
lane 1, resync over link
0
no action
1
lane 1 lane controller checks for
K28.5 /K/ symbols
lane 0, resync over link
0
no action
1
lane 0 controller checks for K28.5 /K/ symbols
Table 108. PAGE_ADDRESS register (address 1Fh) bit description
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
0h
page_address
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
67 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
10.15.2.9 Page 5 allocation map description
Table 109. Page 5 register allocation map
Address Register name R/W Bit definition
b7 b6
Default[1]
Bin Hex
b5
b4
b3
b2
b1
b0
0
1
2
00h ILA_MON_1_0
01h ILA_MON_3_2
02h ILA_BUF_ERR
R
R
R
ILA_MON_LN1[3:0]
ILA_MON_LN3[3:0]
ILA_MON_LN0[3:0
ILA_MON_LN2[3:0]
uuuuuuuu uuh
uuuuuuuu uuh
-
-
-
-
ILA_BUF_
ERR_LN3
ILA_BUF_
ERR_LN2
ILA_BUF_
ERR_LN1
ILA_BUF_ uuuuuuuu uuh
ERR_LN0
3
4
03h CA_MON
R
R
CA_MON_LN3[1:0]
CA_MON_LN2[1:0]
CA_MON_LN1[1:0]
CA_MON_LN0[1:0]
uuuuuuuu uuh
04h DEC_FLAGS
DEC_NIT DEC_NIT DEC_NIT_ DEC_NIT_ DEC_DISP_ DEC_DISP_ DEC_DISP_ DEC_DISP_ uuuuuuuu uuh
_ERR_
LN3
_ERR_
LN2
ERR_LN1
-
ERR_LN0
-
ERR_LN3
ERR_LN2
ERR_LN1
ERR_LN0
5
05h KOUT_FLAG
R
-
-
DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ uuuuuuuu uuh
LN3 LN2 LN1 LN0
6
7
8
9
06h K28_LN0_FLAG
07h K28_LN1_FLAG
08h K28_LN2_FLAG
09h K28_LN3_FLAG
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K28_7_LN0 K28_5_LN0 K28_4_LN0 K28_3_LN0 K28_0_LN0 uuuuuuuu uuh
K28_7_LN1 K28_5_LN1 K28_4_LN1 K28_3_LN1 K28_0_LN1 uuuuuuuu uuh
K28_7_LN2 K28_5_LN2 K28_4_LN2 K28_3_LN2 K28_0_LN2 uuuuuuuu uuh
K28_7_LN3 K28_5_LN3 K28_4_LN3 K28_3_LN3 K28_0_LN3 uuuuuuuu uuh
10 0Ah KOUT_
UNEXPECTED_
-
DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ uuuuuuuu uuh
UNEXP_LN3 UNEXP_LN2 UNEXP_LN1 UNEXP_LN0
FLAG
11 0Bh LOCK_CNT_
MON_LN01
R
R
LOCK_CNT_MON_LN1[3:0]
LOCK_CNT_MON_LN3[3:0]
LOCK_CNT_MON_LN0[3:0]
LOCK_CNT_MON_LN2[3:0]
uuuuuuuu uuh
uuuuuuuu uuh
12 0Ch LOCK_CNT_
MON_LN23
13 0Dh CS_STATE_LNX R
CS_STATE_LN3[1:0]
CS_STATE_LN2[1:0]
CS_STATE_LN1[1:0]
CS_STATE_LN0[1:0]
uuuuuuuu uuh
00000000 00h
14 0Eh RST_BUF_ERR_ R/W
FLAGS
RST_
BUF_
-
-
-
-
-
-
-
ERR_
FLAGS
15 0Fh INTR_MISC_
ENA
R/W
INTR_
INTR_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ 00000000 00h
ENA_ ENA_CS_ CS_INIT_
CS_
CS_INIT_
LN0
BUF_ERR_ BUF_ERR_ BUF_ERR_ BUF_ERR_
LN3 LN2 LN1 LN0
INIT_LN2
LN1
INIT_LN3
16 10h FLAG_CNT_LSB R
_LN0
FLAG_CNT_LN0[7:0]
uuuuuuuu uuh
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 109. Page 5 register allocation map …continued
Address Register name R/W Bit definition
b7 b6
Default[1]
Bin Hex
b5
b4
b3
b2
b1
b0
17 11h FLAG_CNT_
MSB_LN0
R
FLAG_CNT_LN0[15:8]
FLAG_CNT_LN1[7:0]
FLAG_CNT_LN1[15:8]
FLAG_CNT_LN2[7:0]
FLAG_CNT_LN2[15:8]
FLAG_CNT_LN3[7:0]
FLAG_CNT_LN3[15:8]
BER_LEVEL[7:0]
uuuuuuuu uuh
uuuuuuuu uuh
uuuuuuuu uuh
uuuuuuuu uuh
uuuuuuuu uuh
uuuuuuuu uuh
uuuuuuuu uuh
00000000 00h
00000000 00h
18 12h FLAG_CNT_LSB R
_LN1
19 13h FLAG_CNT_
MSB_LN1
R
20 14h FLAG_CNT_LSB R
_LN2
21 15h FLAG_CNT_
MSB_LN2
R
22 16h FLAG_CNT_LSB R
_LN3
23 17h FLAG_CNT_
MSB_LN3
R
24 18h BER_LEVEL_
LSB
R/W
R/W
R/W
25 19h BER_LEVEL_
MSB
BER_LEVEL[15:8]
26 1Ah INTR_ENA
INTR_
INTR_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ 00000000 00h
ENA_
NIT
ENA_
DISP
KOUT
KOUT_
UNEXP
K28_7
K28_5
K28_3
MISC
27 1Bh CNTRL_
FLAGCNT_LN01
R/W
R/W
RST_
CFC_
LN1
SEL_CFC_LN1[2:0]
RST_CFC_
LN0
SEL_CFC_LN0[2:0]
01010101 55h
01010101 55h
28 1Ch CNTRL_
FLAGCNT_LN23
RST_
CFC_LN3
SEL_CFC_LN3[2:0]
RST_CFC_
LN2
SEL_CFC_LN2[2:0]
29 1Dh MON_FLAGS_ R/W RST_NIT
RST_
DISP_
ERR_
RST_KOUT RST_KOUT RST_K28_
RST_K28_
RST_K28_
RST_K28_ 00000000 00h
RESET
_ERR-
FLAGS
_FLAGS
_UNEXPEC LN3_FLAGS LN2_FLAGS LN1_FLAGS LN0_FLAGS
TED_FLAGS
FLAGS
30 1Eh DBG_CNTRL
R/W
R/W
BER_
MODE
INTR_
CLEAR
INTR_MODE[2:0]
-
-
-
-
00000000 00h
00000000 00h
31 1Fh PAGE_
ADDRESS
-
-
-
-
PAGE[2:0]
[1] u = undefined at power-up or after reset.
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.10 Page 5 bit definition detailed description
Please refer to Table 109 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 110. ILA_MON_1_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
3 to 0
ILA_MON_LN1[3:0]
ILA_MON_LN0[3:0]
R
R
-
-
ila_buf_ln1 pointer
ila_buf_ln0 pointer
Table 111. ILA_MON_3_2 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
3 to 0
ILA_MON_LN3[3:0]
ILA_MON_LN2[3:0]
R
R
-
-
ila_buf_ln3 pointer
ila_buf_ln2 pointer
Table 112. ILA_BUF_ERR register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3
ILA_BUF_ERR_LN3
R
lane 3 ila buffer error
0
1
ila_buf_ln3 pointer is in range
ila_buf_ln3 pointer is out of range
lane 2 ila buffer error
2
1
0
ILA_BUF_ERR_LN2
ILA_BUF_ERR_LN1
ILA_BUF_ERR_LN0
R
R
R
0
1
ila_buf_ln2 pointer is in range
ila_buf_ln2 pointer is out of range
lane 1 ila buffer error
0
1
ila_buf_ln1 pointer is in range
ila_buf_ln1 pointer is out of range
lane 0 ila buffer error
0
1
ila_buf_ln0 pointer is in range
ila_buf_ln0 pointer is out of range
Table 113. CA_MON register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
5 to 4
3 to 2
1 to 0
CA_MON_LN3[1:0]
CA_MON_LN2[1:0]
CA_MON_LN1[1:0]
CA_MON_LN0[1:0]
R
R
R
R
-
-
-
-
clock alignment phase monitor lane 3
clock alignment phase monitor lane 2
clock alignment phase monitor lane 1
clock alignment phase monitor lane 0
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
70 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 114. DEC_FLAGS register (address 04h) bit description
Bit
7
Symbol
Access
Value
Description
DEC_NIT_ERR_LN3
DEC_NIT_ERR_LN2
DEC_NIT_ERR_LN1
DEC_NIT_ERR_LN0
DEC_DISP_ERR_LN3
DEC_DISP_ERR_LN2
DEC_DISP_ERR_LN1
DEC_DISP_ERR_LN0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
not-in-table error flag lane 3
not-in-table error flag lane 2
not-in-table error flag lane 1
not-in-table error flag lane 0
disparity error flag lane 3
disparity error flag lane 2
disparity error flag lane 1
disparity error flag lane 0
6
5
4
3
2
1
0
Table 115. KOUT_FLAG register (address 05h) bit description
Bit
3
Symbol
Access
Value
Description
DEC_KOUT_LN3
DEC_KOUT_LN2
DEC_KOUT_LN1
DEC_KOUT_LN0
R
R
R
R
-
-
-
-
/K/ symbols found in lane 3
/K/ symbols found in lane 2
/K/ symbols found in lane 1
/K/ symbols found in lane 0
2
1
0
Table 116. K28_LN0_FLAG register (address 06h) bit description
Bit
4
Symbol
Access
Value
Description
K28_7_LN0
K28_5_LN0
K28_4_LN0
K28_3_LN0
K28_0_LN0
R
R
R
R
R
-
-
-
-
-
K28_7 /F/ symbols found in lane 0
K28_5 /K/ symbols found in lane 0
K28_4 /Q/ symbols found in lane 0
K28_3 /A/ symbols found in lane 0
K28_0 /R/ symbols found in lane 0
3
2
1
0
Table 117. K28_LN1_FLAG register (address 07h) bit description
Bit
4
Symbol
Access
Value
Description
K28_7_LN1
K28_5_LN1
K28_4_LN1
K28_3_LN1
K28_0_LN1
R
R
R
R
R
-
-
-
-
-
K28_7 /F/ symbols found in lane 1
K28_5 /K/ symbols found in lane 1
K28_4 /Q/ symbols found in lane 1
K28_3 /A/ symbols found in lane 1
K28_0 /R/ symbols found in lane 1
3
2
1
0
Table 118. K28_LN2_FLAG register (address 08h) bit description
Bit
4
Symbol
Access
Value
Description
K28_7_LN2
K28_5_LN2
K28_4_LN2
K28_3_LN2
K28_0_LN2
R
R
R
R
R
-
-
-
-
-
K28_7 /F/ symbols found in lane 2
K28_5 /K/ symbols found in lane 2
K28_4 /Q/ symbols found in lane 2
K28_3 /A/ symbols found in lane 2
K28_0 /R/ symbols found in lane 2
3
2
1
0
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
71 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 119. K28_LN3_FLAG register (address 09h) bit description
Bit
4
Symbol
Access
Value
Description
K28_7_LN3
K28_5_LN3
K28_4_LN3
K28_3_LN3
K28_0_LN3
R
R
R
R
R
-
-
-
-
-
K28_7 /F/ symbols found in lane 3
K28_5 /K/ symbols found in lane 3
K28_4 /Q/ symbols found in lane 3
K28_3 /A/ symbols found in lane 3
K28_0 /R/ symbols found in lane 3
3
2
1
0
Table 120. KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description
Bit
3
Symbol
Access
Value
Description
DEC_KOUT_UNEXP_LN3
DEC_KOUT_UNEXP_LN2
DEC_KOUT_UNEXP_LN1
DEC_KOUT_UNEXP_LN0
R
R
R
R
-
-
-
-
unexpected /K/ symbols found in lane 3
unexpected /K/ symbols found in lane 2
unexpected /K/ symbols found in lane 1
unexpected /K/ symbols found in lane 0
2
1
0
Table 121. LOCK_CNT_MON_LN01 register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
LOCK_CNT_MON_LN1[3:0]
R
-
lock_state monitor synchronization word alignment
lane 1
3 to 0
LOCK_CNT_MON_LN0[3:0]
R
-
lock_state monitor synchronization word alignment
lane 0
Table 122. LOCK_CNT_MON_LN23 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
LOCK_CNT_MON_LN3[3:0]
R
-
lock_state monitor synchronization word alignment
lane 3
3 to 0
LOCK_CNT_MON_LN2[3:0]
R
-
lock_state monitor synchronization word alignment
lane 2
Table 123. CS_STATE_LNX register (address 0Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
5 to 4
3 to 2
1 to 0
CS_STATE_LN3[1:0]
CS_STATE_LN2[1:0]
CS_STATE_LN1[1:0]
CS_STATE_LN0[1:0]
R
R
R
R
-
-
-
-
monitor cs_state fsm lane 3
monitor cs_state fsm lane 2
monitor cs_state fsm lane 1
monitor cs_state fsm lane 0
Table 124. RST_BUF_ERR_FLAGS register (address 0Eh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
RST_BUF_ERR_FLAGS
R/W
0
reset ILA_BUF_ERR_LNn flags
DAC1008D650
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
72 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 125. INTR_MISC_ENA register (address 0Fh) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
Description
INTR_ENA_CS_INIT_LN3
INTR_ENA_CS_INIT_LN2
INTR_ENA_CS_INIT_LN1
INTR_ENA_CS_INIT_LN0
INTR_ENA_BUF_ERR_LN3
INTR_ENA_BUF_ERR_LN2
INTR_ENA_BUF_ERR_LN1
INTR_ENA_BUF_ERR_LN0
0
0
0
0
0
0
0
0
intr_misc in case cs_state_ln3 = cs_init
intr_misc in case cs_state_ln2 = cs_init
intr_misc in case cs_state_ln1 = cs_init
intr_misc in case cs_state_ln0 = cs_init
generate interrupt if ILA_BUF_ERR_LN3 = 1
generate interrupt if ILA_BUF_ERR_LN2 = 1
generate interrupt if ILA_BUF_ERR_LN1 = 1
generate interrupt if ILA_BUF_ERR_LN0 = 1
6
5
4
3
2
1
0
Table 126. FLAG_CNT_LSB_LN0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN0[7:0]
R
-
LSBs of flag_counter lane 0
Table 127. FLAG_CNT_MSB_LN0 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN0[15:8]
R
-
MSBs of flag_counter lane 0
Table 128. FLAG_CNT_LSB_LN1 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN1[7:0]
R
-
LSBs of flag_counter lane 1
Table 129. FLAG_CNT_MSB_LN1 register (address 13h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN1[15:8]
R
-
MSBs of flag_counter lane 1
Table 130. FLAG_CNT_LSB_LN2 register (address 14h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN2[7:0]
R
-
LSBs of flag_counter lane 2
Table 131. FLAG_CNT_MSB_LN2 register (address 15h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN2[15:8]
R
-
MSBs of flag_counter lane 2
Table 132. FLAG_CNT_LSB_LN3 register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN3[7:0]
R
-
LSBs of flag_counter lane 3
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
73 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 133. FLAG_CNT_MSB_LN3 register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FLAG_CNT_LN3[15:8]
R
-
MSBs of flag_counter lane 3
Table 134. BER_LEVEL_LSB register (address 18h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
BER_LEVEL[7:0]
R/W
00h
LSBs level used for simple (DC) BER-measurement
Table 135. BER_LEVEL_MSB register (address 19h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
BER_LEVEL[15:8]
R/W
00h
MSBs level used for simple (DC)
BER-measurement
Table 136. INTR_ENA register (address 1Ah) bit description
Bit
Symbol
Access
Value
Description
7
INTR_ENA_NIT
R/W
not-in-table interrupt
no action
0
1
nit-error in ln<x> affects i_ln<x>
disparity-error interrupt
no action
6
5
INTR_ENA_DISP
INTR_ENA_KOUT
R/W
R/W
0
1
disparity-error in ln<x> affects i_ln<x>
K-character interrupt
no action
0
1
detection k-control character in ln<x> affects
i_ln<x>
4
INTR_ENA_KOUT_UNEXP
R/W
unexpected K-character interrupt
0
no action
1
detection unexpected K-character in ln<x> affects
i_ln<x>
3
2
1
0
INTR_ENA_K28_7
INTR_ENA_K28_5
INTR_ENA_K28_3
INTR_ENA_MISC
R/W
R/W
R/W
R/W
K28_7 interrupt
0
no action
1
detection K28_7 in ln<x> affects i_ln<x>
K28_5 interrupt
0
no action
1
detection K28_5 in ln<x> affects i_ln<x>
K28_3 interrupt
0
no action
1
detection K28_3 in ln<x> affects i_ln<x>
miscellaneous interrupt
no action
0
1
detection depends on intr_misc_ena
(see Table 125)
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
74 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 137. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
R/W
Value
0
Description
7
RST_CFC_LN1
SEL_CFC_LN1[2:0]
RST_CFC_LN0
SEL_CFC_LN0[2:0]
reset FLAG_CNT_LN1
6 to 4
3
R/W
5h
0
select FLAG_CNT_LN1 source (see Table 142)
reset FLAG_CNT_LN0
R/W
2 to 0
R/W
5h
select FLAG_CNT_LN0 source (see Table 142)
Table 138. CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
R/W
Value
0
Description
7
RST_CFC_LN3
SEL_CFC_LN3[2:0]
RST_CFC_LN2
SEL_CFC_LN2[2:0]
reset FLAG_CNT_LN3
6 to 4
3
R/W
5h
0
select FLAG_CNT_LN3 source (see Table 142)
reset FLAG_CNT_LN2
R/W
2 to 0
R/W
5h
select FLAG_CNT_LN2 source (see Table 142)
Table 139. MON_FLAGS_RESET register (address 1Dh) bit description
Bit
7
Symbol
Access
R/W
Value
Description
RST_NIT_ERR-FLAGS
RST_DISP_ERR_FLAGS
RST_KOUT_FLAGS
0
0
0
0
0
0
0
0
reset nit-error monitor flags
6
R/W
reset disparity monitor flags
5
R/W
reset K symbols monitor flags
reset unexpected K symbols monitor flags
reset K28_x monitor flags for lane 3
reset K28_x monitor flags for lane 2
reset K28_x monitor flags for lane 1
reset K28_x monitor flags for lane 0
4
RST_KOUT_UNEXPECTED_FLAGS R/W
3
RST_K28_LN3_FLAGS
RST_K28_LN2_FLAGS
RST_K28_LN1_FLAGS
RST_K28_LN0_FLAGS
R/W
R/W
R/W
R/W
2
1
0
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
75 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 140. DBG_CNTRL register (address 1Eh) bit description
Bit
Symbol
Access
Value
Description
7
BER_MODE
R/W
simple BER-measurement
no action
0
1
simple BER-measurement enabled
interrupts clear
6
INTR_CLEAR
R/W
R/W
0
no action
1
clear interrupts (to '1')
5 to 3
INTR_MODE[2:0]
interrupt settings
000
001
010
011
100
101
110
global interrupt depends on lane 0
global interrupt depends on lane 1
global interrupt depends on lane 2
global interrupt depends on lane 3
global interrupt depends on lane 0 or lane 1
global interrupt depends on lane 2 or lane 3
global interrupt depends on lane 0 or lane 1 or
lane 2 or lane 3
111
no interrupt
Table 141. PAGE_ADDRESS register (address 1Fh) bit description
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
0h
page_address
Table 142. Counter source
Default settings are shown highlighted.
SEL_CFC_LNn[2:0]
Source
000
001
010
011
100
101
110
111
not-in-table error
disparity error
K symbol found
unexpected K symbol found
K28_7 (/F/) symbol found
K28_5 (/K/) symbol found
K28_3 (/A/) symbol found
K28_0 (/R/) symbol found
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
76 of 98
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
10.15.2.11 Page 6 allocation map description
Table 143. Page 6 register allocation map
Address Register name
R/W Bit definition
b7 b6
Default[1]
Bin
b5
b4
b3
b2
b1
b0
Hex
0
1
2
3
4
5
6
7
8
9
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
LN0_CFG_0
LN0_CFG_1
LN0_CFG_2
LN0_CFG_3
LN0_CFG_4
LN0_CFG_5
LN0_CFG_6
LN0_CFG_7
LN0_CFG_8
LN0_CFG_9
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LN0_DID[7:0]
-
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
-
-
-
-
-
-
-
-
LN0_BID[3:0]
LN0_LID[4:0]
LN0_L[4:0]
LN0_SCR
LN0_F[7:0]
LN0_M[7:0]
-
-
-
LN0_K[4:0]
LN0_CS[1:0]
-
-
-
-
LN0_N[4:0]
LN0_N’[4:0]
LN0_S[4:0]
LN0_CF[4:0]
-
-
-
-
-
10 0Ah LN0_CFG_10
11 0Bh LN0_CFG_11
12 0Ch LN0_CFG_12
13 0Dh LN0_CFG_13
LN0_HD
LN0_RES1[7:0]
LN0_RES2[7:0]
LN0_FCHK[7:0]
LN1_DID[7:0]
-
16 10h
17 11h
18 12h
19 13h
20 14h
21 15h
22 16h
23 17h
24 18h
25 19h
LN1_CFG_0
LN1_CFG_1
LN1_CFG_2
LN1_CFG_3
LN1_CFG_4
LN1_CFG_5
LN1_CFG_6
LN1_CFG_7
LN1_CFG_8
LN1_CFG_9
-
-
-
-
-
-
-
LN1_BID[3:0]
-
LN1_LID[4:0]
LN1_L[4:0]
LN1_SCR
LN1_F[7:0]
LN1_M[7:0]
-
-
-
LN1_K[4:0]
LN1_CS[1:0]
-
-
-
-
LN1_N[4:0]
LN1_N’[4:0]
LN1_S[4:0]
LN1_CF[4:0]
-
-
-
-
-
26 1Ah LN1_CFG_10
27 1Bh LN1_CFG_11
LN1_HD
LN1_RES1[7:0]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 143. Page 6 register allocation map …continued
Address Register name
R/W Bit definition
b7 b6
Default[1]
Bin
b5
b4
b3
b2
b1
b0
Hex
28 1Ch LN1_CFG_12
29 1Dh LN1_CFG_13
R
R
LN1_RES2[7:0]
LN1_FCHK[7:0]
uuuuuuuu 0xuu
uuuuuuuu 0xuu
00000000 00h
31 1Fh
PAGE_ADDRESS R/W
-
-
-
-
-
PAGE[2:0]
[1] u = undefined at power-up or after reset.
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.12 Page 6 bit definition detailed description
Please refer to Table 143 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 144. LN0_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN0_DID[7:0]
R
-
lane 0 device ID
Table 145. LN0_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
LN0_BID[3:0]
R
-
lane 0 bank ID
Table 146. LN0_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN0_LID[4:0]
R
-
lane 0 lane ID
Table 147. LN0_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN0_SCR
LN0_L[4:0]
R
R
-
-
scrambling on
4 to 0
number of lanes minus 1
Table 148. LN0_CFG_4 register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN0_F[7:0]
R
-
number of octets per frame minus 1
Table 149. LN0_CFG_5 register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN0_K[4:0]
R
-
number of frames per multi-frame minus 1
Table 150. LN0_CFG_6 register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN0_M[7:0]
R
-
number of converters per device minus 1
Table 151. LN0_CFG_7 register (address 07h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
4 to 0
LN0_CS[1:0]
LN0_N[4:0]
R
R
-
-
number of control bits
converter resolution minus 1
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
79 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 152. LN0_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN0_N’[4:0]
R
-
number of bits per sample minus 1
Table 153. LN0_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN0_S[4:0]
R
-
number of samples per converter per frame cycle
minus 1
Table 154. LN0_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN0_HD
R
R
-
-
high density
4 to 0
LN0_CF[4:0]
number of control words per frame cycle
Table 155. LN0_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN0_RES1[7:0]
R
-
lane 0 reserved field
Table 156. LN0_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN0_RES2[7:0]
R
-
lane 0 reserved field
Table 157. LN0_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN0_FCHK[7:0]
R
-
lane 0 checksum
Table 158. LN1_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN1_DID[7:0]
R
-
lane 1 device ID
Table 159. LN1_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
LN1_BID[3:0]
R
-
lane 1 bank ID
Table 160. LN1_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN1_LID[4:0]
R
-
lane 1 lane ID
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
80 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 161. LN1_CFG_3 register (address 13h) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN1_SCR
LN1_L[4:0]
R
R
-
-
scrambling on
4 to 0
number of lanes minus 1
Table 162. LN1_CFG_4 register (address 14h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN1_F[7:0]
R
-
number of octets per frame minus 1
Table 163. LN1_CFG_5 register (address 15h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN1_K[4:0]
R
-
number of frames per multiframe minus 1
Table 164. LN1_CFG_6 register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN1_M[7:0]
R
-
number of converters per device minus 1
Table 165. LN1_CFG_7 register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
4 to 0
LN1_CS[1:0]
LN1_N[4:0]
R
R
-
-
number of control bits
converter resolution minus 1
Table 166. LN1_CFG_8 register (address 18h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN1_N’[4:0]
R
-
number of bits per sample minus 1
Table 167. LN1_CFG_9 register (address 19h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN1_S[4:0]
R
-
number of samples per converter per frame cycle
minus 1
Table 168. LN1_CFG_10 register (address 1Ah) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
4 to 0
LN1_HD
R
R
-
-
high density
LN1_CF[4:0]
number of control words per frame cycle
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
81 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 169. LN1_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN1_RES1[7:0]
R
-
lane 1 reserved field
Table 170. LN1_CFG_12 register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN1_RES2[7:0]
R
-
lane 1 reserved field
Table 171. LN1_CFG_13 register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN1_FCHK[7:0]
R
-
lane 1 checksum
Table 172. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
0h
page_address
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
82 of 98
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10.15.2.13 Page 7 allocation map description
Table 173. Page 7 register allocation map
Address Register name
R/W Bit definition
b7 b6
Default[1]
Bin
b5
b4
b3
b2
b1
b0
Hex
0
1
2
3
4
5
6
7
8
9
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
LN2_CFG_0
LN2_CFG_1
LN2_CFG_2
LN2_CFG_3
LN2_CFG_4
LN2_CFG_5
LN2_CFG_6
LN2_CFG_7
LN2_CFG_8
LN2_CFG_9
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LN2_DID[7:0]
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
uuuuuuuu 0xuu
-
-
-
-
-
-
-
-
-
LN2_BID[3:0]
LN2_LID[4:0]
LN2_L[4:0]
LN2_SCR
LN2_F[7:0]
LN2_M[7:0]
-
-
-
LN2_K[4:0]
LN2_CS[1:0]
-
-
-
-
LN2_N[4:0]
LN2_N’[4:0]
LN2_S[4:0]
LN2_CF[4:0]
-
-
-
-
-
10 0Ah LN2_CFG_10
11 0Bh LN2_CFG_11
12 0Ch LN2_CFG_12
13 0Dh LN2_CFG_13
LN2_HD
LN2_RES1[7:0]
LN2_RES2[7:0]
LN2_FCHK[7:0]
LN3_DID[7:0]
16 10h
17 11h
18 12h
19 13h
20 14h
21 15h
22 16h
23 17h
24 18h
25 19h
LN3_CFG_0
LN3_CFG_1
LN3_CFG_2
LN3_CFG_3
LN3_CFG_4
LN3_CFG_5
LN3_CFG_6
LN3_CFG_7
LN3_CFG_8
LN3_CFG_9
-
-
-
-
-
-
-
-
LN3_BID[3:0]
-
LN3_LID[4:0]
LN3_L[4:0]
LN3_SCR
LN3_F[7:0]
LN3_M[7:0]
-
-
-
LN3_K[4:0]
LN3_CS[1:0]
-
-
-
-
LN3_N[4:0]
LN3_N’[4:0]
LN3_S[4:0]
LN3_CF[4:0]
-
-
-
-
-
26 1Ah LN3_CFG_10
27 1Bh LN3_CFG_11
LN3_HD
LN3_RES1[7:0]
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Table 173. Page 7 register allocation map …continued
Address Register name
R/W Bit definition
b7 b6
Default[1]
Bin
b5
b4
b3
b2
b1
b0
Hex
28 1Ch LN3_CFG_12
29 1Dh LN3_CFG_13
R
R
LN3_RES2[7:0]
LN3_FCHK[7:0]
uuuuuuuu 0xuu
uuuuuuuu 0xuu
00000000 00h
31 1Fh
PAGE_ADDRESS R/W
-
-
-
-
-
PAGE[2:0]
[1] u = undefined at power-up or after reset.
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.14 Page 7 bit definition detailed description
Please refer to Table 173 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 174. LN2_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN2_DID[7:0]
R
-
lane 2 device ID
Table 175. LN2_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
LN2_BID[3:0]
R
-
lane 2 bank ID
Table 176. LN2_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN2_LID[4:0]
R
-
lane 2 lane ID
Table 177. LN2_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN2_SCR
LN2_L[4:0]
R
R
-
-
scrambling on
4 to 0
number of lanes minus 1
Table 178. LN2_CFG_4 register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN2_F[7:0]
R
-
number of octets per frame minus 1
Table 179. LN2_CFG_5 register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN2_K[4:0]
R
-
number of frames per multiframe minus 1
Table 180. LN2_CFG_6 register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN2_M[7:0]
R
-
number of converters per device minus 1
Table 181. LN2_CFG_7 register (address 07h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
4 to 0
LN2_CS[1:0]
LN2_N[4:0]
R
R
-
-
number of control bits
converter resolution minus 1
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
85 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 182. LN2_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN2_N'[4:0]
R
-
number of bits per sample minus 1
Table 183. LN2_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN2_S[4:0]
R
-
number of samples per converter per frame cycle
minus 1
Table 184. LN2_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN2_HD
R
R
-
-
high density
4 to 0
LN2_CF[4:0]
number of control words per frame cycle
Table 185. LN2_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN2_RES1[7:0]
R
-
lane 2 reserved field
Table 186. LN2_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN2_RES2[7:0]
R
-
lane 2 reserved field
Table 187. LN2_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN2_FCHK[7:0]
R
-
lane 2 checksum
Table 188. LN3_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN3_DID[7:0]
R
-
lane 3 device ID
Table 189. LN3_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
3 to 0
LN3_BID[3:0]
R
-
lane 3 bank ID
Table 190. LN3_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN3_LID[4:0]
R
-
lane 3 lane ID
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
86 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 191. LN3_CFG_3 register (address 13h) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN3_SCR
LN3_L[4:0]
R
R
-
-
scrambling on
4 to 0
number of lanes minus 1
Table 192. LN3_CFG_4 register (address 14h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN3_F[7:0]
R
-
number of octets per frame minus 1
Table 193. LN3_CFG_5 register (address 15h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN3_K[4:0]
R
-
number of frames per multiframe minus 1
Table 194. LN3_CFG_6 register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN3_M[7:0]
R
-
number of converters per device minus 1
Table 195. LN3_CFG_7 register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
4 to 0
LN3_CS[1:0]
LN3_N[4:0]
R
R
-
-
number of control bits
converter resolution minus 1
Table 196. LN3_CFG_8 register (address 18h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN3_N'[4:0]
R
-
number of bits per sample minus 1
Table 197. LN3_CFG_9 register (address 19h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
4 to 0
LN3_S[4:0]
R
-
number of samples per converter per frame cycle
minus 1
Table 198. LN3_CFG_10 register (address 1Ah) bit description
Default settings are shown highlighted.
Bit
7
Symbol
Access
Value
Description
LN3_HD
R
R
-
-
high density
4 to 0
LN3_CF[4:0]
number of control words per frame cycle
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
87 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 199. LN3_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN3_RES1[7:0]
R
-
lane 3 reserved field
Table 200. LN3_CFG_12 register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN3_RES2[7:0]
R
-
lane 3 reserved field
Table 201. LN3_CFG_13 register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
LN3_FCHK[7:0]
R
-
lane 3 checksum
Table 202. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
2 to 0
PAGE[2:0]
R/W
0h
page_address
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
88 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
11. Package outline
HVQFN64: plastic thermal enhanced very thin quad flat package; no leads;
64 terminals; body 9 x 9 x 0.85 mm
SOT804-3
D
B
A
terminal 1
index area
A
1
E
A
c
detail X
e
1
1/2 e
C
v
w
C
C
A
B
e
b
L
y
1
y
C
17
32
33
16
e
E
h
e
2
1/2 e
1
48
terminal 1
index area
64
49
X
D
h
0
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
E
A
A
1
b
c
D
D
h
E
h
e
e
e
2
L
v
w
y
y
1
1
max 1.00 0.05 0.30
9.1 7.25 9.1 7.25
0.5
mm nom 0.85 0.02 0.21 0.2 9.0 7.10 9.0 7.10 0.5 7.5 7.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 8.9 6.95 8.9 6.95 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot804-3_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
09-02-24
10-08-06
SOT804-3
Fig 27. Package outline SOT804 (HVQFN64)
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
89 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
12. Abbreviations
Table 203. Abbreviations
Acronym
AQM
Description
Analog Quadrature Modulator
Bit Error Rate
BER
BW
BandWidth
BWA
Broadband Wireless Access
Code Division Multiple Access
Current Mode Logic
CDMA
CML
CMOS
DAC
Complementary Metal Oxide Semiconductor
Digital-to-Analog Converter
DCSMU
DES
Device Configuration Management and Start-up Unit
DESerializer
EDGE
FIR
Enhanced Data rates for GSM Evolution
Finite Impulse Response
FPGA
GSM
Field Programmable Gate Array
Global System for Mobile communications
Intermediate Frequency
IF
ILA
Inter-Lane Alignment
IMD3
LMDS
LSB
third order InterMoDulation product
Local Multipoint Distribution Service
Least Significant Bit
LTE
Long Term Evolution
LVDS
MDS
Low-Voltage Differential Signaling
Multipoint Distribution Service
Multichannel Multipoint Distribution Service
Most Significant Bit
MMDS
MSB
NCO
Numerically Controlled Oscillator
Negative Metal-Oxide Semiconductor
Phase-Locked Loop
NMOS
PLL
SERDES
SFDR
SPI
SERializer/DESerializer
Spurious Free Dynamic Range
Serial Peripheral Interface
TD-SCDMA
WCDMA
WiMax
WLL
Time Division-Synchronous Code Division Multiple Access
Wideband Code Division Multiple Access
Worldwide interoperability for Microwave Access
Wireless Local Loop
DAC1008D650
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Preliminary data sheet
Rev. 1 — 1 October 2010
90 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
13. Revision history
Table 204. Revision history
Document ID
Release date
20101001
Data sheet status
Change notice
Supersedes
DAC1008D650 v.1
Preliminary data sheet
-
-
DAC1008D650
All information provided in this document is subject to legal disclaimers.
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Preliminary data sheet
Rev. 1 — 1 October 2010
91 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
92 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
93 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
16. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .6
Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 6. Digital Layer Processing Latency . . . . . . . . . . .12
Table 7. SYNC_OUT timing . . . . . . . . . . . . . . . . . . . . . .14
Table 8. Read or Write mode access description . . . . .23
Table 9. Number of bytes to be transferred . . . . . . . . . .23
Table 10. SPI timing characteristics . . . . . . . . . . . . . . . .24
Table 11. Interpolation filter coefficients . . . . . . . . . . . . .26
Table 12. Inversion filter coefficients . . . . . . . . . . . . . . . .28
Table 13. DAC transfer function . . . . . . . . . . . . . . . . . . .28
Table 14. IO(fs) coarse adjustment . . . . . . . . . . . . . . . . . .30
Table 15. IO(fs) fine adjustment . . . . . . . . . . . . . . . . . . . .30
Table 16. Digital offset adjustment . . . . . . . . . . . . . . . . .31
Table 17. Auxiliary DAC transfer function . . . . . . . . . . . .32
Table 18. Page 0 register allocation map . . . . . . . . . . . .38
Table 19. COMMON register (address 00h) bit
Table 35. DAC_CURRENT_0 register (address 11h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 36. DAC_CURRENT_1 register (address 12h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 37. DAC_CURRENT_2 register (address 13h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 38. DAC_CURRENT_3 register (address 14h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 39. DAC_SEL_PH_FINE register (address 15h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 40. PHASECORR_CNTRL0 register (address 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 41. PHASECORR_CNTRL1 register (address 17h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 42. DAC_A_AUX_MSB register (address 1Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 43. DAC_A_AUX_LSB register (address 1Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 44. DAC_B_AUX_MSB register (address 1Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 45. DAC_B_AUX_LSB register (address 1Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 46. DAC_B_AUX_LSB register (address 1Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 47. Bias current control table . . . . . . . . . . . . . . . . . 45
Table 48. Page 1 register allocation map . . . . . . . . . . . . 46
Table 49. MDS_MAIN register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 50. MDS_WIN_PERIOD_A register (address 01h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 51. MDS_WIN_PERIOD_B register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 52. MDS_MISCCNTRL0 register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 53. MDS_MAN_ADJUSTDLY register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 54. MDS_AUTO_CYCLES register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 55. MDS_MISCCNTRL1 register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 56. MDS_ADJDELAY register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 57. MDS_STATUS0 register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 58. MDS_STATUS1 register (address 0Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 59. PAGE_ADDRESS register (address 1Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 20. TXCFG register (address 01h) bit description .40
Table 21. PLLCFG register (address 02h) bit description 41
Table 22. FREQNCO_LSB register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 23. FREQNCO_LISB register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 24. FREQNCO_UISB register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 25. FREQNCO_MSB register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 26. PHINCO_LSB register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 27. PHINCO_MSB register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 28. DAC_A_CFG_1 register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 29. DAC_A_CFG_2 register (address 0Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 30. DAC_A_CFG_3 register (address 0Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 31. DAC_B_CFG_1 register (address 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 32. DAC_B_CFG_2 register (address 0Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 33. DAC_B_CFG_3 register (address 0Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 34. DAC_CFG register (address 0Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
continued >>
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
94 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 60. Page 2 register allocation map . . . . . . . . . . . .51
Table 61. MAINCONTROL register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 62. JCLK_CNTRL register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 63. RST_EXT_FCLK register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 64. RST_EXT_DCLK register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 65. DCSMU_PREDIVCNT register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 66. PLL_CHARGETIME register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 67. PLL_RUN_IN_TIME register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 68. CA_RUN_IN_TIME register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 69. SET_VCM_VOLTAGE register (address 16h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 70. SET_SYNC register (address 17h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 71. TYPE_ID register (address 1Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 72. DAC_VERSION register (address 1Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 73. DIG_VERSION register (address 1Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 74. JRX_ANA_VERSION register (address 1Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 75. PAGE_ADDRESS register (address 1Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 76. Lane common-mode voltage adjustment . . . . .55
Table 77. SYNC common-mode voltage adjustment . . . .55
Table 78. SYNC swing voltage adjustment . . . . . . . . . . .55
Table 79. Page 4 register allocation map . . . . . . . . . . . .56
Table 80. SR_DLP_0 register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 81. SR_DLP_1 register (address 01h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 82. FORCE_LOCK register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 83. MAN_LOCK_LN_1_0 register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 84. MAN_LOCK_2_0 register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 85. CA_CNTRL register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 86. SCR_CNTRL register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 87. ILA_CNTRL register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 88. FORCE_ALIGN register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 89. MAN_ALIGN_LN_0_1 register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 90. MAN_ALIGN_LN_2_3 register (address 0Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 91. FA_ERR_HANDLING register (address 0Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 92. SYNCOUT_MODE register (address 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 93. LANE_POLARITY register (address 0Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 94. LANE_SELECT register (address 0Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 95. SOFT_RESET_SCRAMBLER register (address
10h) bit description . . . . . . . . . . . . . . . . . . . . . 64
Table 96. INIT_SCR_S15T8_LN0 register (address 11h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 97. INIT_SCR_S7T1_LN0 (address 12h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 98. INIT_SCR_S15T8_LN1 register (address 13h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 99. INIT_SCR_S7T1_LN1 register (address 14h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 100. INIT_SCR_S15T8_LN2 register (address 15h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 101. INIT_SCR_S7T1_LN2 register (address 16h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 102. INIT_SCR_S15T8_LN3 register (address 17h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 103. INIT_SCR_S7T1_LN3 register (address 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 104. INIT_ILA_BUFPTR_LN01 register (address 19h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 105. INIT_ILA_BUFPTR_LN23 register (address 1Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 106. ERROR_HANDLING register (address 1Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 107. REINIT_CNTRL register (address 1Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 108. PAGE_ADDRESS register (address 1Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 109. Page 5 register allocation map . . . . . . . . . . . . 68
Table 110. ILA_MON_1_0 register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 111. ILA_MON_3_2 register (address 01h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 112. ILA_BUF_ERR register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 113. CA_MON register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
continued >>
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
95 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 114. DEC_FLAGS register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 115. KOUT_FLAG register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 116. K28_LN0_FLAG register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 117. K28_LN1_FLAG register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 118. K28_LN2_FLAG register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 119. K28_LN3_FLAG register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 120. KOUT_UNEXPECTED_FLAG register (address
0Ah) bit description . . . . . . . . . . . . . . . . . . . . .72
Table 121. LOCK_CNT_MON_LN01 register (address 0Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 122. LOCK_CNT_MON_LN23 register (address 0Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 123. CS_STATE_LNX register (address 0Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 124. RST_BUF_ERR_FLAGS register (address 0Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 125. INTR_MISC_ENA register (address 0Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 126. FLAG_CNT_LSB_LN0 register (address 10h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 127. FLAG_CNT_MSB_LN0 register (address 11h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 128. FLAG_CNT_LSB_LN1 register (address 12h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 129. FLAG_CNT_MSB_LN1 register (address 13h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 130. FLAG_CNT_LSB_LN2 register (address 14h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 131. FLAG_CNT_MSB_LN2 register (address 15h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 132. FLAG_CNT_LSB_LN3 register (address 16h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 133. FLAG_CNT_MSB_LN3 register (address 17h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 134. BER_LEVEL_LSB register (address 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 135. BER_LEVEL_MSB register (address 19h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 136. INTR_ENA register (address 1Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 137. CNTRL_FLAGCNT_LN01 register (address 1Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 138. CNTRL_FLAGCNT_LN23 register (address 1Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 139. MON_FLAGS_RESET register (address 1Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 140. DBG_CNTRL register (address 1Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 141. PAGE_ADDRESS register (address 1Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 142. Counter source . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 143. Page 6 register allocation map . . . . . . . . . . . . 77
Table 144. LN0_CFG_0 register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 145. LN0_CFG_1 register (address 01h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 146. LN0_CFG_2 register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 147. LN0_CFG_3 register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 148. LN0_CFG_4 register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 149. LN0_CFG_5 register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 150. LN0_CFG_6 register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 151. LN0_CFG_7 register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 152. LN0_CFG_8 register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 153. LN0_CFG_9 register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 154. LN0_CFG_10 register (address 0Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 155. LN0_CFG_11 register (address 0Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 156. LN0_CFG_12 register (address 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 157. LN0_CFG_13 register (address 0Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 158. LN1_CFG_0 register (address 10h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 159. LN1_CFG_1 register (address 11h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 160. LN1_CFG_2 register (address 12h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 161. LN1_CFG_3 register (address 13h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 162. LN1_CFG_4 register (address 14h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 163. LN1_CFG_5 register (address 15h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 164. LN1_CFG_6 register (address 16h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 165. LN1_CFG_7 register (address 17h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
continued >>
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
96 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
Table 166. LN1_CFG_8 register (address 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 167. LN1_CFG_9 register (address 19h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 168. LN1_CFG_10 register (address 1Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 169. LN1_CFG_11 register (address 1Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 170. LN1_CFG_12 register (address 1Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 171. LN1_CFG_13 register (address 1Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 172. PAGE_ADDRESS register (address 1Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 173. Page 7 register allocation map . . . . . . . . . . . .83
Table 174. LN2_CFG_0 register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 175. LN2_CFG_1 register (address 01h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 176. LN2_CFG_2 register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 177. LN2_CFG_3 register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 178. LN2_CFG_4 register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 179. LN2_CFG_5 register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 180. LN2_CFG_6 register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 181. LN2_CFG_7 register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 182. LN2_CFG_8 register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 183. LN2_CFG_9 register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 184. LN2_CFG_10 register (address 0Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 185. LN2_CFG_11 register (address 0Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 186. LN2_CFG_12 register (address 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 187. LN2_CFG_13 register (address 0Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 188. LN3_CFG_0 register (address 10h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 189. LN3_CFG_1 register (address 11h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 190. LN3_CFG_2 register (address 12h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 191. LN3_CFG_3 register (address 13h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 192. LN3_CFG_4 register (address 14h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 193. LN3_CFG_5 register (address 15h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 194. LN3_CFG_6 register (address 16h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 195. LN3_CFG_7 register (address 17h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 196. LN3_CFG_8 register (address 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 197. LN3_CFG_9 register (address 19h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 198. LN3_CFG_10 register (address 1Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 199. LN3_CFG_11 register (address 1Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 200. LN3_CFG_12 register (address 1Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 201. LN3_CFG_13 register (address 1Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 202. PAGE_ADDRESS register (address 1Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 203. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 204. Revision history . . . . . . . . . . . . . . . . . . . . . . . 91
DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
97 of 98
DAC1008D650
NXP Semiconductors
2×, 4× or 8× interpolating DAC with JESD204A
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
10.13.2 DC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 34
10.13.3 AC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 36
10.13.4 Phase correction . . . . . . . . . . . . . . . . . . . . . . 37
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
10.14
10.15
Power and grounding. . . . . . . . . . . . . . . . . . . 37
Configuration interface. . . . . . . . . . . . . . . . . . 37
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
10.15.1 Register description . . . . . . . . . . . . . . . . . . . . 37
10.15.2 Detailed descriptions of registers. . . . . . . . . . 37
10.15.2.1 Page 0 allocation map description. . . . . . . . . 38
10.15.2.2 Page 0 bit definition detailed description . . . . 40
10.15.2.3 Page 1 allocation map description. . . . . . . . . 46
10.15.2.4 Page 1 bit definition detailed description . . . . 47
10.15.2.5 Page 2 allocation map description. . . . . . . . . 51
10.15.2.6 Page 2 bit definition detailed description . . . . 52
10.15.2.7 Page 4 allocation map description. . . . . . . . . 56
10.15.2.8 Page 4 bit definition detailed description . . . . 58
10.15.2.9 Page 5 allocation map description. . . . . . . . . 68
10.15.2.10 Page 5 bit definition detailed description . . . 70
10.15.2.11 Page 6 allocation map description . . . . . . . . 77
10.15.2.12 Page 6 bit definition detailed description . . . 79
10.15.2.13 Page 7 allocation map description . . . . . . . . 83
10.15.2.14 Page 7 bit definition detailed description . . . 85
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
Application information. . . . . . . . . . . . . . . . . . 11
General description . . . . . . . . . . . . . . . . . . . . 11
JESD204A receiver . . . . . . . . . . . . . . . . . . . . 12
Lane input. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Sync and word align . . . . . . . . . . . . . . . . . . . . 13
Comma detection and word align. . . . . . . . . . 14
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inter-lane alignment . . . . . . . . . . . . . . . . . . . . 15
10.2.5.1 Single device operation . . . . . . . . . . . . . . . . . 15
10.2.5.2 Multi-device operation . . . . . . . . . . . . . . . . . . 16
10.2.5.3 Master/slave mode . . . . . . . . . . . . . . . . . . . . . 17
10.2.5.4 All slave mode . . . . . . . . . . . . . . . . . . . . . . . . 20
10.2.6
10.3
10.3.1
10.3.2
10.4
11
12
13
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 89
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90
Revision history . . . . . . . . . . . . . . . . . . . . . . . 91
Frame assembly. . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface (SPI). . . . . . . . . . . 23
Protocol description . . . . . . . . . . . . . . . . . . . . 23
SPI timing description. . . . . . . . . . . . . . . . . . . 24
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quadrature modulator and Numerically
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 92
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 92
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.1
14.2
14.3
14.4
10.5
10.6
Controlled Oscillator (NCO) . . . . . . . . . . . . . . 27
NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27
Low-power NCO. . . . . . . . . . . . . . . . . . . . . . . 27
Minus_3dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
x / (sin x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DAC transfer function . . . . . . . . . . . . . . . . . . . 28
Full-scale current . . . . . . . . . . . . . . . . . . . . . . 29
Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15
16
17
Contact information . . . . . . . . . . . . . . . . . . . . 93
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.6.1
10.6.2
10.6.3
10.7
10.8
10.9
10.9.1
10.9.1.1 External regulation . . . . . . . . . . . . . . . . . . . . . 29
10.9.2
10.10
10.11
10.12
10.13
Full-scale current adjustment . . . . . . . . . . . . . 29
Digital offset correction . . . . . . . . . . . . . . . . . . 30
Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32
Output configuration . . . . . . . . . . . . . . . . . . . . 33
10.13.1 Basic output configuration . . . . . . . . . . . . . . . 33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 October 2010
Document identifier: DAC1008D650
相关型号：
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