DAC1403D160HW [NXP]

Dual 14 bits DAC, up to 160 MHz, 2 x interpolating; 双通道14位DAC ,高达160兆赫, 2×插值
DAC1403D160HW
型号: DAC1403D160HW
厂家: NXP    NXP
描述:

Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
双通道14位DAC ,高达160兆赫, 2×插值

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DAC1403D160  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
Rev. 02 — 14 August 2008  
Product data sheet  
1. General description  
The DAC1403D160 is optimized to reduce architecture complexity and overall system  
cost. It leads to dynamic performance in multi-carrier support, because of its direct IF  
conversion capabilities. With an internal sampling rate of up to 160 MHz, DAC1403D160  
is an extremely competitive solution for broadband wireless systems transmitters, as well  
as a wide range of applications.  
2. Features  
I Dual 14-bit resolution  
I Spurious-Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz  
I Input data rate up to 80 MHz  
I 2 × interpolation filter  
I Output data rate up to 160 MHz  
I Single 3.3 V power supply  
I Low noise capacitor-free integrated Phase-Locked Loup (PLL)  
I Low power dissipation  
I HTQFP80 package  
I Ambient temperature from 40 °C to +85 °C  
3. Applications  
I Broadband wireless systems  
I Digital radio links  
I Cellular base stations  
I Instrumentation  
I Cable modem  
I Cable Modem Termination System (CMTS)/Data Over Cable Service Interface  
Specification (DOCSIS)  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
DAC1403D160HW HTQFP80  
plastic thermal enhanced thin quad flat package; 80 leads;  
SOT841-1  
body 12 × 12 × 1 mm; exposed die pad  
5. Block diagram  
V
CCA  
U/I  
DAC1403D160  
60  
IVIRES  
11 to 16,  
19 to 24,  
27, 28  
73  
72  
IOUT  
I13 to I0  
LATCH  
DAC  
14  
14  
14  
IOUTN  
FIR  
(CLK × 2)  
PLL  
5
6
CLK  
CLOCK  
DRIVER  
INTERNAL 58  
BAND GAP  
(CLK × 2)  
GAPOUT  
GAPD  
CLKN  
31 to 34,  
37 to 42,  
45 to 48  
(CLK × 2)  
57  
69  
68  
QOUT  
Q13 to Q0  
LATCH  
DAC  
14  
14  
14  
QOUTN  
FIR  
U/I  
59  
2, 8  
i.c.  
QVIRES  
10, 51  
(1)  
V
CCA  
V
CCD  
(2)  
(3)  
(4)  
014aaa509  
V
AGND DGND DEC  
CCA  
(1) Pins 1, 3, 61, 65, 76 and 80.  
(2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79.  
(3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56.  
(4) Pins 18, 26, 36, 43, 63 and 78.  
Fig 1. Block diagram  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
2 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
6. Pinning information  
6.1 Pinning  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
V
V
IVIRES  
QVIRES  
GAPOUT  
GAPD  
CCA  
2
3
i.c.  
CCA  
4
AGND  
CLK  
5
DGND  
DGND  
DGND  
DGND  
DGND  
6
CLKN  
AGND  
i.c.  
7
8
9
DGND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
V
CCD  
V
CCD  
DAC1403D160HW  
I13  
DGND  
DGND  
Q0  
I12  
I11  
I10  
I9  
Q1  
Q2  
DGND  
I8  
Q3  
DGND  
DEC  
I7  
DGND  
DEC  
Q4  
I6  
Q5  
014aaa510  
Fig 2. Pin configuration  
6.2 Pin description  
Table 2.  
Symbol  
VCCA  
Pin description  
Pin  
Type[1] Description  
1
S analog supply voltage  
i.c.  
2
3
4
5
6
7
8
9
I/O  
S
G
I
internally connected; leave open  
analog supply voltage  
analog ground  
VCCA  
AGND  
CLK  
clock input  
CLKN  
AGND  
i.c.  
I
complementary clock input  
analog ground  
G
O
G
internally connected; leave open  
digital ground  
DGND  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
3 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
Table 2.  
Pin description …continued  
Type[1] Description  
Symbol  
VCCD  
I13  
Pin  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
S
I
digital supply voltage  
I data input bit 13 (Most Significant Bit (MSB))  
I data input bit 12  
I data input bit 11  
I data input bit 10  
I data input bit 9  
I12  
I
I11  
I
I10  
I
I9  
I
I8  
I
I data input bit 8  
DGND  
DEC  
I7  
G
O
I
digital ground  
decoupling node  
I data input bit 7  
I6  
I
I data input bit 6  
I5  
I
I data input bit 5  
I4  
I
I data input bit 4  
I3  
I
I data input bit 3  
I2  
I
I data input bit 2  
DGND  
DEC  
I1  
G
O
I
digital ground  
decoupling node  
I data input bit 1  
I0  
I
I data input bit 0 (Least Significant Bit (LSB))  
digital ground  
DGND  
DGND  
Q13  
Q12  
Q11  
Q10  
DGND  
DEC  
Q9  
G
G
I
digital ground  
Q data input bit 13 (MSB)  
Q data input bit 12  
Q data input bit 11  
Q data input bit 10  
digital ground  
I
I
I
G
O
I
decoupling node  
Q data input bit 9  
Q data input bit 8  
Q data input bit 7  
Q data input bit 6  
Q data input bit 5  
Q data input bit 4  
decoupling node  
digital ground  
Q8  
I
Q7  
I
Q6  
I
Q5  
I
Q4  
I
DEC  
DGND  
Q3  
O
G
I
Q data input bit 3  
Q data input bit 2  
Q data input bit 1  
Q data input bit 0 (LSB)  
digital ground  
Q2  
I
Q1  
I
Q0  
I
DGND  
DGND  
G
G
digital ground  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
4 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
Table 2.  
Pin description …continued  
Type[1] Description  
Symbol  
VCCD  
Pin  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
S
G
G
G
G
G
I
digital supply voltage  
digital ground  
DGND  
DGND  
DGND  
DGND  
DGND  
GAPD  
GAPOUT  
QVIRES  
IVIRES  
VCCA  
digital ground  
digital ground  
digital ground  
digital ground  
internal band gap power disable input  
band gap output voltage  
Q DAC biasing resistor  
I DAC biasing resistor  
analog supply voltage  
analog ground  
I/O  
I
I
S
G
O
G
S
G
G
O
O
G
G
O
O
G
G
S
G
O
G
S
AGND  
DEC  
decoupling node  
AGND  
VCCA  
analog ground  
analog supply voltage  
analog ground  
AGND  
AGND  
QOUTN  
QOUT  
AGND  
AGND  
IOUTN  
IOUT  
analog ground  
complementary Q DAC output current  
Q DAC output current  
analog ground  
analog ground  
complementary I DAC output current  
I DAC output current  
analog ground  
AGND  
AGND  
VCCA  
analog ground  
analog supply voltage  
analog ground  
AGND  
DEC  
decoupling node  
AGND  
VCCA  
analog ground  
analog supply voltage  
[1] Type description: S: Supply; G: Ground; I: Input; O: Output.  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
5 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
7. Functional description  
The Digital-to-Analog Converter (DAC) is a segmented architecture composed of a 7-bit  
thermometer sub-DAC and the remaining 7-bit in a binary weighted sub-DAC.  
The device produces two complementary current outputs on both channels, respectively  
pins IOUT/IOUTN and QOUT/QOUTN which need to be connected via a load resistor to  
the ground.  
Figure 3 shows the equivalent analog output circuit of one DAC, which consists of a  
parallel combination of PMOS current sources and associated switches for each segment.  
The cascade source configuration enables the increasing of the output impedance of the  
source and set to improve the dynamic performance of the DAC by introducing less  
distortion.  
Figure 4 shows the internal reference configuration. In this case the bias current is given  
by the output of the internal regulator connected to the inverting input of the internal  
operational amplifiers, while external resistors RI and RQ are connected respectively to  
pins IVIRES and QVIRES. Thus the output current of the two DACs is typically fixed to  
20 mA with an appropriate choice of these resistors. This configuration is optimal for  
temperature drift compensation because the band gap can be matched with the voltage  
on the feedback resistors.  
The relation between full-scale output current IO(fs) and the RI (RQ) is:  
2048 × V  
RI =  
GAPOUT Ω  
-----------------------------------------  
82 × IO( fs)  
The output current can also be adjusted by imposing an external reference voltage to the  
inverting input pin GAPOUT and disabling the internal band gap with pin GAPD set to  
HIGH. At a voltage lower than 1.2 V the current can be set at values lower than 20 mA.  
The input references at pins IVIRES and QVIRES may also be driven by separate  
reference voltages to adjust independently the two DAC currents.  
DAC1403D160  
GAPD  
INTERNAL  
BAND GAP  
AGND  
GAPOUT  
R
I
I DAC current  
sources array  
IVIRES  
DAC1403D160  
IOUT/QOUT  
IOUTN/QOUTN  
R
L
R
L
R
Q
Q DAC current  
sources array  
QVIRES  
AGND AGND  
014aaa514  
014aaa515  
Fig 3. Equivalent analog output circuit  
Fig 4. Internal reference configuration  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
6 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
8. Limiting values  
Table 3.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
[1]  
[1]  
VCCD  
digital supply  
voltage  
0.3  
+3.9  
V
VCCA  
VCC  
VI  
analog supply  
voltage  
0.3  
150  
0.3  
0.3  
0.3  
0.3  
+3.9  
V
supply voltage  
difference  
V
CCA VCCD  
+150  
mV  
V
input voltage  
pins Qn and In referenced to  
DGND  
VCCD + 0.3  
VCCA + 0.3  
VCCA + 0.3  
pins IVIRES, QVIRES and  
GAPD referenced to AGND  
V
pins CLK and CLKN  
referenced to AGND  
V
VO  
output voltage  
pins IOUT, IOUTN, QOUT  
and QOUTN referenced to  
AGND  
V
CCA + 0.3  
V
Tstg  
Tamb  
Tj  
storage  
temperature  
55  
40  
-
+150  
+85  
°C  
°C  
°C  
ambient  
temperature  
junction  
125  
temperature  
[1] All supplies are connected together.  
9. Thermal characteristics  
Table 4.  
Thermal characteristics  
Parameter  
Symbol  
Conditions  
Typ  
Unit  
Rth(j-a)  
thermal resistance from junction in free air  
to ambient  
27.1  
K/W  
Rth(c-a)  
thermal resistance from case to  
ambient  
in free air  
11.8  
K/W  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
7 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
10. Characteristics  
Table 5.  
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 °C to +85 °C; typical values measured at  
CCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in  
Figure 10; unless otherwise specified.  
Characteristics  
V
Symbol  
Supplies  
VCCD  
VCCA  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
digital supply voltage  
analog supply voltage  
digital supply current  
analog supply current  
total power dissipation  
3.0  
3.3  
3.3  
55  
3.6  
3.6  
65  
V
3.0  
V
ICCD  
-
-
-
mA  
mA  
mW  
ICCA  
73  
85  
Ptot  
fclk = 80 MHz;  
422  
540  
fIOUT = fQOUT = 5 MHz  
Clock inputs (CLK and CLKN)  
VI(cm)  
common-mode input  
voltage  
-
-
1.65  
1.0  
-
-
V
V
Vi(dif)(p-p)  
peak-to-peak differential  
input voltage  
Analog outputs (IOUT, IOUTN, QOUT and QOUTN)  
IO(fs)  
Ro  
full-scale output current  
output resistance  
differential outputs  
4
-
-
20  
-
mA  
kΩ  
pF  
[1]  
[1]  
150  
3
Co  
output capacitance  
-
-
Digital inputs (I0 to I13, Q0 to Q13 and GAPD)  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
DGND  
-
0.3 VCCD  
V
0.7 VCCD  
-
VCCD  
V
VIL = 0.3 VCCD  
VIH = 0.7 VCCD  
-
-
5
5
-
-
µA  
µA  
IIH  
Reference voltage output (GAPOUT)  
VGAPOUT  
IGAPOUT  
voltage on pin GAPOUT  
current on pin GAPOUT  
-
-
-
1.31  
1
-
-
-
V
external voltage  
µA  
VGAPOUT voltage variation on pin  
±133  
ppm/°C  
GAPOUT  
Clock timing inputs (CLK and CLKN)  
fclk  
clock frequency  
-
-
-
-
80  
-
MHz  
ns  
tw(clk)H  
tw(clk)L  
HIGH clock pulse width  
LOW clock pulse width  
5
5
-
ns  
Input timing (I0 to I13 and Q0 to Q13); see Figure 5  
th(i)  
input hold time  
1.1  
-
-
3.4  
ns  
ns  
tsu(i)  
input set-up time  
1.5  
+0.7  
Output timing (IOUT, IOUTN, QOUT, QOutN)  
[1]  
ts  
settling time  
to = ± 0.5 LSB  
-
43  
-
ns  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
8 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
Table 5.  
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 °C to +85 °C; typical values measured at  
CCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in  
Figure 10; unless otherwise specified.  
Characteristics …continued  
V
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Digital filter specification (FIR); order N = 42; see Figure 6 and 7 and Table 7  
fdata  
data rate  
-
-
-
-
-
-
80  
-
MHz  
αripple(pb)  
Bp  
αstpb  
td(grp)  
pass-band ripple  
power bandwidth  
stop-band attenuation  
group delay time  
fdata/fclk; 0.005 dB attenuation  
fdata/fclk; 3 dB attenuation  
fdata/fclk = 0.6 to 1  
0.405  
0.479  
69  
-
-
dB  
ns  
11TCLK  
-
Analog signal processing  
Linearity  
INL  
integral non-linearity  
-
±2.9  
±1.5  
120  
0.3  
-
-
LSB  
LSB  
pA/Hz  
%
DNL  
In(o)  
differential non-linearity  
output noise current  
offset error  
-
-
-
-
Eoffset  
EG  
relative to full-scale  
relative to full-scale  
-
-
gain error  
5.4  
+5.4  
-
%
GIQ  
IQ gain mismatch  
between I and Q, relative to  
full-scale  
-
±0.2  
%
Spurious free dynamic range  
SFDR  
spurious free dynamic  
range  
fclk = 80 MHz; BW = Nyquist  
fo = 2.5 MHz at 0 dBFS  
fo = 5 MHz at 0 dBFS  
-
-
-
80  
72  
64  
-
-
-
dBc  
dBc  
dBc  
fo = 13 MHz at 0 dBFS  
Harmonics  
α2H  
second harmonic level  
third harmonic level  
fo = 5 MHz  
fo = 13 MHz  
fo = 5 MHz  
fo = 13 MHz  
-
-
-
-
73  
65  
88  
86  
-
-
-
-
dBc  
dBc  
dBc  
dBc  
α3H  
Two-tone intermodulation  
IMD2  
IMD3  
THD  
second-order  
intermodulation distortion  
fclk = 80 MHZ; fo 1 = 10 MHz;  
fo 2 = 12 MHz; BW = Nyquist  
-
-
65  
84  
-
-
dBc  
dBc  
third-order intermodulation fclk = 80 MHz; fo 1 = 10 MHz;  
distortion  
fo 2 = 12 MHz  
total harmonic distortion  
fclk = 80 MHz; BW = Nyquist (Tamb = 25 °C)  
fo = 2.5 MHz  
fo = 5 MHz  
-
75  
71  
-
-
dBc  
dBc  
68  
NSD  
noise spectral density  
fclk = 80 MHz  
fo = 2.5 MHz  
fo = 5 MHz  
-
-
-
155  
155  
153  
-
-
-
dBm/Hz  
dBm/Hz  
dBm/Hz  
fo = 19 MHz  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
9 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
Table 5.  
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 °C to +85 °C; typical values measured at  
CCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in  
Figure 10; unless otherwise specified.  
Characteristics …continued  
V
Symbol Parameter  
Signal-to-noise ratio  
Conditions  
Min  
Typ  
Max  
Unit  
S/N  
signal-to-noise ratio  
fclk = 80 MHz; BW = Nyquist  
fo = 2.5 MHz  
-
80  
80  
78  
-
-
-
dBc  
dBc  
dBc  
fo = 5 MHz  
70  
-
fo = 19 MHz  
ACPR  
adjacent channel power  
ratio  
baseband; 5 MHz channel spacing; BW = 3.84 MHz  
fo = 2.5 MHz  
fo = 20 MHz  
-
-
69  
71  
-
-
dBc  
dBc  
[1] Guaranteed by design.  
Table 6.  
Band gap  
Band gap disable (GAPD)  
Band gap input/output (GAPOUT)  
output (VGAPOUT = 1.2 V)  
input  
Internal band gap  
enable  
LOW  
HIGH  
disable  
t
su(i)  
I0 to I13,  
Q0 to Q13  
CLKN  
CLK  
50 %  
t
h(i)  
IOUT/IOUTN,  
QOUT/QOUTN  
014aaa511  
Fig 5. Input timing diagram  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
10 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
014aaa512  
014aaa513  
20  
0.6  
output  
(dB)  
normalized output  
20  
60  
0.4  
0.2  
0
100  
140  
180  
0.2  
0
0.2  
0.4  
0.6  
0.8  
o
1.0  
0
10  
20  
30  
40  
normalized frequency (f /f  
)
clk  
t (sample)  
Fig 6. FIR filter frequency response  
Fig 7. FIR filter impulse response  
Table 7.  
Coefficient  
H(1)  
Interpolation FIR filter coefficient  
Coefficient  
H(43)  
H(42)  
H(41)  
H(40)  
H(39)  
H(38)  
H(37)  
H(36)  
H(35)  
H(34)  
H(33)  
H(32)  
H(31)  
H(30)  
H(29)  
H(28)  
H(27)  
H(26)  
H(25)  
H(24)  
H(23)  
-
Value  
10  
H(2)  
0
H(3)  
31  
0
H(4)  
H(5)  
69  
H(6)  
0
H(7)  
138  
0
H(8)  
H(9)  
248  
0
H(10)  
H(11)  
H(12)  
H(13)  
H(14)  
H(15)  
H(16)  
H(17)  
H(18)  
H(19)  
H(20)  
H(21)  
H(22)  
419  
0
678  
0
1083  
0
1776  
0
3282  
0
10364  
16384  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
11 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
11. Application information  
AGND  
DAC1403D160  
1 k  
CLK  
100 nF  
DAC1403D160  
1 kΩ  
R
s
CLK  
V
CCA  
V
CCA  
100 nF  
100 nF  
AGND  
1 kΩ  
1 kΩ  
1 kΩ  
1 kΩ  
CLKN  
V
th  
CLKN  
100 nF  
AGND  
AGND  
014aaa516  
014aaa517  
Fig 8. Single-ended clock schematic  
Fig 9. Differential clock schematic  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
12 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
50 Ω  
50 Ω  
R
L
R
L
1:1  
1:1  
AGND  
AGND  
AGND  
AGND  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
C
C
AGND  
AGND  
AGND AGND AGND  
AGND  
AGND AGND AGND  
3.3 V  
3.3 V  
C
3.3 V  
C
3.3 V  
C
C
C
C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
1.5 kΩ  
1.5 kΩ  
V
V
CCA  
IVIRES  
QVIRES  
GAPOUT  
GAPD  
1
2
3
4
5
6
7
8
9
3.3 V  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
i.c.  
C
CCA  
3.3 V  
C
AGND  
CLK  
C
AGND  
AGND  
DGND  
DGND  
DGND  
DGND  
DGND  
CLKN  
AGND  
i.c.  
AGND  
DGND  
DGND  
3.3 V  
DGND  
3.3 V  
C
V
CCD  
V
CCD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
DAC1403D160  
I13  
I12  
DGND  
DGND  
Q0  
C
DGND  
I11  
I10  
Q1  
I9  
Q2  
I8  
Q3  
DGND  
DEC  
I7  
DGND  
DEC  
Q4  
DGND  
DGND  
C
C
I6  
Q5  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
C
C
014aaa518  
DGND  
DGND  
DGND  
All resistors are 1 % precision resistors.  
C = 100 nF.  
Fig 10. Application diagram  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
13 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
11.1 Alternative parts  
The following alternative parts are also available:  
Table 8.  
Alternative parts  
Type number  
Description  
Sampling frequency  
[1]  
[1]  
DAC1203D160  
Dual 12 bits DAC,  
with 2 × interpolating  
160 MHz  
DAC1003D160  
Dual 10 bits DAC,  
160 MHz  
with 2 × interpolating  
[1] Pin to pin compatible  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
14 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
12. Package outline  
HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad  
SOT841-1  
c
y
exposed die pad  
X
D
h
A
60  
41  
Z
61  
40  
E
e
(A )  
3
A
A
2
E
E
H
E
h
M
w
θ
b
p
A
1
L
p
L
detail X  
pin 1 index  
80  
21  
1
20  
M
v
v
A
M
w
Z
D
b
p
e
D
B
M
H
D
B
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
1
A
2
A
3
b
c
D
D
E
E
e
H
D
H
E
L
L
v
w
y
Z
Z
θ
p
h
h
p
D
E
max  
°
°
0.15 1.05  
0.05 0.95  
0.27 0.20 12.1 6.05 12.1 6.05  
0.17 0.09 11.9 5.95 11.9 5.95  
14.15 14.15  
13.85 13.85  
0.75  
0.45  
1.45 1.45  
1.05 1.05  
7
0
mm  
1.2  
0.25  
0.5  
1
0.2 0.08 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
SOT841-1  
04-01-15  
MS-026  
Fig 11. Package outline SOT841-1 (HTQFP80)  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
15 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
13. Abbreviations  
Table 9.  
Abbreviations  
Description  
BandWidth  
Acronym  
BW  
FIR  
Finite Impulse Response  
Intermediate Frequency  
Least Significant Bit  
IF  
LSB  
MSB  
PLL  
Most Significant Bit  
Phase-Locked Loop  
PMOS  
Positive-Metal Oxide Semiconductor  
14. Glossary  
14.1 Static parameters  
DNL — Differential Non-Linearity. The difference between the ideal and the measured  
output value between successive DAC codes.  
INL — Integral Non-Linearity. The deviation of the transfer function from a best-fit straight  
line (linear regression computation).  
14.2 Dynamic parameters  
IMD2 — Second-order intermodulation distortion. From a dual-tone digital input sine wave  
(these two frequencies are close together), the intermodulation distortion product IMD2 is  
the ratio of the RMS value of either tone and the RMS value of the worst 2nd-order  
intermodulation product.  
IMD3 — Third-order intermodulation distortion. From a dual-tone digital input sine wave  
(these two frequencies are close together), the intermodulation distortion product IMD3 is  
the ratio of the RMS value of either tone and the RMS value of the worst 3rd-order  
intermodulation product.  
S/N — Signal-to-Noise ratio. The ratio of the RMS value of the reconstructed output sine  
wave to the RMS value of the noise excluding the harmonics and the DC component.  
THD — Total Harmonic Distortion. The ratio of the RMS value of the harmonics of the  
output frequency to the RMS value of the output sine wave. Usually, the calculation of  
THD is done on the first 5 harmonics.  
SFDR — Spurious-Free Dynamic Range. The ratio of the RMS value of the reconstructed  
output sine wave and the RMS value of the largest spurious (harmonic and non-harmonic,  
excluding DC component) observed in the frequency domain.  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
16 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
15. Revision history  
Table 10. Revision history  
Document ID  
DAC1403D160_2  
Modifications:  
Release date  
20080814  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
DAC1403D160_1  
Corrections made to row Q0 in Table 2.  
Added condition & correction of value to ts in Table 5.  
Additional definition in Section 14.  
DAC1403D160_1  
20080616  
Product data sheet  
-
-
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
17 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
16. Legal information  
16.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
16.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
16.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
16.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
17. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
DAC1403D160_2  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 02 — 14 August 2008  
18 of 19  
DAC1403D160  
NXP Semiconductors  
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating  
18. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
Functional description . . . . . . . . . . . . . . . . . . . 6  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 7  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Application information. . . . . . . . . . . . . . . . . . 12  
Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16  
8
9
10  
11  
11.1  
12  
13  
14  
14.1  
14.2  
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Static parameters . . . . . . . . . . . . . . . . . . . . . . 16  
Dynamic parameters. . . . . . . . . . . . . . . . . . . . 16  
15  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17  
16  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
16.1  
16.2  
16.3  
16.4  
17  
18  
Contact information. . . . . . . . . . . . . . . . . . . . . 18  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2008.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 14 August 2008  
Document identifier: DAC1403D160_2  

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