DSP56309PV100_技术文档

Order Number: DSP56309/D

Rev. 1.0, 8/2001

MOTOROLA

Semiconductor Products Sector Technical Data

DSP56309

Advance Information

24-BIT GENERAL PURPOSE DIGITAL SIGNAL PROCESSOR

The DSP56309 is a member of the DSP56300 core family of programmable CMOS digital signal processors

(DSPs). This family uses a high performance, single-clock-cycle-per-instruction engine providing a two-fold

performance increase over Motorola’s popular DSP56000 core, while retaining code compatibility. Significant

architectural enhancements in the DSP56300 family include a barrel shifter, 24-bit addressing, an instruction

cache, and direct memory access (DMA). The DSP56309 offers 100 MIPS at 3.0–3.6 V using an internal 100

MHz clock. The large on-chip memory is ideal for wireless infrastructure and wireless local-loop applications.

The DSP56300 core family offers a new level of performance in speed and power provided by its rich

instruction set and low-power dissipation, thus enabling a new generation of wireless, multimedia, and

telecommunications products.

16

6

3

Program RAM

20480 × 24 bit

or

19456 × 24 bit

and 1024 × 24 bit

Instruction

Host

Interface

(HI08)

ESSI

Triple

Timer

SCI

X Data

RAM

Y Data

RAM

7168 × 24 bit 7168 × 24 bit

Cache

Memory

Expansion

Area

Peripheral

Expansion Area

YAB

18

Address

Generation

Unit

External

Address

Bus

XAB

PAB

DAB

Address

Switch

Six Channel

DMA Unit

External

Bus

24-Bit

DSP56300

Core

13

Boot-strap

ROM

Interface

&

Control

I - Cache

Control

DDB

YDB

XDB

PDB

GDB

External

Data Bus

Switch

24

Internal

Data

Bus

Data

Switch

Power

Management

EXTAL

XTAL

Clock

Generator

Data ALU

5

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

+

→

24 × 24 56

56-bit MAC

JTAG

Two 56-bit Accumulators

56-bit Barrel Shifter

PLL

OnCE™

DE

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

2

RESET

PINIT/NMI

Figure 1 DSP56309 Block Diagram

This document contains information on a new product. Specifications and information

herein are subject to change without notice.

TM

CONTENTS

SECTION 1

SECTION 2

SECTION 3

SECTION 4

APPENDIX A

SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . 1-1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . . . . A-1

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when

low.)

“asserted”

“deasserted”

Examples:

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Voltage¹

V_IL/V_OL

V_IH/V_OH

V_IL/V_OL

Signal/Symbol

Logic State

Signal State

True

False

True

Asserted

Deasserted

Asserted

False

Deasserted

Note:

Values for V_IL, V_OL, V_IH, and V_OHare defined by individual product specifications.

DSP56309 Technical Data

ii

FEATURES

High Performance DSP56309 Core

•

100-million instructions per second (MIPS) with a 100 MHz clock at 3.0–3.6 V

Object-code compatible with the DSP56000 core

Highly parallel instruction set

Data arithmetic logic unit (ALU)

— Fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC)

— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

— Conditional ALU instructions

— 24-bit or 16-bit arithmetic support under software control

Program control unit (PCU)

•

— Position independent code (PIC) support

— Addressing modes optimized for DSP applications (including immediate offsets)

— On-chip instruction cache controller

— On-chip memory-expandable hardware stack

— Nested hardware DO loops

— Fast auto-return interrupts

•

Direct memory access (DMA)

— Six DMA channels supporting internal and external accesses

— One-, two-, and three-dimensional transfers (including circular buffering)

— End-of-block-transfer interrupts

— Triggering from interrupt lines, all peripherals, and DMA channels

Phase-locked loop (PLL)

•

— Allows change of low-power divide factor (DF) without loss of lock

— Output clock with skew elimination

Hardware debugging support

— On-Chip Emulation (OnCE ) module

— Joint Test Action Group (JTAG) test access port (TAP)

— Address trace mode reflects internal program RAM accesses at the external port

DSP56309 Technical Data

iii

On-Chip Memory

•

Program RAM, Instruction Cache, X data RAM, and Y data RAM size are programmable.

Instruction

Cache

Switch

Mode

Program RAM

Size

Instruction

Cache Size

X Data RAM

Size

Y Data RAM

Size

disabled

enabled

disabled

enabled

disabled

enabled

20480 × 24 bits

19456 × 24 bits

24576 × 24 bits

23552 × 24 bits

0

7168 × 24 bits

5120 × 24 bits

7168 × 24 bits

5120 × 24 bits

1024 × 24 bits

0

1024 × 24 bits

•

192 x 24-bit bootstrap ROM

Off-Chip Memory Expansion

•

External memory expansion port

Data memory expansion to two 256 K × 24-bit word memory spaces (or up to two 4 M × 24-bit

word memory spaces by using the address attribute AA0–AA3 signals)

•

Program memory expansion to one 256 K × 24-bit words memory space (or up to one 4 M × 24-bit

word memory space by using the address attribute AA0–AA3 signals)

•

Simultaneous glueless interface to four blocks of either SRAM or DRAM through chip select logic

Supports interleaved, non-interfering access to both types of memory without losing in-page

DRAM access, including DMA-driven access

On-Chip Peripherals

•

Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (e.g.,

industry standard architecture) and provides glueless connection to a number of industry standard

microcomputers, microprocessors, and DSPs

•

Two enhanced synchronous serial interfaces (ESSI0 and ESSI1), each with one receiver and three

transmitters (allows six-channel home theater)

•

Serial communications interface (SCI) with baud rate generator

Triple timer module

Up to 34 programmable general purpose input/output (GPIO) pins, depending on which

peripherals are enabled

DSP56309 Technical Data

iv

Reduced Power Dissipation

•

Very low-power CMOS design

Fully-static logic, operation frequency down to 0 Hz (dc)

Wait and stop low-power standby modes

Optimized, cycle-by-cycle power management circuitry (instruction-dependent,

peripheral-dependent, and mode-dependent)

TARGET APPLICATIONS

The DSP56309 is intended for applications benefiting from a large amount of on-chip memory, such as

wireless infrastructure applications.

PRODUCT DOCUMENTATION

The three documents listed in the following table are required for a complete description of the DSP56309

and are necessary to design properly with the part. Chip errata—if any exist—are available at the Motorola

website. Documentation is available from the following locations:

•

A local Motorola distributor

A Motorola semiconductor sales office

A Motorola Literature Distribution Center

The World Wide Web (WWW)

See the back cover for specific addresses and phone numbers.

See your Motorola distributor for detailed information about the multiple support options available to you.

Table 2. DSP56309 Documentation

Name

Description

Order Number

DSP56300 Family

Manual

Detailed description of the DSP56300 family processor core and

instruction set

DSP56300FM/AD

DSP56309 User’s

Manual

Detailed functional description of the DSP56309 memory configura- DSP56309UM/D

tion, operation, and register programming

DSP56309 Techni-

cal Data

DSP56309 features list and physical, electrical, timing, and pack-

age specifications

DSP56309/D

DSP56309 Technical Data

v

DSP56309 Technical Data

vi

SECTION 1

Signal/Connection Descriptions

SIGNAL GROUPINGS

The DSP56309 input and output signals are organized into functional groups, as shown in Table 1-1 and

illustrated in Figure 1-1.

The DSP56309 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice

for this feature is added to the signal descriptions of those inputs.

Table 1-1. DSP56309 Functional Signal Groupings

Number of

Signals

Detailed

Description

Functional Group

Power (V_CC

)

18

Table 1-3

Table 1-4

Ground (GND)

19 in TQFP

66 in MAP-BGA

Clock

2

Table 1-5

Table 1-6

Table 1-7

Table 1-8

Table 1-9

Table 1-10

Table 1-12

PLL

3

Address Bus

Data Bus

18

24

13

5

Port A¹

Bus Control

Interrupt and Mode Control

Host Interface (HI08)

Port B²

16

12

Enhanced Synchronous Serial Interface (ESSI)

Ports C and D³

Table 1-13 and

Table 1-14

Serial Communication Interface (SCI)

Port E⁴

3

6

Table 1-15

Table 1-16

Table 1-17

Timer

JTAG/OnCE Port

Note: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and

control signals.

2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.

3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

DSP56309 Technical Data

1-1

DSP56309

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

Interrupt/

Mode

Control

Power Inputs:

V

PLL

CCP

4

2

Internal Logic

Address Bus

Data Bus

CCQ

V

CCA

CCD

CCC

CCH

V

Non-Multiplexed Multiplexed

Bus

H[0–7]

HA0

HA1

HA2

HCS/HCS

Single DS

HRW

HDS/HDS

Single HR

HREQ/HREQ

HACK/HACK

Port B

GPIO

PB[0–7]

PB8

PB9

PB10

PB13

Bus Control

HI08

Bus

8

HAD[0–7]

HAS/HAS

HA8

HA9

HA10

Double DS

HRD/HRD

HWR/HWR

Double HR

2

V

ESSI/SCI/Timer

CCS

Host

Interface

Grounds:

PLL

1

(HI08) Port

GND

P

P1

4

PB11

PB12

GND

Internal Logic

Address Bus

Data Bus

Bus Control

HI08

Q

4

2

GND

A

D

C

H

GND

HTRQ/HTRQ PB14

HRRQ/HRRQ PB15

2

GND

ESSI/SCI/Timer

S

Port C GPIO

PC[0–2]

PC3

PC4

PC5

3

Enhanced

SC0[0–2]

SCK0

SRD0

Synchronous Serial

0

Interface Port

EXTAL

XTAL

2

Clock

PLL

(ESSI0)

STD0

Port D GPIO

PD[0–2]

PD3

PD4

PD5

CLKOUT

PCAP

PINIT/NMI

3

Enhanced

Synchronous Serial

Interface Port 1

SC1[0–2]

SCK1

SRD1

2

(ESSI1)

STD1

Port A

18

External

Address Bus

Port E GPIO

PE0

PE1

A[0–17]

D[0–23]

Serial

RXD

TXD

SCLK

Communications

24

4

2

External

Data Bus

Interface (SCI) Port

PE2

AA[0–3]/RAS[0–3]

Timer GPIO

TIO0

TIO1

External

Bus

Control

RD

WR

TA

TIO0

TIO1

TIO2

3

Timers

TIO2

BR

BG

BB

CAS

BCLK

TCK

TDI

TDO

TMS

TRST

DE

JTAG/OnCE

Port

Note:

1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or

double Host Request (HR) configurations. Since each of these modes is configured independently, any combination

of these modes is possible. These HI08 signals can also be configured as GPIO signals (PB[0–15]). Signals with

dual designations (for example, HAS/HAS) have configurable polarity.

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals

(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.

3. TIO[0–2] can be configured as GPIO signals.

Figure 1-1. Signals Identified by Functional Group

1-2

DSP56309 Technical Data

In the DSP56309, certain pins have weak keeper circuits. For these pins, a tri-stated signal is not

disconnected electrically during reset; rather, an output is driven by the weak keeper. Consequently, the

value of pull-up or pull-down resistors on such pins should be taken into account for those signals. Refer to

Electrical Design Considerations on page 4-2 for recommended resistor values. Table 1-2 lists the pins

that have weak keeper circuits.

Table 1-2. Pins with Weak Keeper Circuits

Block

Pins

Port A Data Bus

D[0–23]

Host Interface (HI08)

PB[0–15]

Enhanced Synchronous Serial Interface (ESSI)

Synchronous Communication Interface (SCI)

Timers

PC[0–5] and PD[0–5]

PE[0–2]

TIO[0–2]

Note: The keeper circuits remain connected even if the pins are configured for peripheral signals instead of GPIO

signals.

POWER

Table 1-3. Power Inputs

Name

Description

V_CCP

PLL Power

V_CCdedicated for use with Phase Lock Loop (PLL). The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the V_CCpower rail.

V_CCQ

V_CCA

V_CCD

V_CCC

V_CCH

V_CCS

Note:

Quiet Power

An isolated power for the internal processing logic. This input must be tied externally to all other chip power

inputs. The user must provide adequate external decoupling capacitors.

Address Bus Power

An isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other

chip power inputs. The user must provide adequate external decoupling capacitors.

Data Bus Power

An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip

power inputs. The user must provide adequate external decoupling capacitors.

Bus Control Power

An isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power

inputs. The user must provide adequate external decoupling capacitors.

Host Power

An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs.

The user must provide adequate external decoupling capacitors.

ESSI, SCI, and Timer Power

An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip

power inputs. The user must provide adequate external decoupling capacitors.

These designations are package-dependent. Some packages connect all V_CCinputs except V_CCPto each other

internally. On those packages, all power input except V_CCPare labeled V_CC. The total number of V_CC

connections is package-dependent.

DSP56309 Technical Data

1-3

GROUND

Table 1-4. Grounds

Description

Ground Name

GND_P

PLL Ground

Ground dedicated for PLL use. The connection should be provided with an extremely

low-impedance path to ground. V_CCPshould be bypassed to GND_Pby a 0.47 µF capacitor

located as close as possible to the chip package.

GND_P1

GND_Q

GND_A

PLL Ground 1

Ground dedicated for PLL use. The connection should be provided with an extremely

low-impedance path to ground.

Quiet Ground

An isolated ground for the internal processing logic. This connection must be tied externally to all

other chip ground connections. The user must provide adequate external decoupling capacitors.

Address Bus Ground

An isolated ground for sections of the address bus I/O drivers. This connection must be tied

externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors.

GND_D

Data Bus Ground

An isolated ground for sections of the data bus

I/O drivers. This connection must be tied externally to all other chip ground connections. The

user must provide adequate external decoupling capacitors.

GND_C

GND_H

GND_S

Bus Control Ground

An isolated ground for the bus control I/O drivers. This connection must be tied externally to all

other chip ground connections. The user must provide adequate external decoupling capacitors.

Host Ground

An isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other

chip ground connections. The user must provide adequate external decoupling capacitors.

ESSI, SCI, and Timer Ground

An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied

externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors.

Note:

These designations are package-dependent. The MAP-BGA package connects all GND inputs except GND_P

and GND_P1to each other internally. On the MAP-BGA package, all ground connections except GND_Pand

GND_P1are labeled GND. The total number of GND connections is package-dependent.

1-4

DSP56309 Technical Data

CLOCK

Table 1-5. Clock Signals

Signal

Name

State During

Reset

Type

Signal Description

EXTAL

Input

External Clock/Crystal Input

Interfaces the internal crystal oscillator input to an external crystal or an

external clock.

XTAL

Output

Chip-driven

Crystal Output

Connects the internal crystal oscillator output to an external crystal. If an

external clock is used, leave XTAL unconnected.

PHASE LOCK LOOP (PLL)

Table 1-6. Phase Lock Loop Signals

State During

Signal Name

Type

Signal Description

Reset

CLKOUT

Output

Chip-driven

Clock Output

Provides an output clock synchronized to the internal core clock

phase.

If the PLL is enabled and both the multiplication and division factors

equal one, then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the frequency

of EXTAL.

PCAP

Input

PLL Capacitor

Connects an off-chip capacitor to the PLL filter. Connect one

capacitor terminal to PCAP and the other terminal to V_CCP

.

If the PLL is not used, PCAP can be tied to V_CC, GND, or left

floating.

PINIT/NMI

PLL Initial/Non-Maskable Interrupt

During assertion of RESET, the value of PINIT/NMI is written into

the PLL Enable (PEN) bit of the PLL control register, determining

whether the PLL is enabled or disabled. After RESET deassertion

and during normal instruction processing, the PINIT/NMI

Schmitt-trigger input is a negative-edge-triggered Non-Maskable

Interrupt (NMI) request internally synchronized to CLKOUT.

PINIT/NMI can tolerate 5 V.

DSP56309 Technical Data

1-5

EXTERNAL MEMORY EXPANSION PORT (PORT A)

Note:

When the DSP56309 enters a low-power standby mode (Stop or Wait), it releases bus mastership

and tri-states the relevant Port A signals: A[0–17], D[0–23], AA[0–3]//RAS[0–3], RD, WR, BB,

CAS, BCLK, BCLK.

EXTERNAL ADDRESS BUS

Table 1-7. External Address Bus Signals

State During

Reset, Stop, or

Wait

Signal Name

Type

Signal Description

A[0–17]

Output

Tri-stated

Address Bus

When the DSP is the bus master, A[0–17] specify the address

for external program and data memory accesses. Otherwise,

the signals are tri-stated. To minimize power dissipation,

A[0–17] do not change state when external memory spaces are

not being accessed.

EXTERNAL DATA BUS

Table 1-8. External Data Bus Signals

State During

Reset, Stop, or

Wait

Signal Name

Type

Signal Description

D[0–23]

Input/Output

Driven by

Data Bus

keeper circuit

When the DSP is the bus master, D[0–23] provide the

bidirectional data bus for external program and data memory

accesses. When used as outputs, these signals have a weak

keeper circuit that maintains the last state externally even if all

drivers are tri-stated.

EXTERNAL BUS CONTROL

Table 1-9. External Bus Control Signals

State During

Reset, Stop, or

Wait

Signal

Name

Type

Signal Description

AA[0–3]/

Output

Tri-stated

Address Attribute or Row Address Strobe

RAS[0–3]

As AA, these signals function as chip selects or additional address

lines. Unlike address lines, however, the AA lines do not hold their

state after a read or write operation. As RAS, these signals can be

used for Dynamic Random Access Memory (DRAM) interface. These

signals have programmable polarity.

1-6

DSP56309 Technical Data

Table 1-9. External Bus Control Signals (Continued)

State During

Reset, Stop, or

Wait

Signal

Name

Type

Signal Description

RD

Output

Tri-stated

Read Enable

When the DSP is the bus master, RD is asserted to read external

memory on the data bus (D[0–23]). Otherwise, RD is tri-stated.

WR

TA

Output

Input

Tri-stated

Write Enable

When the DSP is the bus master, WR is asserted to write external

memory on the data bus (D[0–23]). Otherwise, WR is tri-stated.

Ignored Input

Transfer Acknowledge

If the DSP56309 is the bus master and there is no external bus activity,

or the DSP56309 is not the bus master, the TA input is ignored. The TA

input is a Data Transfer Acknowledge (DTACK) function that can

extend an external bus cycle indefinitely. Any number of wait states (1,

2,..., infinity) can be added to the wait states inserted by the BCR by

keeping TA deasserted. In typical operation, TA is deasserted at the

start of a bus cycle, asserted to enable completion of the bus cycle,

and deasserted before the next bus cycle. The current bus cycle

completes one clock period after TA is asserted synchronous to

CLKOUT. The number of wait states is determined by the TA input or

by the Bus Control Register (BCR), whichever is longer. The BCR can

set the minimum number of wait states in external bus cycles.

To use the TA functionality, the BCR must be programmed to at least

one wait state. A zero wait state access cannot be extended by TA

deassertion; otherwise improper operation may result. TA can operate

synchronously or asynchronously, depending on the setting of the TAS

bit in the Operating Mode Register (OMR).

TA functionality cannot be used during DRAM-type accesses;

otherwise improper operation may result.

BR

Output

Bus Request

(deasserted)

Asserted when the DSP requests bus mastership and deasserted

when the DSP no longer needs the bus. BR can be asserted or

deasserted independently of whether the DSP56309 is a bus master

or a bus slave. Bus “parking” allows BR to be deasserted even though

the DSP56309 is the bus master (see the description of bus “parking”

in the BB signal description). The Bus Request Hole (BRH) bit in the

BCR allows BR to be asserted under software control, even though the

DSP does not need the bus. BR is typically sent to an external bus

arbitrator that controls the priority, parking and tenure of each master

on the same external bus. BR is affected only by DSP requests for the

external bus, never for the internal bus. During hardware reset, BR is

deasserted and the arbitration is reset to the bus slave state.

DSP56309 Technical Data

1-7

Table 1-9. External Bus Control Signals (Continued)

State During

Reset, Stop, or

Wait

Signal

Name

Type

Signal Description

BG

Input

Ignored Input

Bus Grant

Must be asserted/deasserted synchronous to CLKOUT for proper

operation. An external bus arbitration circuit asserts BG when the

DSP56309 becomes the next bus master. When BG is asserted, the

DSP56309 must wait until BB is deasserted before taking bus

mastership. When BG is deasserted, bus mastership is typically given

up at the end of the current bus cycle. This may occur in the middle of

an instruction that requires more than one external bus cycle for

execution.

BB

Input/

Input

Bus Busy

Output

Indicates that the bus is active and must be asserted and deasserted

synchronous to CLKOUT. Only after BB is deasserted can the pending

bus master become the bus master (and then assert the signal again).

The bus master can keep BB asserted after ceasing bus activity,

regardless of whether BR is asserted or deasserted. This is called

“bus parking” and allows the current bus master to reuse the bus

without re-arbitration until another device requires the bus. BB is

deasserted by an “active pull-up” method (that is, BB is driven high

and then released and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

CAS

Output

Tri-stated

Column Address Strobe

When the DSP is the bus master, DRAM uses CAS to strobe the

column address. Otherwise, if the Bus Mastership Enable (BME) bit in

the DRAM Control Register is cleared, the signal is tri-stated.

BCLK

Bus Clock

When the DSP is the bus master, BCLK is active when the OMR[ATE]

is set. When BCLK is active and synchronized to CLKOUT by the

internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.

Bus Clock Not

When the DSP is the bus master, BCLK is the inverse of the BCLK

signal. Otherwise, the signal is tri-stated.

1-8

DSP56309 Technical Data

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 1-10. Interrupt and Mode Control

State During

Signal Name

Type

Signal Description

Reset

MODA/IRQA

Input

Mode Select A/External Interrupt Request A

Selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable

interrupt request input during normal instruction processing.

MODA/IRQA MODA, MODB, MODC, and MODD select one of

sixteen initial chip operating modes, latched into the OMR when the

RESET signal is deasserted.

Internally synchronized to CLKOUT. If IRQA is asserted

synchronous to CLKOUT, multiple processors can be

re-synchronized using the WAIT instruction and asserting IRQA to

exit the Wait state. If the processor is in the Stop standby state and

IRQA is asserted, the processor will exit the Stop state.

MODA/IRQA can tolerate 5 V.

MODB/IRQB

Input

Mode Select B/External Interrupt Request B

Selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable

interrupt request input during normal instruction processing. MODA,

MODB, MODC, and MODD select one of sixteen initial chip

operating modes, latched into OMR when the RESET signal is

deasserted.

Internally synchronized to CLKOUT. If IRQB is asserted

synchronous to CLKOUT, multiple processors can be

re-synchronized using the WAIT instruction and asserting IRQB to

exit the Wait state.

MODB/IRQB can tolerate 5 V.

MODC/IRQC

Input

Mode Select C/External Interrupt Request C

Selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable

interrupt request input during normal instruction processing. MODA,

MODB, MODC, and MODD select one of sixteen initial chip

operating modes, latched into OMR when the RESET signal is

deasserted.

Internally synchronized to CLKOUT. If IRQC is asserted

synchronous to CLKOUT, multiple processors can be

re-synchronized using the WAIT instruction and asserting IRQC to

exit the Wait state.

MODC/IRQC can tolerate 5 V.

DSP56309 Technical Data

1-9

Table 1-10. Interrupt and Mode Control (Continued)

State During

Signal Name

Type

Signal Description

Reset

MODD/IRQD

Input

Mode Select D/External Interrupt Request D

Selects the initial chip operating mode during hardware reset and

becomes a level-sensitive or negative-edge-triggered, maskable

interrupt request input during normal instruction processing. MODA,

MODB, MODC, and MODD select one of sixteen initial chip

operating modes, latched into OMR when the RESET signal is

deasserted.

Internally synchronized to CLKOUT. If IRQD is asserted

synchronous to CLKOUT, multiple processors can be

re-synchronized using the WAIT instruction and asserting IRQD to

exit the Wait state.

MODD/IRQD can tolerate 5 V.

RESET

Input

Reset

Deassertion of RESET is internally synchronized to the clock out

(CLKOUT). When asserted, the chip is placed in the Reset state and

the internal phase generator is reset. The Schmitt-trigger input

allows a slowly rising input (such as a capacitor charging) to reset

the chip reliably. If RESET is deasserted synchronous to CLKOUT,

exact start-up timing is guaranteed, allowing multiple processors to

start and operate synchronously. When the RESET signal is

deasserted, the initial chip operating mode is latched from the

MODA, MODB, MODC, and MODD inputs. The RESET signal must

be asserted after power-up.

RESET can tolerate 5 V.

HOST INTERFACE (HI08)

The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus. The HI08

supports a variety of standard buses and can directly connect to a number of industry-standard

microcomputers, microprocessors, DSPs, and DMA hardware.

Host Port Usage Considerations

Careful synchronization is required when the system reads multiple-bit registers that are written by another

asynchronous system. This is a common problem when two asynchronous systems are connected (as they

are in the Host port). The considerations for proper operation are discussed in Table 1-11.

1-10

DSP56309 Technical Data

Table 1-11. Host Port Usage Considerations

Action

Description

Asynchronous read of receive

byte registers

When reading the receive byte registers, Receive register High (RXH), Receive

register Middle (RXM), or Receive register Low (RXL), the host interface programmer

should use interrupts or poll the Receive register Data Full (RXDF) flag that indicates

data is available. This assures that the data in the receive byte registers is valid.

Asynchronous write to transmit

byte registers

The host interface programmer should not write to the transmit byte registers, Transmit

register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL),

unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit

byte registers are empty. This guarantees that the transmit byte registers transfer valid

data to the Host Receive (HRX) register.

Asynchronous write to host vector The host interface programmer must change the Host Vector (HV) register only when

the Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt

control logic receives a stable vector.

Host Port Configuration

HI08 signal functions vary according to the programmed configuration of the interface as determined by

the 16 bits in the HI08 Port Control Register (HPCR). Refer to the DSP56309 User’s Manual for detailed

descriptions of HI08 configuration registers.

Table 1-12. Host Interface

State During

Signal Name

Type

Signal Description

Reset or Stop¹

H[0–7]

Input/Output²

Disconnected Host Data

internally

When the HI08 is programmed to interface with a non-multiplexed

host bus and the HI function is selected, these signals are lines 0–7

of the Data bus.

HAD[0–7]

PB[0–7]

Input/Output²

Host Address

When the HI08 is programmed to interface with a multiplexed host

bus and the HI function is selected, these signals are lines 0–7 of

the Address/Data bus.

Input or

Output²

Port B 0–7

When the HI08 is configured as GPIO through the HPCR, these

signals are individually programmed through the HI08 Data

Direction Register (HDDR).

This input is 5 V tolerant.

DSP56309 Technical Data

1-11

Table 1-12. Host Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset or Stop¹

HA0

Input

Disconnected Host Address Input 0

internally

When the HI08 is programmed to interface with a non-multiplexed

host bus and the HI function is selected, this signal is line 0 of the

Host Address bus.

HAS/HAS

Input

Host Address Strobe

When the HI08 is programmed to interface with a multiplexed host

bus and the HI function is selected, this signal is the Host Address

Strobe (HAS) Schmitt-trigger input. The polarity of the address

strobe is programmable, but is configured active-low (HAS) following

reset.

PB8

Input or

Output²

Port B 8

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

HA1

HA8

PB9

Input

Disconnected Host Address Input 1

internally When the HI08 is programmed to interface with a non-multiplexed

host bus and the HI function is selected, this signal is line 1 of the

Host Address bus.

Host Address 8

When the HI08 is programmed to interface with a multiplexed host

bus and the HI function is selected, this signal is line 8 of the Host

Address bus.

Input or

Output²

Port B 9

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

HA2

HA9

PB10

Input

Disconnected Host Address Input 2

internally When the HI08 is programmed to interface with a non-multiplexed

host bus and the HI function is selected, this signal is line 2 of the

Host Address bus.

Host Address 9

When the HI08 is programmed to interface with a multiplexed host

bus and the HI function is selected, this signal is line 9 of the Host

Address bus.

Input or

Output²

Port B 10

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

1-12

DSP56309 Technical Data

Table 1-12. Host Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset or Stop¹

HCS/HCS

Input

Disconnected Host Chip Select

internally

When the HI08 is programmed to interface with a non-multiplexed

host bus and the HI function is selected, this signal is the Host Chip

Select (HCS) input. The polarity of the chip select is programmable,

but is configured active-low (HCS) after reset.

HA10

PB13

Input

Host Address 10

When the HI08 is programmed to interface with a multiplexed host

bus and the HI function is selected, this signal is line 10 of the Host

Address bus.

Input or

Output²

Port B 13

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

HRW

Input

Disconnected Host Read/Write

internally When the HI08 is programmed to interface with a single-data-strobe

host bus and the HI function is selected, this signal is the Host

Read/Write input.

HRD/HRD

Host Read Data

When the HI08 is programmed to interface with a

double-data-strobe host bus and the HI function is selected, this

signal is the Host Read Data strobe (HRD) Schmitt-trigger input.

The polarity of the data strobe is programmable, but is configured as

active-low (HRD) after reset.

PB11

Input or

Output²

Port B 11

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

DSP56309 Technical Data

1-13

Table 1-12. Host Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset or Stop¹

HDS/HDS

Input

Disconnected Host Data Strobe

internally

When the HI08 is programmed to interface with a single-data-strobe

host bus and the HI function is selected, this signal is the Host Data

Strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is

programmable, but is configured as active-low (HDS) following

reset.

HWR/HWR

Input

Host Write Data

When the HI08 is programmed to interface with a

double-data-strobe host bus and the HI function is selected, this

signal is the Host Write Data Strobe (HWR) Schmitt-trigger input.

The polarity of the data strobe is programmable, but is configured as

active-low (HWR) following reset.

PB12

Input or

Output²

Port B 12

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

HREQ/HREQ

Output²

Disconnected Host Request

internally When the HI08 is programmed to interface with a single host

request host bus and the HI function is selected, this signal is the

Host Request (HREQ) output. The polarity of the host request is

programmable, but is configured as active-low (HREQ) following

reset. The host request can be programmed as a driven or

open-drain output.

HTRQ/HTRQ

Output²

Transmit Host Request

When the HI08 is programmed to interface with a double host

request host bus and the HI function is selected, this signal is the

Transmit Host Request (HTRQ) output. The polarity of the host

request is programmable, but is configured as active-low (HTRQ)

following reset. The host request may be programmed as a driven or

open-drain output.

PB14

Input or

Output²

Port B 14

When the HI08 is programmed to interface with a multiplexed host

bus and the signal is configured as GPIO through the HPCR, this

signal is individually programmed through the HDDR.

This input is 5 V tolerant.

1-14

DSP56309 Technical Data

Table 1-12. Host Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset or Stop¹

HACK/HACK

Input

Disconnected Host Acknowledge

internally

When the HI08 is programmed to interface with a single host

request host bus and the HI function is selected, this signal is the

Host Acknowledge (HACK) Schmitt-trigger input. The polarity of the

host acknowledge is programmable, but is configured as active-low

(HACK) after reset.

HRRQ/HRRQ

Output²

Receive Host Request

When the HI08 is programmed to interface with a double host

request host bus and the HI function is selected, this signal is the

Receive Host Request (HRRQ) output. The polarity of the host

request is programmable, but is configured as active-low (HRRQ)

after reset. The host request may be programmed as a driven or

open-drain output.

PB15

Input or

Output²

Port B 15

When the HI08 is configured as GPIO through the HPCR, this signal

is individually programmed through the HDDR.

This input is 5 V tolerant.

Note: 1. The Wait processing state does not affect the signal state.

2. When configured as an output, these signals have a weak keeper circuit that maintains the last state externally

even if all drivers are tri-stated.

DSP56309 Technical Data

1-15

ENHANCED SYNCHRONOUS SERIAL INTERFACE 0 (ESSI0)

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial

communication with a variety of serial devices, including one or more industry-standard CODECs, other

DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI).

Table 1-13. Enhanced Synchronous Serial Interface 0 (ESSI0)

State During¹

Signal

Name

Type

Signal Description

Reset

Stop

SC00

Input or Output²

Input

Disconnected Serial Control 0

internally

Functions in either Synchronous or Asynchronous mode. For

Asynchronous mode, this signal is the receive clock I/O

(Schmitt-trigger input). For Synchronous mode, this signal is

either for Transmitter 1 output or Serial I/O Flag 0.

PC0

Port C 0

The default configuration following reset is GPIO. For PC0,

signal direction is controlled through the Port Directions

Register (PRR0). The signal can be configured as ESSI

signal SC00 through the Port Control Register (PCR0).

This input is 5 V tolerant.

SC01

PC1

Input/Output²

Input

Disconnected Serial Control 1

internally Functions in either Synchronous or Asynchronous mode. For

Asynchronous mode, this signal is the receiver frame sync

I/O. For Synchronous mode, this signal is either Transmitter 2

output or Serial I/O Flag 1.

Input or Output²

Port C 1

The default configuration following reset is GPIO. For PC1,

signal direction is controlled through PRR0. The signal can

be configured as an ESSI signal SC01 through PCR0.

This input is 5 V tolerant.

SC02

Input/Output²

Input

Disconnected Serial Control Signal 2

internally The frame sync for both the transmitter and receiver in

Synchronous mode, and for the transmitter only in

Asynchronous mode. When configured as an output, this

signal is the internally generated frame sync signal. When

configured as an input, this signal receives an external frame

sync signal for the transmitter (and the receiver in

synchronous operation).

PC2

Input or Output²

Port C 2

The default configuration following reset is GPIO. For PC2,

signal direction is controlled through PRR0. The signal can

be configured as an ESSI signal SC02 through PCR0.

This input is 5 V tolerant.

1-16

DSP56309 Technical Data

Table 1-13. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

State During¹

Signal

Name

Type

Signal Description

Reset

Stop

SCK0

Input/Output²

Input

Disconnected Serial Clock

internally

Provides the serial bit rate clock for the ESSI interface for

both the transmitter and receiver in Synchronous modes, or

the transmitter only in Asynchronous modes.

Although an external serial clock can be independent of and

asynchronous to the DSP system clock, it must exceed the

minimum clock cycle time of 6 T (that is, the system clock

frequency must be at least three times the external ESSI

clock frequency). The ESSI needs at least three DSP phases

inside each half of the serial clock.

PC3

Input or Output²

Port C 3

The default configuration following reset is GPIO. For PC3,

signal direction is controlled through PRR0. The signal can

be configured as an ESSI signal SCK0 through PCR0.

This input is 5 V tolerant.

SRD0

PC4

Input/Output²

Input

Disconnected Serial Receive Data

internally Receives serial data and transfers the data to the ESSI

receive shift register. SRD0 is an input when data is being

received.

Input or Output²

Port C 4

The default configuration following reset is GPIO. For PC4,

signal direction is controlled through PRR0. The signal can

be configured as an ESSI signal SRD0 through PCR0.

This input is 5 V tolerant.

STD0

PC5

Input/Output²

Input

Disconnected Serial Transmit Data

internally Transmits data from the serial transmit shift register. STD0 is

an output when data is being transmitted.

Input or Output²

Port C 5

The default configuration following reset is GPIO. For PC5,

signal direction is controlled through PRR0. The signal can

be configured as an ESSI signal STD0 through PCR0.

This input is 5 V tolerant.

Note: 1. The Wait processing state does not affect the signal state.

2. When configured as an output, these signals have a weak keeper circuit that maintains the last state

externally even if all drivers are tri-stated.

DSP56309 Technical Data

1-17

ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 (ESSI1)

Table 1-14. Enhanced Synchronous Serial Interface 1 (ESSI1)

State During¹

Signal

Name

Type

Signal Description

Reset

Stop

SC10

Input or Output²

Input

Disconnected Serial Control 0

internally

Selection of Synchronous or Asynchronous mode

determines function. For Asynchronous mode, this signal is

the receive clock I/O (Schmitt-trigger input). For

Synchronous mode, this signal is either Transmitter 1 output

or Serial I/O Flag 0.

PD0

Port D 0

The default configuration following reset is GPIO. For PD0,

signal direction is controlled through the Port Directions

Register (PRR1). The signal can be configured as an ESSI

signal SC10 through the Port Control Register (PCR1).

This input is 5 V tolerant.

SC11

PD1

Input/Output²

Input

Disconnected Serial Control 1

internally Selection of Synchronous or Asynchronous mode

determines function. For Asynchronous mode, this signal is

the receiver frame sync I/O. For Synchronous mode, this

signal is either Transmitter 2 output or Serial I/O Flag 1.

Input or Output²

Port D 1

The default configuration following reset is GPIO. For PD1,

signal direction is controlled through PRR1. The signal can

be configured as an ESSI signal SC11 through PCR1.

This input is 5 V tolerant.

SC12

Input/Output²

Input

Disconnected Serial Control Signal 2

internally Frame sync for both the transmitter and receiver in

Synchronous mode, for the transmitter only in Asynchronous

mode. When configured as an output, this signal is the

internally generated frame sync signal. When configured as

an input, this signal receives an external frame sync signal

for the transmitter (and the receiver in Synchronous

operation).

PD2

Input or Output²

Port D 2

The default configuration following reset is GPIO. For PD2,

signal direction is controlled through PRR1. The signal can

be configured as an ESSI signal SC12 through PCR1.

This input is 5 V tolerant.

1-18

DSP56309 Technical Data

Table 1-14. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)

State During¹

Signal

Name

Type

Signal Description

Reset

Stop

SCK1

Input/Output²

Input

Disconnected Serial Clock

internally

Provides the serial bit rate clock for the ESSI interface. Clock

input or output can be used by the transmitter and receiver in

Synchronous modes, by the transmitter only in

Asynchronous modes.

Although an external serial clock can be independent of and

asynchronous to the DSP system clock, it must exceed the

minimum clock cycle time of 6T (that is, the system clock

frequency must be at least three times the external ESSI

clock frequency). The ESSI needs at least three DSP phases

inside each half of the serial clock.

PD3

Input or Output²

Port D 3

The default configuration following reset is GPIO. For PD3,

signal direction is controlled through PRR1. The signal can

be configured as an ESSI signal SCK1 through PCR1.

This input is 5 V tolerant.

SRD1

PD4

Input/Output²

Input

Disconnected Serial Receive Data

internally Receives serial data and transfers it to the ESSI receive shift

register. SRD1 is an input when data is being received.

Input or Output²

Port D 4

The default configuration following reset is GPIO. For PD4,

signal direction is controlled through PRR1. The signal can

be configured as an ESSI signal SRD1 through PCR1.

This input is 5 V tolerant.

STD1

PD5

Input/Output²

Input

Disconnected Serial Transmit Data

internally Transmits data from the serial transmit shift register. STD1 is

an output when data is being transmitted.

Input or Output²

Port D 5

The default configuration following reset is GPIO. For PD5,

signal direction is controlled through PRR1. The signal can

be configured as an ESSI signal STD1 through PCR1.

This input is 5 V tolerant.

Note: 1. The Wait processing state does not affect the signal state.

2. When configured as an output, these signals have a weak keeper circuit that maintains the last state

externally even if all drivers are tri-stated.

DSP56309 Technical Data

1-19

SERIAL COMMUNICATION INTERFACE (SCI)

The Serial Communication interface (SCI) provides a full duplex port for serial communication with other

DSPs, microprocessors, or peripherals such as modems.

Table 1-15. Serial Communication Interface (SCI)

State During¹

Signal

Name

Type

Signal Description

Reset

Stop

RXD

Input

Disconnected Serial Receive Data

internally

Receives byte-oriented serial data and transfers it to the SCI

receive shift register.

PE0

Input or Output²

Port E 0

The default configuration following reset is GPIO. When

configured as PE0, signal direction is controlled through the

SCI Port Directions Register (PRR). The signal can be

configured as an SCI signal RXD through the SCI Port

Control Register (PCR).

This input is 5 V tolerant.

TXD

PE1

Output²

Input

Disconnected Serial Transmit Data

internally Transmits data from SCI transmit data register.

Input or Output²

Port E 1

The default configuration following reset is GPIO. When

configured as PE1, signal direction is controlled through the

SCI PRR. The signal can be configured as an SCI signal

TXD through the SCI PCR.

This input is 5 V tolerant.

SCLK

PE2

Input/Output²

Input

Disconnected Serial Clock

internally Provides the input or output clock used by the transmitter

and/or the receiver.

Input or Output²

Port E 2

The default configuration following reset is GPIO. For PE2,

signal direction is controlled through the SCI PRR. The

signal can be configured as an SCI signal SCLK through the

SCI PCR.

This input is 5 V tolerant.

Note: 1. The Wait processing state does not affect the signal state.

2. When configured as an output, these signals have a weak keeper circuit that maintains the last state

externally even if all drivers are tri-stated.

1-20

DSP56309 Technical Data

TIMERS

The DSP56309 has three identical and independent timers. Each can use internal or external clocking,

interrupt the DSP56309 after a specified number of events (clocks), or signal an external device after

counting a specific number of internal events.

Table 1-16. Triple Timer Signals

State During¹

Signal

Name

Type

Signal Description

Reset

Stop

TIO0

Input or Output²

Input

Disconnected Timer 0 Schmitt-Trigger Input/Output

internally As an external event counter or in Measurement mode, TIO0

is input. In Watchdog, Timer, or Pulse Modulation mode, TIO0

is output.

The default mode after reset is GPIO input. This can be

changed to output or configured as a Timer Input/Output

through the Timer 0 Control/Status Register (TCSR0).

This input is 5 V tolerant.

TIO1

Input or Output²

Input

Disconnected Timer 1 Schmitt-Trigger Input/Output

internally As an external event counter or in Measurement mode, TIO1

is input. In Watchdog, Timer, or Pulse Modulation mode, TIO1

is output.

The default mode after reset is GPIO input. This can be

changed to output or configured as a Timer Input/Output

through the Timer 1 Control/Status Register (TCSR1).

This input is 5 V tolerant.

TIO2

Input or Output²

Input

Disconnected Timer 2 Schmitt-Trigger Input/Output

internally As an external event counter or in Measurement mode, TIO2

is input. In Watchdog, Timer, or Pulse Modulation mode, TIO2

is output.

The default mode after reset is GPIO input. This can be

changed to output or configured as a Timer Input/Output

through the Timer 2 Control/Status Register (TCSR2).

This input is 5 V tolerant.

Note: 1. The Wait processing state does not affect the signal state.

2. When configured as an output, these signals have a weak keeper circuit that maintains the last state externally

even if all drivers are tri-stated.

DSP56309 Technical Data

1-21

JTAG/ONCE INTERFACE

Table 1-17. JTAG/OnCE Interface

State During

Reset

Signal Name

Type

Signal Description

TCK

Input

Test Clock

A test clock signal for synchronizing JTAG test logic.

This input is 5 V tolerant.

TDI

Test Data Input

A test data serial signal for test instructions and data. TDI is

sampled on the rising edge of TCK and has an internal

pull-up resistor.

This input is 5 V tolerant.

TDO

Output

Tri-stated

Test Data Output

A test data serial signal for test instructions and data. TDO

can be tri-stated. The signal is actively driven in the shift-IR

and shift-DR controller states and changes on the falling

edge of TCK.

This input is 5 V tolerant.

TMS

Input

Test Mode Select

Sequences the test controller’s state machine, is sampled

on the rising edge of TCK, and has an internal pull-up

resistor.

This input is 5 V tolerant.

TRST

Input

Test Reset

Asynchronously initializes the test controller, has an internal

pull-up resistor, and must be asserted after power up.

This input is 5 V tolerant.

1-22

DSP56309 Technical Data

Table 1-17. JTAG/OnCE Interface (Continued)

State During

Signal Name

Type

Signal Description

Reset

DE

Input/Output

Input

Debug Event

Provides a way to enter Debug mode from an external

command controller (as input) or to acknowledge that the

chip has entered Debug mode (as output). When asserted

as an input, DE causes the DSP56300 core to finish the

current instruction, save the instruction pipeline information,

enter Debug mode, and wait for commands from the debug

serial input line. When a debug request or a breakpoint

condition cause the chip to enter Debug mode DE is

asserted as an output for three clock cycles. DE has an

internal pull-up resistor.

DE is not a standard part of the JTAG Test Access Port

(TAP) Controller. It connects to the OnCE module to initiate

Debug mode directly or to provide a direct external

indication that the chip has entered the Debug mode. All

other interface with the OnCE module must occur through

the JTAG port.

This input is 5 V tolerant.

DSP56309 Technical Data

1-23

1-24

DSP56309 Technical Data

SECTION 2

Specifications

INTRODUCTION

The DSP56309 is fabricated in high density CMOS with transistor-transistor logic (TTL) compatible

inputs and outputs. The DSP56309 specifications are preliminary, based on design simulations, and may

not be fully tested or guaranteed at this early stage of the product life cycle. In particular, certain speeds

may not yet be available at certain power ranges. Finalized specifications will be published after full

characterization and device qualifications are complete.

MAXIMUM RATINGS

CAUTION

This device contains circuitry protecting

against damage due to high static voltage or

electrical fields; however, normal precautions

should be taken to avoid exceeding maximum

voltage ratings. Reliability is enhanced if

unused inputs are tied to an appropriate logic

voltage level (e.g., either GND or V

).

CCx

Note:

In the calculation of timing requirements, adding a maximum value of one specification to a

minimum value of another specification does not yield a reasonable sum. A maximum

specification is calculated using a worst case variation of process parameter values in one

direction. The minimum specification is calculated using the worst case for the same parameters in

the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same

device that has a “minimum” value for another specification; adding a maximum to a minimum

represents a condition that can never exist.

DSP56309 Technical Data

2-1

Table 2-1. Absolute Maximum Ratings¹

Rating

Symbol

Value

Unit

Supply Voltage

V_CC

−0.3 to +4.0

GND − 0.3 to V_CC+ 0.3

GND − 0.3 to 5.5

10

V

All input voltages excluding “5 V tolerant” inputs

All “5 V tolerant” input voltages²

V_IN

V_IN5

I

V

Current drain per pin excluding V_CCand GND

Operating temperature range

mA

°C

T_J

−40 to +100

Storage temperature

T_STG

−55 to +150

Notes: 1. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not

guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to

the device.

2. At power up, ensure that the voltage difference between the 5 V tolerant pins and the chip V_CCnever

exceeds 3.5 V.

THERMAL CHARACTERISTICS

Table 2-2. Thermal Characteristics

TQFP

Value

PBGA³

Value

PBGA⁴

Value

Characteristic

Symbol

Unit

Junction-to-ambient thermal resistance¹

Junction-to-case thermal resistance²

Thermal characterization parameter

R

_θJAor θ_JA

_θJCor θ_JC

Ψ_JT

49.3

8.2

49.4

12.0

2.0

28.5

—

°C/W

R

5.5

—

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed

circuit board per JEDEC Specification JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with

the exception that the cold plate temperature is used for the case temperature.

3. These are simulated values. See note 1 for test board conditions.

4. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid ground

planes internal to the test board.

2-2

DSP56309 Technical Data

DC ELECTRICAL CHARACTERISTICS

Table 2-3. DC Operating Electrical Characteristics⁶

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

V_CC

3.0

3.3

3.6

V

Input high voltage

■

D(0–23), BG, TA

BB

V_IH

V_IHP

2.0

2.3

2.0

—

V_CC

5.25

V

MOD¹/IRQ¹, RESET, PINIT/NMI and all

JTAG/ESSI/SCI/Timer/HI08 pins

EXTAL⁸

■

V_IHX

0.8 × V_CC

—

V_CC

V

Input low voltage

■

D(0–23), BG, BB, TA, MOD¹/IRQ¹, RESET, PINIT

V_IL

V_ILP

V_ILX

–0.3

—

0.8

0.2 × V_CC

V

All JTAG/ESSI/SCI/Timer/HI08 pins

EXTAL⁸

Input leakage current

I_IN

I_TSI

V_OH

–10

—

10

µA

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

Output high voltage

■

TTL (I_OH= –0.4 mA)^5,7

2.4

_CC– 0.01

—

V

CMOS (I_OH= –10 µA)⁵

V

Output low voltage

V_OL

■

TTL (I_OL= 1.6 mA, open-drain pins I_OL= 6.7 mA)^5,7

—

0.4

0.01

V

CMOS (I_OL= 10 µA)⁵

Internal supply current²:

■

In Normal mode

In Wait mode³

In Stop mode⁴

I_CCI

I_CCW

I_CCS

—

160

7.5

100

—

mA

µA

PLL supply current

Input capacitance⁵

—

1

2.5

10

mA

pF

C_IN

—

Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.

2. Power Consumption Considerations on page 4-3 provides a formula to compute the estimated current

requirements in Normal mode. In order to obtain these results, all inputs must be terminated (that is, not

allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A).

The power consumption numbers in this specification are 90 percent of the measured results of this

benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V_CC

3.3 V at T_J= 100°C.

=

3. In order to obtain these results, all inputs must be terminated (that is, not allowed to float).

4. In order to obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that

is, not allowed to float). PLL and XTAL signals are disabled during Stop state.

5. Periodically sampled and not 100 percent tested.

6. V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100 °C, C_L= 50 pF

7. This characteristic does not apply to XTAL and PCAP.

8. Driving EXTAL to the low V_IHXor the high V_ILXvalue may cause additional power consumption (DC

current). To minimize power consumption, the minimum V_IHXshould be no lower than

0.9 × V_CCand the maximum V_ILXshould be no higher than 0.1 × V_CC

.

DSP56309 Technical Data

2-3

AC ELECTRICAL CHARACTERISTICS

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of

IL

0.3 V and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels

IH

shown in Note 6 of Table 2-3. AC timing specifications, which are referenced to device input and output

signals, are measured in production with respect to the 50 percent point of the respective signal transition.

Note:

Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test

conditions are 15 MHz and rated speed.

All specifications for the high impedance state are guaranteed by design.

INTERNAL CLOCKS

Table 2-4. Internal Clocks, CLKOUT

Expression^{1, 2}

Typ

Characteristics

Symbol

Min

Max

Internal operation frequency and CLKOUT with PLL enabled

f

—

(Ef × MF)/

(PDF × DF)

—

Internal operation frequency and CLKOUT with PLL disabled

Internal clock and CLKOUT high period

—

Ef/2

—

■

With PLL disabled

With PLL enabled and MF ≤ 4

T_H

—

ET_C

—

0.49 × ET_C

×

0.51 × ET_C×

PDF × DF/MF

■

With PLL enabled and MF > 4

0.47 × ET_C

×

—

0.53 × ET_C

×

PDF × DF/MF

Internal clock and CLKOUT low period

■

With PLL disabled

With PLL enabled and MF ≤ 4

T_L

—

ET_C

—

0.49 × ET_C

×

0.51 × ET_C

×

PDF × DF/MF

■

With PLL enabled and MF > 4

0.47 × ET_C

×

—

0.53 × ET_C×

PDF × DF/MF

Internal clock and CLKOUT cycle time with PLL enabled

T_C

—

ET_C× PDF ×

—

DF/MF

Internal clock and CLKOUT cycle time with PLL disabled

Instruction cycle time

T_C

—

2 × ET_C

—

I_CYC

T_C

Notes: 1. DF = Division Factor; Ef = External frequency; ET_C= External clock cycle = 1/Ef;

MF = Multiplication Factor; PDF = Predivision Factor; T_C= Internal clock cycle

2. See the PLL and Clock Generator section in the DSP56300 Family Manual for a detailed discussion of the

PLL.

2-4

DSP56309 Technical Data

EXTERNAL CLOCK OPERATION

The DSP56309 system clock can be derived from the on−chip oscillator or it can be externally supplied.

To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL

and XTAL; examples are shown in Figure 2-1.

EXTAL

XTAL

R2

EXTAL

XTAL

R

R1

Note: Make sure that

in the PCTL Register:

■ XTLD (bit 16) = 0

Note: Make sure that

in the PCTL Register:

■ XTLD (bit 16) = 0

C

XTAL1

C

XTAL1

■ If f

≤ 200 kHz,

■ If f

> 200 kHz,

OSC

XTLR (bit 15) = 1

XTLR (bit 15) = 0

Fundamental Frequency

Fork Crystal Oscillator

Fundamental Frequency

Crystal Oscillator

Suggested Component Values:

OSC

f

= 20 MHz

f

= 4 MHz

f

= 32.768 kHz

OSC

R = 680 kΩ ± 10%

C = 56 pF ± 20%

R = 680 kΩ ± 10%

C = 22 pF ± 20%

R1 = 3.9 MΩ ± 10%

C = 22 pF ± 20%

R2 = 200 kΩ ± 10%

Calculations were done for a 4/20 MHz crystal with the

following parameters:

Calculations were done for a 32.768 kHz crystal with the

following parameters:

■ C of 30/20 pF,

L

■ C of 7/6 pF,

■ load capacitance (C ) of 12.5 pF,

0

L

■ series resistance of 100/20 Ω, and

■ drive level of 2 mW.

■ shunt capacitance (C ) of 1.8 pF,

■ series resistance of 40 kΩ, and

■ drive level of 1 µW.

0

Figure 2-1. Crystal Oscillator Circuits

If an externally supplied square wave voltage source is used, disable the internal oscillator circuit during

bootup by setting XTLD (PCTL Register bit 16 = 1—see Section 4.7 in the DSP56309 User’s Manual).

The external square wave source connects to EXTAL; XTAL is not physically connected to the board or

socket. Figure 2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT.

V_IHX

Midpoint

EXTAL

ET_H

ET_L

V_ILX

2

3

Note: The midpoint is 0.5 (V_IHX+ V_ILX).

5

4

ET_C

5

CLKOUT with

PLL disabled

7

CLKOUT with

PLL enabled

6a

6b

Figure 2-2. External Clock Timing

DSP56309 Technical Data

2-5

Table 2-5. Clock Operation

100 MHz

No.

Characteristics

Symbol

Min

Max

1

2

Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock should be 3 ns maximum.

Ef

0

100.0

MHz

EXTAL input high^{1, 2}

■

With PLL disabled (46.7%–53.3% duty cycle⁶)

With PLL enabled (42.5%–57.5% duty cycle⁶)

ET_H

ET_L

ET_C

4.67 ns

4.25 ns 157.0 µs

∞

3

4

EXTAL input low^{1, 2}

■

With PLL disabled (46.7%–53.3% duty cycle⁶)

With PLL enabled (42.5%–57.5% duty cycle⁶)

4.67 ns

4.25 ns 157.0 µs

∞

EXTAL cycle time²

■

With PLL disabled

With PLL enabled

10.00 ns

10.00 ns 273.1 µs

∞

5

6

CLKOUT change from EXTAL fall with PLL disabled

4.3 ns

0.0 ns

11.0 ns

1.8 ns

a. CLKOUT rising edge from EXTAL rising edge with PLL enabled

(MF = 1, 2, or 4; PDF = 1; Ef > 15 MHz)^3,5

b. CLKOUT falling edge from EXTAL falling edge with PLL enabled

0.0 ns

1.8 ns

(MF ≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)^3,5

7

Instruction cycle time = I_CYC= T_C⁴(see Table 2-5) (46.7%–53.3% duty cycle)

■

With PLL disabled

With PLL enabled

I_CYC

20.0 ns

10.00 ns 8.53 µs

∞

Notes: 1. Measured at 50 percent of the input transition

2. The maximum value for PLL enabled is given for minimum V_COand maximum MF.

3. Periodically sampled and not 100 percent tested

4. The maximum value for PLL enabled is given for minimum V_COand maximum DF.

5. The skew is not guaranteed for any other MF value.

6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum

clock high or low time required for correction operation, however, remains the same at lower operating

frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the

specified duty cycle as long as the minimum high time and low time requirements are met.

2-6

DSP56309 Technical Data

PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6. PLL Characteristics

100 MHz

Characteristics

Unit

Min

Max

V_COfrequency when PLL enabled (MF × E_f× 2/PDF)

30

200

MHz

)

PLL external capacitor (PCAP pin to V_CCP) (C_PCAP

■

@ MF ≤ 4

@ MF > 4

(MF × 580) − 100

MF × 830

(MF × 780) − 140

MF × 1470

pF

Note:

C_PCAPis the value of the PLL capacitor (connected between the PCAP pin and V_CCP). The recommended value

in pF for C_PCAPcan be computed from one of the following equations:

(680 × MF) – 120, for MF ≤ 4, or

1100 × MF, for MF > 4.

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

8

9

Delay from RESET assertion to all pins at reset value³

Required RESET duration⁴

—

26.0

ns

Minimum:

50 × ET_C

1000 × ET_C

75000 × ET_C

2.5 × T_C

■

Power on, external clock generator, PLL disabled

500.0

10.0

0.75

25.0

—

ns

µs

ms

ns

■

Power on, external clock generator, PLL enabled

Power on, internal oscillator

During STOP, XTAL disabled (PCTL Bit 16 = 0)

During STOP, XTAL enabled (PCTL Bit 16 = 1)

During normal operation

2.5 × T_C

ns

10 Delay from asynchronous RESET deassertion to first

external address output (internal reset deassertion)⁵

■

Minimum

Maximum

3.25 × T_C+ 2.0

20.25 × T_C+ 10.0

34.5

—

212.5

ns

11 Synchronous reset setup time from RESET deassertion to

CLKOUT Transition 1

■

Minimum

Maximum

5.9

—

10.0

ns

T_C

12 Synchronous reset deasserted, delay time from the CLKOUT

Transition 1 to the first external address output

■

Minimum

Maximum

3.25 × T_C+ 1.0

20.25 × T_C+ 1.0

33.5

—

207.5

ns

13 Mode select setup time

14 Mode select hold time

30.0

0.0

—

ns

DSP56309 Technical Data

2-7

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

100 MHz

Min Max

No.

Characteristics

Expression

Unit

15 Minimum edge-triggered interrupt request assertion width

6.6

—

ns

16 Minimum edge-triggered interrupt request deassertion width

6.6

17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory access address out valid

Minimum:

■

Caused by first interrupt instruction fetch

Caused by first interrupt instruction execution

4.25 × T_C+ 2.0

7.25 × T_C+ 2.0

44.5

74.5

—

ns

18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first

interrupt instruction execution

Minimum:

10 × T_C+ 5.0

105.0

—

ns

19 Delay from address output valid caused by first interrupt

Maximum:

instruction execute to interrupt request deassertion for level 3.75 × T_C+ WS × T_C– 10.94⁸

Note 8 ns

sensitive fast interrupts¹

20 Delay from RD assertion to interrupt request deassertion for

level sensitive fast interrupts¹

Maximum:

3.25 × T_C+ WS × T_C– 10.94⁸

—

21 Delay from WR assertion to interrupt request deassertion for

level sensitive fast interrupts¹

Maximum:

■

DRAM for all WS⁷

SRAM WS = 1

(WS + 3.5) × T_C– 10.94⁸

(WS + 3) × T_C– 10.94⁸

(WS + 2.5) × T_C– 10.94⁸

—

Note 8 ns

SRAM WS = 2, 3

SRAM WS ≥ 4

22 Synchronous interrupt setup time from IRQA, IRQB, IRQC,

IRQD, NMI assertion to the CLKOUT Transition 2

5.9

T_C

ns

23 Synchronous interrupt delay time from the CLKOUT

Transition 2 to the first external address output valid caused

by the first instruction fetch after coming out of Wait

Processing state

■

Minimum

Maximum

8.25 × T_C+ 1.0

24.75 × T_C+ 5.0

83.5

—

252.5

ns

24 Duration for IRQA assertion to recover from Stop state

5.9

—

ns

25 Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)^{2, 3}

■

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ET_C× PDF + (128 K −

delay is enabled (OMR Bit 6 = 0) PLC/2) × T_C

1.3

13.6

ms

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop PLC × ET_C× PDF + (23.75 ± 232.5 12.3

delay is not enabled (OMR Bit 6 = 1)

0.5) × T_C

ns

ms

PLL is active during Stop (PCTL Bit 17 = 1) (Implies No

Stop Delay)

(9.25 ± 0.5) × TC

87.5

97.5

ns

2-8

DSP56309 Technical Data

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

100 MHz

Min Max

No.

Characteristics

Expression

Unit

26 Duration of level sensitive IRQA assertion to ensure interrupt

service (when exiting Stop)^{2, 3}

Minimum:

■

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled

(OMR Bit 6 = 0)

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled

(OMR Bit 6 = 1)

PLC × ET_C× PDF +

(128K − PLC/2) × T_C

13.6

12.3

55.0

—

ms

ns

PLC × ET_C× PDF +

(20.5 ± 0.5) × T_C

PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

5.5 × T_C

27 Interrupt Requests Rate

Maximum:

12T_C

■

HI08, ESSI, SCI, Timer

DMA

IRQ, NMI (edge trigger)

IRQ, NMI (level trigger)

—

120.0

80.0

ns

8T_C

12T_C

120.0

28 DMA Requests Rate

Maximum:

6T_C

■

Data read from HI08, ESSI, SCI

Data write to HI08, ESSI, SCI

Timer

—

60.0

70.0

20.0

30.0

ns

7T_C

2T_C

3T_C

IRQ, NMI (edge trigger)

29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory (DMA source) access address out valid

Minimum:

4.25 × T_C+ 2.0

44.5

—

ns

Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19

through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted

Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when

Level-sensitive mode is used.

DSP56309 Technical Data

2-9

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing⁶(Continued)

100 MHz

Min Max

No.

Characteristics

Expression

Unit

2. This timing depends on several settings:

For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled

during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before

executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) provides the proper delay. While

it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings

for that case.

For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit

17=1), no stabilization delay is required and recovery time is minimal (OMR Bit 6 setting is ignored).

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time

is defined by the PCTL Bit 17 and OMR Bit 6 settings.

For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the

PLL to lock. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000

cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery ends when the last

of these two events occurs. The stop delay counter completes count or PLL lock procedure.

PLC value for PLL disable is 0.

The maximum value for ET_Cis 4096 (maximum MF) divided by the desired internal frequency (that is, for 66

MHz it is 4096/66 MHz = 62 µs). During the stabilization period, T_C, T_H,and T_Lare not constant, and their

width may vary, so timing may vary as well.

3. Periodically sampled and not 100 percent tested

4. For an external clock generator, RESET duration is measured during the time in which RESET is asserted,

V_CCis valid, and the EXTAL input is active and valid.

For internal oscillator, RESET duration is measured during the time in which RESET is asserted and V_CCis

valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is

affected both by the specifications of the crystal and other components connected to the oscillator and

reflects worst case conditions.

When the V_CCis valid, but the other “required RESET duration” conditions (as specified above) are not yet

met, the device circuitry is in an uninitialized state that can result in significant power consumption and

heat-up. Designs should minimize this state to the shortest possible duration.

5. If PLL does not lose lock

6. V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100°C, C_L= 50 pF

7. WS = number of wait states (measured in clock cycles, number of T_C)

8. Use expression to compute maximum value.

2-10

DSP56309 Technical Data

V_IH

RESET

9

10

8

All Pins

Reset Value

A[0–17]

First Fetch

Figure 2-3. Reset Timing

CLKOUT

11

RESET

12

A[0–17]

Figure 2-4. Synchronous Reset Timing

DSP56309 Technical Data

2-11

First Interrupt Instruction

Execution/Fetch

A[0–17]

RD

20

WR

21

19

17

IRQA, IRQB,

IRQC, IRQD,

NMI

a) First Interrupt Instruction Execution

General

Purpose

I/O

18

IRQA,

IRQB,

IRQC,

IRQD,

NMI

b) General Purpose I/O

Figure 2-5. External Fast Interrupt Timing

IRQA, IRQB,

IRQC, IRQD,

NMI

15

IRQA, IRQB,

IRQC, IRQD,

NMI

16

Figure 2-6. External Interrupt Timing (Negative Edge-Triggered)

2-12

DSP56309 Technical Data

CLKOUT

22

IRQA, IRQB,

IRQC, IRQD,

NMI

23

A[0–17]

Figure 2-7. Synchronous Interrupt from Wait State Timing

V_IH

RESET

13

14

V_IH

V_IL

V_IH

V_IL

IRQA, IRQB,

IRQC, IRQD,

NMI

MODA, MODB,

MODC, MODD,

PINIT

Figure 2-8. Operating Mode Select Timing

24

IRQA

25

First Instruction Fetch

A[0–17]

Figure 2-9. Recovery from Stop State Using IRQA

DSP56309 Technical Data

2-13

26

IRQA

25

First IRQA Interrupt

Instruction Fetch

A[0–17]

Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service

DMA Source Address

A[0–17]

RD

WR

29

IRQA, IRQB,

IRQC, IRQD,

NMI

First Interrupt Instruction Execution

Figure 2-11. External Memory Access (DMA Source) Timing

2-14

DSP56309 Technical Data

EXTERNAL MEMORY EXPANSION PORT (PORT A)

SRAM Timing

Table 2-8. SRAM Read and Write Accesses^3,5

100 MHz

No.

Characteristics

Symbol

Expression¹

Unit

Min

Max

100 Address valid and AA assertion pulse width²

101 Address and AA valid to WR assertion

102 WR assertion pulse width

t_RC, t_WC

(WS + 1) × T_C− 4.0

[1 ≤ WS ≤ 3]

(WS + 2) × T_C− 4.0

[4 ≤ WS ≤ 7]

(WS + 3) × T_C− 4.0

[WS ≥ 8]

16.0

56.0

—

ns

—

106.0

t_AS

t_WP

t_WR

0.25 × T_C− 2.0

[WS = 1]

0.75 × T_C− 2.0

[2 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[WS ≥ 4]

0.5

5.5

—

ns

10.5

1.5 × T_C− 4.0

[WS = 1]

WS × T_C− 4.0

[2 ≤ WS ≤ 3]

11.0

16.0

31.0

—

ns

(WS − 0.5) × T_C− 4.0

[WS ≥ 4]

103 WR deassertion to address not valid

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 4.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 4.0

[WS ≥ 8]

0.5

8.5

—

ns

18.5

104 Address and AA valid to input data valid

105 RD assertion to input data valid

t

_AA, t_AC

(WS + 0.75) × T_C−

5.0

—

12.5

7.5

ns

[WS ≥ 1]

t_OE

(WS + 0.25) × T_C–

5.0

[WS ≥ 1]

106 RD deassertion to data not valid (data hold time)

107 Address valid to WR deassertion²

t_OHZ

t_AW

0.0

—

ns

(WS + 0.75) × T_C−

4.0

13.5

[WS ≥ 1]

108 Data valid to WR deassertion (data setup time)

t_DS

(t_DW

(WS − 0.25) × T_C−

3.0

4.5

—

ns

)

[WS ≥ 1]

DSP56309 Technical Data

2-15

Table 2-8. SRAM Read and Write Accesses^3,5(Continued)

100 MHz

No.

Characteristics

Symbol

Expression¹

Unit

Min

Max

109 Data hold time from WR deassertion

t_DH

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 2.0

[WS ≥ 8]

0.5

—

ns

10.5

20.5

—

110 WR assertion to data active

0.75 × T_C− 3.7

[WS = 1]

0.25 × T_C– 3.7

[2 ≤ WS ≤ 3]

-0.25 × T_C− 3.7

[WS ≥ 4]

3.8

-1.2

-6.2

—

ns

111 WR deassertion to data high impedance

112 Previous RD deassertion to data active (write)

113 RD deassertion time

0.25 × T_C+ 0.2

[1 ≤ WS ≤ 3]

1.25 × TC + 0.2

[4 ≤ WS ≤ 7]

2.25 × T_C+ 0.2

[WS > 8]

—

2.7

ns

12.7

22.7

1.25 × T_C– 4.0

[1 ≤ WS ≤ 3]

2.25 × T_C– 4.0

[4 ≤ WS ≤ 7]

3.25 × T_C– 4.0

[WS > 8]

8.5

—

ns

18.5

28.5

0.75 × T_C− 4.0

[1 ≤ WS ≤ 3]

1.75 × T_C− 4.0

[4 ≤ WS ≤ 7]

2.75 × T_C− 4.0

[WS ≥ 8]

3.5

—

ns

13.5

23.5

114 WR deassertion time

0.5 × T_C− 4.0

[WS = 1]

1.0

6.0

—

ns

T_C− 4.0

[2 ≤ WS ≤ 3]

2.5 × T_C− 4.0

[4 ≤ WS ≤ 7]

3.5 × T_C− 4.0

[WS ≥ 8]

21.0

31.0

115 Address valid to RD assertion

116 RD assertion pulse width

0.5 × T_C− 4.0

1.0

8.5

—

ns

(WS + 0.25) × T_C

−4.0

117 RD deassertion to address not valid

0.25 × T_C− 2.0

[1 ≤ WS ≤ 3]

1.25 × T_C− 2.0

[4 ≤ WS ≤ 7]

2.25 × T_C− 2.0

[WS ≥ 8]

0.5

—

ns

10.5

20.5

2-16

DSP56309 Technical Data

Table 2-8. SRAM Read and Write Accesses^3,5(Continued)

100 MHz

No.

Characteristics

Symbol

Expression¹

Unit

Min

Max

118 TA setup before RD or WR deassertion⁴

0.25 × T_C+ 2.0

4.5

—

ns

119 TA hold after RD or WR deassertion

0

Notes: 1. WS is the number of wait states specified in the BCR.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5 · Vcc to 0.5 · Vcc

4. In the case of TA deassertion, timing 118 is relative to the deassertion edge of RD or WR if TA were to

remain active

5.

V_CC= 3.3 V ± 0.3 V; T_J= –40°C to +100°C, C_L= 50 pF

100

A[0–17]

AA[0–3]

117

106

113

116

RD

115

105

WR

104

118

119

TA

Data

In

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-12. SRAM Read Access

DSP56309 Technical Data

2-17

100

A[0–17]

AA[0–3]

107

101

102

103

WR

114

RD

TA

119

118

108

111

110

109

112

Data

Out

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-13. SRAM Write Access

2-18

DSP56309 Technical Data

DRAM Timing

The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should

be based on the timing values in the following timing tables. For example, the selection guide suggests that

four wait states be used for 100 MHz operation with Page Mode DRAM. However, a designer can use the

information in the appropriate table to determine the conditions under which fewer wait states can be used.

The designer can identify specific timings that prevent operation at 100 MHz and then use one of the

following methods to adjust the operation:

•

Run the chip at a slightly lower frequency (for example, 95 MHz).

Use faster DRAMs.

Manipulate control factors such as capacitive and resistive load to improve overall system

performance.

DRAM type

(t_RACns)

Note: This figure should be used for primary

selection. For exact and detailed timings see

Table 2-9 and Table 2-10.

100

80

70

60

50

Chip frequency

(MHz)

120

40

66

80

100

1 Wait states

2 Wait states

3 Wait states

4 Wait states

Figure 2-14. DRAM Page Mode Wait States Selection Guide

DSP56309 Technical Data

2-19

Table 2-9. DRAM Page Mode Timings, Three Wait States^{1, 2, 3}

100 MHz

Min Max

No.

Characteristics

Symbol

Expression

Unit

131 Page mode cycle time for two consecutive accesses of

the same direction

4 × T_C

40.0

35.0

—

ns

Page mode cycle time for mixed (read and write)

accesses⁴

t_PC

3.5 × T_C

132 CAS assertion to data valid (read)

t_CAC

t_AA

2 × T_C− 5.7

3 × T_C− 5.7

—

14.3

24.3

—

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

—

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

2.5 × T_C− 4.0

4.5 × T_C− 4.0

2 × T_C− 4.0

21.0

41.0

16.0

—

138 Last CAS deassertion to RAS assertion⁵

■

BRW[1–0] = 00, 01—not applicable

BRW[1–0] = 10

BRW[1–0] = 11

—

41.5

61.5

—

ns

4.75 × T_C− 6.0

6.75 × T_C− 6.0

139 CAS deassertion pulse width

t_CP

t_ASC

t_CAH

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

1.5 × T_C− 4.0

T_C− 4.0

11.0

6.0

—

19.3

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

2.5 × T_C− 4.0

4 × T_C− 4.0

21.0

36.0

8.5

1.25 × T_C− 4.0

0.75 × TC − 4.0

2.25 × T_C− 4.2

3.5 × T_C− 4.5

3.75 × T_C− 4.3

3.25 × T_C− 4.3

0.5 × T_C– 4.5

2.5 × T_C− 4.0

1.25 × T_C− 4.3

3.5 × T_C− 4.0

2.5 × T_C− 5.7

3.5

18.3

30.5

33.2

28.2

0.5

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_RWL

t_CWL

t_DS

t_DH

21.0

8.2

t_WCS

t_ROH

t_GA

31.0

—

2-20

DSP56309 Technical Data

Table 2-9. DRAM Page Mode Timings, Three Wait States^{1, 2, 3}(Continued)

100 MHz

Min Max

No.

Characteristics

Symbol

Expression

Unit

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

6.0

—

ns

0.75 × T_C– 1.5

0.25 × T_C

156 WR deassertion to data high impedance

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56309.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for

example, t_PCequals 4 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of page-access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

Table 2-10. DRAM Page Mode Timings, Four Wait States^{1, 2, 3}

100 MHz

No.

Characteristics

Symbol

Expression⁴

Unit

Min

Max

131 Page mode cycle time for two consecutive accesses of

the same direction

5 × T_C

50.0

—

ns

Page mode cycle time for mixed (read and write)

accesses⁴

t_PC

4.5 × T_C

45.0

—

132 CAS assertion to data valid (read)

t_CAC

t_AA

2.75 × T_C− 5.7

3.75 × T_C− 5.7

—

21.8

31.8

—

ns

133 Column address valid to data valid (read)

134 CAS deassertion to data not valid (read hold time)

135 Last CAS assertion to RAS deassertion

136 Previous CAS deassertion to RAS deassertion

137 CAS assertion pulse width

—

t_OFF

t_RSH

t_RHCP

t_CAS

t_CRP

0.0

3.5 × T_C− 4.0

6 × T_C− 4.0

31.0

56.0

21.0

—

2.5 × T_C− 4.0

—

138 Last CAS deassertion to RAS assertion⁵

■

BRW[1–0] = 00, 01—Not applicable

BRW[1–0] = 10

BRW[1–0] = 11

—

46.5

66.5

—

ns

5.25 × T_C− 6.0

7.25 × T_C− 6.0

139 CAS deassertion pulse width

t_CP

2 × T_C− 4.0

T_C− 4.0

16.0

6.0

—

ns

140 Column address valid to CAS assertion

141 CAS assertion to column address not valid

t_ASC

t_CAH

3.5 × T_C− 4.0

31.0

DSP56309 Technical Data

2-21

Table 2-10. DRAM Page Mode Timings, Four Wait States^{1, 2, 3}(Continued)

100 MHz

Min Max

No.

Characteristics

Symbol

Expression⁴

Unit

142 Last column address valid to RAS deassertion

143 WR deassertion to CAS assertion

144 CAS deassertion to WR assertion

145 CAS assertion to WR deassertion

146 WR assertion pulse width

t_RAL

t_RCS

t_RCH

t_WCH

t_WP

5 × T_C− 4.0

1.25 × T_C− 4.0

1.25 × T_C– 3.7

3.25 × T_C− 4.2

4.5 × T_C− 4.5

4.75 × T_C− 4.3

3.75 × T_C− 4.3

0.5 × T_C– 4.5

3.5 × T_C− 4.0

1.25 × T_C− 4.3

4.5 × T_C− 4.0

3.25 × T_C− 5.7

46.0

8.5

—

ns

8.8

—

28.3

40.5

43.2

33.2

0.5

—

147 Last WR assertion to RAS deassertion

148 WR assertion to CAS deassertion

149 Data valid to CAS assertion (write)

150 CAS assertion to data not valid (write)

151 WR assertion to CAS assertion

152 Last RD assertion to RAS deassertion

153 RD assertion to data valid

t_RWL

t_CWL

t_DS

—

t_DH

31.0

8.2

—

t_WCS

t_ROH

t_GA

—

41.0

—

26.8

—

154 RD deassertion to data not valid⁶

155 WR assertion to data active

t_GZ

0.0

0.75 × T_C– 1.5

0.25 × T_C

6.0

—

156 WR deassertion to data high impedance

—

2.5

Notes: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56309.

4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for

example, t_PCequals 3 × T_Cfor read-after-read or write-after-write sequences).

5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each

DRAM out-of-page access.

6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

2-22

DSP56309 Technical Data

RAS

CAS

136

135

131

137

139

141

138

140

151

142

Column

Address

Last Column

Address

Column

Address

Row

Add

A[0–17]

144

145

147

WR

RD

146

148

155

149

156

150

D[0–23]

Data Out

Figure 2-15. DRAM Page Mode Write Accesses

DSP56309 Technical Data

2-23

RAS

136

135

131

CAS

137

139

141

138

142

140

Row

Add

Last Column

Address

Column

Address

Column

Address

A[0–17]

WR

143

132

133

153

152

RD

134

154

D[0–23]

Data In

Figure 2-16. DRAM Page Mode Read Accesses

2-24

DSP56309 Technical Data

DRAM Type

(t_RACns)

Note: This figure should be used for primary selection. For exact

and detailed timings, see Table 2-11 and Table 2-12.

100

80

70

60

Chip Frequency

(MHz)

50

120

40 66

80

100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Figure 2-17. DRAM Out-of-Page Wait States Selection Guide

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2}

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RC

t_RAC

t_CAC

t_AA

12 × T_C

120.0

—

55.5

30.5

38.0

—

ns

6.25 × T_C− 7.0

3.75 × T_C− 7.0

4.5 × T_C− 7.0

—

t_OFF

t_RP

0.0

4.25 × T_C− 4.0

7.75 × T_C− 4.0

5.25 × T_C− 4.0

6.25 × T_C− 4.0

38.5

73.5

48.5

58.5

—

t_RAS

t_RSH

t_CSH

—

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

—

DSP56309 Technical Data

2-25

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2}(Continued)

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

166 CAS assertion pulse width

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

3.75 × T_C− 4.0

2.5 × T_C± 4.0

1.75 × T_C± 4.0

5.75 × T_C− 4.0

4.25 × T_C– 6.0

4.25 × T_C− 4.0

1.75 × T_C− 4.0

0.75 × T_C− 4.0

5.25 × T_C− 4.0

7.75 × T_C− 4.0

6 × T_C− 4.0

33.5

21.0

13.5

53.5

36.5

38.5

13.5

3.5

—

29.0

21.5

—

ns

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR³assertion

179 RAS deassertion to WR³assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASR

t_RAH

t_ASC

t_CAH

t_AR

48.5

73.5

56.0

26.0

13.8

0.5

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

3.0 × T_C− 4.0

1.75 × T_C– 3.7

0.25 × T_C− 2.0

5 × T_C− 4.2

45.8

70.8

110.5

113.2

98.2

53.5

48.5

73.5

60.7

11.0

23.5

111.0

7.5 × T_C− 4.2

11.5 × T_C− 4.5

11.75 × T_C− 4.3

10.25 × T_C− 4.3

5.75 × T_C− 4.0

5.25 × T_C− 4.0

7.75 × T_C− 4.0

6.5 × T_C− 4.3

1.5 × T_C− 4.0

2.75 × T_C− 4.0

11.5 × T_C− 4.0

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

t_DH

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

2-26

DSP56309 Technical Data

Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2}(Continued)

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

192 RD assertion to data valid

t_GA

10 × T_C− 7.0

—

0.0

6.0

—

93.0

—

ns

193 RD deassertion to data not valid⁴

194 WR assertion to data active

t_GZ

0.75 × T_C– 1.5

0.25 × T_C

—

195 WR deassertion to data high impedance

2.5

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. Either t_RCHor t_RRHmust be satisfied for read cycles.

4. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^{1, 2}

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

157 Random read or write cycle time

158 RAS assertion to data valid (read)

159 CAS assertion to data valid (read)

160 Column address valid to data valid (read)

161 CAS deassertion to data not valid (read hold time)

162 RAS deassertion to RAS assertion

163 RAS assertion pulse width

t_RC

t_RAC

t_CAC

t_AA

16 × T_C

160.0

—

76.8

41.8

49.3

—

ns

8.25 × T_C− 5.7

4.75 × T_C− 5.7

5.5 × T_C− 5.7

0.0

—

t_OFF

t_RP

0.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

6.25 × T_C− 4.0

8.25 × T_C− 4.0

4.75 × T_C− 4.0

3.5 × T_C± 2

58.5

93.5

58.5

78.5

43.5

33.0

25.5

73.5

56.5

58.5

23.5

—

t_RAS

t_RSH

t_CSH

t_CAS

t_RCD

t_RAD

t_CRP

t_CP

—

164 CAS assertion to RAS deassertion

165 RAS assertion to CAS deassertion

166 CAS assertion pulse width

—

167 RAS assertion to CAS assertion

168 RAS assertion to column address valid

169 CAS deassertion to RAS assertion

170 CAS deassertion pulse width

37.0

29.5

—

2.75 × T_C± 2

7.75 × T_C− 4.0

6.25 × T_C– 6.0

6.25 × T_C− 4.0

2.75 × T_C− 4.0

—

171 Row address valid to RAS assertion

172 RAS assertion to row address not valid

t_ASR

t_RAH

—

DSP56309 Technical Data

2-27

Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States^{1, 2}(Continued)

100 MHz

No.

Characteristics

Symbol

Expression

Unit

Min

Max

173 Column address valid to CAS assertion

174 CAS assertion to column address not valid

175 RAS assertion to column address not valid

176 Column address valid to RAS deassertion

177 WR deassertion to CAS assertion

178 CAS deassertion to WR³assertion

179 RAS deassertion to WR³assertion

180 CAS assertion to WR deassertion

181 RAS assertion to WR deassertion

182 WR assertion pulse width

t_ASC

t_CAH

t_AR

0.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

7 × T_C− 4.0

3.5

58.5

93.5

66.0

46.2

13.8

0.5

—

ns

—

t_RAL

t_RCS

t_RCH

t_RRH

t_WCH

t_WCR

t_WP

—

5 × T_C− 3.8

—

1.75 × T_C– 3.7

0.25 × T_C− 2.0

6 × T_C− 4.2

—

55.8

90.8

150.5

153.2

138.2

83.5

58.5

93.5

90.7

11.0

43.5

151.0

—

9.5 × T_C− 4.2

15.5 × T_C− 4.5

15.75 × T_C− 4.3

14.25 × T_C− 4.3

8.75 × T_C− 4.0

6.25 × T_C− 4.0

9.75 × T_C− 4.0

9.5 × T_C− 4.3

1.5 × T_C− 4.0

4.75 × T_C− 4.0

15.5 × T_C− 4.0

14 × T_C− 5.7

—

183 WR assertion to RAS deassertion

184 WR assertion to CAS deassertion

185 Data valid to CAS assertion (write)

186 CAS assertion to data not valid (write)

187 RAS assertion to data not valid (write)

188 WR assertion to CAS assertion

t_RWL

t_CWL

t_DS

—

t_DH

—

t_DHR

t_WCS

t_CSR

t_RPC

t_ROH

t_GA

—

189 CAS assertion to RAS assertion (refresh)

190 RAS deassertion to CAS assertion (refresh)

191 RD assertion to RAS deassertion

192 RD assertion to data valid

—

134.3

ns

193 RD deassertion to data not valid⁴

194 WR assertion to data active

t_GZ

0.0

6.0

—

0.75 × T_C– 1.5

0.25 × T_C

195 WR deassertion to data high impedance

2.5

Notes: 1. The number of wait states for out-of-page access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. Either t_RCHor t_RRHmust be satisfied for read cycles.

4. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFFand not t_GZ

.

2-28

DSP56309 Technical Data

157

163

165

162

169

RAS

167

168

164

170

166

CAS

171

173

174

175

Row Address

172

Column Address

176

A[0–17]

177

179

191

WR

RD

178

160

159

158

192

193

161

Data

In

D[0–23]

Figure 2-18. DRAM Out-of-Page Read Access

DSP56309 Technical Data

2-29

157

162

163

165

162

RAS

167

168

164

169

166

170

CAS

171

173

172

174

176

Row Address

Column Address

A[0–17]

181

175

188

180

182

WR

RD

184

183

187

186

195

185

194

Data Out

D[0–23]

Figure 2-19. DRAM Out-of-Page Write Access

2-30

DSP56309 Technical Data

157

162

163

165

162

RAS

CAS

190

170

189

177

WR

Figure 2-20. DRAM Refresh Access

DSP56309 Technical Data

2-31

Synchronous Timings

Table 2-13. External Bus Synchronous Timings³

100 MHz

Min Max

No.

Characteristics

Expression^1,2

Unit

198 CLKOUT high to address, and AA valid⁴

199 CLKOUT high to address, and AA invalid⁴

200 TA valid to CLKOUT high (setup time)

201 CLKOUT high to TA invalid (hold time)

202 CLKOUT high to data out active

203 CLKOUT high to data out valid

0.25 × T_C+ 4.0

0.25 × T_C

—

2.5

4.0

0.0

2.5

—

6.5

—

ns

—

0.25 × T_C

0.25 × T_C+ 4.0

0.25 × T_C

—

6.5

—

204 CLKOUT high to data out invalid

205 CLKOUT high to data out high impedance

206 Data in valid to CLKOUT high (setup)

207 CLKOUT high to data in invalid (hold)

208 CLKOUT high to RD assertion

2.5

—

0.25 × T_C

2.5

—

4.0

0.0

6.7

0.0

5.0

—

0.75 × T_C+ 2.5

10.0

4.0

9.3

209 CLKOUT high to RD deassertion

210 CLKOUT high to WR assertion²

0.5 × T_C+ 4.3

[WS = 1 or WS ≥ 4]

[2 ≤ WS ≤ 3]

0.0

4.3

3.8

ns

211 CLKOUT high to WR deassertion

Notes: 1. WS is the number of wait states specified in the BCR.

2. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

3. External bus synchronous timings should be used only for reference to the clock and not for relative

timings.

4. T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR

(See T212) to determine whether the access referenced by A[0–17] is internal or external, when this mode

is enabled

5. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

2-32

DSP56309 Technical Data

CLKOUT

199

198

A[0–17]

AA[0–3]

201

200

TA

211

WR

210

205

203

202

204

D[0–23]

Data Out

208

209

RD

207

206

D[0–23]

Data In

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-21. Synchronous Bus Timings 1 WS (BCR Controlled)

DSP56309 Technical Data

2-33

CLKOUT

198

199

A[0–17]

AA[0–3]

201

200

TA

211

WR

210

205

203

202

204

Data Out

D[0–23]

208

209

RD

207

206

Data In

D[0–23]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-22. Synchronous Bus Timings 2 WS (TA Controlled)

2-34

DSP56309 Technical Data

Arbitration Timings

Table 2-14. Arbitration Bus Timings

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

212 CLKOUT high to BR assertion/deassertion¹

213 BG asserted/deasserted to CLKOUT high (setup)

214 CLKOUT high to BG deasserted/asserted (hold)

215 BB deassertion to CLKOUT high (input setup)

216 CLKOUT high to BB assertion (input hold)

217 CLKOUT high to BB assertion (output)

218 CLKOUT high to BB deassertion (output)

219 BB high to BB high impedance (output)

220 CLKOUT high to address and controls active

221 CLKOUT high to address and controls high impedance

222 CLKOUT high to AA active

0.0

4.0

0.0

4.0

0.0

—

4.0

—

ns

—

4.0

4.5

—

0.25 × T_C

0.75 × T_C

2.5

—

7.5

—

0.25 × T_C

2.5

2.0

—

223 CLKOUT high to AA deassertion

0.25 × T_C+ 4.0

0.75 × T_C

6.5

7.5

224 CLKOUT high to AA high impedance

Notes: 1. T212 is valid for Address Trace mode when the ATE bit in the OMR is set. BR is deasserted for internal

accesses and asserted for external accesses.

2. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible.

DSP56309 Technical Data

2-35

CLKOUT

BR

212

214

216

213

215

BG

BB

217

220

A[0–17]

RD, WR

222

AA[0–3]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-23. Bus Acquisition Timings

2-36

DSP56309 Technical Data

CLKOUT

BR

212

214

213

BG

BB

219

218

221

A[0–17]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-24. Bus Release Timings Case 1 (BRT Bit in OMR Cleared)

DSP56309 Technical Data

2-37

CLKOUT

BR

212

214

213

BG

BB

219

218

221

A[0–17]

RD, WR

224

223

AA[0–3]

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

Figure 2-25. Bus Release Timings Case 2 (BRT Bit in OMR Set)

Table 2-15. Asynchronous Bus Arbitration Timing^1,3

100 MHz²

No.

Characteristics

Expression

Unit

Min

Max

250 BB assertion window from BG input deassertion⁴

2.5 x Tc + 5

—

30

—

ns

251 Delay from BB assertion to BG assertion⁴

2 x Tc + 5

25

Notes: 1. Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode.

2. Asynchronous Arbitration mode is recommended for operation at 100 MHz.

3. If Asynchronous Arbitration mode is active, none of the timings in Table 2-14 is required.

4. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices

on the same bus in the non-overlap manner shown in Figure 2-26.

2-38

DSP56309 Technical Data

BG1

BB

250

BG2

251

Figure 2-26. Asynchronous Bus Arbitration Timing

BG1

BG2

250+251

Figure 2-27. Asynchronous Bus Arbitration Timing

The asynchronous bus arbitration is enabled by internal BB inputs and synchronization circuits on BG.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a DSP56300 part can assume mastership and assert BB, for some time after BG is

deasserted. Timing 250 defines when BB can be asserted.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other DSP56300 components which are potential masters on the same bus. If BG input is

asserted before that time, a situation of BG asserted, and BB deasserted, can cause another DSP56300

component to assume mastership at the same time. Therefore, a non-overlap period between one BG input

active to another BG input active is required. Timing 251 ensures that such a situation is avoided.

DSP56309 Technical Data

2-39

HOST INTERFACE TIMING

Table 2-16. Host Interface Timing^{1, 2}

100 MHz

Min Max

No.

Characteristic¹⁰

Expression

Unit

317 Read data strobe assertion width⁵HACK assertion width

T_C+ 9.0

19.9

9.9

—

ns

318 Read data strobe deassertion width⁵HACK deassertion width

319 Read data strobe deassertion width⁵after “Last Data Register”

reads^8,11, or between two consecutive CVR, ICR, or ISR reads³

HACK deassertion width after “Last Data Register” reads^8,11

2.5 × T_C+ 6.6

31.6

320 Write data strobe assertion width⁶

14.5

—

ns

321 Write data strobe deassertion width⁸

HACK write deassertion width

■

after HCTR, HCVR and “Last Data Register” writes

2.5 × T_C+ 6.6

31.6

16.5

—

ns

■

after TXH:TXM writes (with HLEND=0)⁸

after TXL:TXM writes (with HLEND=1)⁸

322 HAS assertion width

9.9

0.0

9.9

3.3

—

ns

323 HAS deassertion to data strobe assertion⁴

324 Host data input setup time before write data strobe deassertion⁶

325 Host data input hold time after write data strobe deassertion⁶

326 Read data strobe assertion to output data active from high

impedance⁵HACK assertion to output data active from high

impedance

327 Read data strobe assertion to output data valid⁵

HACK assertion to output data valid

—

23.5

9.9

—

ns

328 Read data strobe deassertion to output data high impedance⁵

HACK deassertion to output data high impedance

329 Output data hold time after read data strobe deassertion⁵

Output data hold time after HACK deassertion

3.1

330 HCS assertion to read data strobe deassertion⁵

331 HCS assertion to write data strobe deassertion⁶

332 HCS assertion to output data valid

T_C+ 9.9

19.9

9.9

—

ns

16.5

—

333 HCS hold time after data strobe deassertion⁴

0.0

4.7

3.3

334 Address (HAD[7–0]) setup time before HAS deassertion (HMUX=1)

335 Address (HAD[7–0]) hold time after HAS deassertion (HMUX=1)

—

336 HA[10–8] (HMUX=1), A[2–0] (HMUX=0), HR/W setup time before

data strobe assertion⁴

■

Read

Write

0

4.7

—

ns

337 HA[10–8] (HMUX=1), A[2–0] (HMUX=0), HR/W hold time after data

strobe deassertion⁴

3.3

—

ns

2-40

DSP56309 Technical Data

Table 2-16. Host Interface Timing^{1, 2}(Continued)

100 MHz

Min Max

No.

Characteristic¹⁰

Expression

Unit

338 Delay from read data strobe deassertion to host request assertion

1.5 × T_C+ 10

2.0 × T_C+ 13

25.0

33.0

—

ns

for “Last Data Register” read^{5, 7, 8}

339 Delay from write data strobe deassertion to host request assertion

for “Last Data Register” write^{6, 7, 8}

—

340 Delay from data strobe assertion to host request deassertion for

“Last Data Register” read or write (HROD=0)^{4, 7, 8}

20.2

300.0

341 Delay from data strobe assertion to host request deassertion for

“Last Data Register” read or write (HROD=1, open drain host

request)^{4, 7, 8, 9}

—

Notes: 1. See Host Port Usage Considerations on page 1-10.

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3. This timing is applicable only if two consecutive reads from one of these registers are executed.

4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data

Strobe (HDS) in the Single Data Strobe mode.

5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.

7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host

Request mode.

8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data

transfers. This is RXL/TXL in the Little Endian mode (HLEND = 1), or RXH/TXH in the Big Endian mode

(HLEND = 0).

9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.

10. V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL,

RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ

signal.

317

318

HACK

328

327

326

329

HD7–HD0

HREQ

Figure 2-28. Host Interrupt Vector Register (IVR) Read Timing Diagram

DSP56309 Technical Data

2-41

HA7–HA0

336

337

333

330

HCS

317

HRD, HDS

318

319

328

332

327

329

326

341

HD7–HD0

338

340

HREQ, HRRQ, HTRQ

Figure 2-29. Read Timing Diagram, Non-Multiplexed Bus

2-42

DSP56309 Technical Data

HA7–HA0

337

333

336

331

HCS

320

HWR, HDS

321

325

324

HD7–HD0

340

339

341

HREQ, HRRQ, HTRQ

Figure 2-30. Write Timing Diagram, Non-Multiplexed Bus

DSP56309 Technical Data

2-43

HA[10–8]

336

337

322

HAS

323

317

HRD, HDS

334

318

319

335

327

328

329

HAD[7–0]

Address

Data

326

338

340

341

HREQ, HRRQ, HTRQ

Figure 2-31. Read Timing Diagram, Multiplexed Bus

2-44

DSP56309 Technical Data

HA[10–8]

336

322

HAS

323

320

HWR, HDS

334

324

321

325

335

HAD[7–0]

Data

340

Address

339

341

HREQ, HRRQ, HTRQ

Figure 2-32. Write Timing Diagram, Multiplexed Bus

DSP56309 Technical Data

2-45

SCI TIMING

Table 2-17. SCI Timing

100 MHz

Min Max

No.

Characteristics¹

Symbol

Expression

Unit

2

400 Synchronous clock cycle

401 Clock low period

t_SCC

8 × T_C

80.0

30.0

—

ns

t_SCC/2 − 10.0

402 Clock high period

t_SCC/2 − 10.0

403 Output data setup to clock falling edge (internal clock)

404 Output data hold after clock rising edge (internal clock)

t

_SCC/4 + 0.5 × T_C−17.0 8.0

t_SCC/4 − 0.5 × T_C15.0

t_SCC/4 + 0.5 × T_C+ 25.0 50.0

405 Input data setup time before clock rising edge (internal

clock)

406 Input data not valid before clock rising edge (internal

clock)

t_SCC/4 + 0.5 × T_C− 5.5

—

19.5

ns

407 Clock falling edge to output data valid (external clock)

408 Output data hold after clock rising edge (external clock)

—

18.0

0.0

32.0

—

ns

T_C+ 8.0

409 Input data setup time before clock rising edge (external

clock)

—

410 Input data hold time after clock rising edge (external

clock)

9.0

—

ns

3

411 Asynchronous clock cycle

t_ACC

64 × T_C

640.0

310.0

290.0

—

ns

412 Clock low period

t_ACC/2 − 10.0

413 Clock high period

t

_ACC/2 − 10.0

_ACC/2 − 30.0

t_ACC/2 − 30.0

414 Output data setup to clock rising edge (internal clock)

415 Output data hold after clock rising edge (internal clock)

t

Notes: 1.

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

2. t_SCC= synchronous clock cycle time (For internal clock, t_SCCis determined by the SCI clock control register

and T_C.)

3. t_ACC= asynchronous clock cycle time; value given for 1X Clock mode (For internal clock, t_ACCis determined

by the SCI clock control register and T_C.)

2-46

DSP56309 Technical Data

400

402

404

401

SCLK

(Output)

403

TXD

RXD

Data Valid

405

406

Data

Valid

a) Internal Clock

400

402

401

SCLK

(Input)

407

408

Data Valid

TXD

RXD

409

410

Data Valid

b) External Clock

Figure 2-33. SCI Synchronous Mode Timing

411

413

415

412

414

1X SCLK

(Output)

TXD

Data Valid

Figure 2-34. SCI Asynchronous Mode Timing

DSP56309 Technical Data

2-47

ESSI0/ESSI1 TIMING

Table 2-18. ESSI Timings

100 MHz

Min Max

Cond-

ition⁶

No.

Characteristics^{4, 5, 7}

Symbol

Expression

Unit

430 Clock cycle¹

t_SSICC

3 × T

30.0

40.0

—

x ck

i ck

ns

C

4 × T

C

431 Clock high period

■

For internal clock

For external clock

2 × T − 10.0

10.0

15.0

—

ns

C

1.5 × T

C

432 Clock low period

■

For internal clock

For external clock

2 × T − 10.0

10.0

15.0

—

ns

C

1.5 × T

C

433 RXC rising edge to FSR out (bl) high

434 RXC rising edge to FSR out (bl) low

435 RXC rising edge to FSR out (wr) high²

436 RXC rising edge to FSR out (wr) low²

437 RXC rising edge to FSR out (wl) high

438 RXC rising edge to FSR out (wl) low

—

37.0

22.0 i ck a

x ck

ns

—

37.0 x ck

22.0 i ck a

39.0 x ck

—

37.0 i ck a

—

39.0 x ck

37.0 i ck a

36.0 x ck

—

21.0 i ck a

—

37.0 x ck

22.0 i ck a

439 Data in setup time before RXC (SCK in Synchronous

mode) falling edge

10.0

19.0

—

x ck

i ck

440 Data in hold time after RXC falling edge

441 FSR input (bl, wr) high before RXC falling edge²

442 FSR input (wl) high before RXC falling edge

443 FSR input hold time after RXC falling edge

444 Flags input setup before RXC falling edge

445 Flags input hold time after RXC falling edge

446 TXC rising edge to FST out (bl) high

5.0

3.0

—

x ck

i ck

1.0

23.0

—

x ck

i ck a

3.5

23.0

—

x ck

i ck a

3.0

0.0

—

x ck

i ck a

5.5

19.0

—

x ck

i ck s

6.0

0.0

—

x ck

i ck s

—

29.0

15.0

x ck

i ck

447 TXC rising edge to FST out (bl) low

—

31.0

17.0

x ck

i ck

2-48

DSP56309 Technical Data

Table 2-18. ESSI Timings (Continued)

100 MHz

Min Max

Cond-

ition⁶

No.

Characteristics^{4, 5, 7}

Symbol

Expression

Unit

448 TXC rising edge to FST out (wr) high²

449 TXC rising edge to FST out (wr) low²

450 TXC rising edge to FST out (wl) high

451 TXC rising edge to FST out (wl) low

—

31.0

17.0

x ck

i ck

ns

—

33.0

19.0

x ck

i ck

—

30.0

16.0

x ck

i ck

—

31.0

17.0

x ck

i ck

452 TXC rising edge to data out enable from high

impedance

—

31.0

17.0

x ck

i ck

453 TXC rising edge to Transmitter #0 drive enable

assertion

—

34.0

20.0

x ck

i ck

454 TXC rising edge to data out valid

—

20.0⁸x ck

10.0

i ck

455 TXC rising edge to data out high impedance³

—

31.0

16.0

x ck

i ck

456 TXC rising edge to Transmitter #0 drive enable

deassertion³

—

34.0

20.0

x ck

i ck

457 FST input (bl, wr) setup time before TXC falling edge²

2.0

21.0

—

x ck

i ck

458 FST input (wl) to data out enable from high impedance

459 FST input (wl) to Transmitter #0 drive enable assertion

460 FST input (wl) setup time before TXC falling edge

—

27.0

31.0

—

ns

2.5

21.0

—

x ck

i ck

461 FST input hold time after TXC falling edge

462 Flag output valid after TXC rising edge

4.0

0.0

—

x ck

i ck

ns

—

32.0

18.0

x ck

i ck

DSP56309 Technical Data

2-49

Table 2-18. ESSI Timings (Continued)

100 MHz

Max

Cond-

ition⁶

No.

Characteristics^{4, 5, 7}

Symbol

Expression

Unit

Min

Notes: 1. For the internal clock, the external clock cycle is defined by I_CYCand the ESSI control register.

2. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the

bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as Bit

Length Frame Sync signal), until the one before last bit clock of the first word in frame.

3. Periodically sampled and not 100 percent tested

4. V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

5. TXC (SCK Pin) = Transmit Clock

RXC (SC0 or SCK Pin) = Receive Clock

FST (SC2 Pin) = Transmit Frame Sync

FSR (SC1 or SC2 Pin) Receive Frame Sync

6. i ck = Internal Clock

x ck = External Clock

i ck a = Internal Clock, Asynchronous Mode

(Asynchronous implies that TXC and RXC are two different clocks)

i ck s = Internal Clock, Synchronous Mode

(Synchronous implies that TXC and RXC are the same clock)

7. bl = bit length

wl = word length

wr = word length relative

8. If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the

delay is 20 ns + (0.5 × T_C).

2-50

DSP56309 Technical Data

430

431

432

TXC

(Input/

Output)

446

447

FST (Bit)

Out

450

451

FST (Word)

Out

454

452

454

455

Data Out

First Bit

Last Bit

459

Transmitter

#0 Drive

Enable

457

453

456

461

460

FST (Bit) In

458

461

FST (Word)

In

462

See Note

Flags Out

Note: In Network mode, output flag transitions can occur at the start of each time slot

within the frame. In Normal mode, the output flag state is asserted for the entire

frame period.

Figure 2-35. ESSI Transmitter Timing

DSP56309 Technical Data

2-51

430

431

432

RXC

(Input/

Output)

433

434

FSR (Bit)

Out

437

438

FSR

(Word)

Out

440

439

443

Data In

Last Bit

First Bit

441

FSR (Bit)

In

443

445

442

FSR

(Word)

In

444

Flags In

Figure 2-36. ESSI Receiver Timing

2-52

DSP56309 Technical Data

TIMER TIMING

Table 2-19. Timer Timing

100 MHz

Min Max

No.

Characteristics

Expression

Unit

480

2 × T_C+ 2.0

22.0

9.0

—

ns

TIO Low

481 TIO High

482 Timer setup time from TIO (Input) assertion to CLKOUT rising

edge

10.0

483 Synchronous timer delay time from CLKOUT rising edge to the

external memory access address out valid caused by first interrupt

instruction execution

10.25 × T_C+ 1.0

103.5

—

ns

484 CLKOUT rising edge to TIO (Output) assertion

■

Minimum

Maximum

0.5 × T_C+ 0.5

0.5 × T_C+ 19.8

5.5

—

24.8

ns

485 CLKOUT rising edge to TIO (Output) deassertion

■

Minimum

Maximum

0.5 × T_C+ 0.5

0.5 × T_C+ 19.8

5.5

—

24.8

ns

Note:

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

TIO

480

481

Figure 2-37. TIO Timer Event Input Restrictions

CLKOUT

TIO (Input)

482

Address

483

First Interrupt Instruction Execution

Figure 2-38. Timer Interrupt Generation

DSP56309 Technical Data

2-53

CLKOUT

TIO (Output)

484

485

Figure 2-39. External Pulse Generation

GPIO TIMING

Table 2-20. GPIO Timing

100 MHz

Min Max

No.

Characteristics

Expression

Unit

490

—

0.0

8.5

0.0

67.5

8.5

—

ns

CLKOUT edge to GPIO out valid (GPIO out delay time)

491 CLKOUT edge to GPIO out not valid (GPIO out hold time)

492 GPIO In valid to CLKOUT edge (GPIO in set-up time)

493 CLKOUT edge to GPIO in not valid (GPIO in hold time)

494 Fetch to CLKOUT edge before GPIO change

6.75 × T_C

Note:

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

CLKOUT

(Output)

490

491

GPIO

(Output)

492

493

GPIO

(Input)

Valid

A[0–17]

494

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

Figure 2-40. GPIO Timing

2-54

DSP56309 Technical Data

JTAG TIMING

Table 2-21. JTAG Timing

All frequencies

Min Max

No.

Characteristics^1,2

Unit

500 TCK frequency of operation (1/(T_C× 3); maximum 22 MHz)

501 TCK cycle time in Crystal mode

502 TCK clock pulse width measured at 1.5 V

503 TCK rise and fall times

0.0

45.0

20.0

0.0

22.0

—

MHz

ns

—

3.0

—

504 Boundary scan input data setup time

505 Boundary scan input data hold time

506 TCK low to output data valid

5.0

24.0

0.0

—

40.0

—

507 TCK low to output high impedance

508 TMS, TDI data setup time

0.0

5.0

509 TMS, TDI data hold time

25.0

0.0

—

510 TCK low to TDO data valid

44.0

—

511 TCK low to TDO high impedance

512 TRST assert time

0.0

100.0

40.0

513 TRST setup time to TCK low

—

Notes: 1.

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

501

502

V

M

V

M

TCK

(Input)

IH

V

IL

503

Figure 2-41. Test Clock Input Timing Diagram

DSP56309 Technical Data

2-55

V_IH

505

TCK

(Input)

V_IL

504

Data

Inputs

Input Data Valid

506

507

506

Data

Output Data Valid

Outputs

Data

Outputs

Data

Outputs

Output Data Valid

Figure 2-42. Boundary Scan (JTAG) Timing Diagram

V_IH

509

Input Data Valid

TCK

V_IL

(Input)

508

TDI

TMS

(Input)

510

TDO

(Output)

Output Data Valid

511

TDO

(Output)

510

TDO

(Output)

Output Data Valid

Figure 2-43. Test Access Port Timing Diagram

2-56

DSP56309 Technical Data

TCK

(Input)

513

TRST

(Input)

512

Figure 2-44. TRST Timing Diagram

OnCE MODULE TIMING

Table 2-22. OnCE Module Timing

100 MHz

No.

Characteristics

Expression

Unit

Min

Max

500

1/(T_C× 3),

max 22.0 MHz

0.0

22.0 MHz

TCK frequency of operation

514 DE assertion time in order to enter Debug mode

1.5 × T_C+ 10.0

5.5 × T_C+ 30.0

25.0

—

ns

515 Response time when DSP56309 is executing NOP

instructions from internal memory

—

85.0

516 Debug acknowledge assertion time

3 × T_C– 5.0

25.0

—

ns

Note:

V_CC= 3.3 V ± 0.3 V; T_J= −40°C to +100 °C, C_L= 50 pF

DE

514

515

516

Figure 2-45. OnCE—Debug Request

DSP56309 Technical Data

2-57

2-58

DSP56309 Technical Data

SECTION 3

Packaging

PIN-OUT AND PACKAGE INFORMATION

This section provides information about the available packages for this product, including diagrams of the

package pinouts and tables describing how the signals described in DSP56309 User’s Manual, Section 2,

Signal/Connection Descriptions are allocated for each package.

The DSP56309 is available in two package types:

•

144-pin Thin Quad Flat Pack (TQFP)

196-pin Molded Array Process-Ball Grid Array (MAP-BGA)

DSP56309 Technical Data

3-1

TQFP Package Description

Top and bottom views of the TQFP package are shown in Figure 3-1. and Figure 3-2. with their pin-outs.

D7

D8

A0

BG

109

(Top View)

V_CCD

AA0/RAS0

AA1/RAS1

RD

GND_D

D9

D10

D11

D12

D13

D14

V_CCD

WR

GND_C

V_CCC

BB

BR

TA

BCLK

CLKOUT

GND_C

V_CCC

GND_D

D15

D16

D17

D18

V_CCQL

EXTAL

GND_Q

XTAL

D19

V_CCQL

DSP56309

GND_Q

D20

V_CCD

CAS

AA2/RAS2

AA3/RAS3

V_CCQH

GND_P1

GND_P

PCAP

V_CCP

RESET

HAD0

HAD1

HAD2

HAD3

GND_H

V_CCH

GND_D

D21

D22

D23

MODD/ IRQD

MODC/ IRQC

MODB/ IRQB

MODA/ IRQA

TRST

TDO

TDI

Orientation Mark

TCK

TMS

SC12

37

HAD4

SC11

AA1535

Figure 3-1. DSP56309 Thin Quad Flat Pack (TQFP), Top View

3-2

DSP56309 Technical Data

D7

109

A0

(Bottom View)

D8

V_CCD

BG

AA0/RAS0

AA1/RAS1

RD

GND_D

D9

D10

D11

D12

D13

D14

V_CCD

WR

GND_C

V_CCC

BB

BR

TA

BCLK

CLKOUT

GND_C

V_CCC

V_CCQL

GND_D

D15

D16

D17

D18

D19

V_CCQL

EXTAL

GND_Q

XTAL

GND_Q

D20

V_CCD

CAS

GND_D

D21

AA2/RAS2

AA3/RAS3

V_CCQH

D22

D23

GND_P1

GND_P

MODD/ IRQD

MODC/ IRQC

MODB/ IRQB

MODA/ IRQA

TRST

PCAP

V_CCP

RESET

HAD0

HAD1

HAD2

TDO

TDI

Orientation Mark

TCK

TMS

HAD3

GND_H

V_CCH

SC12

37

SC11

HAD4

1

AA1536

Figure 3-2. DSP56309 Thin Quad Flat Pack (TQFP), Bottom View

DSP56309 Technical Data

3-3

DSP56309 TQFP Signal Identification by Pin Number

No.

Signal Name

SRD1 or PD4

Signal Name

AA2/RAS2

1

26

GND_S

TIO2

TIO1

TIO0

51

2

STD1 or PD5

SC02 or PC2

SC01 or PC1

DE

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

CAS

3

XTAL

GND_Q

EXTAL

V_CCQL

V_CCC

GND_C

CLKOUT

BCLK

TA

4

5

HCS/HCS, HA10, or PB13

HA2, HA9, or PB10

HA1, HA8, or PB9

HA0, HAS/HAS, or PB8

H7, HAD7, or PB7

H6, HAD6, or PB6

H5, HAD5, or PB5

H4, HAD4, or PB4

V_CCH

6

PINIT/NMI

SRD0 or PC4

V_CCS

7

8

9

GND_S

10

11

12

13

14

15

16

17

18

19

20

21

STD0 or PC5

SC10 or PD0

SC00 or PC0

RXD or PE0

TXD or PE1

SCLK or PE2

SCK1 or PD3

SCK0 or PC3

V_CCQL

BR

GND_H

BB

H3, HAD3, or PB3

H2, HAD2, or PB2

H1, HAD1, or PB1

H0, HAD0, or PB0

RESET

V_CCC

GND_C

WR

RD

GND_Q

AA1/RAS1

AA0/RAS0

BG

V_CCQH

V_CCP

HDS/HDS, HWR/HWR, or

PB12

PCAP

22

23

HRW, HRD/HRD, or PB11

47

48

GND_P

72

73

A0

A1

HACK/HACK,

GND_P1

HRRQ/HRRQ, or PB15

24

25

HREQ/HREQ,

HTRQ/HTRQ, or PB14

49

50

V_CCQH

74

75

V_CCA

V_CCS

AA3/RAS3

GND_A

3-4

DSP56309 Technical Data

DSP56309 TQFP Signal Identification by Pin Number (Continued)

No.

Signal Name

76

A2

99

A17

122 D16

123 D17

124 D18

125 D19

126 V_CCQL

127 GND_Q

128 D20

129 V_CCD

130 GND_D

131 D21

132 D22

133 D23

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

A3

100 D0

A4

101 D1

A5

102 D2

V_CCA

GND_A

A6

103 V_CCD

104 GND_D

105 D3

A7

106 D4

A8

107 D5

A9

108 D6

V_CCA

GND_A

A10

A11

GND_Q

V_CCQL

A12

A13

A14

V_CCQH

GND_A

A15

A16

109 D7

110 D8

111 V_CCD

112 GND_D

113 D9

134 MODD/IRQD

135 MODC/IRQC

136 MODB/IRQB

137 MODA/IRQA

138 TRST

114 D10

115 D11

116 D12

117 D13

118 D14

119 V_CCD

120 GND_D

121 D15

139 TDO

140 TDI

141 TCK

142 TMS

143 SC12 or PD2

144 SC11 or PD1

Note: Signal names are based on configured functionality. Most pins supply a single signal. Some pins

provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating

mode after RESET is deasserted, but act as interrupt lines during operation. Some signals have

configurable polarity; these names are shown with and without overbars, such as HAS/HAS.

Some pins have two or more configurable functions; names assigned to these pins indicate the

function for a specific configuration. For example, pin 34 is data line H7 in non-multiplexed bus

mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO

function is enabled for this pin.

DSP56309 Technical Data

3-5

DSP56309 TQFP Signal Identification by Name

No.

Signal Name

A0

A1

72

73

88

89

92

93

94

97

98

99

76

77

78

79

82

83

84

85

70

69

51

50

64

60

61

BG

BR

71

D7

109

110

113

5

63

D8

A10

A11

A12

A13

A14

A15

A16

A17

A2

CAS

CLKOUT

D0

52

D9

59

DE

100

101

114

115

116

117

118

121

122

123

124

125

102

128

131

132

133

105

106

107

108

EXTAL

GND_A

GND_C

GND_D

GND_H

GND_P

GND_P1

GND_Q

GND_S

H0

55

D1

75

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

81

87

96

58

66

A3

104

112

120

130

39

A4

A5

A6

A7

A8

47

A9

D20

D21

D22

D23

D3

48

AA0

AA1

AA2

AA3

BB

19

54

90

127

9

D4

BCLK

D5

26

D6

43

3-6

DSP56309 Technical Data

DSP56309 TQFP Signal Identification by Name (Continued)

No.

Signal Name

H1

H2

42

41

40

37

36

35

34

33

32

30

31

32

31

23

43

42

41

40

37

36

35

34

33

30

21

HRD/HRD

HREQ/HREQ

HRRQ/HRRQ

HRW

22

24

PB4

PB5

PB6

PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

PE1

PE2

PINIT

RAS0

RAS1

37

36

35

34

33

32

12

4

H3

23

H4

22

H5

HTRQ/HTRQ

HWR/HWR

IRQA

24

H6

21

H7

137

136

135

134

137

136

135

134

6

HA0

IRQB

HA1

IRQC

3

HA10

HA2

IRQD

17

7

MODA

MODB

MODC

MODD

NMI

HA8

10

46

11

144

143

16

1

HA9

HACK/HACK

HAD0

HAD1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAS

PB0

43

PB1

42

PB10

31

PB11

22

2

PB12

21

13

14

15

6

PB13

30

PB14

24

PB15

23

HCS/HCS

HDS/HDS

PB2

41

70

69

PB3

40

DSP56309 Technical Data

3-7

DSP56309 TQFP Signal Identification by Name (Continued)

No.

Signal Name

RAS2

RAS3

RD

51

50

68

44

13

12

4

STD1

TA

2

V_CCD

V_CCH

V_CCP

111

119

129

38

45

20

49

95

18

56

91

126

8

62

TCK

141

140

139

29

RESET

RXD

TDI

TDO

TIO0

TIO1

TIO2

TMS

TRST

TXD

V_CCA

V_CCC

V_CCD

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

V_CCQH

V_CCQL

V_CCS

28

3

27

11

144

143

17

16

15

7

142

138

14

74

80

86

V_CCS

25

67

53

57

WR

1

65

XTAL

10

103

3-8

DSP56309 Technical Data

TQFP Package Mechanical Drawing

0.20 T L-M N

4X

4X 36 TIPS

109

PIN 1

IDENT

144

1

108

4X

P

J1

M

L

C

L

V

B

X

X=L, M, OR N

140X

G

B1

V1

VIEW Y

36

73

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DATUMS L, M AND N TO BE

DETERMINED AT THE SEATING PLANE,

DATUM T.

4. DIMENSIONS S AND V TO BE

DETERMINED AT SEATING PLANE,

DATUM T.

5. DIMENSIONS A AND B DO NOT

INCULDE MOLD PROTRUSION.

ALLOWABLE PROTRUSION IS 0.25 PER

SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE H.

6. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLED

37

72

N

A1

S1

A

S

VIEW AB

C

144X

0.1 T

θ2

MILLIMETERS

MIN

MAX

DIM

A

A1

B

B1

C

SEATING

PLANE

20.00 BSC

10.00 BSC

20.00 BSC

10.00 BSC

T

1.40

C1 0.05

C2 1.35

1.60

0.15

1.45

0.27

0.75

0.23

PLATING

D

E

F

0.17

0.45

0.17

J

C2

AA

F

— 0.05

G

J

0.50 BSC

R2

0.09

0.20

θ

K

P

0.50 REF

0.25 BSC

R1

R1 0.13

R2 0.13

0.20

S

S1

V

V1

Y

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

0.25 REF

1.00 REF

BASE

METAL

0.25

GAGE PLANE

D

M

0.08

T L-M N

Z

SECTION J1-J1

(ROTATED 90)

144 PL

(K)

E

AA 0.09

θ

θ1

θ2

0.16

C1

0°

7°

θ 1

(Y)

VIEW AB

11°

13°

(Z)

CASE 918-03

ISSUE C

Figure 3-3. DSP56309 Mechanical Information, 144-pin TQFP Package

DSP56309 Technical Data

3-9

MAP-BGA Package Description

Top and bottom views of the MAP-BGA package are shown in Figure 3-4. and Figure 3-5. with their

pin-outs.

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

NC

SC11

TMS

TDO

MODB

D23

V

D19

D16

D14

D11

D9

D7

NC

CCD

SRD1

SC02

PINIT

STD0

RXD

SC12

STD1

SC01

TDI

TCK

TRST MODD

MODA MODC

D21

D22

D20

D17

D18

D15

D13

D12

D10

D8

D6

D5

D3

NC

D4

V

CCD

C

CCQL

CCD

DE

GND

PB0

GND

EXTAL

CAS

XTAL

GND

BCLK

TA

GND

D1

D2

V

D

E

F

CCD

V

SRD0

SC00

TXD

GND

WR

BR

A17

A16

A14

D0

CCS

SC10

SCLK

V

A15

A12

A11

A9

CCQH

A13

G

SCK1

V

CCQL

V

SCK0

HDS

V

A10

H

J

CCQH

CCQL

CCA

HACK HRW

A8

A7

A5

A3

A1

K

V

HREQ TIO2

V

A6

CCS

CCA

HCS

HA1

H6

TIO1

HA2

H7

TIO0

HA0

H4

V

A4

L

CLK

OUT

V

M

V

RD

A2

CCQH

AA3

CCH

CCP

N

P

H2

H1

RESET GND

V

AA0

BG

A0

P

CCQL

CCC

NC

H5

H3

PCAP

GND

AA2

V

BB

AA1

NC

P1

CCC

AA1528

Figure 3-4. DSP56309 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

3-10

DSP56309 Technical Data

Bottom View

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

NC

D7

D9

D11

D14

D16

D19

V

D23

MODB

TDO

TMS

SC11

NC

CCD

NC

D4

D5

D3

D8

D6

D10

D13

D12

D15

D17

D18

D20

D21

D22

MODD TRST

TDI

SC12

STD1

SC01

SRD1

SC02

PINIT

STD0

RXD

V

MODC MODA TCK

C

CCD

CCQL

V

D2

D1

GND

BCLK

TA

GND

EXTAL

CAS

XTAL

GND

PB0

GND

DE

SRD0

SC00

TXD

SCK0

HDS

TIO2

TIO0

HA0

H4

D

E

F

CCD

D0

A16

A14

A17

GND

WR

BR

GND

NC

V

CCS

A15

A12

A11

A9

V

SC10

SCLK

CCQH

A13

G

V

SCK1

CCQL

V

A10

V

H

J

CCQH

CCA

CCQL

A7

A5

A3

A1

A8

HRW

HACK

K

A6

V

HREQ

TIO1

HA2

H7

V

CCS

CCA

A4

V

HCS

HA1

H6

L

CLK

OUT

M

A2

RD

V

CCP

CCH

N

P

A0

AA0

BG

V

AA3

AA2

GND

RESET

PCAP

H2

CCC

CCQL

P

NC

AA1

BB

V

GND

H1

H3

H5

NC

CCC

P1

AA1529

Figure 3-5. DSP56309 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

DSP56309 Technical Data

3-11

DSP56309 MAP-BGA Signal Identification by Pin Number

No.

Signal Name

A1

Not Connected (NC),

reserved

B12

D8

D9

GND

A2

SC11 or PD1

TMS

B13

B14

C1

C2

C3

C4

C5

C6

C7

C8

C9

D5

D10 GND

D11 GND

D12 D1

A3

NC

A4

TDO

SC02 or PC2

STD1 or PD5

TCK

A5

MODB/IRQB

D23

D13 D2

A6

D14 V_CCD

A7

V_CCD

MODA/IRQA

MODC/IRQC

D22

E1

STD0 or PC5

V_CCS

A8

D19

E2

A9

D16

E3

SRD0 or PC4

GND

A10

A11

A12

A13

A14

B1

D14

V_CCQL

E4

D11

D18

E5

GND

D9

V_CCD

E6

GND

D7

C10 D12

C11 V_CCD

C12 D6

C13 D3

C14 D4

E7

GND

NC

E8

GND

SRD1 or PD4

SC12 or PD2

TDI

E9

GND

B2

E10

E11

E12

E13

E14

F1

GND

B3

GND

B4

TRST

MODD/IRQD

D21

D1

D2

D3

D4

D5

D6

D7

D8

PINIT/NMI

A17

B5

SC01 or PC1

DE

A16

B6

D0

B7

D20

GND

RXD or PE0

SC10 or PD0

SC00 or PC0

GND

B8

D17

GND

F2

B9

D15

GND

F3

B10

B11

D13

GND

F4

D10

GND

F5

GND

3-12

DSP56309 Technical Data

DSP56309 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

SCK0 or PC3

Signal Name

F6

GND

H3

J14

A9

F7

F8

H4

H5

GND

K1

K2

V_CCS

HREQ/HREQ,

HTRQ/HTRQ, or PB14

F9

GND

V_CCQH

A14

H6

H7

H8

H9

GND

K3

TIO2

GND

V_CCA

F10

F11

F12

F13

F14

G1

K4

K5

K6

H10 GND

H11 GND

H12 V_CCA

H13 A10

H14 A11

K7

A15

K8

SCK1 or PD3

SCLK or PE2

TXD or PE1

GND

K9

G2

K10

K11

K12

G3

G4

J1

HACK/HACK,

HRRQ/HRRQ, or PB15

G5

G6

GND

J2

J3

HRW, HRD/HRD, or PB11

K13

K14

A5

A6

HDS/HDS, HWR/HWR, or

PB12

G7

G8

G9

GND

J4

GND

A8

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

HCS/HCS, HA10, or PB13

J5

TIO1

TIO0

GND

J6

G10 GND

G11 GND

G12 A13

G13 V_CCQL

G14 A12

J7

J8

J9

J10

J11

J12

J13

H1

H2

V_CCQH

V_CCQL

A7

DSP56309 Technical Data

3-13

DSP56309 MAP-BGA Signal Identification by Pin Number (Continued)

No.

Signal Name

L11

GND

V_CCA

A3

M13 A1

M14 A2

P1

NC

L12

L13

L14

M1

M2

M3

M4

M5

M6

M7

M8

M9

P2

H5, HAD5, or PB5

N1

N2

N3

N4

N5

N6

N7

N8

N9

H6, HAD6, or PB6

H7, HAD7, or PB7

P3

H3, HAD3, or PB3

A4

P4

H1, HAD1, or PB1

PCAP

HA1, HA8, or PB9

HA2, HA9, or PB10

HA0, HAS/HAS, or PB8

V_CCH

H4, HAD4, or PB4

H2, HAD2, or PB2

RESET

P5

P6

GND_P1

AA2/RAS2

XTAL

P7

GND_P

P8

H0, HAD0, or PB0

V_CCP

AA3/RAS3

CAS

P9

V_CCC

P10

P11

P12

P13

P14

TA

V_CCQH

V_CCQL

BB

EXTAL

N10 BCLK

N11 BR

AA1/RAS1

BG

CLKOUT

M10 BCLK

M11 WR

M12 RD

N12 V_CCC

N13 AA0/RAS0

N14 A0

NC

Note: Signal names are based on configured functionality. Most connections supply a single signal.

Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that

select an operating mode after RESET is deasserted, but act as interrupt lines during operation.

Some signals have configurable polarity; these names are shown with and without overbars,

such as HAS/HAS. Some connections have two or more configurable functions; names assigned

to these connections indicate the function for a specific configuration. For example, connection

N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus

mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike the TQFP

package, most of the GND pins are connected internally in the center of the connection array and

act as heat sink for the chip. Therefore, except for GND_Pand GND_P1that support the PLL, other

GND signals do not support individual subsystems in the chip.

3-14

DSP56309 Technical Data

DSP56309 MAP-BGA Signal Identification by Name

No.

Signal Name

A0

A1

N14

M13

H13

H14

G14

G12

F13

F14

E13

E12

M14

L13

L14

K13

K14

J13

J12

J14

N13

P12

P7

BG

BR

P13

N11

N8

D7

D8

A13

B12

A12

D3

M8

D4

D5

D6

D7

D8

D9

D10

D11

E4

A10

A11

A12

A13

A14

A15

A16

A17

A2

CAS

CLKOUT

D0

D9

M9

DE

E14

D12

B11

A11

C10

B10

A10

B9

EXTAL

GND

D1

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

A3

A4

A9

A5

B8

A6

C8

E5

A7

A8

E6

A8

D13

B7

E7

A9

D20

D21

D22

D23

D3

E8

AA0

AA1

AA2

AA3

BB

B6

E9

C6

E10

E11

F4

A6

N7

C13

C14

B13

C12

P11

M10

N10

D4

F5

BCLK

D5

F6

D6

F7

DSP56309 Technical Data

3-15

DSP56309 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

GND

F8

F9

GND

GND_P

GND_P1

H0

J9

J10

J11

K4

K5

K6

K7

K8

K9

K10

K11

L4

H4

H5

N3

P2

N1

N2

M3

M1

L1

F10

F11

G4

G5

G6

G7

G8

G9

G10

G11

H4

H5

H6

H7

H8

H9

H10

H11

J4

H6

H7

HA0

HA1

HA10

HA2

M2

M1

M2

J1

HA8

HA9

HACK/HACK

HAD0

M5

P4

N4

P3

N3

P2

N1

N2

M3

L1

L5

HAD1

L6

HAD2

L7

HAD3

L8

HAD4

L9

HAD5

L10

L11

N6

P6

M5

P4

N4

P3

HAD6

HAD7

HAS/HAS

HCS/HCS

HDS/HDS

HRD/HRD

HREQ/HREQ

HRRQ/HRRQ

J5

J3

J6

H1

J2

J7

H2

K2

J1

J8

H3

3-16

DSP56309 Technical Data

DSP56309 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

HRW

HTRQ/HTRQ

HWR/HWR

IRQA

IRQB

IRQC

IRQD

MODA

MODB

MODC

MODD

NC

J2

K2

J3

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC0

PC1

PC2

PC3

PC4

PC5

PCAP

PD0

PD1

PD2

PD3

PD4

PD5

PE0

PE1

PE2

PINIT

N4

P3

N3

P2

N1

N2

M3

M1

F3

D2

C1

H3

E3

E1

P5

F2

A2

B2

G1

B1

C2

F1

G3

G2

D1

RAS0

RAS1

RAS2

RAS3

RD

N13

P12

P7

N7

M12

N5

F1

C4

A5

C5

B5

C4

A5

C5

B5

A1

A14

B14

P1

P14

D1

M5

P4

M2

J2

RESET

RXD

SC00

SC01

SC02

SC10

SC11

SC12

SCK0

SCK1

SCLK

SRD0

SRD1

STD0

STD1

TA

F3

D2

C1

F2

A2

B2

H3

G1

G2

E3

B1

E1

C2

P10

C3

B3

A4

L3

NC

NMI

PB0

PB1

PB10

PB11

PB12

PB13

PB14

PB15

J3

TCK

L1

TDI

K2

J1

TDO

TIO0

DSP56309 Technical Data

3-17

DSP56309 MAP-BGA Signal Identification by Name (Continued)

No.

Signal Name

TIO1

TIO2

TMS

TRST

TXD

L2

K3

V_CCC

V_CCD

V_CCH

V_CCP

V_CCQH

P9

A7

V_CCQH

V_CCQL

V_CCS

M7

C7

A3

C9

G13

H2

B4

C11

D14

M4

M6

F12

H1

G3

N9

V_CCA

V_CCC

H12

K12

L12

N12

E2

V_CCS

K1

WR

M11

P8

XTAL

3-18

DSP56309 Technical Data

MAP-BGA Package Mechanical Drawing

Figure 3-6. DSP56309 Mechanical Information, 196-pin MAP-BGA Package

DSP56309 Technical Data

3-19

3-20

DSP56309 Technical Data

SECTION 4

Design Considerations

THERMAL DESIGN CONSIDERATIONS

An estimation of the chip junction temperature, T , in °C can be obtained from this equation:

J

Equation 1: T_J= T_A+ (P_D× R_θJA

Where:

)

T

R

=

ambient temperature °C

package junction-to-ambient thermal resistance °C/W

power dissipation in package

A

θJA

P

D

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and

a case-to-ambient thermal resistance:

Equation 2: R_θJA= R_θJC+ R_θCA

Where:

R

=

package junction-to-ambient thermal resistance °C/W

package junction-to-case thermal resistance °C/W

package case-to-ambient thermal resistance °C/W

θJA

θJC

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or

otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This

model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated

through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations

where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of

the device thermal performance may need the additional modeling capability of a system level thermal

simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which

the package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether

θJA

the thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common ways for determining the junction-to-case thermal

resistance in plastic packages:

DSP56309 Technical Data

4-1

•

To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that

surface has a proper heat sink.

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

If the temperature of the package case (T ) is determined by a thermocouple, the thermal

T

resistance is computed using the value obtained by the equation (T – T )/P .

J

T

D

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the

first definition. From a practical standpoint, that value is also suitable for determining the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading

on the case of the package will estimate a junction temperature slightly hotter than actual temperature.

Hence, the new thermal metric, thermal characterization parameter or Ψ , has been defined to be (T –

JT

J

T )/P . This value gives a better estimate of the junction temperature in natural convection when using the

T

D

surface temperature of the package. Remember that surface temperature readings of packages are subject

to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by

heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to

the top center of the package with thermally conductive epoxy.

ELECTRICAL DESIGN CONSIDERATIONS

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (for example, either GND or V ).

CC

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each V_CCpin on the DSP and from

the board ground to each GND pin.

•

Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of

the package to connect the V_CCpower source to GND.

4-2

DSP56309 Technical Data

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and

CC

GND pins are less than 0.5 in per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for V_CCand GND.

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB,

IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are

recommended.

•

Consider all device loads and parasitic capacitance due to PCB traces when calculating

capacitance. This is especially critical in systems with higher capacitive loads that could create

higher transient currents in the V_CCand GND circuits.

All inputs must be terminated (that is, not allowed to float) using CMOS levels, except for the

three pins with internal pull-up resistors (TRST, TMS, DE).

•

Take special care to minimize noise levels on V_CCP, GND_P, and GND_P1pins.

The following pins must be asserted after power-up: RESET and TRST.

If multiple DSP56309 devices are on the same board, check for cross-talk or excessive spikes on

the supplies due to synchronous operation of the devices.

•

RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied

before deassertion of RESET.

The Port A data bus (D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to

maintain the last output value even when the internal signal is tri-stated. Typically, no pull-up or

pull-down resistors should be used with these signal lines. However, if the DSP is connected to a

device that requires pull-up resistors (such as an MPC8260), the recommended resistor value is 10

KΩ or less. If more than one DSP must be connected in parallel to the other device, the pull-up

resistor value requirement changes as follows:

— 2 DSPs = 5 KΩ or less

— 3 DSPs = 3 KΩ or less

— 4 DSPs = 2 KΩ or less

— 5 DSPs = 1.5 KΩ or less

— 6 DSPs = 1 KΩ or less

POWER CONSUMPTION CONSIDERATIONS

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current

consumption are described in this section. Most of the current consumed by CMOS devices is alternating

current (ac), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by this equation:

Equation 3: I = C × V × f

Where:

DSP56309 Technical Data

4-3

C

=

node/pin capacitance

V = voltage swing

frequency of node/pin toggle

f

=

4-4

DSP56309 Technical Data

Example 4-1. Current Consumption

For a port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 66 MHz clock, toggling at

its maximum possible rate (33 MHz), the current consumption is given by this equation:

Equation 4: I = 50 × 10^–12× 3.3 × 33 × 10⁶= 5.48 mA

The maximum internal current (I max) value reflects the typical possible switching of the internal buses

CCI

on best-case operation conditions, which is not necessarily a real application case. The typical internal

current (I

) value reflects the average switching of the internal buses on typical operating conditions.

CCItyp

For applications that require very low current consumption, do the following:

•

Set the EBD bit when not accessing external memory.

Minimize external memory accesses, and use internal memory accesses.

Minimize the number of pins that are switching.

Minimize the capacitive load on the pins.

Connect the unused inputs to pull-up or pull-down resistors.

Disable unused peripherals.

Disable unused pin activity (for example, CLKOUT and XTAL).

One way to evaluate power consumption is to use a current per MIPS measurement methodology to

minimize specific board effects (that is, to compensate for measured board current not caused by the DSP).

A benchmark power consumption test algorithm is listed in Appendix A of the DSP56309 User’s Manual.

Use the test algorithm, specific test current measurements, and the following equation to derive the current

per MIPS value:

Equation 5: I ⁄ MIPS = I ⁄ MHz = (I_typF2– I_typF1) ⁄ (F2 – F1)

where:

I

F2

F1

=

current at F2

current at F1

typF2

typF1

high frequency (any specified operating frequency)

low frequency (any specified operating frequency less than F2)

Note:

F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33

MHz. The degree of difference between F1 and F2 determines the amount of precision with which

the current rating can be determined for an application.

DSP56309 Technical Data

4-5

PLL PERFORMANCE ISSUES

The following explanations should be considered as general observations on expected PLL behavior.

There is no testing that verifies these exact numbers. These observations were measured on a limited

number of parts and were not verified over the entire temperature and voltage ranges.

Phase Skew Performance

The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and

CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature, and voltage ranges.

As defined in Figure 2-2 on page 2-7, for input frequencies greater than 15 MHz and the MF ≤ 4, this

skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed.

However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2

ns.

Phase Jitter Performance

The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and

CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on

CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15

MHz and MF ≤ 4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF <

10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns.

Frequency Jitter Performance

The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF

(MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5%

and approximately 2%. For large MF (MF > 500), the frequency jitter is 2–3%.

Input (EXTAL) Jitter Requirements

The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is

slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency

of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can

be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the

prescribed values.

4-6

DSP56309 Technical Data

APPENDIX A

Power Consumption Benchmark

The following benchmark program permits evaluation of DSP power usage in a test situation. It enables

the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set

of synthetic DSP application data to emulate intensive sustained DSP operation.

DSP56309 Technical Data

A-1

;**********************************************************************

;*

*

;* CHECKS

;*

Typical Power Consumption

;**********************************************************************

page

nolist

200,55,0,0,0

I_VEC

equ

$000000

; Interrupt vectors for program debug only

; MAIN (external) program starting address

; INTERNAL program memory starting address

; INTERNAL X-data memory starting address

; INTERNAL Y-data memory starting address

START

$8000

$100

$0

INT_PROG

INT_XDAT

INT_YDAT

$0

INCLUDE "ioequ.asm"

INCLUDE "intequ.asm"

list

org

P:START

;

movep #$0123FF,x:M_BCR

; BCR: Area 3 : 1 w.s (SRAM)

;

Area 2 : 0 w.s (SSRAM)

Default: 1 w.s (SRAM)

movep

#$0d0000,x:M_PCTL

; XTAL disable

; PLL enable

; CLKOUT disable

; Load the program

;

move

do

move

nop

#INT_PROG,r0

#PROG_START,r1

#(PROG_END-PROG_START),PLOAD_LOOP

p:(r1)+,x0

x0,p:(r0)+

PLOAD_LOOP

;

; Load the X-data

;

move

do

move

#INT_XDAT,r0

#XDAT_START,r1

#(XDAT_END-XDAT_START),XLOAD_LOOP

p:(r1)+,x0

x0,x:(r0)+

XLOAD_LOOP

;

; Load the Y-data

;

move

do

move

#INT_YDAT,r0

#YDAT_START,r1

#(YDAT_END-YDAT_START),YLOAD_LOOP

p:(r1)+,x0

x0,y:(r0)+

YLOAD_LOOP

;

jmp

PROG_START

INT_PROG

move

#$0,r0

#$0,r4

#$3f,m0

#$3f,m4

move

;

clr

a

b

clr

move

bset

#$0,x0

#$0,x1

#$0,y0

#$0,y1

#4,omr

; ebd

;

sbr

dor

mac

#60,_end

x0,y0,a x:(r0)+,x1

x1,y1,a x:(r0)+,x0

y:(r4)+,y1

y:(r4)+,y0

A-2

DSP56309 Technical Data

add

mac

move

a,b

x0,y0,a x:(r0)+,x1

x1,y1,a

y:(r4)+,y0

b1,x:$ff

_end

bra

nop

sbr

PROG_END

nop

XDAT_START

org

;

x:0

dc

$262EB9

$86F2FE

$E56A5F

$616CAC

$8FFD75

$9210A

$A06D7B

$CEA798

$8DFBF1

$A063D6

$6C6657

$C2A544

$A3662D

$A4E762

$84F0F3

$E6F1B0

$B3829

$8BF7AE

$63A94F

$EF78DC

$242DE5

$A3E0BA

$EBAB6B

$8726C8

$CA361

$2F6E86

$A57347

$4BE774

$8F349D

$A1ED12

$4BFCE3

$EA26E0

$CD7D99

$4BA85E

$27A43F

$A8B10C

$D3A55

$25EC6A

$2A255B

$A5F1F8

$2426D1

$AE6536

$CBBC37

$6235A4

$37F0D

$63BEC2

$A5E4D3

$8CE810

$3FF09

$60E50E

$CFFB2F

$40753C

$8262C5

$CA641A

$EB3B4B

$2DA928

$AB6641

$28A7E6

$4E2127

$482FD4

$7257D

DSP56309 Technical Data

A-3

dc

$E53C72

$1A8C3

$E27540

XDAT_END

YDAT_START

;

org

y:0

$5B6DA

dc

$C3F70B

$6A39E8

$81E801

$C666A6

$46F8E7

$AAEC94

$24233D

$802732

$2E3C83

$A43E00

$C2B639

$85A47E

$ABFDDF

$F3A2C

$2D7CF5

$E16A8A

$ECB8FB

$4BED18

$43F371

$83A556

$E1E9D7

$ACA2C4

$8135AD

$2CE0E2

$8F2C73

$432730

$A87FA9

$4A292E

$A63CCF

$6BA65C

$E06D65

$1AA3A

$A1B6EB

$48AC48

$EF7AE1

$6E3006

$62F6C7

$6064F4

$87E41D

$CB2692

$2C3863

$C6BC60

$43A519

$6139DE

$ADF7BF

$4B3E8C

$6079D5

$E0F5EA

$8230DB

$A3B778

$2BFE51

$E0A6B6

$68FFB7

$28F324

$8F2E8D

$667842

$83E053

$A1FD90

$6B2689

$85B68E

$622EAF

$6162BC

$E4A245

YDAT_END

>

;**************************************************************************

;

EQUATES for DSP56309 I/O registers and ports

Last update: June 11 1995

A-4

DSP56309 Technical Data

;

;**************************************************************************

page

opt

132,55,0,0,0

mex

ioequ

ident

1,0

;------------------------------------------------------------------------

;

EQUATES for I/O Port Programming

;------------------------------------------------------------------------

;

Register Addresses

M_HDR EQU $FFFFC9; Host port GPIO data Register

M_HDDR EQU $FFFFC8; Host port GPIO direction Register

M_PCRC EQU $FFFFBF; Port C Control Register

M_PRRC EQU $FFFFBE

M_PDRC EQU $FFFFBD

M_PCRD EQU $FFFFAF

M_PRRD EQU $FFFFAE

M_PDRD EQU $FFFFAD

M_PCRE EQU $FFFF9F

M_PRRE EQU $FFFF9E

M_PDRE EQU $FFFF9D

M_OGDB EQU $FFFFFC

; Port C Direction Register

; Port C GPIO Data Register

; Port D Control register

; Port D Direction Data Register

; Port D GPIO Data Register

; Port E Control register

; Port E Direction Register

; Port E Data Register

; OnCE GDB Register

;------------------------------------------------------------------------

;

EQUATES for Host Interface

;------------------------------------------------------------------------

;

Register Addresses

M_HCR EQU $FFFFC2

M_HSR EQU $FFFFC3

M_HPCR EQU $FFFFC4

M_HBAR EQU $FFFFC5

M_HRX EQU $FFFFC6

M_HTX EQU $FFFFC7

; Host Control Register

; Host Status Rgister

; Host Polarity Control Register

; Host Base Address Register

; Host Receive Register

; Host Transmit Register

;

HCR bits definition

M_HRIE EQU $0

M_HTIE EQU $1

M_HCIE EQU $2

M_HF2 EQU $3

M_HF3 EQU $4

; Host Receive interrupts Enable

; Host Transmit Interrupt Enable

; Host Command Interrupt Enable

; Host Flag 2

; Host Flag 3

;

HSR bits definition

M_HRDF EQU $0

M_HTDE EQU $1

M_HCP EQU $2

M_HF0 EQU $3

M_HF1 EQU $4

; Host Receive Data Full

; Host Receive Data Emptiy

; Host Command Pending

; Host Flag 0

; Host Flag 1

;

HPCR bits definition

M_HGEN EQU $0

M_HA8EN EQU $1

M_HA9EN EQU $2

M_HCSEN EQU $3

M_HREN EQU $4

M_HAEN EQU $5

M_HEN EQU $6

M_HOD EQU $8

M_HDSP EQU $9

M_HASP EQU $A

M_HMUX EQU $B

M_HD_HS EQU $C

M_HCSP EQU $D

M_HRP EQU $E

M_HAP EQU $F

; Host Port GPIO Enable

; Host Address 8 Enable

; Host Address 9 Enable

; Host Chip Select Enable

; Host Request Enable

; Host Acknowledge Enable

; Host Enable

; Host Request Open Drain mode

; Host Data Strobe Polarity

; Host Address Strobe Polarity

; Host Multiplexed bus select

; Host Double/Single Strobe select

; Host Chip Select Polarity

; Host Request PolarityPolarity

; Host Acknowledge Polarity

DSP56309 Technical Data

A-5

;------------------------------------------------------------------------

;

EQUATES for Serial Communications Interface (SCI)

;------------------------------------------------------------------------

;

Register Addresses

M_STXH EQU $FFFF97

M_STXM EQU $FFFF96

M_STXL EQU $FFFF95

M_SRXH EQU $FFFF9A

M_SRXM EQU $FFFF99

M_SRXL EQU $FFFF98

M_STXA EQU $FFFF94

M_SCR EQU $FFFF9C

M_SSR EQU $FFFF93

M_SCCR EQU $FFFF9B

; SCI Transmit Data Register (high)

; SCI Transmit Data Register (middle)

; SCI Transmit Data Register (low)

; SCI Receive Data Register (high)

; SCI Receive Data Register (middle)

; SCI Receive Data Register (low)

; SCI Transmit Address Register

; SCI Control Register

; SCI Status Register

; SCI Clock Control Register

;

SCI Control Register Bit Flags

M_WDS EQU $7

M_WDS0 EQU 0

M_WDS1 EQU 1

M_WDS2 EQU 2

M_SSFTD EQU 3

M_SBK EQU 4

; Word Select Mask (WDS0-WDS3)

; Word Select 0

; Word Select 1

; Word Select 2

; SCI Shift Direction

; Send Break

M_WAKE EQU 5

M_RWU EQU 6

; Wakeup Mode Select

; Receiver Wakeup Enable

; Wired-OR Mode Select

; SCI Receiver Enable

; SCI Transmitter Enable

; Idle Line Interrupt Enable

; SCI Receive Interrupt Enable

; SCI Transmit Interrupt Enable

; Timer Interrupt Enable

; Timer Interrupt Rate

; SCI Clock Polarity

M_WOMS EQU 7

M_SCRE EQU 8

M_SCTE EQU 9

M_ILIE EQU 10

M_SCRIE EQU 11

M_SCTIE EQU 12

M_TMIE EQU 13

M_TIR EQU 14

M_SCKP EQU 15

M_REIE EQU 16

; SCI Error Interrupt Enable (REIE)

;

SCI Status Register Bit Flags

M_TRNE EQU 0

M_TDRE EQU 1

M_RDRF EQU 2

M_IDLE EQU 3

M_OR EQU 4

; Transmitter Empty

; Transmit Data Register Empty

; Receive Data Register Full

; Idle Line Flag

; Overrun Error Flag

M_PE EQU 5

; Parity Error

M_FE EQU 6

M_R8 EQU 7

; Framing Error Flag

; Received Bit 8 (R8) Address

;

r

SCI Clock Control Registe

M_CD EQU $FFF

M_COD EQU 12

M_SCP EQU 13

M_RCM EQU 14

M_TCM EQU 15

; Clock Divider Mask (CD0-CD11)

; Clock Out Divider

; Clock Prescaler

; Receive Clock Mode Source Bit

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

EQUATES for Synchronous Serial Interface (SSI)

;------------------------------------------------------------------------

;

Register Addresses Of SSI0

M_TX00 EQU $FFFFBC

M_TX01 EQU $FFFFBB

M_TX02 EQU $FFFFBA

M_TSR0 EQU $FFFFB9

M_RX0 EQU $FFFFB8

M_SSISR0 EQU $FFFFB7

M_CRB0 EQU $FFFFB6

M_CRA0 EQU $FFFFB5

M_TSMA0 EQU $FFFFB4

M_TSMB0 EQU $FFFFB3

; SSI0 Transmit Data Register 0

; SSIO Transmit Data Register 1

; SSIO Transmit Data Register 2

; SSI0 Time Slot Register

; SSI0 Receive Data Register

; SSI0 Status Register

; SSI0 Control Register B

; SSI0 Control Register A

; SSI0 Transmit Slot Mask Register A

; SSI0 Transmit Slot Mask Register B

A-6

DSP56309 Technical Data

M_RSMA0 EQU $FFFFB2

M_RSMB0 EQU $FFFFB1

; SSI0 Receive Slot Mask Register A

; SSI0 Receive Slot Mask Register B

;

Register Addresses Of SSI1

M_TX10 EQU $FFFFAC

M_TX11 EQU $FFFFAB

M_TX12 EQU $FFFFAA

M_TSR1 EQU $FFFFA9

M_RX1 EQU $FFFFA8

M_SSISR1 EQU $FFFFA7

M_CRB1 EQU $FFFFA6

M_CRA1 EQU $FFFFA5

M_TSMA1 EQU $FFFFA4

M_TSMB1 EQU $FFFFA3

M_RSMA1 EQU $FFFFA2

M_RSMB1 EQU $FFFFA1

; SSI1 Transmit Data Register 0

; SSI1 Transmit Data Register 1

; SSI1 Transmit Data Register 2

; SSI1 Time Slot Register

; SSI1 Receive Data Register

; SSI1 Status Register

; SSI1 Control Register B

; SSI1 Control Register A

; SSI1 Transmit Slot Mask Register A

; SSI1 Transmit Slot Mask Register B

; SSI1 Receive Slot Mask Register A

; SSI1 Receive Slot Mask Register B

;

SSI Control Register A Bit Flags

M_PM EQU $FF

; Prescale Modulus Select Mask (PM0-PM7)

; Prescaler Range

M_PSR EQU 11

M_DC EQU $1F000

M_ALC EQU 18

M_WL EQU $380000

M_SSC1 EQU 22

; Frame Rate Divider Control Mask (DC0-DC7)

; Alignment Control (ALC)

; Word Length Control Mask (WL0-WL7)

; Select SC1 as TR #0 drive enable (SSC1)

;

SSI Control Register B Bit Flags

M_OF EQU $3

; Serial Output Flag Mask

; Serial Output Flag 0

; Serial Output Flag 1

M_OF0 EQU 0

M_OF1 EQU 1

M_SCD EQU $1C

M_SCD0 EQU 2

M_SCD1 EQU 3

M_SCD2 EQU 4

M_SCKD EQU 5

M_SHFD EQU 6

M_FSL EQU $180

M_FSL0 EQU 7

M_FSL1 EQU 8

M_FSR EQU 9

M_FSP EQU 10

M_CKP EQU 11

M_SYN EQU 12

M_MOD EQU 13

M_SSTE EQU $1C000

M_SSTE2 EQU 14

M_SSTE1 EQU 15

M_SSTE0 EQU 16

M_SSRE EQU 17

M_SSTIE EQU 18

M_SSRIE EQU 19

M_STLIE EQU 20

M_SRLIE EQU 21

M_STEIE EQU 22

M_SREIE EQU 23

; Serial Control Direction Mask

; Serial Control 0 Direction

; Serial Control 1 Direction

; Serial Control 2 Direction

; Clock Source Direction

; Shift Direction

; Frame Sync Length Mask (FSL0-FSL1)

; Frame Sync Length 0

; Frame Sync Length 1

; Frame Sync Relative Timing

; Frame Sync Polarity

; Clock Polarity

; Sync/Async Control

; SSI Mode Select

; SSI Transmit enable Mask

; SSI Transmit #2 Enable

; SSI Transmit #1 Enable

; SSI Transmit #0 Enable

; SSI Receive Enable

; SSI Transmit Interrupt Enable

; SSI Receive Interrupt Enable

; SSI Transmit Last Slot Interrupt Enable

; SSI Receive Last Slot Interrupt Enable

; SSI Transmit Error Interrupt Enable

; SI Receive Error Interrupt Enable

;

SSI Status Register Bit Flags

M_IF EQU $3

M_IF0 EQU 0

M_IF1 EQU 1

M_TFS EQU 2

M_RFS EQU 3

M_TUE EQU 4

M_ROE EQU 5

M_TDE EQU 6

M_RDF EQU 7

; Serial Input Flag Mask

; Serial Input Flag 0

; Serial Input Flag 1

; Transmit Frame Sync Flag

; Receive Frame Sync Flag

; Transmitter Underrun Error FLag

; Receiver Overrun Error Flag

; Transmit Data Register Empty

; Receive Data Register Full

;

SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF

; SSI Transmit Slot Bits Mask A (TS0-TS15)

;

SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF

; SSI Transmit Slot Bits Mask B (TS16-TS31)

;

SSI Receive Slot Mask Register A

DSP56309 Technical Data

A-7

M_SSRSA EQU $FFFF

; SSI Receive Slot Bits Mask A (RS0-RS15)

; SSI Receive Slot Bits Mask B (RS16-RS31)

;

SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF

;------------------------------------------------------------------------

;

EQUATES for Exception Processing

;------------------------------------------------------------------------

;

Register Addresses

M_IPRC EQU $FFFFFF

M_IPRP EQU $FFFFFE

; Interrupt Priority Register Core

; Interrupt Priority Register Peripheral

;

Interrupt Priority Register Core (IPRC)

M_IAL EQU $7

; IRQA Mode Mask

M_IAL0 EQU 0

; IRQA Mode Interrupt Priority Level (low)

; IRQA Mode Interrupt Priority Level (high)

; IRQA Mode Trigger Mode

M_IAL1 EQU 1

M_IAL2 EQU 2

M_IBL EQU $38

M_IBL0 EQU 3

; IRQB Mode Mask

; IRQB Mode Interrupt Priority Level (low)

; IRQB Mode Interrupt Priority Level (high)

; IRQB Mode Trigger Mode

M_IBL1 EQU 4

M_IBL2 EQU 5

M_ICL EQU $1C0

M_ICL0 EQU 6

; IRQC Mode Mask

; IRQC Mode Interrupt Priority Level (low)

; IRQC Mode Interrupt Priority Level (high)

; IRQC Mode Trigger Mode

M_ICL1 EQU 7

M_ICL2 EQU 8

M_IDL EQU $E00

M_IDL0 EQU 9

; IRQD Mode Mask

; IRQD Mode Interrupt Priority Level (low)

; IRQD Mode Interrupt Priority Level (high)

; IRQD Mode Trigger Mode

M_IDL1 EQU 10

M_IDL2 EQU 11

M_D0L EQU $3000

M_D0L0 EQU 12

M_D0L1 EQU 13

M_D1L EQU $C000

M_D1L0 EQU 14

M_D1L1 EQU 15

M_D2L EQU $30000

M_D2L0 EQU 16

M_D2L1 EQU 17

M_D3L EQU $C0000

M_D3L0 EQU 18

M_D3L1 EQU 19

M_D4L EQU $300000

M_D4L0 EQU 20

M_D4L1 EQU 21

M_D5L EQU $C00000

M_D5L0 EQU 22

M_D5L1 EQU 23

; DMA0 Interrupt priority Level Mask

; DMA0 Interrupt Priority Level (low)

; DMA0 Interrupt Priority Level (high)

; DMA1 Interrupt Priority Level Mask

; DMA1 Interrupt Priority Level (low)

; DMA1 Interrupt Priority Level (high)

; DMA2 Interrupt priority Level Mask

; DMA2 Interrupt Priority Level (low)

; DMA2 Interrupt Priority Level (high)

; DMA3 Interrupt Priority Level Mask

; DMA3 Interrupt Priority Level (low)

; DMA3 Interrupt Priority Level (high)

; DMA4 Interrupt priority Level Mask

; DMA4 Interrupt Priority Level (low)

; DMA4 Interrupt Priority Level (high)

; DMA5 Interrupt priority Level Mask

; DMA5 Interrupt Priority Level (low)

; DMA5 Interrupt Priority Level (high)

;

Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3

M_HPL0 EQU 0

M_HPL1 EQU 1

M_S0L EQU $C

M_S0L0 EQU 2

M_S0L1 EQU 3

M_S1L EQU $30

M_S1L0 EQU 4

M_S1L1 EQU 5

M_SCL EQU $C0

M_SCL0 EQU 6

M_SCL1 EQU 7

M_T0L EQU $300

M_T0L0 EQU 8

M_T0L1 EQU 9

; Host Interrupt Priority Level Mask

; Host Interrupt Priority Level (low)

; Host Interrupt Priority Level (high)

; SSI0 Interrupt Priority Level Mask

; SSI0 Interrupt Priority Level (low)

; SSI0 Interrupt Priority Level (high)

; SSI1 Interrupt Priority Level Mask

; SSI1 Interrupt Priority Level (low)

; SSI1 Interrupt Priority Level (high)

; SCI Interrupt Priority Level Mask

; SCI Interrupt Priority Level (low)

; SCI Interrupt Priority Level (high)

; TIMER Interrupt Priority Level Mask

; TIMER Interrupt Priority Level (low)

; TIMER Interrupt Priority Level (high)

A-8

DSP56309 Technical Data

;------------------------------------------------------------------------

;

EQUATES for TIMER

;------------------------------------------------------------------------

;

Register Addresses Of TIMER0

M_TCSR0 EQU $FFFF8F

M_TLR0 EQU $FFFF8E

M_TCPR0 EQU $FFFF8D

M_TCR0 EQU $FFFF8C

; Timer 0 Control/Status Register

; TIMER0 Load Reg

; TIMER0 Compare Register

; TIMER0 Count Register

;

Register Addresses Of TIMER1

M_TCSR1 EQU $FFFF8B

M_TLR1 EQU $FFFF8A

M_TCPR1 EQU $FFFF89

M_TCR1 EQU $FFFF88

; TIMER1 Control/Status Register

; TIMER1 Load Reg

; TIMER1 Compare Register

; TIMER1 Count Register

;

Register Addresses Of TIMER2

M_TCSR2 EQU $FFFF87

M_TLR2 EQU $FFFF86

; TIMER2 Control/Status Register

; TIMER2 Load Reg

M_TCPR2 EQU $FFFF85 ; TIMER2 Compare Register

M_TCR2 EQU $FFFF84

M_TPLR EQU $FFFF83

M_TPCR EQU $FFFF82

; TIMER2 Count Register

; TIMER Prescaler Load Register

; TIMER Prescalar Count Register

;

Timer Control/Status Register Bit Flags

M_TE EQU 0

; Timer Enable

M_TOIE EQU 1

M_TCIE EQU 2

M_TC EQU $F0

M_INV EQU 8

M_TRM EQU 9

M_DIR EQU 11

M_DI EQU 12

M_DO EQU 13

; Timer Overflow Interrupt Enable

; Timer Compare Interrupt Enable

; Timer Control Mask (TC0-TC3)

; Inverter Bit

; Timer Restart Mode

; Direction Bit

; Data Input

; Data Output

M_PCE EQU 15 ; Prescaled Clock Enable

M_TOF EQU 20

M_TCF EQU 21

; Timer Overflow Flag

; Timer Compare Flag

;

Timer Prescaler Register Bit Flags

M_PS EQU $600000 ; Prescaler Source Mask

M_PS0 EQU 21

M_PS1 EQU 22

;

Timer Control Bits

M_TC0 EQU 4

M_TC1 EQU 5

M_TC2 EQU 6

M_TC3 EQU 7

; Timer Control 0

; Timer Control 1

; Timer Control 2

; Timer Control 3

;------------------------------------------------------------------------

;

EQUATES for Direct Memory Access (DMA)

;------------------------------------------------------------------------

;

Register Addresses Of DMA

M_DSTR EQU FFFFF4 ; DMA Status Register

M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0

M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1

M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2

M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3

;

Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register

M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register

M_DCO0 EQU $FFFFED ; DMA0 Counter

DSP56309 Technical Data

A-9

M_DCR0 EQU $FFFFEC ; DMA0 Control Register

Register Addresses Of DMA1

;

M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register

M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register

M_DCO1 EQU $FFFFE9 ; DMA1 Counter

M_DCR1 EQU $FFFFE8 ; DMA1 Control Register

;

Register Addresses Of DMA2

M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register

M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register

M_DCO2 EQU $FFFFE5 ; DMA2 Counter

M_DCR2 EQU $FFFFE4 ; DMA2 Control Register

;

Register Addresses Of DMA4

M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register

M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register

M_DCO3 EQU $FFFFE1 ; DMA3 Counter

M_DCR3 EQU $FFFFE0 ; DMA3 Control Register

;

Register Addresses Of DMA4

M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register

M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register

M_DCO4 EQU $FFFFDD ; DMA4 Counter

M_DCR4 EQU $FFFFDC ; DMA4 Control Register

;

Register Addresses Of DMA5

M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register

M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register

M_DCO5 EQU $FFFFD9 ; DMA5 Counter

M_DCR5 EQU $FFFFD8 ; DMA5 Control Register

;

DMA Control Register

M_DSS EQU $3

M_DSS0 EQU 0

M_DSS1 EQU 1

M_DDS EQU $C

M_DDS0 EQU 2

M_DDS1 EQU 3

; DMA Source Space Mask (DSS0-Dss1)

; DMA Source Memory space 0

; DMA Source Memory space 1

; DMA Destination Space Mask (DDS-DDS1)

; DMA Destination Memory Space 0

; DMA Destination Memory Space 1

M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0)

M_DAM0 EQU 4 ; DMA Address Mode 0

M_DAM1 EQU 5 ; DMA Address Mode 1

M_DAM2 EQU 6 ; DMA Address Mode 2

M_DAM3 EQU 7 ; DMA Address Mode 3

M_DAM4 EQU 8 ; DMA Address Mode 4

M_DAM5 EQU 9 ; DMA Address Mode 5

M_D3D EQU 10

; DMA Three Dimensional Mode

M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)

M_DCON EQU 16 ; DMA Continuous Mode

M_DPR EQU $60000; DMA Channel Priority

M_DPR0 EQU 17 ; DMA Channel Priority Level (low)

M_DPR1 EQU 18 ; DMA Channel Priority Level (high)

M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)

M_DTM0 EQU 19 ; DMA Transfer Mode 0

M_DTM1 EQU 20 ; DMA Transfer Mode 1

M_DTM2 EQU 21 ; DMA Transfer Mode 2

M_DIE EQU 22

M_DE EQU 23

; DMA Interrupt Enable bit

; DMA Channel Enable bit

;

DMA Status Register

M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5)

M_DTD0 EQU 0

M_DTD1 EQU 1

M_DTD2 EQU 2

M_DTD3 EQU 3

M_DTD4 EQU 4

M_DTD5 EQU 5

M_DACT EQU

; DMA Channel Transfer Done Status 0

; DMA Channel Transfer Done Status 1

; DMA Channel Transfer Done Status 2

; DMA Channel Transfer Done Status 3

; DMA Channel Transfer Done Status 4

; DMA Channel Transfer Done Status 5

; DMA Active State

8

M_DCH EQU $E00; DMA Active Channel Mask (DCH0-DCH2)

M_DCH0 EQU

9

; DMA Active Channel 0

A-10

DSP56309 Technical Data

M_DCH1 EQU 10 ; DMA Active Channel 1

M_DCH2 EQU 11 ; DMA Active Channel 2

;------------------------------------------------------------------------

;

EQUATES for Phase Locked Loop (PLL)

;------------------------------------------------------------------------

;

Register Addresses Of PLL

M_PCTL EQU $FFFFFD ; PLL Control Register

PLL Control Register

;

M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11)

M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)

M_XTLR EQU 15 ; XTAL Range select bit

M_XTLD EQU 16 ; XTAL Disable Bit

M_PSTP EQU 17 ; STOP Processing State Bit

M_PEN EQU 18

; PLL Enable Bit

M_PCOD EQU 19 ; PLL Clock Output Disable Bit

M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)

;------------------------------------------------------------------------

;

EQUATES for BIU

;------------------------------------------------------------------------

;

Register Addresses Of BIU

M_BCR EQU $FFFFFB; Bus Control Register

M_DCR EQU $FFFFFA; DRAM Control Register

M_AAR0 EQU $FFFFF9; Address Attribute Register 0

M_AAR1 EQU $FFFFF8; Address Attribute Register 1

M_AAR2 EQU $FFFFF7; Address Attribute Register 2

M_AAR3 EQU $FFFFF6; Address Attribute Register 3

M_IDR EQU $FFFFF5 ; ID Register

;

Bus Control Register

M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)

M_BA1W EQU $3E0; Area 1 Wait Control Mask (BA1W0-BA14)

M_BA2W EQU $1C00; Area 2 Wait Control Mask (BA2W0-BA2W2)

M_BA3W EQU $E000; Area 3 Wait Control Mask (BA3W0-BA3W3)

M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4)

M_BBS EQU 21

M_BLH EQU 22

M_BRH EQU 23

; Bus State

; Bus Lock Hold

; Bus Request Hold

;

DRAM Control Register

M_BCW EQU $3

M_BRW EQU $C

; In Page Wait States Bits Mask (BCW0-BCW1)

; Out Of Page Wait States Bits Mask (BRW0-BRW1)

M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)

M_BPLE EQU 11 ; Page Logic Enable

M_BME EQU 12

M_BRE EQU 13

; Mastership Enable

; Refresh Enable

M_BSTR EQU 14 ; Software Triggered Refresh

M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)

M_BRP EQU 23

; Refresh prescaler

;

Address Attribute Registers

M_BAT EQU $3

M_BAAP EQU 2

M_BPEN EQU 3

M_BXEN EQU 4

M_BYEN EQU 5

M_BAM EQU 6

M_BPAC EQU 7

; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)

; Address Attribute Pin Polarity

; Program Space Enable

; X Data Space Enable

; Y Data Space Enable

; Address Muxing

; Packing Enable

M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3)

M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)

DSP56309 Technical Data

A-11

;

control and status bits in SR

M_CP EQU $c00000; mask for CORE-DMA priority bits in SR

M_CA EQU 0

M_V EQU 1

; Carry

; Overflow

M_Z EQU 2

; Zero

M_N EQU 3

; Negative

M_U EQU 4

; Unnormalized

M_E EQU 5

; Extension

M_L EQU 6

; Limit

M_S EQU 7

; Scaling Bit

M_I0 EQU 8

M_I1 EQU 9

M_S0 EQU 10

M_S1 EQU 11

M_SC EQU 13

M_DM EQU 14

M_LF EQU 15

M_FV EQU 16

M_SA EQU 17

M_CE EQU 19

M_SM EQU 20

M_RM EQU 21

M_CP0 EQU 22

M_CP1 EQU 23

; Interupt Mask Bit 0

; Interupt Mask Bit 1

; Scaling Mode Bit 0

; Scaling Mode Bit 1

; Sixteen_Bit Compatibility

; Double Precision Multiply

; DO-Loop Flag

; DO-Forever Flag

; Sixteen-Bit Arithmetic

; Instruction Cache Enable

; Arithmetic Saturation

; Rounding Mode

; bit 0 of priority bits in SR

; bit 1 of priority bits in SR

;

control and status bits in OMR

M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR

M_MA

M_MB

M_MC

M_MD

equ0

; Operating Mode A

equ1

; Operating Mode B

equ2

equ3

; Operating Mode C

; Operating Mode D

M_EBD EQU 4

M_SD EQU 6

; External Bus Disable bit in OMR

; Stop Delay

M_MS EQU 7

; Memory Switch bit in OMR

; bit 0 of priority bits in OMR

; bit 1 of priority bits in OMR

M_CDP0 EQU 8

M_CDP1 EQU 9

M_BEN

EQU 10 ; Burst Enable

M_TAS EQU 11 ; TA Synchronize Select

M_BRT EQU 12 ; Bus Release Timing

M_ATE EQU 15

M_XYS EQU 16

M_EUN EQU 17

M_EOV EQU 18

M_WRP EQU 19

M_SEN EQU 20

; Address Tracing Enable bit in OMR.

; Stack Extension space select bit in OMR.

; Extensed stack UNderflow flag in OMR.

; Extended stack OVerflow flag in OMR.

; Extended WRaP flag in OMR.

; Stack Extension Enable bit in OMR.

;*************************************************************************

;

EQUATES for DSP56309 interrupts

Last update: June 11 1995

;*************************************************************************

page

opt

132,55,0,0,0

mex

intequ ident

if

1,0

@DEF(I_VEC)

;leave user definition as is.

else

I_VEC EQU $0

endif

;------------------------------------------------------------------------

; Non-Maskable interrupts

A-12

DSP56309 Technical Data

;------------------------------------------------------------------------

I_RESET EQU I_VEC+$00 ; Hardware RESET

I_STACK EQU I_VEC+$02 ; Stack Error

I_ILL EQU I_VEC+$04

I_DBG EQU I_VEC+$06

I_TRAP EQU I_VEC+$08

I_NMI EQU I_VEC+$0A

; Illegal Instruction

; Debug Request

; Trap

; Non Maskable Interrupt

;------------------------------------------------------------------------

; Interrupt Request Pins

;------------------------------------------------------------------------

I_IRQA EQU I_VEC+$10

I_IRQB EQU I_VEC+$12

I_IRQC EQU I_VEC+$14

I_IRQD EQU I_VEC+$16

; IRQA

; IRQB

; IRQC

; IRQD

;------------------------------------------------------------------------

; DMA Interrupts

;------------------------------------------------------------------------

I_DMA0 EQU I_VEC+$18

I_DMA1 EQU I_VEC+$1A

I_DMA2 EQU I_VEC+$1C

I_DMA3 EQU I_VEC+$1E

I_DMA4 EQU I_VEC+$20

I_DMA5 EQU I_VEC+$22

; DMA Channel 0

; DMA Channel 1

; DMA Channel 2

; DMA Channel 3

; DMA Channel 4

; DMA Channel 5

;------------------------------------------------------------------------

; Timer Interrupts

;------------------------------------------------------------------------

I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare

I_TIM0OF EQU I_VEC+$26; TIMER 0 overflow

I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare

I_TIM1OF EQU I_VEC+$2A; TIMER 1 overflow

I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare

I_TIM2OF EQU I_VEC+$2E; TIMER 2 overflow

;------------------------------------------------------------------------

; ESSI Interrupts

;------------------------------------------------------------------------

I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data

I_SI0RDE EQU I_VEC+$32; ESSI0 Receive Data w/ exception Status

I_SI0RLS EQU I_VEC+$34; ESSI0 Receive last slot

I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data

I_SI0TDE EQU I_VEC+$38; ESSI0 Transmit Data w/ exception Status

I_SI0TLS EQU I_VEC+$3A; ESSI0 Transmit last slot

I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data

I_SI1RDE EQU I_VEC+$42; ESSI1 Receive Data w/ exception Status

I_SI1RLS EQU I_VEC+$44

I_SI1TD EQU I_VEC+$46

; ESSI1 Receive last slot

; ESSI1 Transmit data

I_SI1TDE EQU I_VEC+$48; ESSI1 Transmit Data w/ exception Status

I_SI1TLS EQU I_VEC+$4A; ESSI1 Transmit last slot

;------------------------------------------------------------------------

; SCI Interrupts

;------------------------------------------------------------------------

I_SCIRD EQU I_VEC+$50

I_SCIRDE EQU I_VEC+$52

I_SCITD EQU I_VEC+$54

I_SCIIL EQU I_VEC+$56

I_SCITM EQU I_VEC+$58

; SCI Receive Data

; SCI Receive Data With Exception Status

; SCI Transmit Data

; SCI Idle Line

; SCI Timer

;------------------------------------------------------------------------

; HOST Interrupts

;------------------------------------------------------------------------

I_HRDF EQU I_VEC+$60

I_HTDE EQU I_VEC+$62

I_HC EQU I_VEC+$64

; Host Receive Data Full

; Host Transmit Data Empty

; Default Host Command

;------------------------------------------------------------------------

; INTERRUPT ENDING ADDRESS

;------------------------------------------------------------------------

I_INTEND EQU I_VEC+$FF

; last address of interrupt vector space

DSP56309 Technical Data

A-13

A-14

DSP56309 Technical Data

Index

Direct Memory Access (DMA) iii

documentation list v

Double Data Strobe 1-2

DRAM

Numerics

5 V tolerance 1-1

A

out of page

read access 2-29

ac electrical characteristics 2-4

address bus 1-1

Address Trace mode iii, 2-32, 2-35

applications v

arbitration bus timings 2-35

Arithmetic Logic Unit (ALU) iii

wait states selection guide 2-25

write access 2-30

out of page and refresh timings

11 wait states 2-25

15 wait states 2-27

Page mode

read accesses 2-24

wait states selection guide 2-19

write accesses 2-23

Page mode timings

3 wait states 2-20

4 wait states 2-21

refresh access 2-31

DRAM controller iv

DSP56300

B

benchmark test algorithm A-1

bootstrap ROM iv

Boundary Scan (JTAG Port) timing diagram 2-56

bus

address 1-2

data 1-2

external address 1-6

external data 1-6

multiplexed 1-2

core features iii

Family Manual v

DSP56309

non-multiplexed 1-2

bus acquisition timings 2-36

bus control 1-1

block diagram i

description i

features iii

specifications 2-1

Technical Data v

User’s Manual v

bus release timings 2-37, 2-38

C

clock 1-1, 1-5

external 2-4

E

operation 2-6

clocks

internal 2-4

crystal oscillator circuits 2-5

electrical design considerations 4-2, 4-3

Enhanced Synchronous Serial Interface (ESSI) 1-1, 1-2,

1-16, 1-17, 1-18, 1-19

receiver timing 2-52

timings 2-48

transmitter timing 2-51

D

Enhanced Synchronous Serial Interfaces (ESSI) iv

external address bus 1-6

external bus control 1-6, 1-7, 1-8

external bus synchronous timings (SRAM access) 2-32

external clock operation 2-4

Data Arithmetic Logic Unit (Data ALU) iii

data bus 1-1

data memory expansion iv

Data Strobe (DS) 1-2

dc electrical characteristics 2-3

Debug support iii

external data bus 1-6

external interrupt timing (negative edge-triggered) 2-12

external level-sensitive fast interrupt timing 2-12

external memory access (DMA Source) timing 2-14

External Memory Expansion Port 1-6, 2-15

description, general i

design considerations

electrical 4-2, 4-3

PLL 4-6

power consumption 4-3

thermal 4-1

DSP56309 Technical Data

Index-1

Index

keeper circuits 1-3, 1-6, 1-15, 1-17, 1-19, 1-20, 1-21, 4-3

keeper, weak 1-3

F

functional groups 1-2

functional signal groups 1-1

M

MAP-BGA 3-1

G

ball grid drawing (bottom) 3-11

ball grid drawing (top) 3-10

ball list by name 3-15

ball list by number 3-12

mechanical drawing 3-19

maximum ratings 2-1, 2-2

memory expansion port iv

mode control 1-9

general description i

General-Purpose Input/Output (GPIO) iv, 1-2, 1-21

Timers 1-2

General-Purpose Input/Output (GPIO) timing 2-54

ground 1-1, 1-4

PLL 1-4

H

Mode select timing 2-7

multiplexed bus 1-2

multiplexed bus timings

read 2-44

Host Interface (HI08) iv, 1-1, 1-2, 1-10, 1-11, 1-12,

1-13, 1-14, 1-15

Host Interface (HI08) timing 2-40

host port

write 2-45

configuration 1-11

usage considerations 1-10

Host Request

N

non-multiplexed bus 1-2

non-multiplexed bus timings

read 2-42

Double 1-2

Single 1-2

write 2-43

Host Request (HR) 1-2

O

I

off-chip memory iv

information sources v

OnCE

instruction cache iii

module timing 2-57

internal clocks 2-4

OnCE module 1-22

interrupt and mode control 1-1, 1-9

interrupt control 1-9

Debug request 2-57

on-chip DRAM controller iv

On-Chip Emulation (OnCE) module iii

on-chip memory iii

operating mode select timing 2-13

ordering information Back Cover

interrupt timing 2-7

external level-sensitive fast 2-12

external negative edge-triggered 2-12

synchronous from Wait state 2-13

J

P

JTAG iii, 1-22

JTAG Port

package

144-pin TQFP 3-1

196-pin MAP-BGA 3-1

MAP-BGA description 3-10, 3-11, 3-12, 3-15, 3-19

TQFP description 3-2, 3-3, 3-4, 3-6, 3-9

Phase-Lock Loop (PLL) iii, 1-1, 2-7

Characteristics 2-7

reset timing diagram 2-57

timing 2-55, 2-56

JTAG/OnCE port 1-1, 1-2

K

keeper circuit

design considerations 4-6

performance issues 4-6

design considerations 4-3

Phase-Lock Loop (PLL) design considerations 4-6

DSP56309 Technical Data

Index-2

Index

PLL 1-5

Port A 1-1, 1-6

T

Port B 1-1, 1-2, 1-12, 1-13, 1-14, 1-15

Port C 1-1, 1-2, 1-16, 1-17

Port D 1-1, 1-2, 1-18, 1-19

Port E 1-1, 1-20

target applications v

Test Access Port (TAP) iii

timing diagram 2-56

Test Clock (TCLK) input timing diagram 2-55

thermal characteristics 2-2

thermal design considerations 4-1

Timer

Power 1-3

power 1-1

power consumption benchmark test A-1

power consumption design considerations 4-3

power management v

Program Control Unit (PCU) iii

program memory expansion iv

program RAM iv

event input restrictions 2-53

interrupt generation 2-53

timing 2-53

Timers 1-1, 1-2, 1-21

timing

interrupt 2-7

mode select 2-7

Reset 2-7

Stop 2-7

R

recovery from Stop state using IRQA 2-13, 2-14

RESET 1-10

Reset timing 2-7, 2-11

synchronous 2-11

TQFP 3-1

mechanical drawing 3-9

pin list by name 3-6

pin list by number 3-4

pin-out drawing (bottom) 3-3

pin-out drawing (top) 3-2

ROM, bootstrap iv

S

Serial Communication Interface (SCI) 1-1, 1-2, 1-20

Asynchronous mode timing 2-47

Synchronous mode timing 2-47

timing 2-46

Serial Communications Interface (SCI) iv

signal groupings 1-1

W

Wait mode v

weak keeper 1-3

World Wide Web v

signals 1-1

X

functional grouping 1-2

Single Data Strobe 1-2

SRAM

X data RAM iv

Y

read access 2-17

read and write accesses 2-15

support iv

Y data RAM iv

write access 2-18

Stop mode v

Stop state

recovery from 2-13, 2-14

Stop timing 2-7

supply voltage 2-2

Switch mode iv

synchronous bus timings

SRAM

2 wait states 2-34

SRAM 1 wait state (BCR controlled) 2-33

synchronous interrupt from Wait state timing 2-13

synchronous Reset timing 2-11

DSP56309 Technical Data

Index-3

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability

and to place an order.

Supply

Voltage

Count

Frequency

(MHz)

Part

Package Type

Order Number

DSP56309

3.3 V

Thin Quad Flat Pack (TQFP)

144

196

100

DSP56309PV100

DSP56309VF100

Molded Array Process-Ball Grid Array

(MAP-BGA)

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can

and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must

be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent

rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems

intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in

which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or

use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or

unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola

and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. OnCE, DigitalDNA, and the DigitalDNA LOGO are

trademarks owned by Motorola, Inc. All other products or service names are the property of their respective owners.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569

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Technical Information Center: 1-800-521-6274

HOME PAGE: http://www.motorola.com/semiconductors/

Order Number

DSP56309/D


型号：	DSP56309PV100
厂家：	NXP
描述：	IC,DSP,24-BIT,CMOS,QFP,144PIN,PLASTIC
文件：	总132页 (文件大小：1608K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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