DSP56311VL150R2 [NXP]
24 BIT DSP PBFREE;型号: | DSP56311VL150R2 |
厂家: | NXP |
描述: | 24 BIT DSP PBFREE 时钟 外围集成电路 |
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DSP56311
Rev. 8, 2/2005
Freescale Semiconductor
Technical Data
DSP56311
24-Bit Digital Signal Processor
3
16
6
6
Memory Expansion Area
The DSP56311 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
Program
RAM
Triple
Timer
32 K × 24 bits
SCI
HI08
ESSI
EFCOP
or
X Data
RAM
Y Data
RAM
31 K × 24 bits
and
48 K × 24 bits 48 K × 24 bits
Instruction
Cache
1024 × 24 bits
Peripheral
Expansion Area
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
YAB
Address
Generation
Unit
External
Address
Bus
XAB
PAB
DAB
18
Address
Switch
Six Channel
DMA Unit
External
Bus
24-Bit
DSP56300
Core
13
Interface
and
Bootstrap
ROM
Control
I - Cache
Control
DDB
YDB
XDB
PDB
GDB
External
Data
Bus
Internal
Data
Bus
24
What’s New?
Rev. 8 includes the following
changes:
Switch
Data
Switch
•
Adds lead-free packaging and
part numbers.
Power
Management
Data ALU
5
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Clock
Generator
+
→
24 × 24 56 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
JTAG
PLL
OnCE™
DE
EXTAL
XTAL
RESET
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
PCAP
PINIT/NMI
Figure 1. DSP56311 Block Diagram
The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)
controller (see Figure 1). The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining
up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
© Freescale Semiconductor, Inc., 1999, 2005. All rights reserved.
Table of Contents
Data Sheet Conventions.......................................................................................................................................ii
Features...............................................................................................................................................................iii
Target Applications.............................................................................................................................................iv
Product Documentation ......................................................................................................................................iv
Chapter 1
Signals/Connections
1.1
Power ................................................................................................................................................................1-3
Ground ..............................................................................................................................................................1-3
Clock.................................................................................................................................................................1-3
External Memory Expansion Port (Port A) ......................................................................................................1-4
Interrupt and Mode Control ..............................................................................................................................1-7
Host Interface (HI08)........................................................................................................................................1-8
Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11
Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12
Serial Communication Interface (SCI) ...........................................................................................................1-13
Timers .............................................................................................................................................................1-14
JTAG and OnCE Interface ..............................................................................................................................1-15
1.2
1.3
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
Chapter 2
Specifications
2.1
2.2
2.3
2.4
Maximum Ratings.............................................................................................................................................2-1
Thermal Characteristics ....................................................................................................................................2-2
DC Electrical Characteristics............................................................................................................................2-3
AC Electrical Characteristics............................................................................................................................2-4
Chapter 3
Chapter 4
Packaging
3.1
Package Description .........................................................................................................................................3-2
3.2
MAP-BGA Package Mechanical Drawing .....................................................................................................3-10
Design Considerations
4.1
4.2
4.3
4.4
4.5
Thermal Design Considerations........................................................................................................................4-1
Electrical Design Considerations......................................................................................................................4-2
Power Consumption Considerations.................................................................................................................4-3
PLL Performance Issues ...................................................................................................................................4-4
Input (EXTAL) Jitter Requirements .................................................................................................................4-6
Appendix A
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
Indicates a signal that is active when pulled low (For example, the RESET pin is active when
low.)
“asserted”
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
“deasserted”
Examples:
Signal/Symbol
Logic State
Signal State
Asserted
Voltage
VIL/VOL
PIN
True
PIN
PIN
PIN
VIH/VOH
VIH/VOH
VIL/VOL
False
True
False
Deasserted
Asserted
Deasserted
Note: Values for V , V , V , and VOH are defined by individual product specifications.
IL
OL
IH
DSP56311 Technical Data, Rev. 8
ii
Freescale Semiconductor
Features
Table 1 lists the features of the DSP56311 device.
Table 1. DSP56311 Features
Feature
Description
•
Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering
applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
•
•
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
•
•
High-Performance
DSP56300 Core
•
•
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
•
•
•
Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
Operation at the same frequency as the core (up to 150 MHz)
Support for a variety of filter modes, some of which are optimized for cellular base station applications:
•
•
•
•
•
•
•
•
•
Real finite impulse response (FIR) with real taps
Complex FIR with complex taps
Complex FIR generating pure real or pure imaginary outputs alternately
A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
Direct form 2 (DFII) IIR filter
Four scaling factors (1, 4, 8, 16) for IIR output
Adaptive FIR filter with true least mean square (LMS) coefficient updates
Adaptive FIR filter with delayed LMS coefficient updates
Enhanced Filter
Coprocessor (EFCOP)
•
•
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Internal Peripherals
•
•
•
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
•
•
•
192 × 24-bit bootstrap ROM
128 K × 24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
:
Program
RAM Size
Instruction
Cache Size
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
Switch
Mode
MSW1 MSW0
32 K × 24-bit
0
48 K × 24-bit
48 K × 24-bit
16 K × 24-bit
16 K × 24-bit
24 K × 24-bit
24 K × 24-bit
32 K × 24-bit
32 K × 24-bit
40 K × 24-bit
40 K × 24-bit
48 K × 24-bit
48 K × 24-bit
16 K × 24-bit
16 K × 24-bit
24 K × 24-bit
24 K × 24-bit
32 K × 24-bit
32 K × 24-bit
40 K × 24-bit
40 K × 24-bit
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
disabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
0/1
0/1
0
0/1
0/1
0
31 K × 24-bit 1024 × 24-bit
96 K × 24-bit
95 K × 24-bit 1024 × 24-bit
80 K × 24-bit
79 K × 24-bit 1024 × 24-bit
64 K × 24-bit
63 K × 24-bit 1024 × 24-bit
48 K × 24-bit
47 K × 24-bit 1024 × 24-bit
0
Internal Memories
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
*Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
iii
Table 1. DSP56311 Features (Continued)
Feature
Description
•
•
Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K × 24-bit words memory space using the standard external
address lines
External Memory
Expansion
•
•
•
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Internal DRAM controller for glueless interface to dynamic random access memory (DRAMs) up to 100
MHz operating frequency
•
•
•
•
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Power Dissipation
Packaging
•
Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Target Applications
DSP56311 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
•
•
•
•
•
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
DSP resource boards
High-speed modem banks
IP telephony
Product Documentation
The documents listed in Table 2 are required for a complete description of the DSP56311 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2. DSP56311 Documentation
Name
DSP56311
Description
Order Number
DSP56311UM
Detailed functional description of the DSP56311 memory configuration,
operation, and register programming
User’s Manual
DSP56300 Family Detailed description of the DSP56300 family processor core and instruction set DSP56300FM
Manual
Application Notes Documents describing specific applications or optimized device operation
including code examples
See the DSP56311 product website
DSP56311 Technical Data, Rev. 8
iv
Freescale Semiconductor
Signals/Connections
1
The DSP56311 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1
diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Table 1-1. DSP56311 Functional Signal Groupings
Number of
Functional Group
Signals
Power (VCC
)
20
66
2
Ground (GND)
Clock
PLL
3
Address bus
18
24
13
5
Data bus
Port A1
Bus control
Interrupt and mode control
Host interface (HI08)
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
Port B2
Ports C and D3
Port E4
16
12
3
3
OnCE/JTAG Port
6
Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4. Port E signals are the SCI port signals multiplexed with the GPIO signals.
5. There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see
Chapter 3).
Note: The Clock Output (CLKOUT), BCLK, BCLK, CAS, and RAS[0–3] signals used by other DSP56300 family members
are supported by the DSP56311 at operating frequencies up to 100 MHz. Therefore, above 100 MHz, you must
enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register.
When set, the ABE bit eliminates the required set-up and hold times for BB and BG with respect to CLKOUT. In
addition, DRAM access is not supported above 100 MHz.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-1
Signals/Connections
After Reset
IRQA
IRQB
IRQC
IRQD
During Reset
MODA
MODB
MODC
MODD
DSP56311
Interrupt/
Mode Control
Power Inputs:
VCCP
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
PLL
Core Logic
I/O
4
3
3
4
2
RESET
RESET
Address Bus
Data Bus
Bus Control
HI08
Non-Multiplexed Multiplexed
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
Bus
Bus
8
H[0–7]
HA0
HA1
HAD[0–7]
HAS/HAS
HA8
2
ESSI/SCI/Timer
Host
Interface
HA2
HA9
Grounds:
PLL
PLL
(HI08) Port1
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
HA10
GNDP
GNDP1
GND
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ PB14
HRRQ/HRRQ PB15
64
PB11
PB12
Ground plane
Port C GPIO
PC[0–2]
PC3
PC4
PC5
3
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)2
SC0[0–2]
SCK0
SRD0
EXTAL
XTAL
Clock
PLL
STD0
CLKOUT4
PCAP
Port D GPIO
PD[0–2]
PD3
PD4
PD5
3
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)2
SC1[0–2]
SCK1
SRD1
After
Reset
NMI
During
Reset
PINIT
STD1
Port A
18
24
External
Address Bus
A[0–17]
D[0–23]
Port E GPIO
PE0
PE1
Serial
Communications
RXD
TXD
SCLK
Interface (SCI) Port2
External
Data Bus
PE2
AA0/RAS0–
AA3/RAS34
RD
4
Timer GPIO
TIO0
TIO1
External
Bus
Control
TIO0
TIO1
TIO2
Timers3
WR
TA
TIO2
BR
BG
BB
TCK
TDI
TDO
TMS
TRST
DE
OnCE/
JTAG Port
CAS4
BCLK4
BCLK4
Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3. TIO[0–2] can be configured as GPIO signals.
4. CLKOUT, BCLK, BCLK, CAS, and RAS[0–3] are valid only for operating frequencies ≤100 MHz.
Figure 1-1. Signals Identified by Functional Group
DSP56311 Technical Data, Rev. 8
1-2
Freescale Semiconductor
Power
1.1 Power
Table 1-2. Power Inputs
Power Name
Description
VCCP
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the VCC power rail.
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from
all other chip power inputs.
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other chip
power inputs, except VCCQL
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
to all other chip power inputs, except VCCQL
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
other chip power inputs, except VCCQL
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
chip power inputs, except VCCQL
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs, except VCCQL
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs, except VCCQL
.
.
.
.
.
.
Note: The user must provide adequate external decoupling capacitors for all power connections.
1.2 Ground
Table 1-3. Grounds
Name
GNDP
Description
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip
package.
GNDP1
GND
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
1.3 Clock
Table 1-4. Clock Signals
State During
Signal Name
Type
Signal Description
Reset
EXTAL
Input
Output
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator input
to an external crystal or an external clock.
XTAL
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-3
Signals/Connections
1.4 PLL
Table 1-5. Phase-Locked Loop Signals
State During
Signal Name
Type
Output
Signal Description
Reset
CLKOUT
Chip-driven
Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
Note: At operating frequencies above 100 MHz, this signal produces a low-
amplitude waveform that is not usable externally by other devices. Above 100
MHz, you can use the asynchronous bus arbitration option that is enabled by
the Asynchronous Bus Arbitration Enable (ABE) bit in the Operating Mode
Register. When set, the DSP enters the Asynchronous Arbitration mode,
which eliminates the BB and BG set-up and hold time requirements with
respect to CLKOUT.
PCAP
Input
Input
Input
PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to VCCP
.
If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.
PINIT
NMI
Input
Input
PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals: A[0–17], D[0–23], AA[0–3], RD, WR, BB.
1.5.1 External Address Bus
Table 1-6. External Address Bus Signals
State During
Signal Name
Type
Output
Reset, Stop,
Signal Description
or Wait
A[0–17]
Tri-stated
Address Bus—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
DSP56311 Technical Data, Rev. 8
1-4
Freescale Semiconductor
External Memory Expansion Port (Port A)
1.5.2 External Data Bus
Table 1-7. External Data Bus Signals
Signal
Name
State During
Reset
State During
Stop or Wait
Type
Signal Description
D[0–23]
Input/ Output Ignored Input
Last state:
Input: Ignored
Output:
Data Bus—When the DSP is the bus master, D[0–23] are active-high,
bidirectional input/outputs that provide the bidirectional data bus for
external program and data memory accesses. Otherwise, D[0–23]
drivers are tri-stated. If the last state is output, these lines have weak
keepers to maintain the last output state if all drivers are tri-stated.
Last value
1.5.3 External Bus Control
Table 1-8. External Bus Control Signals
Signal
Name
State During Reset,
Stop, or Wait
Type
Output
Signal Description
AA[0–3]
Tri-stated
Address Attribute—When defined as AA, these signals can be used as chip selects
or additional address lines. The default use defines a priority scheme under which
only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit
(Bit 14) of the Operating Mode Register, the priority mechanism is disabled and the
lines can be used together as four external lines that can be decoded externally into
16 chip select signals.
RAS[0–3]
Output
Row Address Strobe—When defined as RAS, these signals can be used as RAS for
DRAM interface. These signals are tri-statable outputs with programmable polarity.
Note: DRAM access is not supported above 100 MHz.
RD
WR
TA
Output
Output
Input
Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low output that is
asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is tri-
stated.
Tri-stated
Write Enable—When the DSP is the bus master, WR is an active-low output that is
asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals
are tri-stated.
Ignored Input
Transfer Acknowledge—If the DSP56311 is the bus master and there is no external
bus activity, or the DSP56311 is not the bus master, the TA input is ignored. The TA
input is a data transfer acknowledge (DTACK) function that can extend an external
bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the
wait states inserted by the bus control register (BCR) by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a bus cycle, asserted to enable
completion of the bus cycle, and deasserted before the next bus cycle. The current
bus cycle completes one clock period after TA is deasserted. The number of wait
states is determined by the TA input or by the BCR, whichever is longer. The BCR
sets the minimum number of wait states in external bus cycles. In order to use the TA
functionality, the BCR must be programmed to at least one wait state. A zero wait
state access cannot be extended by TA deassertion.
At operating frequencies ≤100 MHz, TA can operate synchronously (with respect to
CLKOUT) or asynchronously depending on the setting of the TAS bit in the Operating
Mode Register (OMR). If synchronous mode is selected, the user is responsible for
ensuring that TA transitions occur synchronous to CLKOUT to ensure correct
operation. Synchronous operation is not supported above 100 MHz and the
OMR[TAS] bit must be set to synchronize the TA signal with the internal clock.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-5
Signals/Connections
Table 1-8. External Bus Control Signals (Continued)
Signal
Type
State During Reset,
Signal Description
Stop, or Wait
Name
BR
Output
Reset: Output
(deasserted)
Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted
when the DSP no longer needs the bus. BR may be asserted or deasserted
independently of whether the DSP56311 is a bus master or a bus slave. Bus
State during Stop/Wait “parking” allows BR to be deasserted even though the DSP56311 is the bus master.
depends on BRH bit
setting:
• BRH = 0: Output,
deasserted
• BRH = 1: Maintains
last state (that is, if
asserted, remains
asserted)
(See the description of bus “parking” in the BB signal description.) The bus request
hold (BRH) bit in the BCR allows BR to be asserted under software control even
though the DSP does not need the bus. BR is typically sent to an external bus
arbitrator that controls the priority, parking, and tenure of each master on the same
external bus. BR is affected only by DSP requests for the external bus, never for the
internal bus. During hardware reset, BR is deasserted and the arbitration is reset to
the bus slave state.
BG
Input
Ignored Input
Bus Grant—Asserted by an external bus arbitration circuit when the DSP56311
becomes the next bus master. When BG is asserted, the DSP56311 must wait until
BB is deasserted before taking bus mastership. When BG is deasserted, bus
mastership is typically given up at the end of the current bus cycle. This may occur in
the middle of an instruction that requires more than one external bus cycle for
execution.
The default operation of this bit requires a set-up and hold time as specified in
Chapter 2. An alternate mode can be invoked: set the asynchronous bus arbitration
enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and
BB are synchronized internally. This eliminates the respective set-up and hold time
requirements but adds a required delay between the deassertion of an initial BG input
and the assertion of a subsequent BG input.
BB
Input/ Output Ignored Input
Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
pending bus master become the bus master (and then assert the signal again). The
bus master may keep BB asserted after ceasing bus activity regardless of whether
BR is asserted or deasserted. Called “bus parking,” this allows the current bus master
to reuse the bus without rearbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB is driven high and then released
and held high by an external pull-up resistor).
The default operation of this signal requires a set-up and hold time as specified in
Chapter 2. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the
Operating Mode Register. When this bit is set, BG and BB are synchronized
internally. See BG for additional information.
Note: BB requires an external pull-up resistor.
CAS
Output
Output
Tri-stated
Tri-stated
Column Address Strobe—When the DSP is the bus master, CAS is an active-low
output used by DRAM to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM control register is cleared, the signal is tri-
stated.
Note: DRAM access is not supported above 100 MHz.
BCLK
Bus Clock
When the DSP is the bus master, BCLK is active when the ATE bit in the Operating
Mode Register is set. When BCLK is active and synchronized to CLKOUT by the
internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.
Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude
waveform that is not usable externally by other devices.
BCLK
Output
Tri-stated
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise,
the signal is tri-stated.
Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude
waveform that is not usable externally by other devices.
DSP56311 Technical Data, Rev. 8
1-6
Freescale Semiconductor
Interrupt and Mode Control
1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After
RESET is deasserted, these inputs are hardware interrupt request lines.
Table 1-9. Interrupt and Mode Control
State During
Signal Name
Type
Signal Description
Reset
MODA
Input
Input
Schmitt-trigger
Input
Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
IRQA
External Interrupt Request A—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the STOP or WAIT
standby state and IRQA is asserted, the processor exits the STOP or WAIT
state.
MODB
IRQB
Input
Input
Schmitt-trigger
Input
Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQB is asserted, the processor exits the WAIT state.
MODC
IRQC
Input
Input
Schmitt-trigger
Input
Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request C—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQC is asserted, the processor exits the WAIT state.
MODD
IRQD
Input
Input
Schmitt-trigger
Input
Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request D—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQD is asserted, the processor exits the WAIT state.
RESET
Input
Schmitt-trigger
Input
Reset—Places the chip in the Reset state and resets the internal phase
generator. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET signal is
deasserted, the initial chip operating mode is latched from the MODA, MODB,
MODC, and MODD inputs. The RESET signal must be asserted after
powerup.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-7
Signals/Connections
1.7 Host Interface (HI08)
The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety
of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs,
and DMA hardware.
1.7.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written by another
asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the
Host port). The considerations for proper operation are discussed in Table 1-10.
Table 1-10. Host Port Usage Considerations
Action
Description
Asynchronous read of receive byte
registers
When reading the receive byte registers, Receive register High (RXH), Receive register Middle
(RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll
the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data
in the receive byte registers is valid.
Asynchronous write to transmit byte
registers
The host interface programmer should not write to the transmit byte registers, Transmit register High
(TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register
Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees
that the transmit byte registers transfer valid data to the Host Receive (HRX) register.
Asynchronous write to host vector
The host interface programmer must change the Host Vector (HV) register only when the Host
Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a
stable vector.
1.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits
in the HI08 Port Control Register.
Table 1-11. Host Interface
State During
Reset
Signal Name
H[0–7]
Type
Signal Description
1,2
Input/Output
Ignored Input
Host Data—When the HI08 is programmed to interface with a non-multiplexed
host bus and the HI function is selected, these signals are lines 0–7 of the
bidirectional Data bus.
HAD[0–7]
PB[0–7]
Input/Output
Host Address—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, these signals are lines 0–7 of the
bidirectional multiplexed Address/Data bus.
Input or Output
Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port
Control Register, these signals are individually programmed as inputs or outputs
through the HI08 Data Direction Register.
DSP56311 Technical Data, Rev. 8
1-8
Freescale Semiconductor
Host Interface (HI08)
Table 1-11. Host Interface (Continued)
State During
Reset
Signal Name
HA0
Type
Signal Description
Host Address Input 0—When the HI08 is programmed to interface with a
1,2
Input
Ignored Input
nonmultiplexed host bus and the HI function is selected, this signal is line 0 of
the host address input bus.
HAS/HAS
Input
Host Address Strobe—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is the host
address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is
programmable but is configured active-low (HAS) following reset.
Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
PB8
HA1
Input or Output
Input
Ignored Input
Ignored Input
Ignored Input
Host Address Input 1—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is line 1 of
the host address (HA1) input bus.
HA8
Input
Host Address 8—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, this signal is line 8 of the host address
(HA8) input bus.
PB9
HA2
Input or Output
Input
Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
Host Address Input 2—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is line 2 of
the host address (HA2) input bus.
HA9
Input
Host Address 9—When the HI08 is programmed to interface with a multiplexed
host bus and the HI function is selected, this signal is line 9 of the host address
(HA9) input bus.
PB10
Input or Output
Input
Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
HCS/HCS
Host Chip Select—When the HI08 is programmed to interface with a
nonmultiplexed host bus and the HI function is selected, this signal is the host
chip select (HCS) input. The polarity of the chip select is programmable but is
configured active-low (HCS) after reset.
Host Address 10—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line 10 of the
host address (HA10) input bus.
HA10
Input
Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
PB13
HRW
Input or Output
Input
Ignored Input
Host Read/Write—When the HI08 is programmed to interface with a single-
data-strobe host bus and the HI function is selected, this signal is the Host
Read/Write (HRW) input.
HRD/HRD
Input
Host Read Data—When the HI08 is programmed to interface with a double-
data-strobe host bus and the HI function is selected, this signal is the HRD
strobe Schmitt-trigger input. The polarity of the data strobe is programmable but
is configured as active-low (HRD) after reset.
Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
PB11
Input or Output
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-9
Signals/Connections
Table 1-11. Host Interface (Continued)
State During
Reset
Signal Name
Type
Signal Description
1,2
HDS/HDS
Input
Ignored Input
Host Data Strobe—When the HI08 is programmed to interface with a single-
data-strobe host bus and the HI function is selected, this signal is the host data
strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HDS) following reset.
Host Write Data—When the HI08 is programmed to interface with a double-
data-strobe host bus and the HI function is selected, this signal is the host write
data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is
programmable but is configured as active-low (HWR) following reset.
HWR/HWR
Input
Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
PB12
Input or Output
Output
HREQ/HREQ
Ignored Input
Host Request—When the HI08 is programmed to interface with a single host
request host bus and the HI function is selected, this signal is the host request
(HREQ) output. The polarity of the host request is programmable but is
configured as active-low (HREQ) following reset. The host request may be
programmed as a driven or open-drain output.
Transmit Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
transmit host request (HTRQ) output. The polarity of the host request is
programmable but is configured as active-low (HTRQ) following reset. The host
request may be programmed as a driven or open-drain output.
HTRQ/HTRQ
Output
Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
PB14
Input or Output
Input
HACK/HACK
Ignored Input
Host Acknowledge—When the HI08 is programmed to interface with a single
host request host bus and the HI function is selected, this signal is the host
acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is programmable but is configured as active-low (HACK) after
reset.
HRRQ/HRRQ
Output
Receive Host Request—When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
receive host request (HRRQ) output. The polarity of the host request is
programmable but is configured as active-low (HRRQ) after reset. The host
request may be programmed as a driven or open-drain output.
Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control
Register, this signal is individually programmed as an input or output through the
HI08 Data Direction Register.
PB15
Input or Output
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
DSP56311 Technical Data, Rev. 8
1-10
Freescale Semiconductor
Enhanced Synchronous Serial Interface 0 (ESSI0)
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication
with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals that implement the Freescale serial peripheral interface (SPI).
Table 1-12. Enhanced Synchronous Serial Interface 0
State During
Reset
Signal Name
SC00
Type
Signal Description
1,2
Input or Output
Ignored Input
Ignored Input
Ignored Input
Serial Control 0—For asynchronous mode, this signal is used for the receive
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port C 0—The default configuration following reset is GPIO input PC0. When
configured as PC0, signal direction is controlled through the Port C Direction
Register. The signal can be configured as ESSI signal SC00 through the Port C
Control Register.
PC0
Input or Output
Input/Output
SC01
Serial Control 1—For asynchronous mode, this signal is the receiver frame
sync I/O. For synchronous mode, this signal is used either for transmitter 2
output or for serial I/O flag 1.
PC1
Input or Output
Input/Output
Port C 1—The default configuration following reset is GPIO input PC1. When
configured as PC1, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SC01 through the Port
C Control Register.
SC02
Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode, and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port C 2—The default configuration following reset is GPIO input PC2. When
configured as PC2, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SC02 through the Port
C Control Register.
PC2
Input or Output
Input/Output
SCK0
Ignored Input
Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK0 is a
clock input or output, used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port C 3—The default configuration following reset is GPIO input PC3. When
configured as PC3, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SCK0 through the Port
C Control Register.
PC3
Input or Output
Input
SRD0
Ignored Input
Serial Receive Data—Receives serial data and transfers the data to the ESSI
Receive Shift Register. SRD0 is an input when data is received.
Port C 4—The default configuration following reset is GPIO input PC4. When
configured as PC4, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal SRD0 through the
Port C Control Register.
PC4
Input or Output
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-11
Signals/Connections
Signal Name
Table 1-12. Enhanced Synchronous Serial Interface 0 (Continued)
State During
Type
Signal Description
1,2
Reset
STD0
Output
Ignored Input
Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD0 is an output when data is transmitted.
PC5
Input or Output
Port C 5—The default configuration following reset is GPIO input PC5. When
configured as PC5, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal STD0 through the Port
C Control Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-13. Enhanced Serial Synchronous Interface 1
State During
Reset
Signal Name
SC10
Type
Signal Description
1,2
Input or Output
Ignored Input
Ignored Input
Ignored Input
Serial Control 0—For asynchronous mode, this signal is used for the receive
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port D 0—The default configuration following reset is GPIO input PD0. When
configured as PD0, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC10 through the Port
D Control Register.
PD0
Input or Output
Input/Output
SC11
Serial Control 1—For asynchronous mode, this signal is the receiver frame
sync I/O. For synchronous mode, this signal is used either for Transmitter 2
output or for Serial I/O Flag 1.
PD1
Input or Output
Input/Output
Port D 1—The default configuration following reset is GPIO input PD1. When
configured as PD1, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC11 through the Port
D Control Register.
SC12
Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port D 2—The default configuration following reset is GPIO input PD2. When
configured as PD2, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC12 through the Port
D Control Register.
PD2
Input or Output
DSP56311 Technical Data, Rev. 8
1-12
Freescale Semiconductor
Serial Communication Interface (SCI)
Table 1-13. Enhanced Serial Synchronous Interface 1 (Continued)
State During
Reset
Signal Name
SCK1
Type
Signal Description
1,2
Input/Output
Ignored Input
Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a
clock input or output used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port D 3—The default configuration following reset is GPIO input PD3. When
configured as PD3, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SCK1 through the Port
D Control Register.
PD3
Input or Output
Input
SRD1
Ignored Input
Ignored Input
Serial Receive Data—Receives serial data and transfers the data to the ESSI
Receive Shift Register. SRD1 is an input when data is being received.
Port D 4—The default configuration following reset is GPIO input PD4. When
configured as PD4, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SRD1 through the
Port D Control Register.
PD4
Input or Output
STD1
PD5
Output
Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD1 is an output when data is being transmitted.
Input or Output
Port D 5—The default configuration following reset is GPIO input PD5. When
configured as PD5, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal STD1 through the Port
D Control Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
1.10 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals
such as modems.
Table 1-14. Serial Communication Interface
State During
Reset
Signal Name
RXD
Type
Signal Description
1,2
Input
Ignored Input
Serial Receive Data—Receives byte-oriented serial data and transfers it to the
SCI Receive Shift Register.
PE0
Input or Output
Port E 0—The default configuration following reset is GPIO input PE0. When
configured as PE0, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal RXD through the Port E
Control Register.
TXD
PE1
Output
Ignored Input
Serial Transmit Data—Transmits data from the SCI Transmit Data Register.
Port E 1—The default configuration following reset is GPIO input PE1. When
configured as PE1, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal TXD through the Port E
Control Register.
Input or Output
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-13
Signals/Connections
Signal Name
Table 1-14. Serial Communication Interface (Continued)
State During
Type
Signal Description
1,2
Reset
SCLK
PE2
Input/Output
Ignored Input
Serial Clock—Provides the input or output clock used by the transmitter and/or
the receiver.
Input or Output
Port E 2—The default configuration following reset is GPIO input PE2. When
configured as PE2, signal direction is controlled through the Port E Direction
Register. The signal can be configured as an SCI signal SCLK through the Port
E Control Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
1.11 Timers
The DSP56311 has three identical and independent timers. Each timer can use internal or external clocking and can
either interrupt the DSP56311 after a specified number of events (clocks) or signal an external device after
counting a specific number of internal events.
Table 1-15. Triple Timer Signals
State During
Signal Name
TIO0
Type
Signal Description
1,2
Reset
Input or Output
Ignored Input
Ignored Input
Ignored Input
Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input. When
Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
The default mode after reset is GPIO input. TIO0 can be changed to output or
configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0).
TIO1
TIO2
Input or Output
Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an
external event counter or in measurement mode, TIO1 is used as input. When
Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used
as output.
The default mode after reset is GPIO input. TIO1 can be changed to output or
configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1).
Input or Output
Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an
external event counter or in measurement mode, TIO2 is used as input. When
Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used
as output.
The default mode after reset is GPIO input. TIO2 can be changed to output or
configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2).
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
2. The Wait processing state does not affect the signal state.
DSP56311 Technical Data, Rev. 8
1-14
Freescale Semiconductor
JTAG and OnCE Interface
1.12 JTAG and OnCE Interface
The DSP56300 family and in particular the DSP56311 support circuit-board test strategies based on the IEEE®
Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to
interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or
on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming
models, see the chapter on debugging support in the DSP56300 Family Manual.
Table 1-16. JTAG/OnCE Interface
Signal
Name
State During
Reset
Type
Signal Description
TCK
TDI
Input
Input
Input
Input
Test Clock—A test clock input signal to synchronize the JTAG test logic.
Test Data Input—A test data serial input signal for test instructions and data.
TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.
TDO
TMS
Output
Tri-stated
Test Data Output—A test data serial output signal for test instructions and
data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
Input
Input
Input
Input
Test Mode Select—Sequences the test controller’s state machine. TMS is
sampled on the rising edge of TCK and has an internal pull-up resistor.
TRST
DE
Test Reset—Initializes the test controller asynchronously. TRST has an
internal pull-up resistor. TRST must be asserted during and after power-up
(see EB610/D for details).
Input/ Output
Input
Debug Event—As an input, initiates Debug mode from an external command
controller, and, as an open-drain output, acknowledges that the chip has
entered Debug mode. As an input, DE causes the DSP56300 core to finish
executing the current instruction, save the instruction pipeline information,
enter Debug mode, and wait for commands to be entered from the debug
serial input line. This signal is asserted as an output for three clock cycles
when the chip enters Debug mode as a result of a debug request or as a result
of meeting a breakpoint condition. The DE has an internal pull-up resistor.
This signal is not a standard part of the JTAG TAP controller. The signal
connects directly to the OnCE module to initiate debug mode directly or to
provide a direct external indication that the chip has entered Debug mode. All
other interface with the OnCE module must occur through the JTAG port.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-15
Signals/Connections
DSP56311 Technical Data, Rev. 8
1-16
Freescale Semiconductor
Specifications
2
The DSP56311 is fabricated in high-density CMOS with transistor-transistor logic (TTL) compatible inputs and
outputs.
2.1 Maximum Ratings
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (for example, either GND or V ).
CC
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of
another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum specification is calculated using the worst
case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never
occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum
represents a condition that can never exist.
Table 2-1. Absolute Maximum Ratings
1
1, 2
Rating
Symbol
Value
Unit
Supply Voltage
VCC
VCCQH
VIN
–0.1 to 2.0
–0.3 to 4.0
V
V
Input/Output Supply Voltage
All input voltages
GND – 0.3 to VCCQH + 0.3
10
V
Current drain per pin excluding VCC and GND
Operating temperature range
Storage temperature
I
mA
°C
°C
TJ
–40 to +100
TSTG
–55 to +150
Notes: 1. GND = 0 V, VCC = 1.8 V 0.1 V, VCCQH = 3.3 V 0.3 V, TJ = –40°C to +100°C, CL = 50 pF
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the maximum rating may affect device reliability or cause permanent damage to the device.
3. Power-up sequence: During power-up, and throughout the DSP56311 operation, VCCQH voltage must always be higher or
equal to VCC voltage.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-1
Specifications
2.2 Thermal Characteristics
Table 2-2. Thermal Characteristics
MAP-BGA
Value
Thermal Resistance Characteristic
Symbol
Unit
Junction-to-ambient, natural convection, single-layer board (1s)1,2
Junction-to-ambient, natural convection, four-layer board (2s2p)1,3
Junction-to-ambient, @200 ft/min air flow, single layer board (1s)1,3
Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p)1,3
Junction-to-board4
RθJA
RθJMA
RθJMA
RθJMA
RθJB
49
26
39
22
14
5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case thermal resistance5
RθJC
Junction-to-package-top, natural convection6
Ψ
2
JT
Junction-to-package-top, @200 ft/min air flow6
Ψ
2
JT
Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
DSP56311 Technical Data, Rev. 8
2-2
Freescale Semiconductor
DC Electrical Characteristics
2.3 DC Electrical Characteristics
7
Table 2-3. DC Electrical Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Supply voltage:
•
•
Core (VCCQL) and PLL (VCCP
I/O (VCCQH, VCCA, VCCD, VCCC, VCCH, and VCCS
)
1.7
3.0
1.8
3.3
1.9
3.6
V
V
)
Input high voltage
•
•
D[0–23], BG, BB, TA
VIH
VIHP
2.0
2.0
—
—
VCCQH + 0.3
VCCQH + 0.3
V
V
MOD/IRQ1, RESET, PINIT/NMI and all
JTAG/ESSI/SCI/Timer/HI08 pins
EXTAL8
•
VIHX
0.8 × VCCQH
—
VCCQH
V
Input low voltage
•
•
•
D[0–23], BG, BB, TA, MOD/IRQ1, RESET, PINIT
All JTAG/ESSI/SCI/Timer/HI08 pins
EXTAL8
VIL
VILP
VILX
–0.3
–0.3
–0.3
—
—
—
0.8
0.8
V
V
V
0.2 × VCCQH
Input leakage current
IIN
–10
–10
—
—
10
10
µA
µA
High impedance (off-state) input current
(@ 2.4 V / 0.4 V)
ITSI
Output high voltage
VOH
•
•
TTL (IOH = –0.4 mA)5,7
2.4
CC – 0.01
—
—
—
—
V
V
CMOS (IOH = –10 µA)5
V
Output low voltage
VOL
•
•
TTL (IOL = 3.0 mA, open-drain pins IOL = 6.7 mA)5,7
—
—
—
—
0.4
0.01
V
V
CMOS (IOL = 10 µA)5
Internal supply current2:
•
•
•
In Normal mode
In Wait mode3
In Stop mode4
ICCI
ICCW
ICCS
—
—
—
150
7. 5
100
—
—
—
mA
mA
µA
PLL supply current
Input capacitance5
—
—
1
2.5
10
mA
pF
CIN
—
Notes: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
2. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all
inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see
Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark.
This reflects typical DSP applications. Typical internal supply current is measured with VCCQP = 3.3 V,
VCC = 1.8 V at TJ = 100°C.
3. To obtain these results, all inputs must be terminated (that is, not allowed to float). PLL and XTAL signals are disabled during
Stop state.
4. DC current in Stop mode is evaluated based on measurements. To obtain these results, all inputs not disconnected at Stop
mode must be terminated (that is, not allowed to float).
5. Periodically sampled and not 100 percent tested.
6. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
7. This characteristic does not apply to XTAL and PCAP.
8. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize
power consumption, the minimum VIHX should be no lower than
0.9 × VCCQH and the maximum VILX should be no higher than 0.1 × VCCQH
.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-3
Specifications
2.4 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.3 V
IL
and a V minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of
IH
Table 2-2. AC timing specifications, which are referenced to a device input signal, are measured in production with
respect to the 50 percent point of the respective input signal’s transition. DSP56311 output levels are measured
with the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.
OL
OH
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15
MHz and rated speed.
2.4.1 Internal Clocks
Table 2-4. Internal Clocks
Expression
Characteristics
Symbol
Min
Typ
Max
Internal operation frequency with PLL
enabled
f
f
—
(Ef × MF)/
(PDF × DF)
—
Internal operation frequency with PLL
disabled
—
Ef/2
—
Internal clock high period
•
•
With PLL disabled
With PLL enabled and MF ≤4
TH
—
ETC
—
—
0.49 × ETC
×
0.51 × ETC ×
PDF × DF/MF
0.47 × ETC
PDF × DF/MF
PDF × DF/MF
0.53 × ETC
PDF × DF/MF
•
With PLL enabled and MF > 4
×
—
×
Internal clock low period
•
•
With PLL disabled
With PLL enabled and
MF ≤4
With PLL enabled and
MF > 4
TL
—
ETC
—
—
0.49 × ETC
PDF × DF/MF
0.47 × ETC
×
0.51 × ETC
PDF × DF/MF
0.53 × ETC
×
•
×
—
×
PDF × DF/MF
PDF × DF/MF
Internal clock cycle time with PLL enabled
TC
—
ETC × PDF ×
—
DF/MF
Internal clock cycle time with PLL disabled
Instruction cycle time
TC
—
—
2 × ETC
—
—
ICYC
TC
Notes: 1. DF = Division Factor; Ef = External frequency; ETC = External clock cycle; MF = Multiplication Factor;
PDF = Predivision Factor; TC = internal clock cycle.
2. See the PLL and Clock Generation section in the DSP56300 Family Manual for a details on the PLL.
DSP56311 Technical Data, Rev. 8
2-4
Freescale Semiconductor
AC Electrical Characteristics
2.4.2 External Clock Operation
The DSP56311 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are
shown in Figure 2-1.
EXTAL
XTAL
Suggested Component Values:
f
OSC = 4 MHz
R
fOSC = 20 MHz
R = 680 kΩ ± 10%
C = 22 pF ± 20%
R = 680 kΩ± 10%
C = 56 pF ± 20%
Note: Make sure that in
the PCTL Register:
•
•
XTLD (bit 16) = 0
If fOSC > 200 kHz,
XTLR (bit 15) = 0
Calculations were done for a 4/20 MHz crystal
with the following parameters:
•
•
•
•
C
XTAL1
C
CLof 30/20 pF,
C0 of 7/6 pF,
series resistance of 100/20 Ω, and
drive level of 2 mW.
Fundamental Frequency
Crystal Oscillator
Figure 2-1. Crystal Oscillator Circuits
If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by
setting XTLD (PCTL Register bit 16 = 1—see the DSP56311 User’s Manual). The external square wave source
connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship
between the EXTAL input and the internal clock and CLKOUT.
VIHX
Midpoint
EXTAL
ETH
ETL
VILX
Note:
The midpoint is
0.5 (VIHX + VILX).
2
3
4
ETC
5
5
CLKOUT with
PLL disabled
7
CLKOUT with
PLL enabled
7
6a
6b
Figure 2-2. External Clock Timing
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-5
Specifications
Table 2-5. Clock Operation
Characteristics
Frequency of EXTAL (EXTAL Pin Frequency)
150 MHz
No.
Symbol
Min
Max
1
2
Ef
0
150.0
The rise and fall time of this external clock should be 3 ns maximum.
EXTAL input high1, 2
•
•
With PLL disabled (46.7%–53.3% duty cycle6)
With PLL enabled (42.5%–57.5% duty cycle6)
ETH
ETL
ETC
3.11 ns
2.83 ns
∞
157.0 µs
3
4
EXTAL input low1, 2
•
•
With PLL disabled (46.7%–53.3% duty cycle6)
With PLL enabled (42.5%–57.5% duty cycle6)
3.11 ns
2.83 ns
∞
157.0 µs
EXTAL cycle time2
•
•
With PLL disabled
With PLL enabled
6.67 ns
6.67 ns
∞
273.1 µs
5
6
Internal clock change from EXTAL fall with PLL disabled
4.3 ns
11.0 ns
1.8 ns
a.Internal clock rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or
4, PDF = 1, Ef > 15 MHz)3,5
0.0 ns
b. Internal clock falling edge from EXTAL falling edge with PLL enabled (MF ≤4, PDF
≠ 1, Ef / PDF > 15 MHz)3,5
1.8 ns
0.0 ns
4
7
Instruction cycle time = ICYC = TC
ICYC
(see Figure 2-4) (46.7%–53.3% duty cycle)
•
•
With PLL disabled
With PLL enabled
13.33 ns
6.7 ns
∞
8.53 µs
Notes: 1. Measured at 50 percent of the input transition.
2. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and maximum MF.
3. Periodically sampled and not 100 percent tested.
4. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.
5. The skew is not guaranteed for any other MF value.
6. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
2.4.3 Phase Lock Loop (PLL) Characteristics
Table 2-6. PLL Characteristics
150 MHz
Characteristics
Unit
Min
Max
Voltage Controlled Oscillator (VCO) frequency when PLL enabled
30
300
MHz
(MF × Ef × 2/PDF)
1
PLL external capacitor (PCAP pin to VCCP) (CPCAP
)
•
•
@ MF ≤4
@ MF > 4
(580 × MF) −100
830 × MF
(780 × MF) −140
1470 × MF
pF
pF
Note:
C
PCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP) computed using the appropriate expression
listed above.
DSP56311 Technical Data, Rev. 8
2-6
Freescale Semiconductor
AC Electrical Characteristics
2.4.4 Reset, Stop, Mode Select, and Interrupt Timing
6
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing
150 MHz
No.
Characteristics
Expression
Unit
Min
Max
8
9
Delay from RESET assertion to all pins at reset value3
Required RESET duration4
—
—
26.0
ns
Minimum:
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
•
•
•
•
•
•
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During STOP, XTAL disabled (PCTL Bit 16 = 0)
During STOP, XTAL enabled (PCTL Bit 16 = 1)
During normal operation
333.3
6.67
0.50
0.50
16.7
16.7
—
—
—
—
—
—
ns
µs
ms
ms
ns
2.5 × TC
ns
10
Delay from asynchronous RESET deassertion to first external address
output (internal reset deassertion)5
•
•
Minimum
Maximum
3.25 × TC + 2.0
20.25 × TC + 10
23.7
—
—
145.0
ns
ns
13
14
15
16
17
Mode select set-up time
30.0
0.0
6.6
6.6
—
—
—
—
ns
ns
ns
ns
Mode select hold time
Minimum edge-triggered interrupt request assertion width
Minimum edge-triggered interrupt request deassertion width
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
Minimum:
•
•
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
4.25 × TC + 2.0
7.25 × TC + 2.0
30.4
51.0
—
—
ns
ns
18
19
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
Minimum:
10 × TC + 5.0
72.0
—
—
ns
ns
ns
Delay from address output valid caused by first interrupt instruction
execute to interrupt request deassertion for level sensitive fast
interrupts1, 7, 8
Maximum:
(WS + 3.75) × TC – 10.94
Note 8
Note 8
20
21
Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
Maximum:
(WS + 3.25) × TC – 10.94
—
Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
Maximum:
•
•
•
•
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS ≥ 4
(WS + 3.5) × TC – 10.94
(WS + 3.5) × TC – 10.94
(WS + 3) × TC – 10.94
(WS + 2.5) × TC – 10.94
—
—
—
—
Note 8
Note 8
Note 8
Note 8
ns
ns
ns
ns
24
25
Duration for IRQA assertion to recover from Stop state
5.9
—
ns
Delay from IRQA assertion to fetch of first instruction (when exiting
Stop)2, 3
•
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is PLC × ETC × PDF + (128 K −
1.3
9.1
ms
enabled
PLC/2) × TC
(Operating Mode Register Bit 6 = 0)
•
•
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is PLC × ETC × PDF + (23.75 ± 232.5 ns 12.3 ms
not enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
Delay)
0.5) × TC
(8.25 ± 0.5) × TC
51.7
58.3
ns
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-7
Specifications
6
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
150 MHz
No.
Characteristics
Expression
Unit
Min
Max
26
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)2, 3
Minimum:
PLC × ETC × PDF + (128K −
PLC/2) × TC
•
•
•
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled
(Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
not enabled
(Operating Mode Register Bit 6 = 1)
13.6
12.3
36.7
—
—
—
ms
ms
ns
PLC × ETC × PDF +
(20.5 ± 0.5) × TC
PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)
5.5 × TC
27
28
29
Interrupt Request Rate
Maximum:
12 × TC
8 × TC
8 × TC
12 × TC
•
•
•
•
HI08, ESSI, SCI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
—
—
—
—
80.0
53.3
53.3
80.0
ns
ns
ns
ns
DMA Request Rate
Maximum:
6 × TC
7 × TC
2 × TC
3 × TC
•
•
•
•
Data read from HI08, ESSI, SCI
Data write to HI08, ESSI, SCI
Timer
—
—
—
—
40.0
46.7
13.3
20.0
ns
ns
ns
ns
IRQ, NMI (edge trigger)
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory (DMA source) access address out valid
Minimum:
4.25 × TC + 2.0
30.3
—
ns
Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended
when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode.
2. This timing depends on several settings:
• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL
Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the
Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set,
it is not recommended, and these specifications do not guarantee timings for that case.
• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no
stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).
• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the
PCTL Bit 17 and Operating Mode Register Bit 6 settings.
• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked.
The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in
parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter
completes count or PLL lock procedure completion.
• PLC value for PLL disable is 0.
• The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66
MHz = 62 µs). During the stabilization period, TC, TH, and TL is not constant, and their width may vary, so timing may vary as
well.
3. Periodically sampled and not 100 percent tested.
4. Value depends on clock source:
• For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is
active and valid.
• For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing
reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal
and other components connected to the oscillator and reflects worst case conditions.
• When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
5. If PLL does not lose lock.
6.
VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100°C, CL = 50 pF.
7. WS = number of wait states (measured in clock cycles, number of TC).
8. Use expression to compute maximum value.
DSP56311 Technical Data, Rev. 8
2-8
Freescale Semiconductor
AC Electrical Characteristics
VIH
RESET
9
10
8
All Pins
Reset Value
First Fetch
A[0–17]
Figure 2-3. Reset Timing
First Interrupt Instruction
Execution/Fetch
A[0–17]
RD
20
WR
21
17
19
IRQA, IRQB,
IRQC, IRQD,
NMI
a) First Interrupt Instruction Execution
General
Purpose
I/O
18
IRQA, IRQB,
IRQC, IRQD,
NMI
b) General-Purpose I/O
Figure 2-4. External Fast Interrupt Timing
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-9
Specifications
IRQA, IRQB,
IRQC, IRQD, NMI
15
16
IRQA, IRQB,
IRQC, IRQD, NMI
Figure 2-5. External Interrupt Timing (Negative Edge-Triggered)
VIH
RESET
13
14
VIH
VIH
MODA, MODB,
MODC, MODD,
PINIT
IRQA, IRQB,
IRQC, IRQD, NMI
VIL
VIL
Figure 2-6. Operating Mode Select Timing
24
IRQA
25
First Instruction Fetch
A[0–17]
Figure 2-7. Recovery from Stop State Using IRQA
26
IRQA
25
First IRQA Interrupt
Instruction Fetch
A[0–17]
Figure 2-8. Recovery from Stop State Using IRQA Interrupt Service
DSP56311 Technical Data, Rev. 8
2-10
Freescale Semiconductor
AC Electrical Characteristics
DMA Source Address
A[0–17]
RD
WR
29
IRQA, IRQB,
IRQC, IRQD,
NMI
First Interrupt Instruction Execution
Figure 2-9. External Memory Access (DMA Source) Timing
2.4.5 External Memory Expansion Port (Port A)
2.4.5.1 SRAM Timing
Table 2-8. SRAM Timing
150 MHz
Unit
1
No.
Characteristics
Symbol
Expression
Min
Max
100 Address valid and AA assertion pulse width2
101 Address and AA valid to WR assertion
102 WR assertion pulse width
tRC, tWC
(WS + 2) × TC −4.0
[2 ≤WS ≤7]
(WS + 3) × TC −4.0
22.7
ns
ns
69.3
—
[WS ≥ 8]
tAS
tWP
tWR
0.75 × TC – 3.0
[2 ≤WS ≤3]
1.25 × TC – 3.0
[WS ≥ 4]
2.0
5.3
—
—
ns
ns
WS × TC −4.0
[2 ≤WS ≤3]
(WS −0.5) × TC −4.0
[WS ≥ 4]
9.3
—
—
ns
ns
19.3
103 WR deassertion to address not valid
1.25 × TC −4.0
[2 ≤WS ≤7]
2.25 × TC −4.0
4.3
—
—
ns
ns
11.0
[WS ≥ 8]
104 Address and AA valid to input data valid
105 RD assertion to input data valid
t
AA, tAC
(WS + 0.75) × TC −6.5
[WS ≥ 2]
—
—
11.8
8.5
ns
ns
tOE
(WS + 0.25) × TC −6.5
[WS ≥ 2]
106 RD deassertion to data not valid (data hold time)
107 Address valid to WR deassertion2
tOHZ
tAW
0.0
—
—
ns
ns
(WS + 0.75) × TC −4.0
[WS ≥ 2]
14.3
108 Data valid to WR deassertion (data set-up time)
109 Data hold time from WR deassertion
tDS (tDW
tDH
)
(WS −0.25) × TC −5.4
[WS ≥ 2]
6.3
—
ns
1.25 × TC −4.0
[2 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
4.3
—
—
ns
ns
11.0
110 WR assertion to data active
—
0.25 × TC −4.0
[2 ≤WS ≤3]
–0.25 × TC −4.0
–2.4
–5.7
—
—
ns
ns
[WS ≥ 4]
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-11
Specifications
Table 2-8. SRAM Timing (Continued)
150 MHz
1
No.
Characteristics
Symbol
Expression
Unit
Min
Max
111 WR deassertion to data high impedance
112 Previous RD deassertion to data active (write)
113 RD deassertion time
—
1.25 × TC
[2 ≤WS ≤7]
2.25 × TC
[WS ≥ 8]
—
—
8.3
ns
ns
15.0
—
—
—
2.25 × TC −4.0
[2 ≤WS ≤7]
3.25 × TC −4.0
11.0
17.7
—
—
ns
ns
[WS ≥ 8]
1.75 × TC −4.0
[2 ≤WS ≤7]
2.75 × TC −4.0
[WS ≥ 8]
7.6
—
—
ns
ns
14.3
114 WR deassertion time4
1.5 × TC −4.0
[2 ≤WS ≤7]
2.5 × TC −4.0
[WS ≥ 8]
6.0
—
—
ns
ns
12.7
115 Address valid to RD assertion
116 RD assertion pulse width
—
—
—
0.5 × TC −2.8
0.5
11.0
4.3
—
—
—
ns
ns
ns
(WS + 0.25) × TC −4.0
117 RD deassertion to address not valid
1.25 × TC −4.0
[2 ≤WS ≤7]
2.25 × TC −4.0
[WS ≥ 8]
11.0
—
ns
118 TA set-up before RD or WR deassertion5
119 TA hold after RD or WR deassertion
—
—
0.25 × TC + 1.5
3.2
0
—
—
ns
ns
Notes: 1. WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example,
for a category of [2 ≤WS ≤7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise.
2. Timings 100 and107 are guaranteed by design, not tested.
3. All timings for 150 MHz are measured from 0.5 × VCCQH to 0.5 × VCCQH
.
4. The WS number applies to the access in which the deassertion of WR occurs and assumes the next access uses a minimal
number of wait states.
5. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.
DSP56311 Technical Data, Rev. 8
2-12
Freescale Semiconductor
AC Electrical Characteristics
100
A[0–17]
AA[0–3]
117
106
113
116
RD
105
WR
104
118
119
TA
Data
In
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-10. SRAM Read Access
100
A[0–17]
AA[0–3]
107
101
102
103
WR
RD
114
119
109
118
TA
108
Data
Out
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-11. SRAM Write Access
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-13
Specifications
2.4.5.2 DRAM Timing
The selection guides in Figure 2-12 and Figure 2-15 are for primary selection only. Final selection should be based
on the timing in the following tables. For example, the selection guide suggests that four wait states must be used
for 100 MHz operation with Page Mode DRAM. However, consulting the appropriate table, a designer can evaluate
whether fewer wait states might suffice by determining which timing prevents operation at 100 MHz, running the
chip at a slightly lower frequency (for example, 95 MHz), using faster DRAM (if it becomes available), and
manipulating control factors such as capacitive and resistive load to improve overall system performance.
Note:
This figure should be used for primary selection. For exact
and detailed timings, see the following tables.
DRAM type
(tRAC ns)
100
80
70
60
Chip frequency
(MHz)
50
120
40
66
80
100
1 Wait states
2 Wait states
3 Wait states
4 Wait states
Figure 2-12. DRAM Page Mode Wait State Selection Guide
1,2,3
Table 2-9. DRAM Page Mode Timings, Three Wait States
100 MHz
4
No.
Characteristics
Symbol
Expression
Unit
Min
Max
131 Page mode cycle time for two consecutive accesses of the same
direction
4 × TC
40.0
—
ns
Page mode cycle time for mixed (read and write) accesses
132 CAS assertion to data valid (read)
tPC
tCAC
tAA
3.5 × TC
2 × TC −5.7
3 × TC −5.7
35.0
—
—
ns
ns
ns
14.3
24.3
133 Column address valid to data valid (read)
—
DSP56311 Technical Data, Rev. 8
2-14
Freescale Semiconductor
AC Electrical Characteristics
1,2,3
Table 2-9. DRAM Page Mode Timings, Three Wait States
(Continued)
100 MHz
4
No.
Characteristics
Symbol
Expression
Unit
Min
Max
134 CAS deassertion to data not valid (read hold time)
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS deassertion
137 CAS assertion pulse width
tOFF
tRSH
tRHCP
tCAS
tCRP
0.0
—
—
—
—
ns
ns
ns
ns
2.5 × TC −4.0
4.5 × TC −4.0
2 × TC −4.0
21.0
41.0
16.0
138 Last CAS deassertion to RAS assertion5
•
•
•
BRW[1–0] = 00, 01—not applicable
BRW[1–0] = 10
BRW[1–0] = 11
—
—
41.5
61.5
—
—
—
—
ns
ns
4.75 × TC −6.0
6.75 × TC −6.0
139 CAS deassertion pulse width
tCP
tASC
tCAH
tRAL
tRCS
tRCH
tWCH
tWP
1.5 × TC −4.0
TC −4.0
11.0
6.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
2.5 × TC −4.0
4 × TC −4.0
21.0
36.0
8.5
—
—
1.25 × TC −4.0
0.75 × TC −4.0
2.25 × TC −4.2
3.5 × TC −4.5
3.75 × TC −4.3
3.25 × TC −4.3
0.5 × TC – 4.5
2.5 × TC −4.0
1.25 × TC −4.3
3.5 × TC −4.0
2.5 × TC −5.7
—
3.5
—
18.3
30.5
33.2
28.2
0.5
—
—
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
tRWL
tCWL
tDS
—
—
—
tDH
21.0
8.2
—
tWCS
tROH
tGA
—
31.0
—
—
19.3
—
154 RD deassertion to data not valid6
155 WR assertion to data active
tGZ
0.0
0.75 × TC – 1.5
0.25 × TC
6.0
—
156 WR deassertion to data high impedance
—
2.5
Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. The asynchronous delays specified in the expressions are valid for the DSP56311.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 ×
TC for read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or
maximum value listed, as appropriate.
5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-
access.
6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-15
Specifications
1,2,3
Table 2-10. DRAM Page Mode Timings, Four Wait States
100 MHz
4
No.
Characteristics
Symbol
Expression
Unit
Min
Max
131 Page mode cycle time for two consecutive accesses of the same
direction
5 × TC
50.0
—
ns
Page mode cycle time for mixed (read and write) accesses
132 CAS assertion to data valid (read)
tPC
tCAC
tAA
4.5 × TC
45.0
—
—
21.8
31.8
—
ns
ns
ns
ns
ns
ns
ns
2.75 × TC −5.7
3.75 × TC −5.7
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold time)
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS deassertion
137 CAS assertion pulse width
—
tOFF
tRSH
tRHCP
tCAS
tCRP
0.0
3.5 × TC −4.0
6 × TC −4.0
31.0
56.0
21.0
—
—
2.5 × TC −4.0
—
138 Last CAS deassertion to RAS assertion5
•
•
•
BRW[1–0] = 00, 01—Not applicable
BRW[1–0] = 10
BRW[1–0] = 11
—
—
46.5
66.5
—
—
—
—
ns
ns
5.25 × TC −6.0
7.25 × TC −6.0
139 CAS deassertion pulse width
tCP
tASC
tCAH
tRAL
tRCS
tRCH
tWCH
tWP
2 × TC −4.0
TC −4.0
16.0
6.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
3.5 × TC −4.0
5 × TC −4.0
31.0
46.0
8.5
—
—
1.25 × TC −4.0
1.25 × TC – 3.7
3.25 × TC −4.2
4.5 × TC −4.5
4.75 × TC −4.3
3.75 × TC −4.3
0.5 × TC – 4.5
3.5 × TC −4.0
1.25 × TC −4.3
4.5 × TC −4.0
3.25 × TC −5.7
—
8.8
—
28.3
40.5
43.2
33.2
0.5
—
—
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
tRWL
tCWL
tDS
—
—
—
tDH
31.0
8.2
—
tWCS
tROH
tGA
—
41.0
—
—
26.8
—
154 RD deassertion to data not valid6
155 WR assertion to data active
tGZ
0.0
0.75 × TC – 1.5
0.25 × TC
6.0
—
156 WR deassertion to data high impedance
—
2.5
Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. The asynchronous delays specified in the expressions are valid for the DSP56311.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals
3 × TC for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value
listed, as appropriate.
5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
.
DSP56311 Technical Data, Rev. 8
2-16
Freescale Semiconductor
AC Electrical Characteristics
RAS
CAS
136
131
135
137
139
138
142
140
151
141
Column
Address
Last Column
Address
Column
Address
Row
Add
A[0–17]
144
145
147
148
WR
RD
146
155
156
150
149
D[0–23]
Data Out
Data Out
Data Out
Figure 2-13. DRAM Page Mode Write Accesses
RAS
CAS
136
131
135
137
140
139
138
142
141
Last Column
Address
Row
Add
Column
Address
Column
Address
A[0–17]
WR
143
132
133
153
152
RD
134
154
D[0–23]
Data In
Data In
Data In
Figure 2-14. DRAM Page Mode Read Accesses
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-17
Specifications
DRAM Type
(tRAC ns)
Note:
This figure should be used for primary selection. For exact and
detailed timings, see the following tables.
100
80
70
60
Chip Frequency
(MHz)
50
120
40
66
80
100
4 Wait States
8 Wait States
11 Wait States
15 Wait States
Figure 2-15. DRAM Out-of-Page Wait State Selection Guide
1,2
Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States
100 MHz
3
No.
Characteristics
Symbol
Expression
Unit
Min
Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
tRC
tRAC
tCAC
tAA
12 × TC
120.0
—
—
55.5
30.5
38.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.25 × TC −7.0
3.75 × TC −7.0
4.5 × TC −7.0
—
—
tOFF
tRP
0.0
4.25 × TC −4.0
7.75 × TC −4.0
5.25 × TC −4.0
6.25 × TC −4.0
3.75 × TC −4.0
2.5 × TC ± 4.0
1.75 × TC ± 4.0
5.75 × TC −4.0
4.25 × TC – 6.0
4.25 × TC −4.0
38.5
73.5
48.5
58.5
33.5
21.0
13.5
53.5
36.5
38.5
—
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
—
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
—
—
—
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
29.0
21.5
—
—
171 Row address valid to RAS assertion
tASR
—
DSP56311 Technical Data, Rev. 8
2-18
Freescale Semiconductor
AC Electrical Characteristics
1,2
Table 2-11. DRAM Out-of-Page and Refresh Timings, Eleven Wait States
(Continued)
100 MHz
3
No.
Characteristics
Symbol
Expression
Unit
Min
Max
172 RAS assertion to row address not valid
173 Column address valid to CAS assertion
174 CAS assertion to column address not valid
175 RAS assertion to column address not valid
176 Column address valid to RAS deassertion
177 WR deassertion to CAS assertion
178 CAS deassertion to WR4 assertion
179 RAS deassertion to WR4 assertion
180 CAS assertion to WR deassertion
181 RAS assertion to WR deassertion
182 WR assertion pulse width
tRAH
tASC
tCAH
tAR
1.75 × TC −4.0
0.75 × TC −4.0
5.25 × TC −4.0
7.75 × TC −4.0
6 × TC −4.0
13.5
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
93.0
—
—
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
48.5
73.5
56.0
26.0
13.8
0.5
tRAL
tRCS
tRCH
tRRH
tWCH
tWCR
tWP
3.0 × TC −4.0
1.75 × TC – 3.7
0.25 × TC −2.0
5 × TC −4.2
45.8
70.8
110.5
113.2
98.2
53.5
48.5
73.5
60.7
11.0
23.5
111.0
—
7.5 × TC −4.2
11.5 × TC −4.5
11.75 × TC −4.3
10.25 × TC −4.3
5.75 × TC −4.0
5.25 × TC −4.0
7.75 × TC −4.0
6.5 × TC −4.3
1.5 × TC −4.0
2.75 × TC −4.0
11.5 × TC −4.0
10 × TC −7.0
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
186 CAS assertion to data not valid (write)
187 RAS assertion to data not valid (write)
188 WR assertion to CAS assertion
tRWL
tCWL
tDS
tDH
tDHR
tWCS
tCSR
tRPC
tROH
tGA
189 CAS assertion to RAS assertion (refresh)
190 RAS deassertion to CAS assertion (refresh)
191 RD assertion to RAS deassertion
192 RD assertion to data valid
193 RD deassertion to data not valid5
194 WR assertion to data active
tGZ
0.0
0.75 × TC – 1.5
0.25 × TC
6.0
195 WR deassertion to data high impedance
—
Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±± .
4. Either tRCH or tRRH must be satisfied for read cycles.
5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-19
Specifications
1,2
Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States
100 MHz
3
No.
Characteristics
Symbol
Expression
Unit
Min
Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
tRC
tRAC
tCAC
tAA
16 × TC
160.0
—
—
76.8
41.8
49.3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.25 × TC −5.7
4.75 × TC −5.7
5.5 × TC −5.7
0.0
—
—
tOFF
tRP
0.0
6.25 × TC −4.0
9.75 × TC −4.0
6.25 × TC −4.0
8.25 × TC −4.0
4.75 × TC −4.0
3.5 × TC ± 2
58.5
93.5
58.5
78.5
43.5
33.0
25.5
73.5
56.5
58.5
23.5
3.5
—
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tCP
—
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
—
—
—
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
37.0
29.5
—
2.75 × TC ± 2
7.75 × TC −4.0
6.25 × TC – 6.0
6.25 × TC −4.0
2.75 × TC −4.0
0.75 × TC −4.0
6.25 × TC −4.0
9.75 × TC −4.0
7 × TC −4.0
—
171 Row address valid to RAS assertion
172 RAS assertion to row address not valid
173 Column address valid to CAS assertion
174 CAS assertion to column address not valid
175 RAS assertion to column address not valid
176 Column address valid to RAS deassertion
177 WR deassertion to CAS assertion
178 CAS deassertion to WR4 assertion
179 RAS deassertion to WR4 assertion
180 CAS assertion to WR deassertion
181 RAS assertion to WR deassertion
182 WR assertion pulse width
tASR
tRAH
tASC
tCAH
tAR
—
—
—
58.5
93.5
66.0
46.2
13.8
0.5
—
—
tRAL
tRCS
tRCH
tRRH
tWCH
tWCR
tWP
—
5 × TC −3.8
—
1.75 × TC – 3.7
0.25 × TC −2.0
6 × TC −4.2
—
—
55.8
90.8
150.5
153.2
138.2
83.5
58.5
93.5
90.7
11.0
43.5
151.0
—
—
9.5 × TC −4.2
15.5 × TC −4.5
15.75 × TC −4.3
14.25 × TC −4.3
8.75 × TC −4.0
6.25 × TC −4.0
9.75 × TC −4.0
9.5 × TC −4.3
1.5 × TC −4.0
4.75 × TC −4.0
15.5 × TC −4.0
14 × TC −5.7
—
—
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
186 CAS assertion to data not valid (write)
187 RAS assertion to data not valid (write)
188 WR assertion to CAS assertion
tRWL
tCWL
tDS
—
—
—
tDH
—
tDHR
tWCS
tCSR
tRPC
tROH
tGA
—
—
189 CAS assertion to RAS assertion (refresh)
190 RAS deassertion to CAS assertion (refresh)
191 RD assertion to RAS deassertion
192 RD assertion to data valid
—
—
—
134.3
—
193 RD deassertion to data not valid5
tGZ
0.0
194 WR assertion to data active
0.75 × TC – 1.5
0.25 × TC
6.0
—
195 WR deassertion to data high impedance
—
2.5
Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±± .
4. Either tRCH or tRRH must be satisfied for read cycles.
5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
.
DSP56311 Technical Data, Rev. 8
2-20
Freescale Semiconductor
AC Electrical Characteristics
157
163
162
162
165
RAS
167
168
164
169
170
166
CAS
171
173
174
175
Row Address
172
Column Address
176
A[0–17]
177
179
191
WR
RD
178
160
159
193
161
158
192
Data
In
D[0–23]
Figure 2-16. DRAM Out-of-Page Read Access
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-21
Specifications
157
162
163
162
165
RAS
167
164
169
168
170
166
CAS
173
172
171
174
176
Row Address
Column Address
A[0–17]
181
175
188
180
182
WR
184
183
187
RD
186
195
185
194
D[0–23]
Data Out
Figure 2-17. DRAM Out-of-Page Write Access
157
162
162
163
RAS
190
170
177
165
189
CAS
WR
Figure 2-18. DRAM Refresh Access
DSP56311 Technical Data, Rev. 8
2-22
Freescale Semiconductor
AC Electrical Characteristics
2.4.5.3 Asynchronous Bus Arbitration Timings
Table 2-13. Asynchronous Bus Timings
150 MHz
No.
Characteristics
Expression
Unit
Min
Max
250
251
BB assertion window from BG input deassertion.
Delay from BB assertion to BG assertion
2.5 × Tc + 5
2 × Tc + 5
—
22
—
ns
ns
18.3
Notes: 1. Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.
2. At 150 MHz, Asynchronous Arbitration mode is recommended.
3. To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300
devices (on the same bus), as shown in Figure 2-19, where BG1 is the BG signal for one DSP56300 device while BG2 is the
BG signal for a second DSP56300 device.
BG1
BB
250
BG2
251
250+251
Figure 2-19. Asynchronous Bus Arbitration Timing
The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the
reason for timing 250.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other
DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG
is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.
Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251
ensures that overlaps are avoided.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-23
Specifications
2.4.6 Host Interface Timing
1,2,12
Table 2-14. Host Interface Timings
150 MHz
10
No.
Characteristic
Expression
Unit
Min
Max
317 Read data strobe assertion width5
HACK assertion width
TC + 6.5
13.1
—
ns
ns
ns
318 Read data strobe deassertion width5
HACK deassertion width
6.5
—
—
319 Read data strobe deassertion width5 after “Last Data Register” reads8,11, or
between two consecutive CVR, ICR, or ISR reads3
2.5 × TC + 4.4
20.8
HACK deassertion width after “Last Data Register” reads8,11
320 Write data strobe assertion width6
—
ns
8.7
321 Write data strobe deassertion width8
HACK write deassertion width
•
after ICR, CVR and “Last Data Register” writes
2.5 × TC + 4.4
20.8
10.9
—
—
ns
ns
•
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND= 0), or
after TXL:TXM:TXH writes (with HLEND = 1)
322 HAS assertion width
6.5
0.0
6.5
2.2
2.2
—
—
—
—
—
ns
ns
ns
ns
ns
323 HAS deassertion to data strobe assertion4
324 Host data input set-up time before write data strobe deassertion6
325 Host data input hold time after write data strobe deassertion6
326 Read data strobe assertion to output data active from high impedance5
HACK assertion to output data active from high impedance
327 Read data strobe assertion to output data valid5
HACK assertion to output data valid
—
—
16.5
6.5
—
ns
ns
ns
328 Read data strobe deassertion to output data high impedance5
HACK deassertion to output data high impedance
329 Output data hold time after read data strobe deassertion5
Output data hold time after HACK deassertion
2.2
330 HCS assertion to read data strobe deassertion5
331 HCS assertion to write data strobe deassertion6
332 HCS assertion to output data valid
TC + 6.5
13.1
6.5
—
—
—
ns
ns
ns
ns
ns
ns
13.0
—
333 HCS hold time after data strobe deassertion4
0.0
3.0
2.2
334 Address (HAD[0–7]) set-up time before HAS deassertion (HMUX=1)
335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1)
—
—
336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W set-up time before data strobe
assertion4
•
•
Read
Write
0
3.0
—
—
ns
ns
337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe
deassertion4
2.2
—
—
—
ns
ns
ns
338 Delay from read data strobe deassertion to host request assertion for “Last Data
Register” read5, 7, 8
TC + 3.5
10.1
13.4
339 Delay from write data strobe deassertion to host request assertion for “Last Data
Register” write6, 7, 8
1.5 × TC + 3.5
DSP56311 Technical Data, Rev. 8
2-24
Freescale Semiconductor
AC Electrical Characteristics
1,2,12
Table 2-14. Host Interface Timings
(Continued)
150 MHz
Unit
10
No.
Characteristic
Expression
Min
Max
340 Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=0)4, 7, 8
—
13.0
ns
ns
341 Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=1, open drain host request)4, 7, 8, 9
—
300.0
Notes: 1. See the Programmer’s Model section in the chapter on the HI08 in the DSP56311 User’s Manual.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. This timing is applicable only if two consecutive reads from one of these registers are executed.
4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the
Single Data Strobe mode.
5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.
8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the
Little Endian mode (HLEND = 1).
9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.
10. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.
12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc).
317
318
HACK
328
327
329
326
H[0–7]
HREQ
Figure 2-20. Host Interrupt Vector Register (IVR) Read Timing Diagram
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-25
Specifications
HA[2–0]
336
337
333
337
330
HCS
HRW
HDS
336
317
318
328
332
327
319
329
326
341
H[7–0]
338
340
HREQ (single host request)
HRRQ (double host request)
Figure 2-21. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe
HA[2–0]
336
337
333
330
HCS
HRD
317
318
328
332
327
319
329
326
341
H[7–0]
338
340
HREQ (single host request)
HRRQ (double host request)
Figure 2-22. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe
DSP56311 Technical Data, Rev. 8
2-26
Freescale Semiconductor
AC Electrical Characteristics
HA[2–0]
336
337
333
337
331
HCS
HRW
HDS
336
320
321
324
325
H[7–0]
339
340
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-23. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe
HA[2–0]
336
337
333
331
HCS
320
HWR
321
324
325
H[7–0]
339
340
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-24. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-27
Specifications
,
HA[10–8]
336
337
322
HAS
323
336
337
HRW
HDS
317
334
318
319
335
327
328
329
HAD[7–0]
Address
Data
326
338
340
341
HREQ (single host request)
HRRQ (double host request)
Figure 2-25. Read Timing Diagram, Multiplexed Bus, Single Data Strobe
HA[10–8]
336
337
322
HAS
323
317
HRD
334
318
319
335
327
328
329
HAD[7–0]
Address
Data
326
338
340
341
HREQ (single host request)
HRRQ (double host request)
Figure 2-26. Read Timing Diagram, Multiplexed Bus, Double Data Strobe
DSP56311 Technical Data, Rev. 8
2-28
Freescale Semiconductor
AC Electrical Characteristics
HA[10–8]
336
337
337
322
HAS
HRW
HDS
323
336
320
334
324
321
325
335
HAD[7–0]
Data
340
Address
339
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-27. Write Timing Diagram, Multiplexed Bus, Single Data Strobe
,
HA[10–8]
336
337
322
HAS
323
320
HWR
334
324
321
325
335
HAD[7–0]
Data
340
Address
339
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-28. Write Timing Diagram, Multiplexed Bus, Double Data Strobe
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-29
Specifications
2.4.7 SCI Timing
Table 2-15. SCI Timings
150 MHz
1
No.
Characteristics
Symbol
Expression
Unit
Min
Max
2
400 Synchronous clock cycle
401 Clock low period
tSCC
8 × TC
53.3
16.7
16.7
6.7
—
—
—
—
ns
ns
ns
ns
tSCC/2 −10.0
402 Clock high period
tSCC/2 −10.0
403 Output data set-up to clock falling edge (internal
clock)
t
SCC/4 + 0.5 × TC −10.0
404 Output data hold after clock rising edge (internal
clock)
tSCC/4 −0.5 × TC
10.0
41.7
—
—
—
ns
ns
ns
ns
ns
ns
ns
405 Input data set-up time before clock rising edge
(internal clock)
tSCC/4 + 0.5 × TC + 25.0
406 Input data not valid before clock rising edge
(internal clock)
t
SCC/4 + 0.5 × TC −5.5
11.5
32.0
—
407 Clock falling edge to output data valid (external
clock)
—
408 Output data hold after clock rising edge (external
clock)
TC + 8.0
14.7
0.0
409 Input data set-up time before clock rising edge
(external clock)
—
410 Input data hold time after clock rising edge
(external clock)
9.0
—
3
411 Asynchronous clock cycle
412 Clock low period
tACC
64 × TC
427.0
203.5
203.5
183.5
—
—
—
—
ns
ns
ns
ns
t
t
ACC/2 −10.0
ACC/2 −10.0
413 Clock high period
414 Output data set-up to clock rising edge (internal
clock)
tACC/2 −30.0
415 Output data hold after clock rising edge (internal
clock)
t
ACC/2 −30.0
183.5
—
ns
Notes: 1. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
2. tSCC = synchronous clock cycle time (for internal clock, tSCC is determined by the SCI clock control register and TC).
3. ACC = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, tACC is determined by the SCI clock
control register and TC).
t
DSP56311 Technical Data, Rev. 8
2-30
Freescale Semiconductor
AC Electrical Characteristics
400
402
404
401
SCLK
(Output)
403
Data Valid
405
TXD
RXD
406
Data
Valid
a) Internal Clock
400
402
401
SCLK
(Input)
407
408
TXD
RXD
Data Valid
409
410
Data Valid
b) External Clock
Figure 2-29. SCI Synchronous Mode Timing
411
413
415
412
1X SCLK
(Output)
414
TXD
Data Valid
Figure 2-30. SCI Asynchronous Mode Timing
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-31
Specifications
2.4.8 ESSI0/ESSI1 Timing
Table 2-16. ESSI Timings
150 MHz
Cond-
ition
4, 6
No.
Characteristics
Symbol
Expression
Unit
5
Min Max
430 Clock cycle1
tSSICC
6 × TC
8 × TC
40.0
53.4
—
—
x ck
i ck
ns
ns
431 Clock high period
•
•
For internal clock
For external clock
4 × TC −10.0
3 × TC
16.7
20.0
—
—
ns
ns
432 Clock low period
•
•
For internal clock
For external clock
4 × TC −10.0
3 × TC
16.7
20.0
—
—
ns
ns
433 RXC rising edge to FSR out (bit-length) high
434 RXC rising edge to FSR out (bit-length) low
435 RXC rising edge to FSR out (word-length-relative) high2
—
—
37.0
22.0
x ck
i ck a
ns
ns
ns
—
—
37.0
22.0
x ck
i ck a
—
—
39.0
37.0
x ck
i ck a
436 RXC rising edge to FSR out (word-length-relative) low2
437 RXC rising edge to FSR out (word-length) high
438 RXC rising edge to FSR out (word-length) low
—
—
39.0
37.0
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
36.0
21.0
x ck
i ck a
—
—
37.0
22.0
x ck
i ck a
439 Data in set-up time before RXC (SCK in Synchronous mode)
falling edge
—
—
x ck
i ck
10.0
19.0
440 Data in hold time after RXC falling edge
5.0
3.0
—
—
x ck
i ck
441 FSR input (bl, wr)6 high before RXC falling edge2
442 FSR input (wl)6 high before RXC falling edge
443 FSR input hold time after RXC falling edge
444 Flags input set-up before RXC falling edge
445 Flags input hold time after RXC falling edge
446 TXC rising edge to FST out (bit-length) high
447 TXC rising edge to FST out (bit-length) low
448 TXC rising edge to FST out (word-length-relative) high2
449 TXC rising edge to FST out (word-length-relative) low2
450 TXC rising edge to FST out (word-length) high
1.0
23.0
—
—
x ck
i ck a
—
—
x ck
i ck a
3.5
23.0
3.0
0.0
—
—
x ck
i ck a
—
—
x ck
i ck s
5.5
19.0
6.0
0.0
—
—
x ck
i ck s
—
—
29.0
15.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
—
—
31.0
17.0
x ck
i ck
—
—
33.0
19.0
x ck
i ck
—
—
30.0
16.0
x ck
i ck
DSP56311 Technical Data, Rev. 8
2-32
Freescale Semiconductor
AC Electrical Characteristics
Table 2-16. ESSI Timings (Continued)
150 MHz
Cond-
4, 6
No.
Characteristics
Symbol
Expression
Unit
5
ition
Min Max
451 TXC rising edge to FST out (word-length) low
452 TXC rising edge to data out enable from high impedance
453 TXC rising edge to transmitter 0 drive enable assertion
454 TXC rising edge to data out valid
—
—
31.0
17.0
x ck
i ck
ns
ns
ns
ns
ns
ns
ns
—
—
31.0
17.0
x ck
i ck
—
—
34.0
20.0
x ck
i ck
35 + 0.5 × TC
—
—
38.4
21.0
x ck
i ck
455 TXC rising edge to data out high impedance3
456 TXC rising edge to transmitter 0 drive enable deassertion3
457 FST input (bl, wr)6 set-up time before TXC falling edge2
—
—
31.0
16.0
x ck
i ck
—
—
34.0
20.0
x ck
i ck
2.0
21.0
—
—
x ck
i ck
458 FST input (wl)6 to data out enable from high impedance
459 FST input (wl) to transmitter 0 drive enable assertion
460 FST input (wl)6 set-up time before TXC falling edge
—
—
27.0
31.0
—
—
ns
ns
ns
—
—
x ck
i ck
2.5
21.0
461 FST input hold time after TXC falling edge
462 Flag output valid after TXC rising edge
4.0
0.0
—
—
x ck
i ck
ns
ns
—
—
32.0
18.0
x ck
i ck
Notes: 1. For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and
the ESSI Control Register.
2. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform,
but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last
bit clock of the first word in the frame.
3. Periodically sampled and not 100 percent tested
4. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.
5. TXC (SCK Pin) = transmit clock
RXC (SC0 or SCK pin) = receive clock
FST (SC2 pin) = transmit frame sync
FSR (SC1 or SC2 pin) receive frame sync
6. i ck = Internal Clock; x ck = external clock
i ck a = internal clock, Asynchronous mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = internal clock, Synchronous mode (synchronous implies that TXC and RXC are the same clock)
bl = bit length
wl = word length
wr = word length relative
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-33
Specifications
430
431
432
TXC
(Input/
Output)
446
447
FST (Bit)
Out
450
451
FST (Word)
Out
454
452
454
455
First Bit
Last Bit
Data Out
459
Transmitter 0
Drive
Enable
457
453
456
461
FST (Bit) In
458
461
460
FST (Word)
In
462
See Note
Flags Out
Note:
In Network mode, output flag transitions can occur at the start of each time slot within the frame. In
Normal mode, the output flag state is asserted for the entire frame period.
Figure 2-31. ESSI Transmitter Timing
DSP56311 Technical Data, Rev. 8
2-34
Freescale Semiconductor
AC Electrical Characteristics
430
431
RXC
(Input/
432
Output)
433
434
FSR (Bit)
Out
437
438
FSR
(Word)
Out
440
439
Last Bit
First Bit
Data In
443
441
FSR (Bit)
In
443
445
442
FSR
(Word)
In
444
Flags In
Figure 2-32. ESSI Receiver Timing
2.4.9 Timer Timing
Table 2-17. Timer Timing
150 MHz
Unit
No.
Characteristics
Expression
Min
Max
480
481
2 × TC + 2.0
2 × TC + 2.0
15.4
15.4
—
—
ns
ns
TIO Low
TIO High
Note:
VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
TIO
480
481
Figure 2-33. TIO Timer Event Input Restrictions
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-35
Specifications
2.4.10 Considerations For GPIO Use
2.4.10.1 Operating Frequency of 100 MHz or Less
Table 2-18. GPIO Timing
100 MHz
No.
Characteristics
Expression
Unit
Min
Max
490
—
0.0
8.5
0.0
67.5
8.5
—
—
—
—
ns
ns
ns
ns
ns
CLKOUT edge to GPIO out valid (GPIO out delay time)
491 CLKOUT edge to GPIO out not valid (GPIO out hold time)
492 GPIO In valid to CLKOUT edge (GPIO in set-up time)
493 CLKOUT edge to GPIO in not valid (GPIO in hold time)
494 Fetch to CLKOUT edge before GPIO change
Minimum: 6.75 × TC
Note:
VCC = 3.3 V ± 0.3 V; TJ = −40°C to +100 °C, CL = 50 pF.
CLKOUT
(Output)
490
491
GPIO
(Output)
492
493
GPIO
(Input)
Valid
A[0–17]
494
Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO
and R0 contains the address of the GPIO data register.
Figure 2-34. GPIO Timing
DSP56311 Technical Data, Rev. 8
2-36
Freescale Semiconductor
AC Electrical Characteristics
2.4.10.2 With an Operating Frequency above 100 MHz
The following considerations can be helpful when GPIO is used for output or input with an operating frequency
above 100 MHz (that is, when CLKOUT is not available).
•
GPIO as Output:
— The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core
clock cycles. This is true, assuming that the instruction is a one-cycle instruction and that there are no
pipeline stalls or any other pipeline delays.
— The maximum rise or fall time of a GPIO pin is 13 ns (TTL levels, assuming that the maximum of 50
pF load limit is met).
•
GPIO as Input—GPIO inputs are not synchronized with the core clock. When only one GPIO bit is polled,
this lack of synchronization presents no problem, since the read value can be either the previous value or
the new value of the corresponding GPIO pin. However, there is the risk of reading an intermediate state if:
— Two or more GPIO bits are treated as a coupled group (for example, four possible status states encoded
in two bits).
— The read operation occurs during a simultaneous change of GPIO pins (for example, the change of 00
to 11 may happen through an intermediate state of 01 or 10).
Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two
consecutive read operations have identical results.
2.4.11 JTAG Timing
Table 2-19. JTAG Timing
All frequencies
Min Max
No.
Characteristics
Unit
500
501
502
503
504
505
506
507
508
509
510
511
512
513
TCK frequency of operation (1/(TC × 3); maximum 22 MHz)
TCK cycle time in Crystal mode
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
0.0
45.0
20.0
0.0
22.0
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
3.0
—
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
5.0
24.0
0.0
—
40.0
40.0
—
TCK low to output high impedance
TMS, TDI data set-up time
0.0
5.0
TMS, TDI data hold time
25.0
0.0
—
TCK low to TDO data valid
44.0
44.0
—
TCK low to TDO high impedance
TRST assert time
0.0
100.0
40.0
TRST set-up time to TCK low
—
Notes: 1. VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.
2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-37
Specifications
501
502
VM
502
VM
VIH
TCK
(Input)
VIL
503
503
Figure 2-35. Test Clock Input Timing Diagram
VIH
TCK
(Input)
VIL
504
505
Data
Inputs
Input Data Valid
506
507
506
Data
Outputs
Output Data Valid
Data
Outputs
Data
Outputs
Output Data Valid
Figure 2-36. Boundary Scan (JTAG) Timing Diagram
VIH
TCK
(Input)
VIL
509
508
Input Data Valid
TDI
TMS
(Input)
510
TDO
(Output)
Output Data Valid
511
TDO
(Output)
510
TDO
(Output)
Output Data Valid
Figure 2-37. Test Access Port Timing Diagram
DSP56311 Technical Data, Rev. 8
2-38
Freescale Semiconductor
AC Electrical Characteristics
TCK
(Input)
513
TRST
(Input)
512
Figure 2-38. TRST Timing Diagram
2.4.12 OnCE Module TimIng
Table 2-20. OnCE Module Timing
150 MHz
Unit
No.
Characteristics
Expression
Min
Max
500 TCK frequency of operation
Max 22.0 MHz
1.5 × TC + 10.0
5.5 × TC + 30.0
0.0
20.0
—
22.0
—
MHz
ns
514 DE assertion time in order to enter Debug mode
515 Response time when DSP56311 is executing NOP instructions from
internal memory
67.0
ns
516 Debug acknowledge assertion time
3 × TC + 5.0
25.0
—
ns
Note:
VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF
DE
514
515
516
Figure 2-39. OnCE—Debug Request
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-39
Specifications
DSP56311 Technical Data, Rev. 8
2-40
Freescale Semiconductor
Packaging
3
This section includes diagrams of the DSP56311 package pin-outs and tables showing how the signals described in
Chapter 1 are allocated for the package. The DSP56311 is available in a 196-pin molded array plastic-ball grid
array (MAP-BGA) package.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
3-1
Packaging
3.1 Package Description
Top and bottom views of the MAP-BGA packages are shown in Figure 3-1 and Figure 3-2 with their pin-outs.
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
NC
SC11
TMS
TDO
IRQB
D23
V
D19
D16
D14
D11
D9
D7
NC
CCD
SRD1
SC02
PINIT
STD0
RXD
SC12
STD1
SC01
TDI
TCK
DE
TRST IRQD
IRQA IRQC
D21
D22
D20
D17
D18
D15
D13
D12
D10
D8
D6
D5
D3
NC
D4
V
V
V
CCD
C
CCQL
CCD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EXTAL
CAS
XTAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
BCLK
BCLK
TA
GND
D1
D2
V
D
E
F
CCD
V
SRD0
SC00
TXD
SCK0
HDS
TIO2
TIO0
HA0
H4
GND
GND
GND
GND
GND
GND
GND
GND
GND
WR
BR
A17
A16
A14
D0
CCS
SC10
SCLK
V
A15
A12
A11
A9
CCQH
A13
G
SCK1
GND
V
CCQL
V
V
GND
V
A10
H
J
CCQH
CCQL
CCA
HACK
HRW
GND
A8
A7
A5
K
V
HREQ
TIO1
HA2
H7
GND
V
A6
CCS
CCA
HCS
HA1
H6
GND
V
A3
A4
L
CCA
M
CLKOUT
V
V
V
RD
A1
A2
CCH
CCP
CCQH
AA3
N
P
H2
RESET GND
V
V
AA0
BG
A0
P
CCQL
CCC
NC
H5
H3
H1
PCAP GND
AA2
V
BB
AA1
NC
P1
CCC
Figure 3-1. DSP56311 MAP-BGA Package, Top View
DSP56311 Technical Data, Rev. 8
3-2
Freescale Semiconductor
Package Description
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
NC
D7
D9
D11
D14
D16
D19
V
D23
IRQB
TDO
TMS
SC11
NC
CCD
NC
D4
D5
D3
D8
D6
D10
D13
D12
D15
D17
D18
D20
D21
D22
IRQD TRST
IRQC IRQA
TDI
TCK
DE
SC12
STD1
SC01
SRD1
SC02
PINIT
STD0
RXD
V
V
V
CCQL
C
CCD
CCD
V
D2
D1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EXTAL
CAS
XTAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H0
GND
GND
GND
GND
GND
GND
GND
GND
D
E
F
CCD
D0
A16
A14
A17
GND
GND
GND
GND
GND
GND
GND
WR
BR
GND
GND
GND
GND
GND
GND
GND
SRD0
SC00
TXD
SCK0
HDS
TIO2
TIO0
HA0
H4
V
CCS
A15
A12
A11
A9
V
SC10
SCLK
CCQH
G
V
A13
SCK1
CCQL
A10
V
V
V
CCQH
H
J
CCA
A8
CCQL
A7
A5
HRW
HACK
K
A6
V
HREQ
TIO1
HA2
H7
V
CCS
CCA
CCA
A4
A3
V
HCS
HA1
H6
L
M
A2
A1
RD
V
V
V
BCLK CLKOUT
CCQH
CCP
CCH
H2
N
P
A0
AA0
BG
V
V
AA3
GND
RESET
PCAP
BCLK
TA
CCC
CCQL
P
NC
AA1
BB
V
AA2
GND
H1
H3
H5
NC
CCC
P1
Figure 3-2. DSP56311 MAP-BGA Package, Bottom View
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
3-3
Packaging
Table 3-1. Signal List by Ball Number
Ball
No.
Ball
Ball
No.
Signal Name
Signal Name
No.
Signal Name
A1
A2
Not Connected (NC), reserved
B12
B13
B14
C1
D8
D9
D10
D11
D12
D13
D14
E1
GND
GND
GND
D1
SC11 or PD1
TMS
D5
A3
NC
A4
TDO
SC02 or PC2
STD1 or PD5
TCK
A5
MODB/IRQB
D23
C2
D2
A6
C3
VCCD
A7
VCCD
C4
MODA/IRQA
MODC/IRQC
D22
STD0 or PC5
VCCS
A8
D19
C5
E2
A9
D16
C6
E3
SRD0 or PC4
GND
A10
A11
A12
A13
A14
B1
D14
C7
VCCQL
D18
E4
D11
C8
E5
GND
D9
C9
VCCD
E6
GND
D7
C10
C11
C12
C13
C14
D1
D12
E7
GND
NC
VCCD
E8
GND
SRD1 or PD4
SC12 or PD2
TDI
D6
E9
GND
B2
D3
E10
E11
E12
E13
E14
F1
GND
B3
D4
GND
B4
TRST
MODD/IRQD
D21
PINIT/NMI
SC01 or PC1
DE
A17
B5
D2
A16
B6
D3
D0
B7
D20
D4
GND
RXD or PE0
SC10 or PD0
SC00 or PC0
GND
B8
D17
D5
GND
F2
B9
D15
D6
GND
F3
B10
B11
D13
D7
GND
F4
D10
D8
GND
F5
GND
DSP56311 Technical Data, Rev. 8
3-4
Freescale Semiconductor
Package Description
Signal Name
Table 3-1. Signal List by Ball Number (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
F6
F7
F8
GND
GND
GND
H3
H4
H5
SCK0 or PC3
J14
K1
A9
GND
GND
VCCS
K2
HREQ/HREQ,
HTRQ/HTRQ, or PB14
F9
F10
F11
F12
F13
F14
G1
GND
GND
GND
VCCQH
A14
H6
H7
GND
GND
GND
GND
GND
GND
VCCA
A10
K3
K4
TIO2
GND
GND
GND
GND
GND
GND
GND
GND
VCCA
H8
K5
H9
K6
H10
H11
H12
H13
H14
J1
K7
A15
K8
SCK1 or PD3
SCLK or PE2
TXD or PE1
GND
K9
G2
K10
K11
K12
G3
A11
G4
HACK/HACK,
HRRQ/HRRQ, or PB15
G5
G6
GND
GND
GND
GND
GND
GND
GND
A13
J2
J3
HRW, HRD/HRD, or PB11
K13
K14
L1
A5
HDS/HDS, HWR/HWR, or PB12
A6
G7
J4
GND
GND
GND
GND
GND
GND
GND
GND
A8
HCS/HCS, HA10, or PB13
G8
J5
L2
TIO1
TIO0
GND
GND
GND
GND
GND
GND
GND
G9
J6
L3
G10
G11
G12
G13
G14
H1
J7
L4
J8
L5
J9
L6
VCCQL
A12
J10
J11
J12
J13
L7
L8
VCCQH
VCCQL
L9
H2
A7
L10
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
3-5
Packaging
Table 3-1. Signal List by Ball Number (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
L11
L12
L13
L14
M1
GND
M13
M14
N1
A1
A2
P1
P2
NC
VCCA
A3
H5, HAD5, or PB5
H6, HAD6, or PB6
H7, HAD7, or PB7
H4, HAD4, or PB4
H2, HAD2, or PB2
RESET
P3
H3, HAD3, or PB3
A4
N2
P4
H1, HAD1, or PB1
HA1, HA8, or PB9
HA2, HA9, or PB10
HA0, HAS/HAS, or PB8
VCCH
N3
P5
PCAP
GNDP1
AA2/RAS2
XTAL
VCCC
TA
M2
N4
P6
M3
N5
P7
M4
N6
GNDP
P8
M5
H0, HAD0, or PB0
VCCP
N7
AA3/RAS3
CAS
P9
M6
N8
P10
P11
P12
P13
P14
M7
VCCQH
N9
VCCQL
BB
M8
EXTAL
N10
N11
N12
N13
N14
BCLK2
AA1/RAS1
BG
M9
CLKOUT2
BCLK2
BR
M10
M11
M12
VCCC
NC
WR
AA0/RAS0
A0
RD
Notes: 1. Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a
signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as
interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars,
such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate
the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode,
data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike in
the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink
for the chip. Therefore, except for GNDP and GNDP1 that support the PLL, other GND signals do not support individual
subsystems in the chip.
2. CLKOUT, BCLK, and BCLK are available only if the operating frequency is ≤100 MHz.
DSP56311 Technical Data, Rev. 8
3-6
Freescale Semiconductor
Package Description
Ball
Table 3-2. Signal List by Signal Name
Ball
No.
Ball
Signal Name
Signal Name
No.
Signal Name
No.
A0
A1
N14
M13
H13
H14
G14
G12
F13
F14
E13
E12
M14
L13
L14
K13
K14
J13
J12
J14
N13
P12
P7
BR
CAS
CLKOUT
D0
N11
N8
D9
DE
A12
D3
M8
D4
D5
D6
D7
D8
D9
D10
D11
E4
A10
A11
A12
A13
A14
A15
A16
A17
A2
M9
EXTAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E14
D12
B11
A11
C10
B10
A10
B9
D1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
A3
A9
A4
B8
E5
A5
C8
E6
A6
A8
E7
A7
D13
B7
E8
A8
D20
D21
D22
D23
D3
E9
A9
B6
E10
E11
F4
AA0
AA1
AA2
AA3
BB
C6
A6
C13
C14
B13
C12
A13
B12
F5
N7
D4
F6
P11
M10
N10
P13
D5
F7
BCLK
BCLK
BG
D6
F8
D7
F9
D8
F10
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
3-7
Packaging
Table 3-2. Signal List by Signal Name (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
H5
H6
H7
H8
H9
H10
H11
J4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDP
GNDP1
H0
K4
K5
K6
K7
K8
K9
K10
K11
L4
H7
HA0
N2
M3
M1
L1
HA1
HA10
HA2
M2
M1
M2
J1
HA8
HA9
HACK/HACK
HAD0
M5
P4
N4
P3
N3
P2
N1
N2
M3
L1
L5
HAD1
L6
HAD2
L7
HAD3
L8
HAD4
L9
HAD5
L10
L11
N6
P6
M5
P4
N4
P3
N3
P2
N2
HAD6
HAD7
HAS/HAS
HCS/HCS
HDS/HDS
HRD/HRD
HREQ/HREQ
HRRQ/HRRQ
HRW
J5
J3
J6
H1
J2
J7
H2
K2
J1
J8
H3
J9
H4
J2
J10
J11
H5
HTRQ/HTRQ
HWR/HWR
K2
J3
H6
DSP56311 Technical Data, Rev. 8
3-8
Freescale Semiconductor
Package Description
Ball
Table 3-2. Signal List by Signal Name (Continued)
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
No.
IRQA
IRQB
IRQC
IRQD
MODA
MODB
MODC
MODD
NC
C4
A5
C5
B5
C4
A5
C5
B5
A1
A14
B14
P1
P14
D1
M5
P4
M2
J2
PC3
PC4
H3
E3
E1
P5
F2
STD1
TA
C2
P10
C3
PC5
TCK
PCAP
PD0
TDI
B3
TDO
A4
PD1
A2
B2
G1
B1
C2
F1
TIO0
TIO1
TIO2
TMS
L3
PD2
L2
PD3
K3
PD4
A3
NC
PD5
TRST
TXD
B4
NC
PE0
G3
H12
K12
L12
N12
P9
NC
PE1
G3
G2
D1
N13
P12
P7
N7
M12
N5
F1
VCCA
VCCA
VCCA
VCCC
VCCC
VCCD
VCCD
VCCD
VCCD
VCCH
VCCP
VCCQH
VCCQH
VCCQH
VCCQL
VCCQL
VCCQL
VCCQL
VCCS
VCCS
WR
NC
PE2
NMI
PINIT
RAS0
RAS1
RAS2
RAS3
RD
PB0
PB1
PB10
PB11
PB12
PB13
PB14
PB15
PB2
A7
C9
J3
C11
D14
M4
M6
F12
H1
L1
RESET
RXD
K2
J1
SC00
SC01
SC02
SC10
SC11
SC12
SCK0
SCK1
SCLK
SRD0
SRD1
STD0
F3
N4
P3
N3
P2
N1
N2
M3
M1
F3
D2
C1
F2
PB3
PB4
M7
C7
PB5
A2
B2
H3
G1
G2
E3
B1
E1
PB6
G13
H2
PB7
PB8
N9
PB9
E2
PC0
K1
PC1
D2
C1
M11
P8
PC2
XTAL
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
3-9
Packaging
3.2 MAP-BGA Package Mechanical Drawing
Figure 3-3. DSP56311 Mechanical Information, 196-pin MAP-BGA Package
DSP56311 Technical Data, Rev. 8
3-10
Freescale Semiconductor
Design Considerations
4
This section describes various areas to consider when incorporating the DSP56311 device into a system design.
4.1 Thermal Design Considerations
An estimate of the chip junction temperature, T , in ° C can be obtained from this equation:
J
Equation 1: TJ = TA + (PD × RθJA
±
Where:
T
=
=
=
ambient temperature °C
A
R
package junction-to-ambient thermal resistance °C/W
power dissipation in package
θJA
P
D
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-
to-ambient thermal resistance, as in this equation:
Equation 2: RθJA = RθJC + RθCA
Where:
R
R
R
=
=
=
package junction-to-ambient thermal resistance °C/W
package junction-to-case thermal resistance °C/W
package case-to-ambient thermal resistance °C/W
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to change
θJC
the case-to-ambient thermal resistance, R
. For example, the user can change the air flow around the device, add
θCA
a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal
dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages
with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the
ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case
and an alternate path through the PCB, analysis of the device thermal performance may need the additional
modeling capability of a system-level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimates obtained from R
do not satisfactorily answer whether the thermal
θJA
performance is adequate, a system-level model may be appropriate.
A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance
in plastic packages.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
4-1
Design Considerations
•
To minimize temperature variation across the surface, the thermal resistance is measured from the junction
to the outside surface of the package (case) closest to the chip mounting area when that surface has a
proper heat sink.
•
•
To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is
measured from the junction to the point at which the leads attach to the case.
If the temperature of the package case (T ) is determined by a thermocouple, thermal resistance is
T
computed from the value obtained by the equation (T – T )/P .
J
T
D
As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first
definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case
thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will
yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric,
thermal characterization parameter or Ψ , has been defined to be (T – T )/P . This value gives a better estimate
JT
J
T
D
of the junction temperature in natural convection when the surface temperature of the package is used. Remember
that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of
the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a
40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (for example, either GND or V ).
CC
Use the following list of recommendations to ensure correct DSP operation.
•
Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the
board ground to each GND pin.
•
Use at least four 0.01–0.1 µF bypass capacitors for the core and PLL power and six 0.01–0.1 µF bypass
capacitors for I/O power positioned as closely as possible to the four sides of the package to connect the
V
CC power source to GND.
•
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins
are less than 0.5 inch per capacitor lead.
Use at least a four-layer PCB with two inner layers for VCC and GND.
DSP56311 Technical Data, Rev. 8
4-2
Freescale Semiconductor
Power Consumption Considerations
•
•
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This
recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD,
TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.
Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the VCC and GND circuits.
All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with
internal pull-up resistors (TRST, TMS, DE).
•
•
Take special care to minimize noise levels on the VCCP, GND , and GNDP1 pins.
P
The following pins must be asserted during power-up: RESET and TRST. A stable EXTAL signal should be
supplied before deassertion of RESET. If the V reaches the required level before EXTAL is stable or
CC
other “required RESET duration” conditions are met (see Table 2-7), the device circuitry can be in an
uninitialized state that may result in significant power consumption and heat-up. Designs should minimize
this condition to the shortest possible duration.
•
•
•
Ensure that during power-up, and throughout the DSP56311 operation, V
is always higher or equal to
CCQH
the V voltage level.
CC
If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due
to synchronous operation of the devices.
The Port A data bus (D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to maintain the
last output value even when the internal signal is tri-stated. Typically, no pull-up or pull-down resistors
should be used with these signal lines. However, if the DSP is connected to a device that requires pull-up
resistors (such as an MPC8260), the recommended resistor value is 10 KΩ or less. If more than one DSP
must be connected in parallel to the other device, the pull-up resistor value requirement changes as
follows:
— 2 DSPs = 7 KΩ or less
— 3 DSPs = 4 KΩ or less
— 4 DSPs = 3 KΩ or less
— 5 DSPs = 2 KΩ or less
— 6 DSPs = 1.5 KΩ or less
4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption
are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is
charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this
formula:
Equation 3: I = C × V × f
Where:
C
V
f
=
=
=
node/pin capacitance
voltage swing
frequency of node/pin toggle
Example 4-1. Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33
MHz), the current consumption is expressed in Equation 4.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
4-3
Design Considerations
Equation 4: I = 50 × 10–12 × 3.3 × 33 × 106 = 5.48 mA
The maximum internal current (I max) value reflects the typical possible switching of the internal buses on best-
CCI
case operation conditions—not necessarily a real application case. The typical internal current (I
) value
CCItyp
reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for
applications that require very low current consumption:
1. Set the EBD bit when you are not accessing external memory.
2. Minimize external memory accesses, and use internal memory accesses.
3. Minimize the number of pins that are switching.
4. Minimize the capacitive load on the pins.
5. Connect the unused inputs to pull-up or pull-down resistors.
6. Disable unused peripherals.
7. Disable unused pin activity (for example, CLKOUT, XTAL).
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize
specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark
power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current
measurements, and the following equation to derive the current-per-MIPS value.
Equation 5: ⁄ MIPS = I ⁄ MHz = (ItypF2 – ItypF1± ⁄ (F2 – F1
Where:
I
=
=
current at F2
current at F1
typF2
I
typF1
F2
F1
=
=
high frequency (any specified operating frequency)
low frequency (any specified operating frequency lower than F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The
degree of difference between F1 and F2 determines the amount of precision with which the current rating
can be determined for an application.
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no
test that replicates these exact numbers. These observations were measured on a limited number of parts and were
not verified over the entire temperature and voltage ranges.
4.4.1 Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a
given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 2-
2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF ≤4, this skew is
greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10
and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns.
DSP56311 Technical Data, Rev. 8
4-4
Freescale Semiconductor
PLL Performance Issues
4.4.2 Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT
for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These
variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤4, this
jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies
greater than 10 MHz, this jitter is less than ±2 ns.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
4-5
Design Considerations
4.4.3 Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10)
this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 percent and
approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent.
4.5 Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow
(that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is
fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase
and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.
DSP56311 Technical Data, Rev. 8
4-6
Freescale Semiconductor
Power Consumption Benchmark A
The following benchmark program evaluates DSP56311 power use in a test situation. It enables the PLL, disables
the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP
application data to emulate intensive sustained DSP operation.
;**************************************************************************
;**************************************************************************
;*
;*
;*
*
*
*
CHECKS
Typical Power Consumption
;**************************************************************************
page
200,55,0,0,0
nolist
I_VEC EQU $000000
START EQU $8000
INT_PROG EQU $100
INT_XDAT EQU $0
INT_YDAT EQU $0
; Interrupt vectors for program debug only
; MAIN (external) program starting address
; INTERNAL program memory starting address
; INTERNAL X-data memory starting address
; INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm"
INCLUDE "intequ.asm"
list
org
P:START
;
;
movep #$0243FF,x:M_BCR ;
movep #$0d0000,x:M_PCTL
; BCR: Area 3 = 2 w.s (SRAM)
; Default: 2w.s (SRAM)
; XTAL disable
; PLL enable
; CLKOUT disable
;
;
; Load the program
move
move
do
move
move
nop
#INT_PROG,r0
#PROG_START,r1
#(PROG_END-PROG_START),PLOAD_LOOP
p:(r1)+,x0
x0,p:(r0)+
PLOAD_LOOP
;
; Load the X-data
;
move
#INT_XDAT,r0
move
do
move
move
#XDAT_START,r1
#(XDAT_END-XDAT_START),XLOAD_LOOP
p:(r1)+,x0
x0,x:(r0)+
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-1
Power Consumption Benchmark
XLOAD_LOOP
;
; Load the Y-data
;
move
move
do
move
move
#INT_YDAT,r0
#YDAT_START,r1
#(YDAT_END-YDAT_START),YLOAD_LOOP
p:(r1)+,x0
x0,y:(r0)+
YLOAD_LOOP
;
jmp
INT_PROG
PROG_START
move
#$0,r0
#$0,r4
#$3f,m0
#$3f,m4
move
move
move
;
clr
a
clr
b
move
move
move
move
bset
#$0,x0
#$0,x1
#$0,y0
#$0,y1
#4,omr
; ebd
;
sbr
dor
mac
mac
add
mac
mac
move
#60,_end
x0,y0,ax:(r0)+,x1
x1,y1,ax:(r0)+,x0
a,b
x0,y0,ax:(r0)+,x1
x1,y1,a
y:(r4)+,y1
y:(r4)+,y0
y:(r4)+,y0
b1,x:$ff
_end
bra
nop
nop
nop
nop
sbr
PROG_END
nop
nop
XDAT_START
;
org
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
x:0
$262EB9
$86F2FE
$E56A5F
$616CAC
$8FFD75
$9210A
$A06D7B
$CEA798
$8DFBF1
$A063D6
$6C6657
$C2A544
$A3662D
$A4E762
$84F0F3
DSP56311 Technical Data, Rev. 8
A-2
Freescale Semiconductor
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
$E6F1B0
$B3829
$8BF7AE
$63A94F
$EF78DC
$242DE5
$A3E0BA
$EBAB6B
$8726C8
$CA361
$2F6E86
$A57347
$4BE774
$8F349D
$A1ED12
$4BFCE3
$EA26E0
$CD7D99
$4BA85E
$27A43F
$A8B10C
$D3A55
$25EC6A
$2A255B
$A5F1F8
$2426D1
$AE6536
$CBBC37
$6235A4
$37F0D
$63BEC2
$A5E4D3
$8CE810
$3FF09
$60E50E
$CFFB2F
$40753C
$8262C5
$CA641A
$EB3B4B
$2DA928
$AB6641
$28A7E6
$4E2127
$482FD4
$7257D
$E53C72
$1A8C3
$E27540
XDAT_END
YDAT_START
;
org
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
y:0
$5B6DA
$C3F70B
$6A39E8
$81E801
$C666A6
$46F8E7
$AAEC94
$24233D
$802732
$2E3C83
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-3
Power Consumption Benchmark
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
$A43E00
$C2B639
$85A47E
$ABFDDF
$F3A2C
$2D7CF5
$E16A8A
$ECB8FB
$4BED18
$43F371
$83A556
$E1E9D7
$ACA2C4
$8135AD
$2CE0E2
$8F2C73
$432730
$A87FA9
$4A292E
$A63CCF
$6BA65C
$E06D65
$1AA3A
$A1B6EB
$48AC48
$EF7AE1
$6E3006
$62F6C7
$6064F4
$87E41D
$CB2692
$2C3863
$C6BC60
$43A519
$6139DE
$ADF7BF
$4B3E8C
$6079D5
$E0F5EA
$8230DB
$A3B778
$2BFE51
$E0A6B6
$68FFB7
$28F324
$8F2E8D
$667842
$83E053
$A1FD90
$6B2689
$85B68E
$622EAF
$6162BC
$E4A245
YDAT_END
;**************************************************************************
;
;
;
;
;
EQUATES for DSP56311 I/O registers and ports
Last update: June 11 1995
;**************************************************************************
DSP56311 Technical Data, Rev. 8
A-4
Freescale Semiconductor
page
opt
132,55,0,0,0
mex
ioequ
ident
1,0
;------------------------------------------------------------------------
;
;
;
EQUATES for I/O Port Programming
;------------------------------------------------------------------------
Register Addresses
;
M_HDR EQU $FFFFC9
M_HDDR EQU $FFFFC8
M_PCRC EQU $FFFFBF
M_PRRC EQU $FFFFBE
M_PDRC EQU $FFFFBD
M_PCRD EQU $FFFFAF
M_PRRD EQU $FFFFAE
M_PDRD EQU $FFFFAD
M_PCRE EQU $FFFF9F
M_PRRE EQU $FFFF9E
M_PDRE EQU $FFFF9D
M_OGDB EQU $FFFFFC
; Host port GPIO data Register
; Host port GPIO direction Register
; Port C Control Register
; Port C Direction Register
; Port C GPIO Data Register
; Port D Control register
; Port D Direction Data Register
; Port D GPIO Data Register
; Port E Control register
; Port E Direction Register
; Port E Data Register
; OnCE GDB Register
;------------------------------------------------------------------------
;
;
;
EQUATES for Host Interface
;------------------------------------------------------------------------
;
Register Addresses
M_HCR EQU $FFFFC2
M_HSR EQU $FFFFC3
M_HPCR EQU $FFFFC4
M_HBAR EQU $FFFFC5
M_HRX EQU $FFFFC6
M_HTX EQU $FFFFC7
; Host Control Register
; Host Status Register
; Host Polarity Control Register
; Host Base Address Register
; Host Receive Register
; Host Transmit Register
;
HCR bits definition
M_HRIE EQU $0
M_HTIE EQU $1
M_HCIE EQU $2
M_HF2 EQU $3
M_HF3 EQU $4
; Host Receive interrupts Enable
; Host Transmit Interrupt Enable
; Host Command Interrupt Enable
; Host Flag 2
; Host Flag 3
;
HSR bits definition
M_HRDF EQU $0
M_HTDE EQU $1
M_HCP EQU $2
M_HF0 EQU $3
M_HF1 EQU $4
; Host Receive Data Full
; Host Receive Data Empty
; Host Command Pending
; Host Flag 0
; Host Flag 1
;
HPCR bits definition
M_HGEN EQU $0
M_HA8EN EQU $1
M_HA9EN EQU $2
M_HCSEN EQU $3
; Host Port GPIO Enable
; Host Address 8 Enable
; Host Address 9 Enable
; Host Chip Select Enable
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-5
Power Consumption Benchmark
M_HREN EQU $4
M_HAEN EQU $5
M_HEN EQU $6
M_HOD EQU $8
M_HDSP EQU $9
M_HASP EQU $A
M_HMUX EQU $B
M_HD_HS EQU $C
M_HCSP EQU $D
M_HRP EQU $E
M_HAP EQU $F
; Host Request Enable
; Host Acknowledge Enable
; Host Enable
; Host Request Open Drain mode
; Host Data Strobe Polarity
; Host Address Strobe Polarity
; Host Multiplexed bus select
; Host Double/Single Strobe select
; Host Chip Select Polarity
; Host Request Polarity
; Host Acknowledge Polarity
;------------------------------------------------------------------------
;
;
;
EQUATES for Serial Communications Interface (SCI)
;------------------------------------------------------------------------
;
Register Addresses
M_STXH EQU $FFFF97
M_STXM EQU $FFFF96
M_STXL EQU $FFFF95
M_SRXH EQU $FFFF9A
M_SRXM EQU $FFFF99
M_SRXL EQU $FFFF98
M_STXA EQU $FFFF94
M_SCR EQU $FFFF9C
M_SSR EQU $FFFF93
M_SCCR EQU $FFFF9B
; SCI Transmit Data Register (high)
; SCI Transmit Data Register (middle)
; SCI Transmit Data Register (low)
; SCI Receive Data Register (high)
; SCI Receive Data Register (middle)
; SCI Receive Data Register (low)
; SCI Transmit Address Register
; SCI Control Register
; SCI Status Register
; SCI Clock Control Register
;
SCI Control Register Bit Flags
M_WDS EQU $7
M_WDS0 EQU 0
M_WDS1 EQU 1
M_WDS2 EQU 2
M_SSFTD EQU 3
M_SBK EQU 4
; Word Select Mask (WDS0-WDS3)
; Word Select 0
; Word Select 1
; Word Select 2
; SCI Shift Direction
; Send Break
M_WAKE EQU 5
M_RWU EQU 6
; Wakeup Mode Select
; Receiver Wakeup Enable
; Wired-OR Mode Select
; SCI Receiver Enable
; SCI Transmitter Enable
; Idle Line Interrupt Enable
; SCI Receive Interrupt Enable
; SCI Transmit Interrupt Enable
; Timer Interrupt Enable
; Timer Interrupt Rate
; SCI Clock Polarity
M_WOMS EQU 7
M_SCRE EQU 8
M_SCTE EQU 9
M_ILIE EQU 10
M_SCRIE EQU 11
M_SCTIE EQU 12
M_TMIE EQU 13
M_TIR EQU 14
M_SCKP EQU 15
M_REIE EQU 16
; SCI Error Interrupt Enable (REIE)
;
SCI Status Register Bit Flags
M_TRNE EQU 0
M_TDRE EQU 1
M_RDRF EQU 2
M_IDLE EQU 3
M_OR EQU 4
M_PE EQU 5
M_FE EQU 6
M_R8 EQU 7
; Transmitter Empty
; Transmit Data Register Empty
; Receive Data Register Full
; Idle Line Flag
; Overrun Error Flag
; Parity Error
; Framing Error Flag
; Received Bit 8 (R8) Address
DSP56311 Technical Data, Rev. 8
A-6
Freescale Semiconductor
;
SCI Clock Control Register
M_CD EQU $FFF
M_COD EQU 12
M_SCP EQU 13
M_RCM EQU 14
M_TCM EQU 15
; Clock Divider Mask (CD0-CD11)
; Clock Out Divider
; Clock Prescaler
; Receive Clock Mode Source Bit
; Transmit Clock Source Bit
;------------------------------------------------------------------------
;
;
;
EQUATES for Synchronous Serial Interface (SSI)
;------------------------------------------------------------------------
;
;
Register Addresses Of SSI0
M_TX00 EQU $FFFFBC
M_TX01 EQU $FFFFBB
M_TX02 EQU $FFFFBA
M_TSR0 EQU $FFFFB9
M_RX0 EQU $FFFFB8
M_SSISR0 EQU $FFFFB7
M_CRB0 EQU $FFFFB6
M_CRA0 EQU $FFFFB5
M_TSMA0 EQU $FFFFB4
M_TSMB0 EQU $FFFFB3
M_RSMA0 EQU $FFFFB2
M_RSMB0 EQU $FFFFB1
; SSI0 Transmit Data Register 0
; SSIO Transmit Data Register 1
; SSIO Transmit Data Register 2
; SSI0 Time Slot Register
; SSI0 Receive Data Register
; SSI0 Status Register
; SSI0 Control Register B
; SSI0 Control Register A
; SSI0 Transmit Slot Mask Register A
; SSI0 Transmit Slot Mask Register B
; SSI0 Receive Slot Mask Register A
; SSI0 Receive Slot Mask Register B
;
Register Addresses Of SSI1
M_TX10 EQU $FFFFAC
M_TX11 EQU $FFFFAB
M_TX12 EQU $FFFFAA
M_TSR1 EQU $FFFFA9
M_RX1 EQU $FFFFA8
M_SSISR1 EQU $FFFFA7
M_CRB1 EQU $FFFFA6
M_CRA1 EQU $FFFFA5
M_TSMA1 EQU $FFFFA4
M_TSMB1 EQU $FFFFA3
M_RSMA1 EQU $FFFFA2
M_RSMB1 EQU $FFFFA1
; SSI1 Transmit Data Register 0
; SSI1 Transmit Data Register 1
; SSI1 Transmit Data Register 2
; SSI1 Time Slot Register
; SSI1 Receive Data Register
; SSI1 Status Register
; SSI1 Control Register B
; SSI1 Control Register A
; SSI1 Transmit Slot Mask Register A
; SSI1 Transmit Slot Mask Register B
; SSI1 Receive Slot Mask Register A
; SSI1 Receive Slot Mask Register B
;
SSI Control Register A Bit Flags
M_PM EQU $FF
M_PSR EQU 11
; Prescale Modulus Select Mask (PM0-PM7)
; Prescaler Range
M_DC EQU $1F000
M_ALC EQU 18
; Frame Rate Divider Control Mask (DC0-DC7)
; Alignment Control (ALC)
M_WL EQU $380000
M_SSC1 EQU 22
; Word Length Control Mask (WL0-WL7)
; Select SC1 as TR #0 drive enable (SSC1)
;
SSI Control Register B Bit Flags
M_OF EQU $3
M_OF0 EQU 0
M_OF1 EQU 1
M_SCD EQU $1C
M_SCD0 EQU 2
M_SCD1 EQU 3
M_SCD2 EQU 4
M_SCKD EQU 5
; Serial Output Flag Mask
; Serial Output Flag 0
; Serial Output Flag 1
; Serial Control Direction Mask
; Serial Control 0 Direction
; Serial Control 1 Direction
; Serial Control 2 Direction
; Clock Source Direction
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-7
Power Consumption Benchmark
M_SHFD EQU 6
; Shift Direction
M_FSL EQU $180
M_FSL0 EQU 7
; Frame Sync Length Mask (FSL0-FSL1)
; Frame Sync Length 0
M_FSL1 EQU 8
; Frame Sync Length 1
M_FSR EQU 9
M_FSP EQU 10
; Frame Sync Relative Timing
; Frame Sync Polarity
M_CKP EQU 11
; Clock Polarity
M_SYN EQU 12
; Sync/Async Control
M_MOD EQU 13
; SSI Mode Select
M_SSTE EQU $1C000
M_SSTE2 EQU 14
M_SSTE1 EQU 15
M_SSTE0 EQU 16
M_SSRE EQU 17
M_SSTIE EQU 18
M_SSRIE EQU 19
M_STLIE EQU 20
M_SRLIE EQU 21
M_STEIE EQU 22
M_SREIE EQU 23
; SSI Transmit enable Mask
; SSI Transmit #2 Enable
; SSI Transmit #1 Enable
; SSI Transmit #0 Enable
; SSI Receive Enable
; SSI Transmit Interrupt Enable
; SSI Receive Interrupt Enable
; SSI Transmit Last Slot Interrupt Enable
; SSI Receive Last Slot Interrupt Enable
; SSI Transmit Error Interrupt Enable
; SI Receive Error Interrupt Enable
;
SSI Status Register Bit Flags
M_IF EQU $3
M_IF0 EQU 0
M_IF1 EQU 1
M_TFS EQU 2
M_RFS EQU 3
M_TUE EQU 4
M_ROE EQU 5
M_TDE EQU 6
M_RDF EQU 7
; Serial Input Flag Mask
; Serial Input Flag 0
; Serial Input Flag 1
; Transmit Frame Sync Flag
; Receive Frame Sync Flag
; Transmitter Underrun Error FLag
; Receiver Overrun Error Flag
; Transmit Data Register Empty
; Receive Data Register Full
;
SSI Transmit Slot Mask Register A
M_SSTSA EQU $FFFF
; SSI Transmit Slot Bits Mask A (TS0-TS15)
; SSI Transmit Slot Bits Mask B (TS16-TS31)
; SSI Receive Slot Bits Mask A (RS0-RS15)
; SSI Receive Slot Bits Mask B (RS16-RS31)
;
SSI Transmit Slot Mask Register B
M_SSTSB EQU $FFFF
;
SSI Receive Slot Mask Register A
M_SSRSA EQU $FFFF
;
SSI Receive Slot Mask Register B
M_SSRSB EQU $FFFF
;------------------------------------------------------------------------
;
;
;
EQUATES for Exception Processing
;------------------------------------------------------------------------
;
Register Addresses
M_IPRC EQU $FFFFFF
M_IPRP EQU $FFFFFE
; Interrupt Priority Register Core
; Interrupt Priority Register Peripheral
DSP56311 Technical Data, Rev. 8
A-8
Freescale Semiconductor
;
Interrupt Priority Register Core (IPRC)
M_IAL EQU $7
; IRQA Mode Mask
M_IAL0 EQU 0
M_IAL1 EQU 1
M_IAL2 EQU 2
; IRQA Mode Interrupt Priority Level (low)
; IRQA Mode Interrupt Priority Level (high)
; IRQA Mode Trigger Mode
M_IBL EQU $38
M_IBL0 EQU 3
M_IBL1 EQU 4
; IRQB Mode Mask
; IRQB Mode Interrupt Priority Level (low)
; IRQB Mode Interrupt Priority Level (high)
; IRQB Mode Trigger Mode
M_IBL2 EQU 5
M_ICL EQU $1C0
M_ICL0 EQU 6
M_ICL1 EQU 7
; IRQC Mode Mask
; IRQC Mode Interrupt Priority Level (low)
; IRQC Mode Interrupt Priority Level (high)
; IRQC Mode Trigger Mode
M_ICL2 EQU 8
M_IDL EQU $E00
M_IDL0 EQU 9
; IRQD Mode Mask
; IRQD Mode Interrupt Priority Level (low)
; IRQD Mode Interrupt Priority Level (high)
; IRQD Mode Trigger Mode
M_IDL1 EQU 10
M_IDL2 EQU 11
M_D0L EQU $3000
M_D0L0 EQU 12
M_D0L1 EQU 13
M_D1L EQU $C000
M_D1L0 EQU 14
M_D1L1 EQU 15
M_D2L EQU $30000
M_D2L0 EQU 16
M_D2L1 EQU 17
M_D3L EQU $C0000
M_D3L0 EQU 18
M_D3L1 EQU 19
M_D4L EQU $300000
M_D4L0 EQU 20
M_D4L1 EQU 21
M_D5L EQU $C00000
M_D5L0 EQU 22
M_D5L1 EQU 23
; DMA0 Interrupt priority Level Mask
; DMA0 Interrupt Priority Level (low)
; DMA0 Interrupt Priority Level (high)
; DMA1 Interrupt Priority Level Mask
; DMA1 Interrupt Priority Level (low)
; DMA1 Interrupt Priority Level (high)
; DMA2 Interrupt priority Level Mask
; DMA2 Interrupt Priority Level (low)
; DMA2 Interrupt Priority Level (high)
; DMA3 Interrupt Priority Level Mask
; DMA3 Interrupt Priority Level (low)
; DMA3 Interrupt Priority Level (high)
; DMA4 Interrupt priority Level Mask
; DMA4 Interrupt Priority Level (low)
; DMA4 Interrupt Priority Level (high)
; DMA5 Interrupt priority Level Mask
; DMA5 Interrupt Priority Level (low)
; DMA5 Interrupt Priority Level (high)
;
Interrupt Priority Register Peripheral (IPRP)
M_HPL EQU $3
M_HPL0 EQU 0
M_HPL1 EQU 1
M_S0L EQU $C
M_S0L0 EQU 2
M_S0L1 EQU 3
M_S1L EQU $30
M_S1L0 EQU 4
M_S1L1 EQU 5
M_SCL EQU $C0
M_SCL0 EQU 6
M_SCL1 EQU 7
M_T0L EQU $300
M_T0L0 EQU 8
M_T0L1 EQU 9
; Host Interrupt Priority Level Mask
; Host Interrupt Priority Level (low)
; Host Interrupt Priority Level (high)
; SSI0 Interrupt Priority Level Mask
; SSI0 Interrupt Priority Level (low)
; SSI0 Interrupt Priority Level (high)
; SSI1 Interrupt Priority Level Mask
; SSI1 Interrupt Priority Level (low)
; SSI1 Interrupt Priority Level (high)
; SCI Interrupt Priority Level Mask
; SCI Interrupt Priority Level (low)
; SCI Interrupt Priority Level (high)
; TIMER Interrupt Priority Level Mask
; TIMER Interrupt Priority Level (low)
; TIMER Interrupt Priority Level (high)
;------------------------------------------------------------------------
;
;
;
EQUATES for TIMER
;------------------------------------------------------------------------
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-9
Power Consumption Benchmark
;
Register Addresses Of TIMER0
M_TCSR0 EQU $FFFF8F
M_TLR0 EQU $FFFF8E
M_TCPR0 EQU $FFFF8D
M_TCR0 EQU $FFFF8C
; Timer 0 Control/Status Register
; TIMER0 Load Reg
; TIMER0 Compare Register
; TIMER0 Count Register
;
Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B
M_TLR1 EQU $FFFF8A
M_TCPR1 EQU $FFFF89
M_TCR1 EQU $FFFF88
; TIMER1 Control/Status Register
; TIMER1 Load Reg
; TIMER1 Compare Register
; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87
M_TLR2 EQU $FFFF86
M_TCPR2 EQU $FFFF85
M_TCR2 EQU $FFFF84
M_TPLR EQU $FFFF83
M_TPCR EQU $FFFF82
; TIMER2 Control/Status Register
; TIMER2 Load Reg
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags
M_TE EQU 0
; Timer Enable
M_TOIE EQU 1
M_TCIE EQU 2
M_TC EQU $F0
M_INV EQU 8
M_TRM EQU 9
M_DIR EQU 11
M_DI EQU 12
M_DO EQU 13
M_PCE EQU 15
M_TOF EQU 20
M_TCF EQU 21
; Timer Overflow Interrupt Enable
; Timer Compare Interrupt Enable
; Timer Control Mask (TC0-TC3)
; Inverter Bit
; Timer Restart Mode
; Direction Bit
; Data Input
; Data Output
; Prescaled Clock Enable
; Timer Overflow Flag
; Timer Compare Flag
;
Timer Prescaler Register Bit Flags
M_PS EQU $600000
M_PS0 EQU 21
; Prescaler Source Mask
M_PS1 EQU 22
;
Timer Control Bits
M_TC0 EQU 4
M_TC1 EQU 5
M_TC2 EQU 6
M_TC3 EQU 7
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
;------------------------------------------------------------------------
;
;
;
EQUATES for Direct Memory Access (DMA)
;------------------------------------------------------------------------
;
Register Addresses Of DMA
M_DSTR EQU FFFFF4
M_DOR0 EQU $FFFFF3
M_DOR1 EQU $FFFFF2
; DMA Status Register
; DMA Offset Register 0
; DMA Offset Register 1
DSP56311 Technical Data, Rev. 8
A-10
Freescale Semiconductor
M_DOR2 EQU $FFFFF1
M_DOR3 EQU $FFFFF0
; DMA Offset Register 2
; DMA Offset Register 3
;
Register Addresses Of DMA0
M_DSR0 EQU $FFFFEF
M_DDR0 EQU $FFFFEE
M_DCO0 EQU $FFFFED
M_DCR0 EQU $FFFFEC
; DMA0 Source Address Register
; DMA0 Destination Address Register
; DMA0 Counter
; DMA0 Control Register
;
Register Addresses Of DMA1
M_DSR1 EQU $FFFFEB
M_DDR1 EQU $FFFFEA
M_DCO1 EQU $FFFFE9
M_DCR1 EQU $FFFFE8
; DMA1 Source Address Register
; DMA1 Destination Address Register
; DMA1 Counter
; DMA1 Control Register
;
Register Addresses Of DMA2
M_DSR2 EQU $FFFFE7
M_DDR2 EQU $FFFFE6
M_DCO2 EQU $FFFFE5
M_DCR2 EQU $FFFFE4
; DMA2 Source Address Register
; DMA2 Destination Address Register
; DMA2 Counter
; DMA2 Control Register
;
Register Addresses Of DMA4
M_DSR3 EQU $FFFFE3
M_DDR3 EQU $FFFFE2
M_DCO3 EQU $FFFFE1
M_DCR3 EQU $FFFFE0
; DMA3 Source Address Register
; DMA3 Destination Address Register
; DMA3 Counter
; DMA3 Control Register
;
Register Addresses Of DMA4
M_DSR4 EQU $FFFFDF
M_DDR4 EQU $FFFFDE
M_DCO4 EQU $FFFFDD
M_DCR4 EQU $FFFFDC
; DMA4 Source Address Register
; DMA4 Destination Address Register
; DMA4 Counter
; DMA4 Control Register
;
Register Addresses Of DMA5
M_DSR5 EQU $FFFFDB
M_DDR5 EQU $FFFFDA
M_DCO5 EQU $FFFFD9
M_DCR5 EQU $FFFFD8
; DMA5 Source Address Register
; DMA5 Destination Address Register
; DMA5 Counter
; DMA5 Control Register
;
DMA Control Register
M_DSS EQU $3
M_DSS0 EQU 0
M_DSS1 EQU 1
M_DDS EQU $C
M_DDS0 EQU 2
M_DDS1 EQU 3
M_DAM EQU $3f0
M_DAM0 EQU 4
M_DAM1 EQU 5
M_DAM2 EQU 6
M_DAM3 EQU 7
M_DAM4 EQU 8
M_DAM5 EQU 9
M_D3D EQU 10
; DMA Source Space Mask (DSS0-Dss1)
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask (DDS-DDS1)
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode Mask (DAM5-DAM0)
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
; DMA Address Mode 5
; DMA Three Dimensional Mode
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-11
Power Consumption Benchmark
M_DRS EQU $F800
M_DCON EQU 16
M_DPR EQU $60000
M_DPR0 EQU 17
M_DPR1 EQU 18
M_DTM EQU $380000
M_DTM0 EQU 19
M_DTM1 EQU 20
M_DTM2 EQU 21
M_DIE EQU 22
; DMA Request Source Mask (DRS0-DRS4)
; DMA Continuous Mode
; DMA Channel Priority
; DMA Channel Priority Level (low)
; DMA Channel Priority Level (high)
; DMA Transfer Mode Mask (DTM2-DTM0)
; DMA Transfer Mode 0
; DMA Transfer Mode 1
; DMA Transfer Mode 2
; DMA Interrupt Enable bit
; DMA Channel Enable bit
M_DE EQU 23
;
DMA Status Register
M_DTD EQU $3F
M_DTD0 EQU 0
M_DTD1 EQU 1
M_DTD2 EQU 2
M_DTD3 EQU 3
M_DTD4 EQU 4
M_DTD5 EQU 5
; Channel Transfer Done Status MASK (DTD0-DTD5)
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; DMA Active State
M_DACT EQU
M_DCH EQU $E00
M_DCH0 EQU
8
; DMA Active Channel Mask (DCH0-DCH2)
; DMA Active Channel 0
9
M_DCH1 EQU 10
M_DCH2 EQU 11
; DMA Active Channel 1
; DMA Active Channel 2
;------------------------------------------------------------------------
;
;
;
EQUATES for Enhanced Filter Co-Processor (EFCOP)
;------------------------------------------------------------------------
M_FDIR
M_FDOR
M_FKIR
M_FCNT
M_FCSR
M_FACR
M_FDBA
M_FCBA
M_FDCH
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$FFFFB0
$FFFFB1
$FFFFB2
$FFFFB3
$FFFFB4
$FFFFB5
$FFFFB6
$FFFFB7
$FFFFB8
; EFCOP Data Input Register
; EFCOP Data Output Register
; EFCOP K-Constant Register
; EFCOP Filter Counter
; EFCOP Control Status Register
; EFCOP ALU Control Register
; EFCOP Data Base Address
; EFCOP Coefficient Base Address
; EFCOP Decimation/Channel Register
;------------------------------------------------------------------------
;
;
;
EQUATES for Phase Locked Loop (PLL)
;------------------------------------------------------------------------
Register Addresses Of PLL
M_PCTL EQU $FFFFFD
PLL Control Register
M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11)
;
; PLL Control Register
;
M_DF EQU $7000
M_XTLR EQU 15
M_XTLD EQU 16
M_PSTP EQU 17
M_PEN EQU 18
; Division Factor Bits Mask (DF0-DF2)
; XTAL Range select bit
; XTAL Disable Bit
; STOP Processing State Bit
; PLL Enable Bit
DSP56311 Technical Data, Rev. 8
A-12
Freescale Semiconductor
M_PCOD EQU 19
; PLL Clock Output Disable Bit
M_PD EQU $F00000
; PreDivider Factor Bits Mask (PD0-PD3)
;------------------------------------------------------------------------
;
;
;
EQUATES for BIU
;------------------------------------------------------------------------
;
Register Addresses Of BIU
M_BCR EQU $FFFFFB
M_DCR EQU $FFFFFA
M_AAR0 EQU $FFFFF9
M_AAR1 EQU $FFFFF8
M_AAR2 EQU $FFFFF7
M_AAR3 EQU $FFFFF6
M_IDR EQU $FFFFF5
; Bus Control Register
; DRAM Control Register
; Address Attribute Register 0
; Address Attribute Register 1
; Address Attribute Register 2
; Address Attribute Register 3
; ID Register
;
Bus Control Register
M_BA0W EQU $1F
M_BA1W EQU $3E0
M_BA2W EQU $1C00
M_BA3W EQU $E000
M_BDFW EQU $1F0000
M_BBS EQU 21
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
; Area 2 Wait Control Mask (BA2W0-BA2W2)
; Area 3 Wait Control Mask (BA3W0-BA3W3)
; Default Area Wait Control Mask (BDFW0-BDFW4)
; Bus State
M_BLH EQU 22
; Bus Lock Hold
M_BRH EQU 23
; Bus Request Hold
;
DRAM Control Register
M_BCW EQU $3
M_BRW EQU $C
M_BPS EQU $300
M_BPLE EQU 11
M_BME EQU 12
M_BRE EQU 13
M_BSTR EQU 14
M_BRF EQU $7F8000
M_BRP EQU 23
; In Page Wait States Bits Mask (BCW0-BCW1)
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
; DRAM Page Size Bits Mask (BPS0-BPS1)
; Page Logic Enable
; Mastership Enable
; Refresh Enable
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
; Refresh prescaler
;
Address Attribute Registers
M_BAT EQU $3
M_BAAP EQU 2
M_BPEN EQU 3
M_BXEN EQU 4
M_BYEN EQU 5
M_BAM EQU 6
; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)
; Address Attribute Pin Polarity
; Program Space Enable
; X Data Space Enable
; Y Data Space Enable
; Address Muxing
M_BPAC EQU 7
M_BNC EQU $F00
M_BAC EQU $FFF000
; Packing Enable
; Number of Address Bits to Compare Mask (BNC0-BNC3)
; Address to Compare Bits Mask (BAC0-BAC11)
;
control and status bits in SR
M_CP EQU $c00000
M_CA EQU 0
; mask for CORE-DMA priority bits in SR
; Carry
M_V EQU 1
; Overflow
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-13
Power Consumption Benchmark
M_Z EQU 2
; Zero
M_N EQU 3
; Negative
M_U EQU 4
; Unnormalized
M_E EQU 5
; Extension
M_L EQU 6
; Limit
M_S EQU 7
; Scaling Bit
M_I0 EQU 8
M_I1 EQU 9
M_S0 EQU 10
M_S1 EQU 11
M_SC EQU 13
M_DM EQU 14
M_LF EQU 15
M_FV EQU 16
M_SA EQU 17
M_CE EQU 19
M_SM EQU 20
M_RM EQU 21
M_CP0 EQU 22
M_CP1 EQU 23
; Interupt Mask Bit 0
; Interupt Mask Bit 1
; Scaling Mode Bit 0
; Scaling Mode Bit 1
; Sixteen_Bit Compatibility
; Double Precision Multiply
; DO-Loop Flag
; DO-Forever Flag
; Sixteen-Bit Arithmetic
; Instruction Cache Enable
; Arithmetic Saturation
; Rounding Mode
; bit 0 of priority bits in SR
; bit 1 of priority bits in SR
;
control and status bits in OMR
M_CDP EQU $300
; mask for CORE-DMA priority bits in OMR
; Operating Mode A
; Operating Mode B
; Operating Mode C
; Operating Mode D
M_MA
M_MB
M_MC
M_MD
equ0
equ1
equ2
equ3
M_EBD EQU 4
M_SD EQU 6
M_MS EQU 7
M_CDP0 EQU 8
M_CDP1 EQU 9
; External Bus Disable bit in OMR
; Stop Delay
; Memory Switch bit in OMR
; bit 0 of priority bits in OMR
; bit 1 of priority bits in OMR
; Burst Enable
M_BEN
EQU 10
M_TAS EQU 11
M_BRT EQU 12
M_ATE EQU 15
M_XYS EQU 16
M_EUN EQU 17
M_EOV EQU 18
M_WRP EQU 19
M_SEN EQU 20
; TA Synchronize Select
; Bus Release Timing
; Address Tracing Enable bit in OMR.
; Stack Extension space select bit in OMR.
; Extensed stack UNderflow flag in OMR.
; Extended stack OVerflow flag in OMR.
; Extended WRaP flag in OMR.
; Stack Extension Enable bit in OMR.
;*************************************************************************
;
;
;
;
;
EQUATES for DSP56311 interrupts
Last update: June 11 1995
;*************************************************************************
page
opt
132,55,0,0,0
mex
intequ ident
1,0
if
@DEF(I_VEC)
;leave user definition as is.
else
DSP56311 Technical Data, Rev. 8
A-14
Freescale Semiconductor
I_VEC EQU $0
endif
;------------------------------------------------------------------------
; Non-Maskable interrupts
;------------------------------------------------------------------------
I_RESET EQU I_VEC+$00
I_STACK EQU I_VEC+$02
I_ILL EQU I_VEC+$04
I_DBG EQU I_VEC+$06
I_TRAP EQU I_VEC+$08
I_NMI EQU I_VEC+$0A
; Hardware RESET
; Stack Error
; Illegal Instruction
; Debug Request
; Trap
; Non Maskable Interrupt
;------------------------------------------------------------------------
; Interrupt Request Pins
;------------------------------------------------------------------------
I_IRQA EQU I_VEC+$10
I_IRQB EQU I_VEC+$12
I_IRQC EQU I_VEC+$14
I_IRQD EQU I_VEC+$16
; IRQA
; IRQB
; IRQC
; IRQD
;------------------------------------------------------------------------
; DMA Interrupts
;------------------------------------------------------------------------
I_DMA0 EQU I_VEC+$18
I_DMA1 EQU I_VEC+$1A
I_DMA2 EQU I_VEC+$1C
I_DMA3 EQU I_VEC+$1E
I_DMA4 EQU I_VEC+$20
I_DMA5 EQU I_VEC+$22
; DMA Channel 0
; DMA Channel 1
; DMA Channel 2
; DMA Channel 3
; DMA Channel 4
; DMA Channel 5
;------------------------------------------------------------------------
; Timer Interrupts
;------------------------------------------------------------------------
I_TIM0C EQU I_VEC+$24
I_TIM0OF EQU I_VEC+$26
I_TIM1C EQU I_VEC+$28
I_TIM1OF EQU I_VEC+$2A
I_TIM2C EQU I_VEC+$2C
I_TIM2OF EQU I_VEC+$2E
; TIMER 0 compare
; TIMER 0 overflow
; TIMER 1 compare
; TIMER 1 overflow
; TIMER 2 compare
; TIMER 2 overflow
;------------------------------------------------------------------------
; ESSI Interrupts
;------------------------------------------------------------------------
I_SI0RD EQU I_VEC+$30
I_SI0RDE EQU I_VEC+$32
I_SI0RLS EQU I_VEC+$34
I_SI0TD EQU I_VEC+$36
I_SI0TDE EQU I_VEC+$38
I_SI0TLS EQU I_VEC+$3A
I_SI1RD EQU I_VEC+$40
I_SI1RDE EQU I_VEC+$42
I_SI1RLS EQU I_VEC+$44
I_SI1TD EQU I_VEC+$46
I_SI1TDE EQU I_VEC+$48
I_SI1TLS EQU I_VEC+$4A
; ESSI0 Receive Data
; ESSI0 Receive Data w/ exception Status
; ESSI0 Receive last slot
; ESSI0 Transmit data
; ESSI0 Transmit Data w/ exception Status
; ESSI0 Transmit last slot
; ESSI1 Receive Data
; ESSI1 Receive Data w/ exception Status
; ESSI1 Receive last slot
; ESSI1 Transmit data
; ESSI1 Transmit Data w/ exception Status
; ESSI1 Transmit last slot
;------------------------------------------------------------------------
; SCI Interrupts
;------------------------------------------------------------------------
I_SCIRD EQU I_VEC+$50
I_SCIRDE EQU I_VEC+$52
I_SCITD EQU I_VEC+$54
; SCI Receive Data
; SCI Receive Data With Exception Status
; SCI Transmit Data
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
A-15
Power Consumption Benchmark
I_SCIIL EQU I_VEC+$56
I_SCITM EQU I_VEC+$58
; SCI Idle Line
; SCI Timer
;------------------------------------------------------------------------
; HOST Interrupts
;------------------------------------------------------------------------
I_HRDF EQU I_VEC+$60
I_HTDE EQU I_VEC+$62
I_HC EQU I_VEC+$64
; Host Receive Data Full
; Host Transmit Data Empty
; Default Host Command
;-----------------------------------------------------------------------
; EFCOP Filter Interrupts
;-----------------------------------------------------------------------
I_FDIIE EQU
I_FDOIE EQU
I_VEC+$68
I_VEC+$6A
; EFilter input buffer empty
; EFilter output buffer full
;------------------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;------------------------------------------------------------------------
I_INTEND EQU I_VEC+$FF
; last address of interrupt vector space
DSP56311 Technical Data, Rev. 8
A-16
Freescale Semiconductor
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core
Frequency
(MHz)
Supply
Voltage
Pin
Count
Part
Package Type
Solder Spheres
Order Number
DSP56311
1.8 V core
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
196
150
Lead-free
DSP56311VL150
DSP56311VF150
Lead-bearing
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Document Order No.: DSP56311
Rev. 8
2/2005
相关型号:
DSP56321FC240
Digital Signal Processor, 24-Bit Size, 24-Ext Bit, 240MHz, CMOS, PBGA196, FLIP CHIP, PLASTIC, BGA-196
MOTOROLA
DSP56321TFC220D
24-BIT, 220 MHz, OTHER DSP, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDED ARRAY PROCESS, BGA-196
MOTOROLA
DSP56321TFC240D
Digital Signal Processor, 24-Ext Bit, 240MHz, CMOS, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDED ARRAY PROCESS, BGA-196
MOTOROLA
DSP56321TFC240D
24-BIT, 240 MHz, OTHER DSP, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDED ARRAY PROCESS, BGA-196
NXP
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