DSP56F802TA60E [NXP]
0-BIT, 60 MHz, OTHER DSP, PQFP32, ROHS COMPLIANT, PLASTIC, LQFP-32;
| 型号： | DSP56F802TA60E |
| 厂家： | 
NXP |
| 描述： | 0-BIT, 60 MHz, OTHER DSP, PQFP32, ROHS COMPLIANT, PLASTIC, LQFP-32 时钟 外围集成电路 |
| 文件： | 总40页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
56F802
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F802
Rev. 9
01/2007
freescale.com
56F802 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• 8K × 16-bit words (16KB) Program Flash
• 1K × 16-bit words (2KB) Program RAM
• 2K × 16-bit words (4KB) Data Flash
• 1K × 16-bit words (2KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 4 shared GPIO
• 6-channel PWM Module with fault input
• Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
• Serial Communications Interface (SCI)
• 32-pin LQFP Package
• Two General Purpose Quad Timers with 2 external
outputs
PWM Outputs
6
PWMA
Fault A0
RESET
VCAPC
2
V
V
*
V
V
SSA
DD
SS
DDA
5
2
3
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
A/D1
A/D2
VREF
2
3
ADC
Interrupt
Controller
Data ALU
Address
Generation
Unit
Bit
Manipulation
Unit
Program Controller
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
and
Hardware Looping Unit
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
PAB
PLL
•
PDB
Quad Timer C
•
•
Quad Timer D
or GPIO
Boot Flash
2048x 16 Flash
2
Relaxation
Oscillator
.
XDB2
CGDB
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
•
•
•
•
XAB1
16-Bit
56800
Core
XAB2
•
INTERRUPT
CONTROLS
IPBB
CONTROLS
16
SCI0
or
16
2
COP/
GPIO
COP RESET
Watchdog
MODULE CONTROLS
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
ADDRESS BUS [8:0]
DATA BUS [15:0]
*includes TCS pin which is reserved for factory use and is tied to VSS
56F802 Block Diagram
56F802 Technical Data, Rev. 9
Freescale Semiconductor
3
Part 1 Overview
1.1 56F802 Features
1.1.1
Processing Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
Memory
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory including a low-cost, high-volume Flash solution
— 8K × 16 bit words of Program Flash
•
— 1K × 16-bit words of Program RAM
— 2K × 16-bit words of Data Flash
— 1K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
•
Programmable Boot Flash supports customized boot code and field upgrades of stored code through a
variety of interfaces (JTAG)
1.1.3
Peripheral Circuits for 56F802
•
Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection;
supports both center- and edge-aligned modes
•
Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support two
simultaneous conversions; ADC and PWM modules can be synchronized
•
•
•
Two General Purpose Quad Timers with two external pins (or two GPIO)
Serial Communication Interface (SCI) with two pins (or two GPIO)
Four multiplexed General Purpose I/O (GPIO) pins
56F802 Technical Data, Rev. 9
4
Freescale Semiconductor
56F802 Description
•
•
•
•
•
•
Computer-Operating Properly (COP) watchdog timer
External interrupts via GPIO
Trimmable on-chip relaxation oscillator
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4
Energy Information
•
•
•
•
•
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
Integrated power supervisor
1.2 56F802 Description
The 56F802 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many
peripherals that are especially useful for applications such as motion control, home appliances, encoders,
tachometers, limit switches, power supply and control, engine management, and industrial control for
power, lighting, automation and HVAC.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F802 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time
56F802 Technical Data, Rev. 9
Freescale Semiconductor
5
insertion, and separate top and bottom output polarity control. The up-counter value is programmable to
support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width
control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:
ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM
(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection
with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”,
write-once protection feature for key parameters is also included. The PWM is double-buffered and
includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The PWM
modules provide a reference output to synchronize the Analog-to-Digital Converters.
The 56F802 incorporates two 12-bit Analog-to-Digital Converters (ADCs) with a total of five channels.
A full set of standard programmable peripherals is provided that include a Serial Communications
Interface (SCI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator eliminates the need
for an external crystal.
1.3 State of the Art Development Environment
•
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
•
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F802. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F802 Chip Documentation
Topic
Description
Order Number
56800E
Family Manual
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
56800EFM
DSP56F801/803/805/807
User’s Manual
Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F802, 56F803, 56F805, and 56F807
DSP56F801-7UM
DSP56F802
56F802E
56F802
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
56F802
Errata
Details any chip issues that might be present
56F802 Technical Data, Rev. 9
6
Freescale Semiconductor
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications
56F802 Technical Data, Rev. 9
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F802 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-10, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of
Pins
Detailed
Description
Functional Group
Power (VDD or VDDA
)
3
4
Table 2-2
Table 2-3
Ground (VSS, VSSA, TCS)
Supply Capacitors
2
1
7
2
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Program Control
Pulse Width Modulator (PWM) Port and Fault Input
Serial Communications Interface (SCI) Port1
Analog-to-Digital Converter (ADC) Port (including VREF)
6
Table 2-8
Quad Timer Module Port
2
5
Table 2-9
JTAG/On-Chip Emulation (OnCE)
1. Alternately, GPIO pins
Table 2-10
56F802 Technical Data, Rev. 9
8
Freescale Semiconductor
Introduction
VDD
VSS
Power Port
Ground Port
Power Port
Ground Port
2
3*
1
VDDA
VSSA
1
PWMA0-5
Fault A0
6
1
Other
VCAPC
Supply Port
2
56F802
TXD0 (GPIOB0)
RXD0 (GPIOB1)
1
1
SCI0 Port or
GPIO
ANA2-4, ANA6-7
VREF
5
1
ADCA Port
TCK
TMS
TDI
1
1
1
1
1
JTAG/OnCE™
Port
Quad
Timer D or
GPIO
TD1-2 (GPIOA1-2)
2
1
TDO
TRST
RESET
Program
Control
*includes TCS pin which is reserved for factory use and is tied to VSS
1
Figure 2-1 56F802 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parenthesis.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
9
2.2 Power and Ground Signals
Table 2-2 Power Inputs
No. of Pins
Signal Name
VDD
Signal Description
2
Power—These pins provide power to the internal structures of the chip, and should
all be attached to VDD.
1
VDDA
Analog Power—This pin is a dedicated power pin for the analog portion of the chip
and should be connected to a low noise 3.3V supply.
Table 2-3 Grounds
No. of Pins
Signal Name
VSS
Signal Description
2
GND—These pins provide grounding for the internal structures of the chip, and should
all be attached to VSS.
1
1
VSSA
TCS
Analog Ground—This pin supplies an analog ground.
TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional VSS.
Table 2-4 Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State During
Signal Description
Reset
2
VCAPC Supply
Supply
VCAPC—Connect each pin to a 2.2 μF or greater bypass
capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, refer to
Section 5.2
56F802 Technical Data, Rev. 9
10
Freescale Semiconductor
Interrupt and Program Control Signals
2.3 Interrupt and Program Control Signals
Table 2-5 Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
RESET
Input
(Schmitt)
Input
Reset—This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
2.4 Pulse Width Modulator (PWM) Signals
Table 2-6 Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
1
PWMA0-5
FAULTA0
Output
Tri-stated
Input
PWMA0-5— These are six PWMA output pins.
Input
FAULTA0 —This fault input is used for disabling selected PWMA
(Schmitt)
outputs in cases where fault conditions originate off-chip.
2.5 Serial Communications Interface (SCI) Signals
Table 2-7 Serial Communications Interface (SCI0) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TXD0
Output
Input
Input
Transmit Data (TXD0)—SCI0 transmit data output
GPIOB0
Input/Ou
tput
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.
After reset, the default state is SCI output.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
11
Table 2-7 Serial Communications Interface (SCI0) Signals (Continued)
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
RXD0
Input
Input
Input
Receive Data (RXD0)—SCI0 receive data input
GPIOB1
Input/
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can
Output
be individually programmed as an input or output pin.
After reset, the default state is SCI input.
2.6 Analog-to-Digital Converter (ADC) Signals
Table 2-8 Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
3
2
1
ANA2-4
ANA6-7
VREF
Input
Input
Input
Input
Input
Input
ANA2-4—Analog inputs to ADC, channel 1
ANA6-7—Analog inputs to ADC, channel 2
VREF—Analog reference voltage. Must be set to VDDA - 0.3V for
optimal performance.
2.7 Quad Timer Module Signals
Table 2-9 Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Signal Description
Reset
2
TD1-2
Input/
Input
TD1-2—Timer D Channel 1-2
Output
GPIOA1-2
Input/
Input
Port A GPIO—These pins are General Purpose I/O (GPIO) pins that
Output
can be individually programmed as input or output pins.
After reset, the default state is the quad timer input.
56F802 Technical Data, Rev. 9
12
Freescale Semiconductor
JTAG/OnCE
2.8 JTAG/OnCE
Table 2-10 JTAG/On-Chip Emulation (OnCE) Signals
No. of Signal
Signal State During
Signal Description
Pins
Name
Type
Reset
1
TCK
Input
Input, pulled Test Clock Input—This input pin provides a gated clock to synchronize the
(Schmitt) low internally test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
1
TMS
Input
Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG TAP
(Schmitt) high internally controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
1
1
1
TDI
TDO
TRST
Input
Input, pulled Test Data Input—This input pin provides a serial input data stream to the
(Schmitt) high internally JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
Output
Tri-stated
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
Input
Input, pulled Test Reset—As an input, a low signal on this pin provides a reset signal to the
(Schmitt) high internally JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted at power-up and whenever RESET is asserted. The only exception
occurs in a debugging environment, since the OnCE/JTAG module is under
the control of the debugger. In this case it is not necessary to assert TRST
when asserting RESET. Outside of a debugging environment RESET should
be permanently asserted by grounding the signal, thus disabling the
OnCE/JTAG module on the device.
Note: For normal operation, connect TRST directly to VSS. If the design is to be
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
Part 3 Specifications
3.1 General Characteristics
The 56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
13
The 56F802 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic
Symbol
VDD
VIN
Min
VSS – 0.3
VSS – 0.3
- 0.3
Max
VSS + 4.0
VSS + 5.5V
0.3
Unit
V
Supply voltage
All other input voltages, excluding Analog inputs
Voltage difference VDD to VDDA
V
ΔVDD
ΔVSS
VIN
V
Voltage difference VSS to VSSA
- 0.3
0.3
V
Analog Inputs ANAx, VREF
VSS – 0.3
—
VDDA + 0.3V
10
V
Current drain per pin excluding VDD, VSS, & PWM ouputs
I
mA
Table 3-2 Recommended Operating Conditions
Characteristic
Supply voltage, digital
Symbol
VDD
Min
3.0
Typ
3.3
3.3
-
Max
3.6
3.6
0.1
0.1
Unit
V
Supply Voltage, analog
VDDA
ΔVDD
ΔVSS
3.0
V
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
-0.1
-0.1
V
-
V
56F802 Technical Data, Rev. 9
14
Freescale Semiconductor
General Characteristics
Table 3-2 Recommended Operating Conditions
Characteristic
ADC reference voltage1
Symbol
VREF
TA
Min
2.7
Typ
–
Max
VDDA
85
Unit
V
Ambient operating temperature
1. VREF must be 0.3V below VDDA
–40
–
°C
.
6
Table 3-3 Thermal Characteristics
Value
32-pin LQFP
50.2
Note
Characteristic
Comments
Symbol
Unit
s
Junction to ambient
Natural convection
RθJA
°C/W
2
Junction to ambient (@1m/sec)
RθJMA
47.1
38.7
°C/W
°C/W
2
Junction to ambient
Natural convection
Four layer board (2s2p)
RθJMA
(2s2p)
1,2
Junction to ambient (@1m/sec) Four layer board (2s2p)
Junction to case
RθJMA
RθJC
ΨJT
37.4
17.8
3.07
°C/W
°C/W
°C/W
W
1,2
3
Junction to center of case
I/O pin power dissipation
4
P I/O
User Determined
P D = (IDD x VDD + P I/O
(TJ - TA) /RθJA
Power dissipation
P D
)
W
Junction to center of case
PDMAX
W
7
Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (ΨJT), is the "resistance" from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady state customer environments.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
15
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6. See Section 5.1 from more details on thermal design considerations.
7. TJ = Junction Temperature
TA = Ambient Temperature
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Input high voltage (XTAL/EXTAL)
Symbol
VIHC
VILC
VIHS
VILS
VIH
Min
2.25
0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
30
—
—
—
Max
2.75
0.5
5.5
0.8
5.5
0.8
1
Unit
V
Input low voltage (XTAL/EXTAL)
V
Input high voltage (Schmitt trigger inputs)1
2.2
-0.3
2.0
-0.3
-1
V
Input low voltage (Schmitt trigger inputs)1
Input high voltage (all other digital inputs)
V
V
Input low voltage (all other digital inputs)
VIL
V
Input current high (pullup/pulldown resistors disabled, VIN=VDD
)
IIH
μA
μA
μA
μA
μA
μA
KΩ
μA
μA
μA
Input current low (pullup/pulldown resistors disabled, VIN=VSS
Input current high (with pullup resistor, VIN=VDD
Input current low (with pullup resistor, VIN=VSS
Input current high (with pulldown resistor, VIN=VDD
)
IIL
-1
1
)
IIHPU
IILPU
IIHPD
IILPD
RPU, RPD
IOZL
-1
1
)
-210
20
-50
180
1
)
Input current low (with pulldown resistor, VIN=VSS
Nominal pullup or pulldown resistor value
Output tri-state current low
Output tri-state current high
2
)
-1
-10
-10
-15
10
10
15
IOZH
IIHA
Input current high (analog inputs, VIN=VDDA
)
2
IILA
-15
—
—
15
—
μA
Input current low (analog inputs, VIN=VSSA
)
Output High Voltage (at IOH)
VOH
VDD – 0.7
V
56F802 Technical Data, Rev. 9
16
Freescale Semiconductor
DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Output Low Voltage (at IOL)
Symbol
VOL
Min
—
4
Typ
—
—
—
—
—
8
Max
0.4
—
Unit
V
Output source current
Output sink current
IOH
mA
mA
mA
mA
pF
IOL
4
—
PWM pin output source current3
IOHP
IOLP
CIN
10
16
—
—
—
PWM pin output sink current4
Input capacitance
—
—
Output capacitance
VDD supply current
COUT
12
—
pF
5
IDDT
Run6 (80MHz Operation)
Run6 (60MHz Operation)
—
—
—
120
102
96
130
111
102
mA
mA
mA
Wait7
Stop
—
62
70
mA
V
Low Voltage Interrupt, external power supply8
Low Voltage Interrupt, internal power supply9
Power on Reset10
VEIO
VEIC
2.4
2.7
3.0
2.0
—
2.2
1.7
2.4
2.0
V
V
VPOR
1. Schmitt Trigger inputs are: FAULTA0, TCS, TCK, TMS, TDI, RESET, and TRST
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA
)
6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured
with PLL enabled.
8. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via
separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions
when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated).
9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless
the external power supply drops below the minimum specified value (3.0V).
56F802 Technical Data, Rev. 9
Freescale Semiconductor
17
10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,
this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally
regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates.
160
IDD Analog
IDD Total
IDD Digital
120
80
40
0
10
20
60
70
50
30
80
40
Freq. (MHz)
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
Low
VIL
High
VIH
90%
Input Signal
50%
Midpoint1
10%
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
56F802 Technical Data, Rev. 9
18
Freescale Semiconductor
Flash Memory Characteristics
•
•
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 3-3 Signal States
3.4 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Mode
Standby
Read
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
Word Program
Page Erase
Mass Erase
L
H
H
H
H
H
L
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 3-6 IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Program information block
Erase information block
Erase both blocks
Read main memory block
Program main memory block
Erase main memory block
Erase main memory block
Word program
Page erase
Mass erase
56F802 Technical Data, Rev. 9
Freescale Semiconductor
19
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Program time
Symbol
Min
20
Typ
Max
Unit
us
Figure
–
–
–
–
–
–
Figure 3-4
Figure 3-5
Figure 3-6
Tprog*
Terase*
Tme*
Erase time
20
–
–
ms
Mass erase time
100
10,000
10
ms
Endurance1
ECYC
20,000
30
cycles
years
Data Retention1
DRET
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
–
–
5
5
–
–
us
us
Figure 3-4,
Figure 3-5,
Figure 3-6
Tnvs*
NVSTR hold time
Figure 3-4,
Figure 3-5
Tnvh*
NVSTR hold time (mass erase)
NVSTR to program set up time
Recovery time
–
–
–
100
10
1
–
–
–
us
us
us
Figure 3-6
Figure 3-4
Tnvh1*
Tpgs*
Trcv*
Figure 3-4,
Figure 3-5,
Figure 3-6
Cumulative program
HV period2
–
3
–
ms
Figure 3-4
Thv
Program hold time3
–
–
–
–
–
–
–
–
–
Figure 3-4
Figure 3-4
Figure 3-4
Tpgh
Tads
Tadh
Address/data set up time3
Address/data hold time3
1. One Cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
56F802 Technical Data, Rev. 9
20
Freescale Semiconductor
Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
NVSTR
Tnvs
Tprog
Tpgh
Tpgs
Tnvh
Trcv
Thv
Figure 3-4 Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
Figure 3-5 Flash Erase Cycle
56F802 Technical Data, Rev. 9
Freescale Semiconductor
21
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
Figure 3-6 Flash Mass Erase Cycle
3.5 Clock Operation
The 56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates a
master reference frequency that determines the speed at which chip operations occur.
The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.
3.5.1
Use of On-Chip Relaxation Oscillator
The 56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal
or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting the 8-bit
IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output frequency of
the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures 9 and 10
show the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim
value.
During factory production test, an oscillator calibration procedure is executed which determines an
o
optimum trim value for a given device (8MHz at 25 C). This optimum trim value is then stored at address
$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence
(executed after power-up and RESET). This trim routine automatically sets the oscillator frequency by
programming the IOSCTL register with the optimum trim value.
56F802 Technical Data, Rev. 9
22
Freescale Semiconductor
Clock Operation
Due to the inherent frequency tolerances required for SCI communication, changing the factory-trimmed
oscillator frequency is not recommended. If modification of the Boot Flash contents are required, code
must be included which retrieves the optimum trim value (from address $103F in the Data Flash
Information Block) and writes it to the IOSCTL register. Note that the IFREN bit in the Data Flash control
register must be set in order to read the Data Flash Information Block.
Table 3-8 Relaxation Oscillator Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Frequency Accuracy1
Symbol
Δf
Min
—
Typ
+2
Max
+5
Unit
%
%/oC
%/V
Frequency Drift over Temp
Δf/Δt
Δf/ΔV
—
+0.1
0.1
—
Frequency Drift over Supply
1. Over full temperature range.
—
—
8.4
8.3
8.2
8.1
8.0
7.9
7.8
-40
-25
-5
15
35
55
75
85
Temperature (oC)
Figure 3-7 Typical Relaxation Oscillator Frequency vs. Temperature
o
(Trimmed to 8MHz @ 25 C)
56F802 Technical Data, Rev. 9
Freescale Semiconductor
23
11
10
9
8
7
6
5
0
10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
o
Figure 3-8 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25 C
3.5.2
Phase Locked Loop Timing
Table 3-9 PLL Timing
Characteristic
Frequency for the PLL1
Symbol
fosc
Min
4
Typ
8
Max
Unit
MHz
MHz
ms
10
PLL output frequency2
803
—
fout/2
tplls
40
—
—
—
PLL stabilization time4 0o to +85oC
PLL stabilization time4 -40o to 0oC
10
tplls
100
200
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. Will not exceed 60MHz for the DSP56F802TA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
56F802 Technical Data, Rev. 9
24
Freescale Semiconductor
Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 3
Table 3-10 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
RESET Assertion to Address, Data and Control Signals High
Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
tRA
275,000T
128T
—
—
ns
ns
OMR Bit 6 = 1
RESET De-assertion to First External Address Output
Edge-sensitive Interrupt Request Width
tRDA
tIRW
33T
34T
—
ns
ns
1.5T
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. Parameters listed are guaranteed by design.
General
Purpose
I/O Pin
tIG
IRQA
b) General Purpose I/O
Figure 3-9 External Level-Sensitive Interrupt Timing
56F802 Technical Data, Rev. 9
Freescale Semiconductor
25
3.7 Quad Timer Timing
1, 2
Table 3-11 Timer Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Timer input period
Symbol
PIN
Min
4T+6
2T+3
2T
Max
—
Unit
ns
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
1T
—
ns
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 3-10 Timer Timing
56F802 Technical Data, Rev. 9
26
Freescale Semiconductor
Serial Communication Interface (SCI) Timing
3.8 Serial Communication Interface (SCI) Timing
4
Table 3-12 SCI Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
BR
Min
—
Max
(fMAX*2.5)/(80)
1.04/BR
Unit
Mbps
ns
Baud Rate1
RXD2 Pulse Width
TXD3 Pulse Width
RXDPW
TXDPW
0.965/BR
0.965/BR
1.04/BR
ns
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 3-11 RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 3-12 TXD Pulse Width
56F802 Technical Data, Rev. 9
Freescale Semiconductor
27
3.9 Analog-to-Digital Converter (ADC) Characteristics
Table 3-13 ADC Characteristics
Characteristic
ADC input voltages
Symbol
Min
Typ
Max
Unit
01
12
—
—
VREF
2
VADCIN
—
V
Resolution
RES
INL
—
12
Bits
Integral Non-Linearity3
Differential Non-Linearity
LSB4
LSB3
+/- 4
+/- 5
+/- 1
DNL
+/- 0.9
Monotonicity
GUARANTEED
—
ADC internal clock5
Conversion range
fADIC
RAD
tADPU
tADC
0.5
VSSA
—
5
VDDA
—
MHz
V
—
2.5
6
Power-up time
msec
tAIC cycles6
tAIC cycles6
Conversion time
—
—
Sample time
tADS
—
1
—
pF6
—
Input capacitance
CADI
EGAIN
VOFFSET
THD
—
1.00
+10
55
5
1.10
+230
60
—
1.15
+325
—
Gain Error (transfer gain)5
Offset Voltage5
mV
dB
—
Total Harmonic Distortion5
Signal-to-Noise plus Distortion5
Effective Number of Bits5
SINAD
ENOB
SFDR
54
56
—
8.5
60
9.5
65
—
bit
Spurious Free Dynamic Range5
Spurious Free Dynamic Range
ADC Quiescent Current (both ADCs)
—
dB
SFDR
IADC
65
—
70
50
—
—
dB
mA
VREF Quiescent Current (both ADCs)
IVREF
—
12
16.5
mA
1. For optimum ADC performance, keep the minimum VADCIN value > 250mV. Inputs less than 250mV volts may convert
to a digital output code of 0 or cause erroneous conversions.
2. VREF must be equal to or less than VDDA - 0.3V and must be greater than 2.7V.
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. tAIC = 1/fADIC
56F802 Technical Data, Rev. 9
28
Freescale Semiconductor
JTAG Timing
ADC analog input
1
3
2
4
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at
sampling time. (1pf)
Figure 3-13 Equivalent Analog Input Circuit
3.10 JTAG Timing
1, 3
Table 3-14 JTAG Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF
Characteristic
TCK frequency of operation2
Symbol
fOP
Min
DC
100
50
Max
10
Unit
MHz
ns
TCK cycle time
tCY
—
TCK clock pulse width
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
tPW
—
ns
tDS
0.4
1.2
—
—
ns
tDH
—
ns
tDV
26.6
23.5
—
ns
tTS
—
ns
tTRST
50
ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
29
tCY
tPW
tPW
VIH
VM
VIL
VM
TCK
(Input)
VM = VIL + (VIH – VIL)/2
Figure 3-14 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
tDV
(Input)
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 3-15 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 3-16 TRST Timing Diagram
56F802 Technical Data, Rev. 9
30
Freescale Semiconductor
Package and Pin-Out Information 56F802
Part 4 Packaging
4.1 Package and Pin-Out Information 56F802
This section contains package and pin-out information for the 32-pin LQFP configuration of the 56F802.
ORIENTATION
PWMA4
MARK
ANA3
PIN 25
PWMA5
TD1
VREF
PIN 1
ANA2
TD2
TXDO
VSS
FAULTA0
VSS
VDD
VDD
VSSA
VDDA
PIN 17
PIN 9
RXD0
Figure 4-1 Top View, 56F802 32-pin LQFP Package
56F802 Technical Data, Rev. 9
Freescale Semiconductor
31
Table 4-1 56F802 Pin Identification by Pin Number
Pin No.
Signal Name
PWMA4
PWMA5
TD1
Pin No.
Signal Name
TCS
Pin No.
17
Signal Name
VDDA
Pin No.
25
Signal Name
ANA4
1
2
3
4
9
10
11
12
TCK
18
VSSA
26
ANA6
TMS
19
VDD
27
ANA7
TD2
TDI
20
VSS
28
PWMA0
5
6
TXDO
VSS
13
14
VCAPC2
TDO
21
22
FAULTA0
ANA2
29
30
VCAPC1
PWMA1
7
8
VDD
15
16
TRST
23
24
VREF
ANA3
31
32
PWMA2
PWMA3
RXD0
RESET
56F802 Technical Data, Rev. 9
32
Freescale Semiconductor
Package and Pin-Out Information 56F802
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE A, B AND D TO BE DETERMINED
AT DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSIONS b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION
BY MORE THEN 0.08 MM. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTURSION: 0.07 MM.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
MMPERSIDE.D1ANDE1AREMAXIMUMPLASTIC
BODY SIZE DIMENSIONS INCLUDING MOLD
MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTIONOFTHELEADBETWEEN0.1MMAND0.25
MM FROM THE LEAD TIP.
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
MAX
1.60
0.15
1.45
0.45
1.40
0.05
1.35
0.30
0.30
0.09
0.09
0.40
0.20
0.16
9.00 BSC
D1
e
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
E
E1
L
L1
O
O1
R1
R2
S
0.50
0.70
1.00 REF
°
0
°
7
° REF
12
0.08
0.08
0.20
--
0.20 REF
Figure 4-2 32-pin LQFP Mechanical Information (Case 873A)
Please see www.freescale.com for the most current case outline.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
33
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , in °C can be obtained from the equation:
J
Equation 1:TJ = TA + (PD × RθJA
)
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:RθJA = RθJC + RθCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For example, the user can change the air flow around
θCA
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R
the thermal performance is adequate, a system level model may be appropriate.
do not satisfactorily answer whether
θJA
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
56F802 Technical Data, Rev. 9
34
Freescale Semiconductor
Electrical Design Considerations
•
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Use the following list of considerations to assure correct operation:
•
Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS (GND) pin.
•
The minimum bypass requirement is to place 0.1 μF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
performance tolerances.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
35
•
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.
Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with ceramic or tantalum
capacitors which tend to provide better performance tolerances.
•
•
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
•
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
•
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
56F802 Technical Data, Rev. 9
36
Freescale Semiconductor
Electrical Design Considerations
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
Table 6-1 56F802 Ordering Information
Ambient
Frequency
(MHz)
Supply
Voltage
Pin
Count
Part
Package Type
Order Number
56F802
56F802
3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP)
3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP)
32
32
80
60
DSP56F802TA80
DSP56F802TA60
56F802
56F802
3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP)
3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP)
32
32
80
60
DSP56F802TA80E*
DSP56F802TA60E*
*This package is RoHS compliant.
56F802 Technical Data, Rev. 9
Freescale Semiconductor
37
56F802 Technical Data, Rev. 9
38
Freescale Semiconductor
Electrical Design Considerations
56F802 Technical Data, Rev. 9
Freescale Semiconductor
39
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F802
Rev. 9
01/2007
相关型号：
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