FS32V232CKN1CUBR [NXP]
ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache;
| 型号： | FS32V232CKN1CUBR |
| 厂家： | 
NXP |
| 描述： | ARM Cortex-M4, 32-bit CPU 16 KB/16 KB I-/D- L1 Cache |
| 文件： | 总90页 (文件大小：1889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number S32V234
Rev. 9, 03/2020
NXP Semiconductors
Data Sheet: Technical Data
S32V234
S32V234 Data Sheet
Features
• Safety concept
– ISO 26262, ASIL level target
• ARM® Cortex®-A53, 64-bit CPU
– Up to 1000 MHz Quad ARM Cortex-A53
– 32 KB/32 KB I-/D- L1 Cache
– NEON MPE co-processor
– Measures to detect faults in memory and logic
– Measures to detect single point and latent faults
– Quantitative out of context analysis of functional
safety (FMEDA) tailored to application specifics
– Safety manual and FMEDA report available
– Dual precision FPU
– 2 clusters with 2 CPUs and 256 KB L2 cache each
– Memory Management Unit
• Security
– GIC Interrupt Controller
– ECC/parity error support for its memories
– Generic timers
– Fault encapsulation by hardware for redundant
executed application software on multiple core
cluster
– CSE with 16 KB of on-chip Secure RAM and ROM.
– ARM TrustZone (TZ) architecture support
– Boot from NOR flash with AES-128 (CTR)
– On-Chip One-Time Programmable element
Controller (OCOTP_CTRL) with on chip electrical
fuse array.
– System JTAG Controller (SJC)
• ARM Cortex-M4, 32-bit CPU
– Up to 133 MHz
• Debug functionality
– 16 KB/16 KB I-/D- L1 Cache
– 32+32 KB tightly coupled memory (TCM)
– ECC/parity support for its memories
– Standard JTAG and Compact JTAG
– 16-bit Trace port, Serial Wire Output port
• Timers
• Clocks
– General purpose timers (FTM)
– Two Periodic Interrupt Timer (PIT)
– IEEE 1588 Timers (part of Ethernet Subsystem)
– Phase Locked Loops (PLLs)
– 1 external crystal oscillator (FXOSC)
– 1 FIRC oscillator
• Analog
• System protection and power management features
– Flexible run modes to consume low power based on
application needs
– 1x 12-bit 1.8 V SAR ADC with self-test
• Communications
– UART(w/ LIN2.1l)
– Serial peripheral interface (SPI)
– I2C blocks
– PCI express 2.0 with endpoint and root complex
support
– LFAST serial link
– 1 GBit Ethernet with PTP IEEE 1588
– FD-CAN
– FlexRay Dual Channel, Version 2.1 RevA
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Power gating of unused A53 cores and GPU
– Low and high voltage warning and detect
– Hardware CRC module to support fast cyclic
redundancy checks (CRC)
– 120-bit unique chip identifier
– Hardware watchdog
– eDMA controller with 32 channels (with
DMAMUX)
– Extended Resource Domain Controller
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Memory interfaces
– 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock
frequency with ECC (SEC-DED-TED) triple error detection support for subregion
– QuadSPI supporting Execute-In-Place (XIP)
– Boot flash fault detection and correction using two-dimensional parity.
– Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
• Video input interfaces, Image processing, graphics processing, display
– Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding
– GPU GC3000 with frame buffer compression
– 2x VIU (Video interface unit) for camera input
– 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)
– Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions
(exposure control, gamma correction)
– 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) cores
configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMD
engines with 32 16-bit CUs each.
– CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter
– JPEG video decoder (8/12-bit)
– H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats
– H.264 video encode (8/10/12-bit), High-intra only
– Fast DMA for data transfers between DRAM and System RAM with CRC
• Human-Machine Interface (HMI)
– GPIO pins with interrupt support, DMA request capability, digital glitch filter
– Configurable slew rate and drive strength on all output pins
• System RAM
– 4 MB On-Chip System RAM with ECC
S32V234 Data Sheet, Rev. 9, 03/2020
2
NXP Semiconductors
Table of Contents
1
2
Block diagram.................................................................................... 5
6.3 Memory interfaces...................................................................26
6.3.1 QuadSPI AC specifications....................................... 26
6.4 DDR SDRAM Specific Parameters (DDR3, DDR3L, and
LPDDR2)................................................................................ 31
6.4.1 DDR3 and DDR3L timing parameters .....................31
6.4.2 DDR3 and DDR3L read cycle...................................33
6.4.3 DDR3 and DDR3L write cycle................................. 34
6.4.4 LPDDR2 timing parameter........................................35
6.4.5 LPDDR2 read cycle...................................................37
6.4.6 LPDDR2 write cycle................................................. 38
6.5 Communication modules.........................................................39
6.5.1 DSPI timing...............................................................39
6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface
(uSDHC)....................................................................43
Family comparison.............................................................................5
2.1 Feature Set...............................................................................5
Ordering parts.....................................................................................8
3.1 Ordering information...............................................................8
General............................................................................................... 8
4.1 Operation above maximum operating conditions................... 8
4.2 Recommended operating conditions....................................... 9
4.3 Power Management Controller (PMC) electrical
3
4
specifications...........................................................................10
4.4 Power consumption.................................................................11
4.5 Electrostatic discharge (ESD) specifications.......................... 13
4.6 Electromagnetic Compatibility (EMC) specifications............ 13
4.7 PCB routing guidelines........................................................... 13
I/O parameters....................................................................................15
5.1 General purpose I/O parameters..............................................15
5.1.1 GPIO speed at various voltage levels........................15
5.1.2 DC electrical specifications.......................................17
5.2 DDR pads................................................................................ 18
5.2.1 DDR3 mode...............................................................18
5
6.5.2.1
6.5.2.2
SDR mode timing specifications........... 43
DDR mode timing specifications...........45
6.5.3 LFAST electrical characteristics............................... 48
6.5.3.1
6.5.3.2
LFAST interface timing diagrams.........48
LFAST Interface electrical
characteristics........................................ 49
5.2.1.1
DDR3 mode DC electrical
6.5.4 FlexRay......................................................................50
specifications......................................... 18
6.5.4.1
6.5.4.2
6.5.4.3
6.5.4.4
FlexRay timing parameters....................50
TxEN......................................................50
TxD........................................................51
RxD........................................................52
5.2.2 DDR3L mode............................................................ 18
5.2.2.1
DDR3L mode DC electrical
specifications......................................... 18
5.2.3 LPDDR2 mode.......................................................... 19
6.5.5 Ethernet Controller (ENET) Parameters................... 53
5.2.3.1
LPDDR2 mode DC electrical
6.5.5.1
6.5.5.2
Ethernet Switching Specifications.........53
Receive and Transmit signal timing
specifications......................................... 19
5.3 Boot Configuration Pins Specification....................................20
Peripheral operating requirements and behaviors..............................20
6.1 Analog modules.......................................................................20
6.1.1 ADC electrical specifications....................................20
specifications for RMII interfaces......... 53
Receive and Transmit signal timing
6
6.5.5.3
6.5.5.4
6.5.5.5
specifications for MII interfaces............54
Receive and Transmit signal timing
6.1.1.1
Input equivalent circuit..........................21
specifications for RGMII interfaces...... 56
MII/RMII Serial Management channel
timing (MDC/MDIO)............................ 57
6.1.2 Thermal Monitoring Unit (TMU)..............................23
6.2 Clocks and PLL interfaces modules........................................23
6.2.1 Main oscillator electrical characteristics................... 23
6.2.2 48 MHz FIRC electrical characteristics.................... 24
6.2.3 PLL electrical specifications..................................... 24
6.2.4 DFS electrical specifications..................................... 25
6.2.5 LFAST PLL Electrical Specifications.......................25
6.5.6 PCI Express specifications........................................ 58
6.5.7 IIC timing.................................................................. 59
6.5.8 LINFlex timing..........................................................60
6.6 Display modules......................................................................61
6.6.1 Display Control Unit (2D-ACE) Parameters.............61
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
3
6.6.1.1
6.6.1.2
Interface to TFT panels..........................61
Interface to TFT LCD Panels—Pixel
Level Timings........................................62
Interface to TFT LCD panels—access
level........................................................63
6.10 External interrupt timing (IRQ pin)........................................ 74
Thermal attributes.............................................................................. 75
7.1 Thermal attributes................................................................... 75
Dimensions.........................................................................................76
8.1 Obtaining package dimensions ...............................................76
Pinouts................................................................................................76
9.1 Package pinouts and signal descriptions................................. 76
7
8
9
6.6.1.3
6.6.2 Video input unit (VIU) timing specifications............64
6.6.3 MIPICSI2 D-PHY electrical and timing parameters.65
6.6.3.6
NOTICE OF DISCLAIMER................. 68
10 Reset sequence................................................................................... 76
10.1 Reset sequence duration..........................................................76
10.2 Boot performance matrix........................................................ 77
10.3 Reset sequence description......................................................78
11 Power sequencing requirements.........................................................80
12 Revision history................................................................................. 81
6.7 Debug specifications............................................................... 69
6.7.1 JTAG interface timing...............................................69
6.7.2 Debug trace timing specifications............................. 73
6.8 Wakeup Unit (WKPU) AC specifications.............................. 74
6.9 RESET pin glitch filter specifications.....................................74
S32V234 Data Sheet, Rev. 9, 03/2020
4
NXP Semiconductors
Block diagram
1 Block diagram
GIC-400
Core0
Debug Core1
1000MHz
Cortex-A53
NEON/FPU
32KB 32KB
Debug
Core2
Debug Core3
1000MHz
Cortex-A53
NEON/FPU
32KB 32KB
Debug
1000MHz
Cortex-A53
1000MHz
Cortex-A53
NEON/FPU
32KB 32KB
NEON/FPU
32KB 32KB
256KB
L2-
Cache
256KB
L2-
Cache
I-Cache D-Cache I-Cache D-Cache
I-Cache D-Cache I-Cache D-Cache
CRC
Debug
Debug
Display
Control
Unit
NVIC
APEX-2_0
(2xAPU)
APEX-2_1
(2xAPU)
Fast
DMA
64KB
TCM
CoreP
133MHz
Cortex-
M4
CSE-FL Security
GPU
GC3000
Engine
CMEM
16x 2Kx64
CMEM
16x 2Kx64
(2D-ACE)
16KB
DRAM
SCU
SCU
Debug
16KB
I-Cache D-Cache
32KB
32KB
32KB
32KB
128-bits
128-bits
1KB
FUSE IF
ROM
IMEM
MEMIF
BlkDMA
DMEM
IMEM
Seq
DMEM
DMA
MEM
eDMA
16KB
CCI-400 incl. EDC
Debug
Concentrator
Seq
DMA
MEMIF
DMA
CDC420
Encoder
DEC200 DEC200
Decoder Encoder
Sideband
Outputs
BIU
MC
BlkDMA
128-bits
128-bits
SRAM - all others
64-bits AHB
Cortex-A53
128-
bits
128-
bits
64-
bits
64-
bits
128-
bits
64-bits
AHB
64-bits
AHB
64-bits
AHB
32-bits 64-bits
64-bits 64-bits
64-bits
64-
bits
MC
MC
AHB
AHB
AHB
AHB
Hierarchical NIC 301 AXI Bus System incl. EDC
AXBS Bus System incl. EDC
XRDC
XRDC
128-bits
XRDC
XRDC
XRDC
32-bits
128-
bits
128-
bits
SEQ
64-bits
64-bits
64-bits
AHB
64-bits
64-bits
DRAM -
all others all others
64-bits
64-bits
SRAM -
OTFAD
QoS 301 incl. EDC
XRDC
Debug
Peripheral
Bridge 1
Peripheral
Bridge 0
QuadSPI
NOR Flash Ctrl
ROM
Ctrl
MIPI-CSI2
MIPI-CSI2
ISP0
Debug
32-bits
2x4-bits
32-bits
32-bits
4KB
DRAM-ECC
DRAM-ECC
SWT_0
SWT_1
STM_0
PIT_0
STCU
MC
ISP1
ISP2
• • •
ISPN
H.264 Encoder
H.264 Decoder
JPEG Decoder
PRAM
SRAM Controller
Multi Ported
Multi Banked
64KB
CRAM
16KB
KRAM
4/2x4/8-bits
QSPI Flash
64 KB
ROM
(boot)
32-bit MMDC_0
LPDDR2
32-bit MMDC_1
LPDDR2
DDR3(L)
DDR3(L)
External NOR Flash
Off-Chip
DDR-PHY
DDR-PHY
MC
CGM, RGM,
PCU, ME
533 MHz
1066 MT/s
DDR
533 MHz
1066 MT/s
DDR
4MB SRAM
24+Banks
ECC x64 Internal
Figure 1. Block diagram
2 Family comparison
2.1 Feature Set
This family of devices supports the following features:
Table 1. Feature Set
Feature
S32V234
S32V232
ARM Cortex-A53 Core
• Up to 1000 MHz Quad ARM Cortex-A53
• 32 KB/32 KB I-/D- L1 Cache
• NEON MPE co-processor
• Dual precision FPU
• Up to 1000 MHz Dual ARM Cortex-A53
(single cluster)
• The remaining features are same as
S32V234
• 256 KB L2 Cache per cluster
• MMU
• GIC interrupt controller
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
5
Family comparison
Feature
Table 1. Feature Set (continued)
S32V234
S32V232
• ECC/parity error support for its
memories
• Generic timers
ARM Cortex-M4 Core
• Up to 133 MHz
• Same as S32V234
• 16 KB/16 KB I-/D- L1 Cache
• 32+32 KB tightly coupled memory
(TCM)
• ECC/parity support for its memories
Clocks
• Phase Locked Loops (PLLs)
• 1 external crystal ocillators (FXOSC)
• 1 FIRC
• Same as S32V234
System, protection and power
management features
• Flexible run modes to consume lower
power based on application needs.
• Peripheral clock enable registers can
disable clocks to unused modules,
thereby reducing currents
• Same as S32V234
• Low and high voltage warning and
detect
• Hardware CRC module to support fast
cyclic redundancy checks (CRC)
• 120-bit unique chip identifier
• Hardware watchdog
• Safe eDMA controller with 32 channels
(with DMAMUX)
• Extended Resource Domain Controller
Safety concept
• ISO 26262, ASIL level target as per
safety concept
• Same as S32V234
• Measures detecting faults in memory
and logic
• Measures to detect single point and
latent faults
• Quantitative out of context analysis of
functional safety (FMEDA) tailored to
application specifics
• Safety manual and FMEDA report
available
• Boot flash authentication and fault
detection and correction using AES-128
and two-dimensional parity.
• Double and triple fault detection and
single fault correction scheme for
external DDR-RAM including address/
page fault detection.
• Fault encapsulation by hardware for
redundant executed application
software on multiple core cluster.
• Structural software based self test
routines providing high diagnostic
coverage.
Debug
Timers
• Standard JTAG
• 16-bit Trace port, Serial Wire Output
port
• Same as S32V234
• Same as S32V234
• General purpose timers (FTM)
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
6
NXP Semiconductors
Family comparison
Table 1. Feature Set (continued)
Feature
S32V234
S32V232
• Two Periodic Interrupt Timer (PIT)
• IEEE 1588 Timers (part of Ethernet
Subsystem)
Communications
• UART(w/ LIN2.1l)
• Same as S32V234
• Serial peripheral interface (SPI)
• I2C blocks
• PCI express 2.0 with endpoint and root
complex support
• LFAST serial link
• 1 GBit Ethernet with PTP IEEE 1588
• FD-CAN
• Flexray Dual Channel, Version 2.1
RevA
Memory Interfaces
• 32-bit DRAM Controller with support for
LPDDR2/DDR3/DDR3L - Data rate of
up to 1066 MT/s at 533 MHz clock
frequency with ECC (SEC-DED-TED)
single error correction, double error
detection, and triple error detection
support for subregion
• Same as S32V234
• Dual QuadSPI supporting Execute-In-
Place (XIP)
Video input interfaces, Image
processing, graphics
processing, display
• Display Control Unit (2D-ACE) with 24-
bit RGB, GPU framebuffer decoding
• GPU GC3000 with frame buffer
compression
• Same as S32V234
• 2x Video interface unit (VIU) for camera
input
• 2x CSI with 4 lanes for camera input
(support 1080p @ 30fps)
• Image signal processor (ISP),
supporting 2x1 or 1x2 MPixel @ 30fps
and 4x1 MPixel for subset of functions
(exposure control, gamma correction)
• 2x APEX2-CL Image cognition
processor (dual 32-bit array processor)
• JPEG video decoder (8/12-bit)
• H.264 video decoder (8/10/12-bit), High-
intra and constrained baseline formats
• H.264 video encoder (8/10/12-bit), I-
frames only
• Safe Fast DMA for data transfers
between DRAM and System RAM with
CRC
Analog
• 1x 12-bit SAR ADC with self-test
• Same as S32V234
• Same as S32V234
Human-Machine Interface
(HMI)
• SIUL, GPIO pins with interrupt support,
DMA request capability, digital glitch
filter.
• Configurable slew rate and drive
strength on all output pins
System RAM
• 4 MB On-Chip System RAM with ECC
• Run modes:
• 3 MB On-Chip System RAM with ECC
• Same as S32V234
Power Consumption
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
7
Ordering parts
Table 1. Feature Set
Feature
S32V234
S32V232
• Frequency scaling and clock
gating for processing blocks and
peripherals in run mode
3 Ordering parts
3.1 Ordering information
K N1 V UB R
B
FS32V23
4
Device Family
Core configuration
Speed configuration
Device configuration
Temeprature options
Shipping method
Speed configuration
Temperature options
Core configuration
Shipping method
R = Tape and reel
(blank) = Trays
B = Arm Cortex - A53 @800 MHz
C = Arm Cortex - A53 @1 GHz
C = -40 to 105°C
V = -40 to 125 °C
2 = Dual Arm Cortex - A53
4 = Quad Arm Cortex - A53
Device configuration*
ISP
Low power
3D GPU CSE
eIQ Auto
(leakage based)
No
Yes
No
K
L
Yes
Yes
No
No
Yes
Yes
No
K becomes Q
L becomes R
M becomes S
O becomes T
J becomes U
M
O
J
Yes Yes
Yes Yes
Yes
No
No
Yes
Yes
No
* All combinations are not orderable
NOTE
Not all combinations are orderable. For the latest information
on orderable parts check https:// www.nxp.com/s32v234 Buy/
Parametrics section.
4 General
4.1 Operation above maximum operating conditions
S32V234 Data Sheet, Rev. 9, 03/2020
8
NXP Semiconductors
General
Table 2. Operation above maximum operating conditions
1.8 V DGO Voltage Domain
Electrical Specifications
Value
Conditions
< 60 s
Junct Temp
25 °C
Absolute Maximum Supply 3.0 V
Voltage
Absolute Maximum Supply 2.3 V
Voltage
< 10 hr
25 °C
Core Voltage Domain
Electrical Specifications
Value
Conditions
< 60 s
Junct Temp
25 °C
Absolute Maximum Supply 1.29 V
Voltage
Absolute Maximum Supply 1.1 V
Voltage
< 10 hr
25 °C
3.3 V DGO Voltage Domain
Electrical Specifications
Value
Conditions
< 60 s
Junct Temp
25 °C
Absolute Maximum Supply 4.95 V
Voltage
Absolute Maximum Supply 4.29 V
Voltage
< 10 hr
25 °C
4.2 Recommended operating conditions
Table 3. Recommended operating conditions
Symbol
VDD_GPIO0
Parameter
3.3 V I/O segment GPIO0 supply voltage
1.8 V input/output supply voltage
3.3 V input/output supply voltage
Conditions
Min
Max
Unit
—
3.15
1.71
3.15
3.6
V
V
V
VDD_GPIO<n=1,2>
VDD_HV_IO_VIU0
VDD_HV_IO_VIU1
VDD_HV_IO_DIS
VDD_HV_IO_FLA
VDD_HV_IO_ETH
—
—
1.95
3.6
1.5 V I/O supply voltage
1.8 V I/O supply voltage
2.5 V I/O supply voltage
3.3 V I/O supply voltage
Common ground voltage1
1.0 V core domain supply voltage2
—
—
—
—
—
—
1.425
1.71
2.375
3.15
0
1.575
1.95
2.625
3.6
V
V
V
V
V
V
VSS
0
VDD_LV_CORE_SOC
,
0.95
1.05
VDD_LV_CORE_ARM
VDD_LV_CORE_GPU
,
VDD_HV_CSI
VDD_LV_CSI
VDD_HV_PLL
1.8 V supply voltage (for MIPICSI2 D PHY)
1.0 V supply voltage (for MIPICSI2 D PHY)
1.8 V supply voltage (for analog circuits, PLLs)
—
—
—
1.71
0.95
1.71
1.95
1.05
1.95
V
V
V
,
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
9
General
Table 3. Recommended operating conditions (continued)
Symbol
VDD_HV_LFASTPLL
VDD_HV_FXOSC
Parameter
Conditions
Min
Max
Unit
,
,
VDD_HV_PMC
,
,
VDDIO_LFAST
VDD_HV_EFUSE
VDD_HV_DDR
VDD_LV_PLL
VDD_LV_POST
VREFH_ADC
VDD_HV_ADV
VSS_HV_ADV
VREFL_ADC
,
1.0 V supply voltage (for analog circuits, PLLs)
—
0.95
1.05
V
1.8 V ADC high reference voltage
1.8 V ADC supply voltage
—
—
—
—
—
—
—
—
—
—
—
—
1.71
1.71
0
1.95
1.95
0
V
V
ADC ground and low reference voltage
1.8 V ADC supply ground
V
0
0
V
VDD_DDR_IO
DDR I/O supply voltage LPDDR2
DDR I/O supply voltage DDR3
DDR I/O supply voltage DDR3L
PCIe supply voltages
1.14
1.425
1.283
0.95
1.71
-40
1.30
1.575
1.45
1.05
1.95
1053
125
25
V
V
V
PCIE_VP
PCIE_VPH
TA
V
V
Ambient temperature
°C
°C
TJ
Junction temperature under bias
Supply ramp rate for all supplies on the device
-40
TVDD
0.05
V/ms
1. All the grounds viz. VSS, VSS_FXOSC, and VSS_HV_ADV are tied together at the package level.
2. VDD_LV_CORE_SOC, VDD_LV_CORE_ARM, and VDD_LV_CORE_GPU supply balls should all be connected together to one power
plane and one regulator to avoid voltage level differences. If the GPU is power gated as it is not used, the
VDD_LV_CORE_GPU supply balls have to be statically connected to the ground plane. If the second ARM CPUs per cluster is
power gated as they are not used, the VDD_LV_CORE_ARM supply balls have to be statically connected to the ground plane.
3. Maximum ambient temperature requires management of the heat dissipation to ensure the device junction temperature
does not exceed the maximum.
4.3 Power Management Controller (PMC) electrical specifications
PMC is composed of the following blocks:
• Low voltage detector (LVD_33_PMC) for 3.3 V VDD_GPIO0 supply (GPIO
segment and PMC) and Low Voltage Detector for FIRC (VDD_HV_FXOSC)
• Low voltage detector (LVD_18) for VDD_HV_PMC
• Low voltage detector (LVD_18) for VDD_HV_FXOSC
• High voltage detector (HVD_18) for VDD_HV_PMC
• Low voltage detector (LVD_CORE) for VDD_LV_CORE_SOC
• High voltage detector (HVD_CORE) for VDD_LV_CORE_SOC
• Power on Reset (POR)
S32V234 Data Sheet, Rev. 9, 03/2020
10
NXP Semiconductors
General
Unit
Table 4. PMC electrical specifications
Supply
Parameter Conditions Threshold
Min
Typical
Max
Status
during
power-up
VDD_LV_CORE_SOC
low voltage Native
monitoring
VTL1
VTH2
VTL
836
880
924
Enabled
mV
850
895
940
Trimmed
896
910
924
VTH
VTL
911
925
946
VDD_LV_CORE_SOC
VDD_HV_PMC
high
voltage
monitoring
Trimmed
1049
1064
1065
1080
1093
1093
Disabled
Enabled
mV
mV
VTH
PMC
Native
VTL
VTH
VTL
VTH
VTL
VTH
1511
1525
1620
1635
2004
2019
1590
1605
1650
1665
2045
2060
1670
1685
1680
1695
2086
2101
supply low
voltage
monitor
Trimmed
Trimmed
VDD_HV_PMC
VDD_GPIO0
PMC
Disabled
Enabled
mV
mV
supply high
voltage
monitor
low voltage Native
monitor
VTL
VTH
VTL
VTH
VTL
VTH
VTL
VTH
–
2727
2746
2857
2876
1511
1525
1620
1635
1176
2870
2890
2915
2935
1590
1605
1650
1665
1200
3014
3035
2973
2994
1670
1685
1680
1695
1224
Trimmed
VDD_HV_FXOSC
PMC_BGREF
FXOSC
supply low
voltage
Native
Enabled
Enabled
mV
mV
Trimmed
monitor
PMC Band Trimmed
Gap
Reference
value
1. Lower threshold/assert point
2. Upper threshold/release point
4.4 Power consumption
The following table shows the power consumption data. These specifications are subject
to change per device characterization.
Table 5. Power consumption
Parameter
Description
Max Values
125C Tj
105C Tj
VDD_LV_CORE (Static)1, 2
32V234BL Device in reset
3 A
2.3 A
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
11
General
Table 5. Power consumption (continued)
Parameter
Description
Max Values
125C Tj
6.0 A
6.4 A
4.8 A
2.7 A
4.4 A
105C Tj
S32V232BM Device in reset
S32V234CO Device in reset
S32V234CK Device in reset
S32V232BL Device in reset
S32V232CK Device in reset
4.5 A
4.8 A
3.5 A
2.0 A
3.2 A
VDD_LV_CORE (Dynamic)
VDD_HV_CSI
4x A53 CPU with Dhrystone
MIPS running on each CPU
@1 GHz3
1.4 A
Current for both MIPICSI2
interfaces operating as per
1) 10 mA
2) 1 mA
1) RX Operation at 1.5 Gbps
per MIPICSI2
2) MIPICSI2 not used (IP
Powered and Disabled)
VDD_LV_CSI
Current for both MIPICSI2
interfaces operating as per
1) 40 mA
2) 13 mA
1) RX Operation at 1.5 Gbps
per MIPICSI2
2) MIPICSI2 not used (IP
Powered and Disabled)
VDD_HV_PLL
All five PLLs operating at 1
GHz VCO frequency
35 mA
VDD_HV_LFASTPLL
Use case:
1) 26 mA
2) .1 mA
1) PLL operating with 320
MHz (LFAST used)
2) PLL not operational
(LFAST not used)
VDD_HV_FXOSC
Shared supply for FXOSC
operating with 40 MHz crystal
and FIRC oscillator
5 mA
VDD_HV_PMC
As per default usage (no use
case differentiation)
10 mA
VDD_HV_EFUSE
Use case:
1) 10 mA
1) eFuse programming
happening
VDD_LV_PLL
PCIE_VP
All five PLLs operating at 1
GHz VCO frequency
80 mA
Use case:
1) 80 mA
2) 30 mA
1) 5 GHz operation (PCIe 2.0)
2) Reset/idle
PCIE_VPH
Use case:
1) 50 mA
2) 20 mA
1) 5 GHz operation (PCIe 2.0)
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
12
NXP Semiconductors
General
Table 5. Power consumption (continued)
Parameter
Description
Max Values
125C Tj
105C Tj
2) Reset/idle
VDD_HV_ADV
VDD_REFH_ADC
ADC operational
1 mA
Voltage reference for ADC
80 μA
1. Data represented is at 125 °C Tj and 1.01 V vdd conditions
2. Includes SoC, GPU, and ARM supply combinations depending on use case description.
3. Adder to the static idd current component. 4xCortex A53 executing Dhrystone MIPS in AArch64 and the interconnect,
System RAM, FastDMA, Cortex M4, peripheral bridges, FCCU, CSE, MEMU, PCIe, and STCU are clocked - static power
consumption excluded.
4.5 Electrostatic discharge (ESD) specifications
Electrostatic discharges are applied to the pins of each sample in conformity with AEC-
Q100-002/-011 to meet the HBM and CDM ratings described below.
Table 6. ESD ratings1
Symbol
VESD(HBM)
Parameter
Conditions
Class
Max value2
2000
Unit
Electrostatic discharge
(Human Body Model)
TA = 25 °C conforming to AEC- H1C
Q100-002
V
V
VESD(CDM)
Electrostatic discharge
(Charged Device Model)
TA = 25 °C conforming to AEC- C3A
Q100-011
500
1. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
2. Data based on characterization results, not tested in production.
4.6 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
4.7 PCB routing guidelines
DDR3/DDR3L PCB design
• CLK/Addess/Commands
• Route with 50 ohm controlled impedance and differential pair (CLK) with 100
ohm controlled impedance
• Use Fly by topology in case of multiple memory components
• Address and command lines Terminated to VTT with 50 ohm
• To be referenced with Power, not Ground
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
13
General
• Address/Cmd to be routed within 66 mils with respect to CLK and to be matched
from controller to memory; memory to memory as well
• All traces to be routed in internal layers
• Preference is to use only two layers for routing this group
• Limit the via number to less than three
NOTE
The differential clock lines on the DDR3 interface should
use AC termination scheme, with a 0.1 µF series capacitor
and referenced to DDR IO supply (VDD_DDR_IO).
• Data/Strobe
• Route with 50 ohm controlled impedance and differential pair (DQS strobe) with
100 ohm controlled impedance
• Data to be routed within 33 mils with respect to respective strobe
• To be referenced with Ground
• All traces to be routed in internal layers
• Strictly to be routed in only two layers
• Avoid more than two vias
LPDDR2 PCB design
• CLK/Addess/Commands
• Route with 50 ohm controlled impedance and differential pair (CLK) with 100
ohm controlled impedance
• To be referenced with Power, not Ground
• Address/Cmd to be routed within 66 mils with respect to CLK and to be matched
from controller to memory
• All traces to be routed in internal layers and delay should be less than 150 ps
• Preference is to use only two layers for routing this group
• Limit the via number to less than three
• Data/Strobe
• Route with 50 ohm controlled impedance and differential pair (DQS strobe) with
100 ohm controlled impedance
• Data to be routed within 33 mils with respect to respective strobe
• To be referenced with Ground
• All traces to be routed in internal layers and delay should be less than 150 ps
• Strictly to be routed in only two layers
• Avoid more than two vias
GPIO Interfaces
• QuadSPI
• Put 22 ohm series termination on board when operating with
SIUL2_MSCRn[DSE] 111
S32V234 Data Sheet, Rev. 9, 03/2020
14
NXP Semiconductors
I/O parameters
• TRACE
• Put 22 ohm series termination on board when operating with
SIUL2_MSCRn[DSE] 111
• ENET
• Put 22 ohm series termination on board when operating with
SIUL2_MSCRn[DSE] 111
5 I/O parameters
5.1 General purpose I/O parameters
5.1.1 GPIO speed at various voltage levels
NOTE
Rise/fall times numbers in Datasheet are guaranteed by design;
to obtain actual rise/fall times parameters with specific
packages and boards, use appropriate I/O IBIS model.
Table 7. GPIO rise/fall times (1.8 V range)
Parameter
Symbol
Drive strength
SIUL2_MSCRn[D
SE]
Slew
rate
Test
conditions
Typ
Max
Unit
IO output
tpr
001
slow
15 pF Cload
on pad
7.17/7.55
7.13/7.52
3.14/3.31
2.66/3.04
2.56/2.51
1.97/2.20
3.08/3.02
2.59/2.58
2.56/2.42
1.84/1.96
1.82/1.67
1.13/1.24
ns
transition
fast
time, rise/fall1
010
011
100
101
111
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
1. Max condition: wcs model, 0.9 V vddi, 1.62 V ovdd, and 125 °C. Input transition time is 120 ps.
Slow slew rate means SIUL2_MSCRn[SRE] = ‘00’, fast slew rate means SIUL2_MSCRn[SRE] = ‘11’
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
15
General purpose I/O parameters
Table 8. GPIO rise/fall times (2.5 V range)
Parameter
Symbol
Drive strength
SIUL2_MSCRn[D
SE]
Slew
rate
Test
conditions
Typ
Max
Unit
IO output
tpr
001
slow
15 pF Cload
on pad
7.41/8.22
7.36/8.16
3.30/3.74
2.76/3.38
3.44/3.04
2.75/2.55
4.05/3.54
3.56/2.97
3.39/2.93
2.72/2.47
2.31/2.03
1.80/1.75
ns
transition
fast
time, rise/fall1
010
011
100
101
111
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
1. Max condition for tpr: wcs model, 0.9 V vddi, 2.25 V ovdd, and 125 °C. Input transition time is 125 ps. Slow slew rate
means SIUL2_MSCRn[SRE] = ‘00’, fast slew rate means SIUL2_MSCRn[SRE] = ‘11’
Table 9. GPIO rise/fall times (3.3 V range)
Parameter
Symbol
Drive strength
SIUL2_MSCRn[D
SE]
Slew
rate
Test
conditions
Typ
Max
Unit
IO output
tpr
001
slow
15 pF Cload
on pad
7.75/8.45
7.65/8.39
3.49/3.89
2.84/3.52
3.47/3.16
2.90/2.73
4.09/3.58
3.73/3.07
3.29/3.00
2.68/2.37
2.23/2.18
1.47/1.57
ns
transition
fast
time, rise/fall1
010
011
100
101
111
slow
fast
slow
fast
slow
fast
slow
fast
slow
fast
1. Max condition for tpr: wcs model, 0.9 V vddi, 2.97 V ovdd, and 125 °C. Input transition time is 120 ps.
slow slew rate means SIUL2_MSCRn[SRE] = ‘00’, fast slew rate means SIUL2_MSCRn[SRE] = ‘11’
S32V234 Data Sheet, Rev. 9, 03/2020
16
NXP Semiconductors
General purpose I/O parameters
NOTE
The maximum rise time for all GPIO pins is 1 ms. Input pins do
not support hysteresis, therefore very slow ramps (like the ones
generated by an RC circuit with a large RC value) can induce
bounces in the input read state during the transition from logic
low to logic high or vice versa.
5.1.2 DC electrical specifications
Table 10. DC electrical specifications
Symbol
Parameter
Test conditions
Ioh=-100 μA
Min
Typ
Max
Unit
Voh
Vol
Vihf
Vil
High-level output voltage
Low-level output voltage
High-Level DC input voltage
Low-Level DC input voltage
ovdd1-0.15 —
—
V
Iol=100 μA
—
—
—
—
—
—
0.15
V
—
—
0.7*ovdd
ovdd
V
0
0.2*ovdd
V
Iin2
Input current (no pull-up/down) Vin = ovdd or 0
—
—
8
μA
μA
Iin_33pu2
Iin_50pu2
Iin_100pu2
Iin_100pd2
Input current (33 kilohm PU)
Input current (50 kilohm PU)
Vin = 0
220
6
Vin = ovdd
Vin = 0
—
—
—
—
—
—
150
6
μA
μA
μA
Vin = ovdd
Input current (100 kilohm PU) Vin = 0
Vin = ovdd
Input current (100 kilohm PD) Vin = 0
Vin = ovdd
60
6
8
50
1. ovdd is the IO supply for the pads.
2. Max condition: bcs model, 3.6 V, and 125 °C. These values are for I/O buffers.
NOTE
After bootup, application software should switch to manual
voltage detect mode using VSEL_x settings of SRC_GPR14
register to ensure optimum performance of the GPIO pads.
Please refer to SRC chapter in the Reference Manual for the
register details.
Table 11. Current-draw Characteristics for DDR_VREF
Symbol
Parameter
Min
Max
Unit
DDR_VREF
Current-draw characteristics for
DDR_VREF
—
1
mA
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
17
General purpose I/O parameters
5.2 DDR pads
5.2.1 DDR3 mode
5.2.1.1 DDR3 mode DC electrical specifications
Table 12. DDR3 mode DC electrical specifications
Parameter
Symbol
Test
Min
Typ
Max
Unit
conditions
High-level output voltage
Low-level output voltage
High-level DC input voltage
High-level DC input voltage
Input reference voltage
Voh
Vol
Ioh=-100 μA
0.8*ovdd
—
—
—
—
—
—
0.2*ovdd
ovdd
V
V
Iol=100 μA
Vih (DC)
Vil (DC)
Vref
—
Vref + 0.2
ovss
V
—
Vref - 0.2
0.51*ovdd
—
V
—
—
0.49*ovdd 0.5*ovdd
V
Termination voltage1
Input current (no pullup/pulldown)3
Vtt2
—
—
0.5*ovdd
V
Iin
Vi = 0 or ovdd
—
—
5
μA
%
Pullup/pulldown impedance
mismatch
MMpupd
34 Ohm full
strength driver
-10
+10
Driver 240 Ohm unit calibration
resolution
Rres
—
—
—
—
10
50
Ω
Rkeep4
Pad keeper
resistance
—
20
kΩ
1. Vtt is expected to track ovdd/2.
2. Vtt is not applied directly to the device. Minimum and Maximum values are system dependant.
3. Typ condition: typ model, 1.5V, and 25 °C. Max condition: bcs model, 1.575V, and -40 °C. Min condition: wcs model,
1.425V, and 125 °C.
4. Typ condition: typ model, 1.5 V, and 25 °C, max condition: wcs model, 1.425 V, and 125 °C, min condition: bcs model,
1.575 V, and -40 °C.
5.2.2 DDR3L mode
5.2.2.1 DDR3L mode DC electrical specifications
Table 13. DDR3L mode DC electrical specifications
Parameter
Symbol
Voh
Test conditions
Ioh = -100 μA
Iol = 100 μA
—
Min
0.8*ovdd
—
Typ
—
Max
—
Unit
V
High-level output voltage
Low-level output voltage
High-level DC input voltage
Vol
—
0.2*ovdd
ovdd
V
Vih (DC)
Vref + 0.2
—
V
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
18
NXP Semiconductors
LPDDR2 mode
Table 13. DDR3L mode DC electrical specifications (continued)
Parameter
High-level DC input voltage
Input reference voltage
Vref current draw
Symbol
Vil (DC)
Vref
Test conditions
Min
Typ
Max
Unit
V
—
ovss
—
Vref - 0.2
—
0.49*ovdd 0.5*ovdd
0.51*ovdd
V
Icc-vref
Vtt1
—
—
—
—
0.5*ovdd
—
1
—
5
mA
V
Termination voltage
—
Vi = 0 or ovdd
—
Input current (no pullup/pulldown)
Iin
—
μA
%
Pullup/pulldown impedance
mismatch (full strength driver)
MMpupd
-10
—
+10
Driver unit (240 Ohm) calibration
resolution
Rres
—
—
—
—
—
10
50
Ω
Rkeep
Pad keeper
resistance
20
kΩ
1. Vtt is not applied directly to the device. Minimum and Maximum values are system dependant.
5.2.3 LPDDR2 mode
5.2.3.1 LPDDR2 mode DC electrical specifications
Table 14. LPDDR2 mode DC electrical specifications
Parameter
Symbol
Voh
Test conditions
Min
0.9*ovdd
—
Typ
—
Max
—
Unit
High-level output voltage
Low-level output voltage
Input reference voltage
High-level DC input voltage
High-level DC input voltage
Ioh = -100 μA
V
V
Vol
Iol = 100 μA
—
0.1*ovdd
Vref
—
0.49*ovdd 0.5*ovdd 0.51*ovdd
V
Vih (DC)
Vil (DC)
Iin
—
—
Vref + 0.17
ovss
—
—
—
ovdd
Vref - 0.17
5
V
V
Input current (no pullup/
pulldown)1
Vi = ovdd or 0
—
μA
Pullup/pulldown impedance
mismatch
MMpupd
Rres
34 Ohm full strength
driver
-15
—
—
—
—
+15
10
%
Ω
Driver 240 Ohm unit
calibration resolution
—
Rkeep2
Pad keeper
resistance
—
20
50
kΩ
1. Typ condition: typ model, 1.2 V, and 25 °C. Max condition: bcs model, 1.32 V, and -40 °C. Min condition: wcs model, 1.14
V, and 125 °C.
2. Typ condition: typ model, 1.2 V, and 25 °C, max condition: wcs model, 1.14 V, and 125 °C, min condition: bcs model, 1.32
V, and -40 °C.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
19
Peripheral operating requirements and behaviors
5.3 Boot Configuration Pins Specification
Value driven on RCON and BOOTMOD pins should be stable for at least 1 µs after
RESET pin is deasserted.
NOTE
External pull up/down resistors must be used on the
BOOTMOD pins in order to ensure latching at the correct state.
NOTE
NXP would anticipate that most customers would use the boot
from fuses option in a production environment. However, there
is no reliability impact if the device is configured by RCON
rather than fuses.
6 Peripheral operating requirements and behaviors
6.1 Analog modules
6.1.1 ADC electrical specifications
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-
Digital Converter.
S32V234 Data Sheet, Rev. 9, 03/2020
20
NXP Semiconductors
Analog modules
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal = (VrefH-VrefL)/4096 = 1.8V/4096 =
. 439mV
Total Unadjusted Error TUE = +/-10 LSB =
+/-4.39 mV
code out7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(5)
4
3
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 2. ADC characteristics and error definitions
NOTE
While measuring scaled supply voltages on ADC Channels,
Maximum (+5/-10%) variation can be expected .
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
21
Analog modules
6.1.1.1 Input equivalent circuit
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
S
F
L
SW1
AD
C
V
C
C
P1
C
S
A
F
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 3. Input equivalent circuit
Table 15. ADC conversion characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
fCK
ADC Input Clock frequency
(Bus clock)
—
20
20
—
80
40
fAD_clk
ADC Conversion clock
frequency1
MHz
fs
Sampling frequency
Sample time2
Conversion time3
—
—
—
—
—
—
—
0.5
—
—
5
MHz
ns
tsample
tconv
CS
500
1400
—
ns
ADC input sampling
capacitance
pF
CP1
ADC input pin capacitance 1
ADC input pin capacitance 2
—
—
—
—
—
—
—
—
—
5
pF
pF
Ω
CP2
0.8
875
RSW1
Internal resistance of analog
source
RAD
Internal resistance of analog
source
—
—
—
825
Ω
INL4
DNL
OFS
GNE
Integral non linearity
Differential non linearity
Offset error
—
–3
–2
–6
–6
—
—
—
—
—
—
3
2
6
6
LSB
LSB
LSB
LSB
nA
—
—
Gain error
—
Input (single ADC Max leakage
channel)
125C
2000
TUE
Total unadjusted error
—
–8
—
8
LSB
S32V234 Data Sheet, Rev. 9, 03/2020
22
NXP Semiconductors
Clocks and PLL interfaces modules
1. Please see description of Clock & reset section in ADC chapter in Reference Manual for details. User need to generate
AD_clk = 40 MHz for 0.5 MSPS operation. For example, if fck = 80 MHz, configure MCR[8].ADCLKSE = 0 and
MCR[4].ADCLKDIV = 0 (default).
2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming. For internal ADC channels, the minimum sampling time required is 3 microsecond.
3. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
4. Specifications are quoted here for input signal ranging from 150 mV to VDD_HV_ADC - 150 mV. For signals outside this
range, the Specifications may degrade beyond limits specified in this table.
6.1.2 Thermal Monitoring Unit (TMU)
The following table describes TMU electrical characteristics.
Table 16. TMU electrical characteristics
Symbol
Parameter
Conditions
Value
Typ
Unit
Min
Max
Tj
Temperature monitoring
range
—
—
-40
—
125
°C
TSENS
TACC
Sensitivity
Accuracy
—
2.5
—
—
mV/°C
°C
TJ = -40 °C to 40 °C
TJ = 40 °C to 125 °C
-10
-6
+10
+6
—
°C
6.2 Clocks and PLL interfaces modules
6.2.1 Main oscillator electrical characteristics
The device provides an oscillator/resonator driver of a Pierce-type structure.
Table 17. Main oscillator electrical characteristics
Symbol
Parameter
Conditions
Value
Typ
40.0
Unit
Min
Max
fFXOSCHS
TFXOSCHSSU
VIH
Oscillator frequency
—
—
—
n/a
21
MHz
ms
Oscillator start-up time
fFXOSCHS = 40 MHz
—
—
Input high level CMOS
Schmitt Trigger
Vref =
Vref+0.5
0
VDD_HV_FXOS V
C
0.5*VDD_HV_FXOSC
where VDD_HV_FXOSC
is FXOSC HV Supply
VIL
Input low level CMOS
Schmitt Trigger
Vref =
—
Vref – 0.5
V
0.5*VDD_HV_FXOSC
where VDD_HV_FXOSC
is FXOSC HV Supply
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
23
Clocks and PLL interfaces modules
1. The start-up time is dependent upon crystal characteristics, board leakage, etc, high ESR and excessive capacitive loads
can cause long start-up time
Following crystals are used in internal crystal oscillator validation:
• NX3225 – 40 MHz; Load capacitance = 8 pF
• NX5032 – 40 MHz; Load capacitance = 8 pF
6.2.2 48 MHz FIRC electrical characteristics
Table 18. FIRC electrical specifications
Symbol
Parameter
Conditions
Value
Typ
Unit
Min
Max
FTarget
FIRC target
frequency
(trimmed)
—
—
—
48
—
—
MHz
%
δFvar_T
FIRC frequency
variation with
respect to
-10
+10
supply and
temperature
after process
trimming
6.2.3 PLL electrical specifications
Table 19. PLL electrical characteristics 1
Symbol
Parameter
Conditions
Value
Typ
Unit
Min
Max
fPLLIN
PLL input clock2
PLL input clock duty cycle 2
—
—
—
—
—
—
203
—
—
—
—
—
—
—
403
60
MHz
%
ΔPLLIN
40
—
tPLLLOCK
ΔPLLT
PLL lock time
100
150
560
32
µs
Period jitter
—
ps
ΔPLLTIE
fPLLMOD
δPLLMOD
TIE
—
ps
SSCG modulation frequency
—
kHz
%
SSCG modulation depth (Down —
Spread)
0.50
2.74
1. The jitter values are gauranteed for following conditions:
1. Measurement being done on LFAST TX pad with observed frequency greater than 250 M and less than 320 M
2. Minimum SOC activity - Operations required to observe clock must be functional.
3. Maximum frequency change in SSCG modulation is limited by following relation: Modulation Depth * VCO Frequency
< PLL Reference (PFD) Frequency
2. PLL0IN clock retrieved from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using
internal RCOSC or external oscillator is used in functional mode.
3. The PLLIN clock is the frequency after the PREDIV(Pre-divider) value division, and before the Phase detector block.
Please refer to the PLLs section of clocking chapter in the Reference Manual.
S32V234 Data Sheet, Rev. 9, 03/2020
24
NXP Semiconductors
Clocks and PLL interfaces modules
4. STEPSIZE x STEPNO < 18432
For the PLL frequencies supported by this device, refer to the Table - "PLL frequencies"
in the "Clocking" chapter of the Reference Manual.
6.2.4 DFS electrical specifications
DFS takes input clock from PLL output. Here is relation between input and output clock
of each phase divider:
F(dfsclkout) = F(dfsclkin)/[mfi+(mfn/256)]
mfi : integer part of division [1:255]
mfn: Fractional part of division [1:255]
Table 20. DFS electrical specification1
Parameter
Input Frequency
Period jitter
TIE
Min
Typical
Max
Unit
800
—
—
—
—
1066
300
MHz
ps
—
600
ps
1. DFSes mfi, mfn and frequencies are defined and restricted as per Reference Manual. See the table "DFS (mfi, mfn)
settings" in the "Clocking" chapter of the Reference Manual for the supported mfi and mfn combinations.
6.2.5 LFAST PLL Electrical Specifications
The following table lists AC specification of the LFAST PLL block.
Table 21. LFAST PLL Interface AC
Specifications
Parameter
PLL input clock
Min
Typical
Max
Unit
10
312
—
—
—
—
—
84
26
MHz
MHz
µs
PLL VCO Frequency
Phase Lock time
RMS Period Jitter
Long Term Jitter2
Random Jitter
320
50
—
401
—
ps
—
ps
Deterministic Jitter
Total Jitter @ BER 10-9
—
—
80
—
1.313
ps
ns
1.09
1. When SysClk = 26 MHz
2. VCO clock measured over 100 µs acquisition at ZipWire TX LVDS across 100 ohm load
3. Only Total Jitter is given a maximum specification as variation of Random and Deterministic jitter is not critical. Any
combined Random and Deterministic jitter yielding a Total Jitter @ 10-9 BER is within maximum specification and is
acceptable
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
25
Memory interfaces
6.3 Memory interfaces
6.3.1 QuadSPI AC specifications
• Measurements are with a load of 35 pF on output pins. Input slew: 1 ns,
SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11
• QuadSPI input timing is with 15 pF load on flash output.
• QuadSPI_MCR[DQS_EN] must be set as 1 for SDR READ
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
The following table lists various QuadSPI modes and their corresponding configurations.
Please refer to the device Reference Manual for register and bit descriptions.
Table 22. QuadSPI read/write settings
Modes supported by QuadSPI_ QuadSPI_ QuadS Quad QuadSP QuadSPI_SO QuadSPI_SO QuadSPI_
QuadSPI
MCR[DDR MCR[DQS PI_MC SPI_M I_MCR
CCR
CCR
[FDCC_FA]
FLSHCR[
TDH]
_EN]
_EN]
R
CR
[DQS_M [FDCC_FB]
DSL]
[DQS_ [REF
CD]
000
CLK_
SEL]
SDR mode Internal
0
1
1
1
1
1
1
1
39h @ 3.3 V
3Fh @ 1.8 V
39h @ 3.3 V
3Fh @ 1.8 V
00
DQS mode
DDR mode Internal
DQS mode
000
000
0
0
1
0
4Ah @ 3.3 V 4Ah @ 3.3 V
01
01
50h @ 1.8 V
00h
50h @ 1.8 V
00h
External
DQS mode
(supported
by
HyperFlas
h)
SDR mode
For SDR mode, QuadSPI_MCR[DQS_EN] must be set as '1'.
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26
NXP Semiconductors
Memory interfaces
1
2
3
Clock
SCK
CS
Tck
Tih
Tis
Data in
Figure 4. QuadSPI input timing (SDR mode) diagram
NOTE
• A negative time indicates the actual capture edge inside the
device is earlier than clock appearing at pad.
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 23. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tis
Setup time for incoming data
Hold time for incoming data
SCK clock frequency
2.5
1
—
—
ns
Tih
ns
FSCK
—
104
MHz
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NXP Semiconductors
27
Memory interfaces
1
2
3
Clock
SCK
CS
Tck
Tcsh
Tcss
Toh
Tov
Data out
Figure 5. QuadSPI output timing (SDR mode) diagram
Table 24. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
—
1.5
—
ns
Toh
–1.5
—
2
ns
FSCK
Tcss
Tcsh
SCK clock frequency
104
—
MHz
ns
Chip select output setup time
Chip select output hold time
1
—
ns
NOTE
For any frequency setup and hold specifications of the memory
should be met.
DDR mode
1
2
3
Clock
SCK
CS
Tck
Tih
Tis
Data in
Figure 6. QuadSPI input timing (DDR mode) diagram
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28
NXP Semiconductors
Memory interfaces
Configuration
Table 25. QuadSPI input timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
2.5 @ 3.3 V
2 @ 1.8 V
1.5
Max
Tis
Setup time for incoming data
—
ns
—
—
Tih
Hold time for incoming data
SCK Clock Frequency
—
ns
FSCK
—
50 (Internal DQS) MHz
@ 3.3 V
See Table 22
56 (Internal DQS)
@ 1.8 V
1
2
3
Clock
SCK
CS
Tck
Tov
Toh
Data out
Figure 7. QuadSPI output timing (DDR mode) diagram
Table 26. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
1/(4*FSCK) + 1.5
Tov
Toh
Output Data Valid
Output Data Hold
—
ns
ns
1/(4*FSCK) —
- 1.5
HyperFlash mode
Maximum clock frequency = 100 MHz.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
29
Memory interfaces
RDS
TsMIN
ThMIN
DI[7:0]
Figure 8. QuadSPI input timing (HyperFlash mode) diagram
Table 27. QuadSPI input timing (HyperFlash mode) specifications
Symbol
Parameter
Value
Unit
Min
0.950
0.950
Max
TsMIN
ThMIN
Setup time for incoming data
Hold time for incoming data
—
—
ns
ns
CK
CK 2
TclkSKMAX
TclkSKMIN
THO
TDVO
Output Invalid Data
Figure 9. QuadSPI output timing (HyperFlash mode) diagram
Table 28. QuadSPI output timing (HyperFlash mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
TdvMAX
Tho
Output Data Valid
Output Data Hold
—
1
3.7
—
ns
ns
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
30
NXP Semiconductors
Memory interfaces
Table 28. QuadSPI output timing (HyperFlash mode) specifications (continued)
Symbol
Parameter
Value
Unit
Min
Max
T/4 + 0.150 ns
T/4 – 0.150 — ns
TclkSKMAX
TclkSKMIN
Ck to Ck2 skew max
Ck to Ck2 skew min
—
6.4 DDR SDRAM Specific Parameters (DDR3, DDR3L, and
LPDDR2)
6.4.1 DDR3 and DDR3L timing parameters
NOTE
Operating voltages of DDR3 and DDR3L are different.
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NXP Semiconductors
31
Memory interfaces
Figure 10. DDR3 and DDR3L command and address timing parameters
NOTE
RESET pin has an external weak pull DOWN requirement if
DDR3 memory is NOT required to support content retention in
the device low power modes where core voltage is off but
DRAM voltage is on.
NOTE
RESET pin has an external weak pull UP requirement if DDR3
memory is required to support content retention in the device
low power modes where core voltage is off but DRAM voltage
is on.
NOTE
CKE pin has an external weak pull down requirement.
S32V234 Data Sheet, Rev. 9, 03/2020
32
NXP Semiconductors
Memory interfaces
NOTE
DDR3 and DDR3L timing parameters are compliant with
JESD79-3F and JESD79-3-1A.01 specifications respectively.
Table 29. DDR3 and DDR3L timing parameter
ID
Parameter
Symbol
CK = 533 MHz
Unit
Min
Max
DDR1
DDR2
DDR4
CK clock high-level
width
tCH
tCL
tIS
0.47
0.53
tCK (avg)
tCK (avg)
ps
CK clock low-level
width
0.47
280
0.53
—
CS, RAS, CAS,
CKE, WE, ODT
setup time
DDR5
CS, RAS, CAS,
CKE, WE, ODT
hold time
tIH
300
—
ps
DDR6
DDR7
Address output
setup time
tIS
tIH
280
300
—
—
ps
ps
Address output
hold time
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
33
Memory interfaces
6.4.2 DDR3 and DDR3L read cycle
Figure 11. DDR3 and DDR3L read cycle
Table 30. DDR3 and DDR3L read cycle
ID
Parameter
Symbol
CK = 533 MHz
Unit
Min
Max
DDR26
Minimum required DQ valid
window width
—
563
—
ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
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34
NXP Semiconductors
Memory interfaces
6.4.3 DDR3 and DDR3L write cycle
Figure 12. DDR3 and DDR3L write cycle
Table 31. DDR3 and DDR3L write cycle
ID
Parameter
Symbol
CK = 533 MHz
Unit
Min
Max
DDR17
DDR18
DDR21
DQ and DQM setup time to DQS
(differential strobe)
tDS
tDH
206
—
ps
ps
DQ and DQM hold time to DQS
(differential strobe)
280
—
DQS latching rising transitions to
associated clock edges
tDQSS
-0.25
+0.25
tCK (avg)
DDR22
DDR22
DQS high level width
DQS low level width
tDQSH
tDQSL
0.45
0.45
0.55
0.55
tCK (avg)
tCK (avg)
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
35
Memory interfaces
6.4.4 LPDDR2 timing parameter
Figure 13. LPDDR2 command and address timing parameter
NOTE
RESET pin has a external weak pull DOWN requirement if
LPDDR2 memory is NOT required to support content retention
in the device low power modes where core voltage is off but
DRAM voltage is on.
NOTE
RESET pin has a external weak pull UP requirement if
LPDDR2 memory is required to support content retention in the
device low power modes where core voltage is off but DRAM
voltage is on.
NOTE
CKE pin has a external weak pull down requirement.
NOTE
LPDDR2 timing parameters are compliant with JESD209-2B
specification.
Table 32. LPDDR2 timing parameter
ID
Parameter
Symbol
CK = 533 MHz
Min
Unit
Max
0.55
0.55
—
LP1
LP2
LP3
LP4
LP3
LP4
SDRAM clock high-level width
SDRAM clock LOW-level width
CS, CKE setup time
CS, CKE hold time
tCH (avg)
tCL (avg)
tIS
0.45
0.45
235
250
235
250
tCK (avg)
tCK (avg)
ps
ps
ps
ps
tIH
—
CA setup time
tIS
—
CA hold time
tIH
—
S32V234 Data Sheet, Rev. 9, 03/2020
36
NXP Semiconductors
Memory interfaces
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
6.4.5 LPDDR2 read cycle
Figure 14. LPDDR2 read cycle
Table 33. LPDDR2 read cycle
ID
Parameter
Symbol
CK = 533 MHz
Unit
Min
Max
LP26
Minimum required DQ valid
window width for LPDDR2
—
364
—
ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
37
Memory interfaces
6.4.6 LPDDR2 write cycle
Figure 15. LPDDR2 write cycle
Table 34. LPDDR2 write cycle
ID
Parameter
Symbol
CK = 533 MHz
Unit
Min
Max
LP17
LP18
LP21
DQ and DQM setup time to DQS
(differential strobe)
tDS
tDH
280
—
ps
ps
DQ and DQM hold time to DQS
(differential strobe)
220
—
DQS latching rising transitions to
associated clock edges
tDQSS
0.75
1.25
tCK (avg)
LP22
LP23
DQS high level width
DQS low level width
tDQSH
tDQSL
0.4
0.4
—
—
tCK (avg)
tCK (avg)
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
S32V234 Data Sheet, Rev. 9, 03/2020
38
NXP Semiconductors
Communication modules
6.5 Communication modules
6.5.1 DSPI timing
Measurements are with a load of 45 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Table 35. DSPI timing
No.
Symbol
tSCK
Parameter
Conditions
Min
Max
Unit
1
DSPI cycle time
Master (MTFE = 0)
401
40
-
-
-
-
-
ns
Slave (MTFE = 0)
Slave Receive Only Mode2
16
2
3
4
5
6
tCSC
tASC
tSDC
tA
PCS to SCK delay
After SCK delay
SCK duty cycle
-
163
164
ns
ns
ns
ns
ns
-
-
tSCK/2 - 1.5
tSCK/2 + 1.5
Slave access time
SS active to SOUT valid
-
-
40
15
tDIS
Slave SOUT disable
time
SS inactive to SOUT High-Z
or invalid
7
8
9
tPCSC
tPASC
tSUI
PCSx to PCSS time
PCSS to PCSx time
-
13
13
15
2
-
ns
ns
ns
-
-
Data setup time for
inputs
Master (MTFE = 0)
Slave
-
-
Master (MTFE = 1, CPHA = 0) 6
Master (MTFE = 1, CPHA = 1) 20
-
-
10
11
12
tHI
Data hold time for
inputs
Master (MTFE = 0)
Slave
-4
4
-
ns
ns
ns
-
Master (MTFE = 1, CPHA = 0) 11
Master (MTFE = 1, CPHA = 1) -4
-
-
tSUO
Data valid (after SCK
edge)
Master (MTFE = 0)
Slave
-
-
4
16
12
4
-
Master (MTFE = 1, CPHA = 0) -
Master (MTFE = 1, CPHA = 1) -
tHO
Data hold time for
outputs
Master (MTFE = 0)
Slave
-2
3
-
Master (MTFE = 1, CPHA = 0) 5
Master (MTFE = 1, CPHA = 1) -2
-
-
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
39
Communication modules
1. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3.
2. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on
SIN, but no valid data is transmitted on SOUT.
3. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler"
configuration is "3" (01h) and SPI_CTARn[CSSCK] - "PCS to SCK Delay Scaler" configuration is "2" (0000h).
4. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler"
configuration is "3" (01h) and SPI_CTARn[ASC] - "After SCK Delay Scaler" configuration is "2" (0000h).
NOTE
DSPI Timing specs on this chip are valid with Slave in Classic
Mode only.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL =1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 16. DSPI classic SPI timing — master, CPHA = 0
S32V234 Data Sheet, Rev. 9, 03/2020
40
NXP Semiconductors
Communication modules
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL =1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 17. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Figure 18. DSPI classic SPI timing — slave, CPHA = 0
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
41
Communication modules
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 19. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Figure 20. DSPI modified transfer format timing — master, CPHA = 0
S32V234 Data Sheet, Rev. 9, 03/2020
42
NXP Semiconductors
Communication modules
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 21. DSPI modified transfer format timing — master, CPHA = 1
8
7
PCSS
PCSx
Figure 22. DSPI PCS strobe (PCSS) timing
6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
Booting from eMMC must be at voltage of 3.3 V. The operation at 1.8 V is possible only
during run-time, that is after the boot has completed. This voltage restriction during
booting does not apply to SD/SDIO/SDHC/SDXC modes.
Measurements are with a load of 40 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11.
uSDHC_VEND_SPEC[CMD_OE_PRE_EN] field should be programmed to 1 for proper
functioning of uSDHC external interface.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
43
Communication modules
6.5.2.1 SDR mode timing specifications
Figure 23. SDR CMD-DATx Read Timing
Figure 24. SDR CMD-DATx Write Timing
Table 36. SDR mode timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
2
SD1
Clock Frequency (Low
Speed)
fPP
fPP
0
0
400
kHz
Clock Frequency (SD/
SDIO Full Speed/High
Speed)
25/50
MHz
3
Clock Frequency (MMC
Full Speed/High Speed)
fPP
0
20/52
400
55
MHz
kHz
%
Clock Frequency
(Identification Mode)
fOD
100
SD2
Clock Duty Cycle
tDC
45
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
44
NXP Semiconductors
Communication modules
Table 36. SDR mode timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD3
SD4
CLK to Data/CMD Valid
tDVO
—
3.2
—
ns
ns
CLK to Data/CMD Invalid tHO
-6.3
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
SD5
SD6
DATA/CMD Input Setup
time
tSUI
4.5
—
ns
ns
DATA/CMD Input Hold
time
tHI
0
—
1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode,
clock frequency can be any value between 0–52 MHz.
6.5.2.2 DDR mode timing specifications
Figure 25. DDR Data Read timing
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
45
Communication modules
Figure 26. DDR DATA Write timing
Figure 27. DDR CMD Read Timing
Figure 28. DDR CMD Write Timing
S32V234 Data Sheet, Rev. 9, 03/2020
46
NXP Semiconductors
Communication modules
Unit
Table 37. DDR mode timing specification
ID
Parameter
Symbols
Min
Max
Card Input Clock
DD1
DD1
DD2
Clock Frequency
(eMMC4.4 DDR)
fPP
fPP
tDC
0
52
50
55
MHz
MHz
%
Clock Frequency (SD3.0
DDR)
0
Clock Duty Cycle
45
uSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
DD3
DD4
DD5
DD6
CLK to Data Valid
CLK to Data Invalid
CLK to CMD Valid
CLK to CMD Invalid
tDVO
tHO
tDVO
tHO
—
6.2
—
ns
ns
ns
ns
2.5
—
3.25
—
–6.2
uSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
DD7
DD8
DD9
DD10
Data Input Setup Time
Data Input Hold Time
CMD Input Setup Time
CMD Input Hold Time
tSUI
tHI
tSUI
tHI
2.3
1.5
4.5
0
—
—
—
—
ns
ns
ns
ns
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
47
LFAST electrical characteristics
6.5.3 LFAST electrical characteristics
6.5.3.1 LFAST interface timing diagrams
Figure 29. LFAST timing definition
S32V234 Data Sheet, Rev. 9, 03/2020
48
NXP Semiconductors
LFAST electrical characteristics
VIH
Differential TX
Data Lines
90%
10%
pad_p/pad_n
VIL
Tfall
Trise
Figure 30. Rise/fall time
6.5.3.2 LFAST Interface electrical characteristics
Table 38. LFAST electrical characteristics
Symbol
Parameter
Conditions
Value1
Unit
Min
1.71
Typ
Max
1.95
VDDIO_LFAST
Data Rate
Operating supply conditions
Data rate
—
—
—
—
V
DATARATE
STARTUP
TSTRT_BIAS
TRANSMITTER
VOS_DRF
—
—
312/320
0.5
Typ+0.1% Mbps
Bias startup time2
3
µs
Common mode voltage
—
—
1.1
1.2
1.475
450
V
|ΔVOD_DRF
|
Differential output voltage
swing (terminated)
250
350
mV
TTR_DRF
Rise/Fall time (20% - 80% of
swing)3
Capacitance4
—
—
0.1
—
—
—
0.73
5
ns
COUT_DRF
pF
RECEIVER
VICOM_DRF
Common mode voltage
Differential input voltage
—
0.155
150
100
80
—
—
1.56
—
V
|ΔVI_DRF
|
VICOM_DRF>1.4 V
mV
mV
Ω
VICOM_DRF<= 1.4 V
RIN_DRF
CIN_DRF
LIN_DRF
Terminating resistance
Capacitance7
Parasitic Inductance8
—
—
—
100
3.5
5
150
6
—
pF
nH
—
10
LFAST Clock characteristics
FRF_REF
ERRREF
DCREF
SysClk Frequency
—
—
—
10
-1
—
—
—
26
1
MHz
%
SysClk Frequency Error
SysClk Duty Cycle
45
55
%
1. All values need to be confirmed during device characterization.
2. Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.
3. Rise/fall time is defined for 20 to 80% signal voltage levels, at 2pF Cload and 100 Ohm termination resistor load.
4. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation needed to verify
LFAST template compliancy.
5. Absolute min = 0.15 V - (250 mV/2) = 0.025 V
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
49
FlexRay
6. Absolute max = 1.5 V + (450 mV/2) = 1.725 V
7. Total capacitance including silicon, package pin and bond wire
8. Total inductance including silicon, package pin and bond wire
6.5.4 FlexRay
6.5.4.1 FlexRay timing parameters
This section provides the FlexRay interface timing characteristics for the input and output
signals. These numbers are recommended per the FlexRay Electrical Physical Layer
Specification, Version 3.0.1, and subject to change per the final timing analysis of the
device.
6.5.4.2 TxEN
TxEN
80 %
20 %
dCCTxEN
dCCTxEN
FALL
RISE
Figure 31. TxEN signal
Table 39. TxEN output characteristics1
Name
dCCTxENRISE25
Description
Min
Max
Unit
Rise time of TxEN signal at CC
Fall time of TxEN signal at CC
-
-
-
9
ns
ns
ns
dCCTxENFALL25
dCCTxEN01
9
Sum of delay between Clk to Q of
the last FF and the final output
buffer, rising edge
25
dCCTxEN10
Sum of delay between Clk to Q of
the last FF and the final output
buffer, falling edge
-
25
ns
1. TxEN pin load maximum 25 pF.
S32V234 Data Sheet, Rev. 9, 03/2020
50
NXP Semiconductors
FlexRay
PE_Clk
TxEN
dCCTxEN10
dCCTxEN01
Figure 32. TxEN signal propagation delays
6.5.4.3 TxD
TxD
dCCTxD50%
80 %
50 %
20 %
dCCTxDRISE
dCCTxDFALL
Figure 33. TxD signal
Table 40. TxD output characteristics
Name
Description1
Min
Max
Unit
dCCTxAsym
Asymmetry of sending CC @ 25 pF -2.45
load (=dCCTxD50% - 100 ns)
2.45
ns
ns
dCCTxDRISE25+dCCTxDFALL25
Sum of Rise and Fall time of TxD
signal at the output
-
9
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
51
FlexRay
Table 40. TxD output characteristics (continued)
Name
Description1
Min
Max
Unit
dCCTxD01
dCCTxD10
Sum of delay between Clk to Q of
the last FF and the final output
buffer, rising edge
-
-
25
25
ns
ns
Sum of delay between Clk to Q of
the last FF and the final output
buffer, falling edge
1. TxD pin load maximum 25 pF.
PE_Clk*
TxD
dCCTxD
10
dCCTxD
01
*FlexRay Protocol Engine Clock
Figure 34. TxD signal propagation delays
6.5.4.4 RxD
Table 41. RxD input characteristics
Name
C_CCRxD
Description
Input capacitance on RxD pin
Threshold for detecting logic high
Threshold for detecting logic low
Min
Max
Unit
-
7
pF
%
uCCLogic_1
uCCLogic_0
dCCRxD01
35
30
-
70
65
10
%
Sum of delay from actual input to the D input of
the first FF, rising edge
ns
dCCRxD10
Sum of delay from actual input to the D input of
the first FF, falling edge
-
10
ns
S32V234 Data Sheet, Rev. 9, 03/2020
52
NXP Semiconductors
Ethernet Controller (ENET) Parameters
6.5.5 Ethernet Controller (ENET) Parameters
6.5.5.1 Ethernet Switching Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. For MII and
RMII mode, output load is equal to 25 pF and pad settings are SIUL2_MSCRn[DSE] =
101 and SIUL2_MSCRn[SRE] = 11. For RGMII, output load is 5 pF and pad settings are
SIUL2_MSCRn[DSE] = 111 and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
6.5.5.2 Receive and Transmit signal timing specifications for RMII
interfaces
This section provides timing specifications that meet the requirements for RMII
interfaces for a range of transceiver devices.
Table 42. Receive signal timing for RMII interfaces
Symbol
Characteristic
RMII Mode
Min Max
Unit
—
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
—
35%
35%
4
50
MHz
E3, E7
E4, E8
E1
65%
65%
—
RMII_CLK period
RMII_CLK pulse width low
RMII_CLK period
RXD[1:0], CVS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN valid
RMII_CLK to TXD[1:0], TXEN invalid
ns
ns
ns
ns
E2
2
—
E6
—
2
14
E5
—
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
53
Ethernet Controller (ENET) Parameters
Figure 35. RMII receive signal timing diagram
Figure 36. RMII transmit signal timing diagram
6.5.5.3 Receive and Transmit signal timing specifications for MII
interfaces
This section provides timing specifications that meet the requirements for MII interfaces
for a range of transceiver devices.
S32V234 Data Sheet, Rev. 9, 03/2020
54
NXP Semiconductors
Ethernet Controller (ENET) Parameters
t
CYC
t
PWH
RX_CLK
(Input)
t
t
S
H
RXDn,
RX_DV,
RX_ER
(Input)
(n = 0-3)
Figure 37. MII receive signal timing diagram
Table 43. Receive signal timing for MII interfaces
Characteristic
Symbol
MII Mode
Unit
Min
-
Typ
Max
RX_CLK clock period (100/10 MBPS)
RX_CLK duty cycle, tPWH/tCYC
Input setup time before RX_CLK
Input hold time after RX_CLK
tCYC
-
40/400
-
65
-
ns
%
35
5
50
-
tS
ns
ns
tH
5
-
-
t
CYC
t
PWH
TX_CLK
(Input)
t
D
TXDn,
TX_EN,
TX_ER
(Output)
t
HO
Note: Device pins applicable to MII interface are applicable to TMII interface,
and operates at 50 MHz reference clock.
Figure 38. MII transmit signal timing diagram
Table 44. Transmit signal timing for MII interfaces
Characteristic
Symbol
MII Mode
Unit
Min
Typ
Max
-
TX_CLK clock period (100/10 MBPS)
TX_CLK duty cycle, tPWH/tCYC
TX_CLK to Output Valid
tCYC
-
-
35
-
40/400
ns
%
50
-
65
25
-
tD
ns
ns
TX_CLK to Output Invalid
tHO
2
-
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
55
Ethernet Controller (ENET) Parameters
6.5.5.4 Receive and Transmit signal timing specifications for RGMII
interfaces
This section provides timing specs that meet the requirements for RGMII interfaces for a
range of transceiver devices.
Table 45. Receive signal timing for RGMII interfaces
Characteristic
Symbol
RGMII Mode
Typ
Unit
Min
7.2
Max
8.8
500
, 1
Clock cycle duration
Tcyc
—
—
—
—
—
—
ns
ps
ns
%
, 2
3
Data to clock output skew at transmitter TskewT
-500
1
Data to clock input skew at receiver
Duty cycle for Gigabit
TskewR
2.6
55
Duty_G 3
Duty_T3
Tr/Tf
45
40
-
Duty cycle for 10/100T
60
%
Rise/fall time (20–80%)
0.75
ns
1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns 40 ns and 40 ns 4 ns respectively.
2. For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an
additional delay of greater than 1.5 ns and less than 2 ns will be added to the associated clock signal. For 10/100, the max
value is unspecified.
3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as
long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed
transitioned between.
RGMII_TXC (at transmitter)
TskewT
RGMII_TXDn (n = 0 to 3)
TXEN
TXERR
RGMII_TX_CTL
Figure 39. RGMII Transmit signal timing diagram original
RGMII_RXDn (n = 0 to 3)
RXERR
RXDV
RGMII_RX_CTL
TskewR
RGMII_RXC (at receiver)
Figure 40. RGMII Receive signal timing diagram original
S32V234 Data Sheet, Rev. 9, 03/2020
56
NXP Semiconductors
Ethernet Controller (ENET) Parameters
6.5.5.5 MII/RMII Serial Management channel timing (MDC/MDIO)
Output load is equal to 45 pF and pad settings are SIUL2_MSCRn[DSE] = 101 and
SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Ethernet works with a maximum frequency of MDC at 2.5 MHz. ENET_MSCR
[HOLDTIME] should be set to 010 when Module Clock = 133 MHz. MDIO pin must
have external pull up.
Figure 41. MDIO input timing
Figure 42. MDIO output timing
Table 46. MDIO interface timing specification
ID
Parameter
Clock Duty Cycle
Symbols
Min
Max
Unit
MDCO
tMDC
Table continues on the next page...
40
60
%
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
57
Ethernet Controller (ENET) Parameters
Table 46. MDIO interface timing specification (continued)
ID
Parameter
Symbols
MDIO Output Timing
Min
Max
Unit
MDC1
MDC2
MDC to MDIO Valid
tDVO
—
50
—
ns
ns
MDC to MDIO Invalid
tHO
10
MDIO Input Timing
MDC3
MDC4
MDIO Input Setup time
MDIO Input Hold time
tSUI
tHI
50
0
—
—
ns
ns
6.5.6 PCI Express specifications
The PCI Express link conforms to the PCI Express Base Specification, Revision 2.1. The
following summary of Transmitter and Receiver specifications are copied directly from
the Base Specification. Consult the Base Specification for additional details.
Table 47. PCI Express transmitter specifications1
Symbol
UI
Parameter
2.5 GT/s
5.0 GT/s
Units
ps
Unit Interval
199.94 (min) 200.06
(max)
399.88 (min)
400.12 (max)
VTX-DIFF-PP
Differential p-p Tx
voltage swing
V
0.8 (min)
1.2 (max)
0.8 (min)
1.2 (max)
VTX-DE-RATIO-3.5dB
VTX-DE-RATIO-6dB
TMIN-PULSE
Tx de-emphasis level
ratio
dB
dB
UI
UI
3.0 (min)
4.0 (max)
3.0 (min)
4.0 (max)
Tx de-emphasis level
N/A
5.5 (min)
6.5 (max)
Instantaneous lone
pulse width
Not specified
0.75 (min)
0.9 (min)
TTX-EYE
Transmitter Eye
including all jitter
sources
0.75 (min)
TTX-EYE-MEDIAN-to-MAX-
Maximum time between 0.125 (max)
the jitter median and
max deviation from the
median
Not specified
0.15 (max)
UI
JITTER
TTX-HF-DJ-DD
Tx deterministic jitter > Not specified
1.5 MHz
UI
TTX-LF-RMS
BWTX-PLL
Tx RMS jitter < 1.5 MHz Not specified
3.0
ps RMS
MHz
Maximum Tx PLL
bandwidth
22 (max)
16 (max)
BWTX-PLL-LO-3dB
BWTX-PLL-LO-1dB
PKGTX-PLL2
Minimum Tx PLL BW
for 3 dB peaking
1.5 (min)
8 (min)
MHz
MHz
dB
Minimum Tx PLL BW
for 1 dB peaking
Not specified
5 (min)
Tx PLL peaking with 5 Not specified
MHz min BW
1.0 (max)
S32V234 Data Sheet, Rev. 9, 03/2020
58
NXP Semiconductors
Ethernet Controller (ENET) Parameters
1. See Table 4-9 2.5 and 5.0 GT/s Transmitter Specifications in PCI Express Base Specification for further details.
Table 48. PCI Express receiver specifications1
Symbol
Parameter
Unit Interval
2.5 GT/s
5.0 GT/s
Units
UI
ps
V
399.88 (min)
400.12 (max)
199.94 (min)
200.06 (max)
VRX-DIFF-PP-CC
Differential Rx peak-
peak voltage for
common Refclk Rx
architecture
0.175 (min)
1.2 (max)
0.120 (min)
1.2 (max)
TRX-EYE
Receiver eye time
opening
0.40 (min)
N/A
UI
UI
UI
TRX-TJ-CC
TRX-DJ-DD-CC
Max Rx inherent timing N/A
error
0.40 (max)
0.30 (max)
Max Rx inherent
deterministic timing
error
N/A
1. See Table 4-12 2.5 and 5.0 GT/s Receiver Specifications in PCI Express Base Specification for further details.
6.5.7 IIC timing
Table 49. IIC SCL and SDA input timing specifications
Number
Symbol
Parameter
Value
Unit
Min
Max
1
—
D
Start condition
hold time
2
—
IP bus cycle1
2
4
6
7
—
—
—
—
D
D
D
D
Clock low time
Data hold time
Clock high time
8
—
—
—
—
IP bus cycle1
25
4
ns
IP bus cycle1
Data setup time 250 (standard
ns
mode); 100 (fast
mode)2
8
9
—
—
D
D
Start condition
setup time (for
repeated start
condition only)
2
2
—
—
IP bus cycle1
IP bus cycle1
Stop condition
setup time
1. Inter Peripheral Clock is the clock at which the IIC peripheral is working in the device
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
59
Ethernet Controller (ENET) Parameters
2. pg_clk frequency should be greater than 5 MHz for standard mode and 20 MHz for fast mode.
Table 50. IIC SCL and SDA output timing specifications
Number
Symbol
Parameter
Value
Unit
Min
Max
11
—
D
Start condition
hold time
6
—
—
IP bus cycle2
21
33
—
—
D
D
Clock low time
10
—
IP bus cycle1
ns
SCL/SDA rise
time
99.6
41
51
—
—
D
D
Data hold time
7
—
IP bus cycle1
ns
SCL/SDA fall
time
—
99.5
61
71
81
—
—
—
D
D
D
Clock high time 10
—
—
—
IP bus cycle1
IP bus cycle1
IP bus cycle1
Data setup time
2
Start condition
setup time (for
repeated start
condition only)
20
91
—
D
Stop condition
setup time
11
—
IP bus cycle1
1. Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed.
The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed in IFDR.
2. Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
3. Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA
takes to reach a high level depends on external signal capacitance and pullup resistor values.
Figure 43. IIC input/output timing
6.5.8 LINFlex timing
The maximum bit rate is 1.875 MBit/s.
S32V234 Data Sheet, Rev. 9, 03/2020
60
NXP Semiconductors
Display modules
6.6 Display modules
6.6.1 Display Control Unit (2D-ACE) Parameters
6.6.1.1 Interface to TFT panels
This section provides the LCD interface timing for a generic active matrix color TFT
panel.
Measurements are with a load of 20 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
In the figure below1, signals are shown with positive polarity. The sequence of events for
active matrix interface timing:
• PCLK latches data into the panel on its positive edge (when positive polarity is
selected). In active mode, PCLK runs continuously. This signal frequency could be
from 5 to 150 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one
PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data
to be shifted onto the display. When disabled, the data is invalid and the trace is off.
1. LD[23:0]” signal is “line data,” an aggregation of the 2D-ACE’s RGB signals—R[0:7], G[0:7] and B[0:7].
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
61
Display modules
VSYNC
LINE
n-1
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
HSYNC
DE
1
2
3
m-1
m
PCLK
LD[23:0]
Figure 44. TFT LCD interface timing overview
6.6.1.2 Interface to TFT LCD Panels—Pixel Level Timings
This section provides the horizontal timing (timing of one line), including both the
horizontal sync pulse and data. All parameters shown in the figure below are
programmable. This timing diagram corresponds to positive polarity of the PCLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of
the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The
default is active-high. The DE signal is always active-high. Pixel clock inversion and a
flexible programmable pixel clock delay are also supported. They are programmed via
the clock divide . The DELTA_X and DELTA_Y parameters are programmed via the
DISP_SIZE register. The PW_H, BP_H and FP_H parameters are programmed via the
HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
Table 51. LCD interface timing parameters—horizontal and vertical
Symbol
tPCP
Characteristic
Display pixel clock period
Unit
6.66
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWH
tBPH
tFPH
tSW
HSYNC pulse width
HSYNC back porch width
HSYNC front porch width
Screen width
PW_H * tPCP
BP_H * tPCP
FP_H * tPCP
DELTA_X * tPCP
(PW_H + BP_H + FP_H + DELTA_X ) * tPCP
PWV * tHSP
tHSP
tPWV
tBPV
tFPV
HSYNC (line) period
VSYNC pulse width
VSYNC back porch width
VSYNC front porch width
BP_V * tHSP
FP_V * tHSP
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
62
NXP Semiconductors
Display modules
Table 51. LCD interface timing parameters—horizontal and vertical (continued)
Symbol
tSH
tVSP
Characteristic
Unit
Screen height
VSYNC (frame) period
DELTA_Y * tHSP
ns
ns
(PW_V + BP_V + FP_V + DELTA_Y ) * tHSP
tHSP
tPWH
tPCP
tBPH
tSW
tFPH
Start
of line
PCLK
LD[23:0]
HSYNC
DE
Invalid Data
1
2
3
Invalid Data
DELTA_X
Figure 45. Horizontal sync timing
tVSP
tPWV
tHCP
tBPV
tSH
tFPV
Start of
Frame
HSYNC
LD[23:0]
(Line Data)
Invalid Data
1
2
3
Invalid Data
DELTA_Y
HSYNC
DE
Figure 46. Vertical sync pulse
6.6.1.3 Interface to TFT LCD panels—access level
This section provides the access level timing parameters of the LCD interface.
Table 52. LCD Interface Timing Parameters—Access Level
Symbol
tCKP
tDV
Description
Min
Max
Unit
Pixel Clock Period
6.66
_
_
3
3
ns
TFT interface data valid after pixel clock
TFT interface HSYNC valid after pixel clock
ns
ns
tDV
_
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
63
Display modules
Table 52. LCD Interface Timing Parameters—Access Level (continued)
Symbol
tDV
tDV
tHO
Description
Min
Max
Unit
TFT interface VSYNC valid after pixel clock
TFT interface DE valid after pixel clock
TFT interface output hold time for data and control bits
Relative skew between the data bits
_
_
0
_
3
ns
ns
ns
ns
3
_
1.5
Figure 47. LCD Interface Timing Parameters—Access Level
6.6.2 Video input unit (VIU) timing specifications
Clock
fPIX_CLK
tDHD
tDSU
Data/Hsync/Vsync
Figure 48. VIU timing diagram
Table 53. VIU timing parameters
Parameter
fPIX_CK
Description
Min
Typ
Max
Unit
VIU pixel clock
frequency
—
3
—
—
—
100
—
MHz
ns
tDSU
tDHD
VIU Data/Hsync/
Vsync setup time
VIU Data/Hsync/
Vsync hold time
1
—
ns
S32V234 Data Sheet, Rev. 9, 03/2020
64
NXP Semiconductors
Display modules
6.6.3 MIPICSI2 D-PHY electrical and timing parameters
The MIPICSI2 D-PHY2 is compliant with MIPICSI2 version 1.0, D-PHY specification
Rev. 1.01.00 (for MIPICSI2 sensor port x4 lanes)
6.6.3.1 Electrical and timing Information
Table 54. Electrical and timing Information
Symbol
HS Line Receiver DC Specifications
VIDTH Differential input high voltage
Parameters
Test conditions
Min
Typ
Max
Unit
-
-
-
70
-
mV
mV
threshold
VIDTL
Differential input low voltage
threshold
-70
VIHHS
Single ended input high voltage
Single ended input low voltage
Input common mode voltage
-
-
-
-
-
460
-
mV
mV
mV
mV
VILHS
-40
70
-
VCMRXDC
VTERM-EN
330
450
Single-ended threshold for HS
termination enable
ZID
Differential input impedance
80
-
125
ohm
LP Line Receiver DC Specifications
VILLP
Input low voltage
Input high voltage
-
-
-
-
550
-
mV
mV
mV
VIHLP
880
-
VIL-ULPS
Input low voltage (ultra low power
state)
300
VHYST
Input hysteresis
25
-
-
mV
2. All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may
be disclosed, reproduced or used for any purpose other than as needed to support the use of the products of NXP Inc.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
65
Display modules
6.6.3.2 D-PHY signaling levels
The signal levels are different for differential HS mode and single-ended LP mode. The
figure below shows both the HS and LP signal levels on the left and right sides,
respectively. The HS signaling levels are below the LP low-level input threshold such
that LP receiver always detects low on HS signals.
Table 55. D-PHY RX calibrator specifications
Symbol
Parameter
Min
Typ
Max
Unit
REXT
T cal
External reference
resistor, 1%
accuracy, for
-
-
15
2
-
-
KΩ
µs
autocalibration
Time from when
PD_RX signal goes
low to when
CALCOMPL goes
high
Figure 49. D-PHY signaling levels
6.6.3.3 D-PHY switching characteristics
Table 56. D-PHY switching characteristics
Symbol
Parameters
Test
Min
Typ
Max
Unit
conditions
HS Line Receiver AC Specifications
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
66
NXP Semiconductors
Display modules
Table 56. D-PHY switching characteristics (continued)
Symbol
Parameters
Test
Min
Typ
Max
Unit
conditions
-
Maximum serial data rate
On
80
-
1500
Mbps
DATAP/N
inputs. 80
OHM<= RL
<= 125
OHM
Δ
Common mode interference beyond 450
VCMRX(HF) MHz
-
-
-
-
100
50
mVpp
mVpp
pF
Δ
Common mode interference between 50
-50
-
VCMRX(LF) MHz and 450 MHz
CCM
Common mode termination
60
LP Line Receiver AC Specification
eSPIKE
TMIN
VINT
Input pulse rejection
-
-
-
-
-
300
Vps
ns
Minimum pulse response
Pk-to-Pk interference voltage
Interference frequency
20
-
-
200
-
mV
MHz
fINT
450
6.6.3.4 Low-Power Receiver timing
Figure 50. Input Glitch Rejection of Low-Power Receivers
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
67
Display modules
6.6.3.5 Data to Clock timing
Figure 51. Data to Clock timing definition
Table 57. Data to Clock timing specifications
Symbol
TCLKP
Parameters
Clock Period
Test conditions
Min
1.33
Typ
Max
Unit
—
—
—
—
—
—
—
25
ns
ns
UIINST
UI Instantaneuous
—
—
.667
0.21
0.152
0.21
12.5
—
TSETUP
Data to Clock Setup Time
UIINST
UIINST
UIINST
UIINST
—
THOLD
Clock to Data Hold Time
—
—
0.152
—
1. when D-PHY is supporting maximum data rate > 1 Gbps.
2. when D-PHY is supporting maximum data rate = 1 Gbps.
6.6.3.6 NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR
owned or controlled by any of the authors or developers of this material or MIPI®. The
material contained herein is provided on an “AS IS” basis and to the maximum extent
permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS,
and the authors and developers of this material and MIPI hereby disclaim all other
warranties and conditions, either express, implied or statutory, including, but not limited
to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike
effort, of lack of viruses, and of lack of negligence.
S32V234 Data Sheet, Rev. 9, 03/2020
68
NXP Semiconductors
Debug specifications
All materials contained herein are protected by copyright laws, and may not be
reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise
exploited in any manner without the express prior written permission of MIPI Alliance.
MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, trade names,
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used without its express prior written permission.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET
ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR
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OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF
THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE
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GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY
INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES
WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE,
ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT,
SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER
OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF
SUCH DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of
this Document is further notified that MIPI: (a) does not evaluate, test or verify the
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respects the contents of this Document or otherwise.
6.7 Debug specifications
6.7.1 JTAG interface timing
Measurements are with a load of 45 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
69
Debug specifications
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Table 58. JTAG pin AC electrical characteristics1
#
Symbol
Characteristic
JTAG/SWD TCK Cycle Time2
CJTAG TCK Cycle Time
Min
Max
Unit
1
tJCYC
253
504
40
-
-
ns
ns
%
-
2
tJDC
TCK Clock Pulse Width
60
3
tTCKRISE
tTMSS, tTDIS
tTMSH, tTDIH
tTDOV
TCK Rise and Fall Times (40% - 70%)
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
-
5
5
-
6
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
-
185
7
tTDOI
0
-
8
tTDOHZ
-
18
-
9
tJCMPPW
tJCMPS
100
40
-
10
11
12
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
-
tBSDV
6006
tBSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
-
600
13
14
15
tBSDHZ
tBSDST
tBSDHT
TCK Falling Edge to Output High Impedance
Boundary Scan Input Valid to TCK Rising Edge
-
600
ns
ns
ns
15
-
-
TCK Rising Edge to Boundary Scan Input Invalid 15
1. These specifications apply to boundary scan, JTAG and CJTAG, and serial wire debug modes.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
3. Cycle time is 25 ns assuming full cycle timing. Cycle time is 50 ns assuming half cycle timing
4. Cycle time is 50 ns assuming full cycle timing. Cycle time is 100 ns assuming half cycle timing
5. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
6. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
Table 59. PCIe JTAG AC electrical characteristics1
#
Symbol
Characteristic
Min
Max
Unit
1
2
3
4
5
6
7
8
9
tJCYC
tJDC
TCK Cycle Time2
253
40
-
-
ns
%
TCK Clock Pulse Width
60
1
tTCKRISE
tTMSS, tTDIS
tTMSH, tTDIH
tTDOV
TCK Rise and Fall Times (40% - 70%)
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
ns
ns
ns
ns
ns
ns
ns
5
-
5
-
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
-
214
tTDOI
0
-
tTDOHZ
-
21
-
tJCMPPW
100
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
70
NXP Semiconductors
Debug specifications
Table 59. PCIe JTAG AC electrical characteristics1 (continued)
#
Symbol
tJCMPS
Characteristic
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
Min
Max
Unit
10
11
12
40
-
-
ns
ns
ns
tBSDV
6005
tBSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
-
600
13
14
15
tBSDHZ
tBSDST
tBSDHT
TCK Falling Edge to Output High Impedance
Boundary Scan Input Valid to TCK Rising Edge
-
600
ns
ns
ns
15
-
-
TCK Rising Edge to Boundary Scan Input Invalid 15
1. These specifications apply to boundary scan, JTAG and CJTAG, and serial wire debug modes.
2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.
Refer to pad specification for allowed transition frequency
3. Cycle time is 25 ns assuming full cycle timing. Cycle time is 50 ns assuming half cycle timing.
4. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
5. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
TCK
2
3
2
1
3
Figure 52. JTAG test clock input timing
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
71
Debug specifications
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 53. JTAG test access port timing
TCK
10
JCOMP
9
Figure 54. JTAG JCOMP timing
S32V234 Data Sheet, Rev. 9, 03/2020
72
NXP Semiconductors
Debug specifications
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 55. JTAG boundary scan timing
6.7.2 Debug trace timing specifications
Measurements are with a load of 20 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Table 60. Debug trace operating behaviors
Symbol
Tcyc
Description
Min.
—
Max.
150
—
Typical
Unit
MHz
ns
Clock frequency
Low pulse width
—
Twl
2.8
2.95
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
73
Debug specifications
Table 60. Debug trace operating behaviors (continued)
Symbol
Twh
Description
Min.
2.8
—
Max.
—
Typical
2.95
Unit
ns
High pulse width
Data output valid
Data output hold
tDV
2.2
—
1.3
0
ns
tHO
0
ns
Figure 56. TRACE_CLKOUT specifications
6.8 Wakeup Unit (WKPU) AC specifications
Table 61. WKPU glitch filter specifications
Symbol
WFNMI
WNFNMI
Parameter
Min
Typ
Max
Unit
NMI pulse width that is rejected
NMI pulse width that is passed
-
-
-
20
-
ns
ns
400
6.9 RESET pin glitch filter specifications
Table 62. RESET pin glitch filter specifications
Symbol
WFRESET
Parameter
Min
Typ
Max
Unit
RESET pulse width that is
rejected
-
-
-
20
-
ns
ns
WNFRESET
RESET pulse width that is passed 400
6.10 External interrupt timing (IRQ pin)
Table 63. External interrupt timing
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
tIPWL
IRQ pulse width low
-
3
-
tCYC
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
74
NXP Semiconductors
Thermal attributes
Table 63. External interrupt timing (continued)
No.
Symbol
Parameter
IRQ pulse width high
IRQ edge to edge time1
Conditions
Min
Max
Unit
tCYC
tCYC
2
3
tIPWH
tICYC
-
-
3
6
-
-
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
1
2
3
Figure 57. External interrupt timing
7 Thermal attributes
7.1 Thermal attributes
Table 64. Thermal Resistance Data
Symbol
Parameter
Conditions
Estimate
s (w/
Unit
Lid)
RθJA
Junction to Ambient Natural Convection1 Single layer board (1s)
Junction to Ambient Natural Convection1 Four layer board (2s2p)
29
18
20
13
6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJMA
RθJMA
RθJB
Junction to Ambient (@200 ft/min)1
Junction to Ambient (@200 ft/min)1
Junction to Board2
Single layer board (1s)
Four layer board (2s2p)
Four layer board (2s2p)
Four layer board (2s2p)
Four layer board (2s2p)
RθJCtop
Junction to Case (Top)2
1
Junction to Lid Top3
0.32
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
3. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the
cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the
thermal resistance of the interface layer between the package and cold plate.
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
75
Dimensions
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
Package
Body size
Pitch
NXP document number
621 FC-BGA
17 mm x 17 mm
0.65 mm
98ASA00819D
9 Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Reset sequence
This section describes different reset sequences and details the duration for which the
device remains in reset condition in each of those conditions.
10.1 Reset sequence duration
Table 65 specifies the minimum and the maximum reset sequence duration for the five
different reset sequences described in Reset sequence description.
Table 65. RESET sequences1
No. Symbol
Parameter
TReset
Typ
—
Unit
Min
25
Max
~50
90
1
2
3
TDRB
TDR
Destructive Reset Sequence, All LBIST/MBIST enabled
Destructive Reset Sequence, BIST disabled
ms
µs
50
—
TERLB External Reset Sequence Long, Unsecure Boot, BIST enabled
25
—
~50
ms
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
76
NXP Semiconductors
Reset sequence
Table 65. RESET sequences1 (continued)
No. Symbol
Parameter
TReset
Unit
Min
50
2
Typ
—
Max
90
7
4
5
TFRL
TFRS
Functional Reset Sequence Long, Unsecure Boot, BIST disabled
Functional Reset Sequence Short, Unsecure Boot, BIST disabled
µs
µs
—
1. All the Reset durations assume boot code execution time for Execute-in-place for QuadSPI booting, Unsecure mode with
Trimmed FIRC module. Boot code is using execution using PLL and no DCD download is assumed. Secure Boot duration
and DCD download time is dependent on the given application image. DCD downloads and application image download/
authentication times will be over and above these durations.
10.2 Boot performance matrix
Total Boot execution time will be the addition of DCD execution time to configure DDR
and application image download time.
Table 66. Boot execution time
Boot QSPI_ CSE_
sourc CLOC CLOC clock config (FAST execut AST
CM4
QSPI SRAM DCD DDR(F DDR(F DDR(F DDR(F Authe Authe Authe
AST AST AST nticati nticati nticati
BOOT) BOOT) BOOT) BOOT)
e
K
K
(core uratio BOOT)
count
er
regist
er
ion
time
for
on
on
on
n
Non
secur
e
time
from
DDR
time
from
DDR
time
from
DDR
DDR
clock)
Boot
Length MHz
in bytes
100
133
MHz
133
MHz
HyperFl 4Mbyte NA
ash
4 MB
NA
256 KB 128 KB 32 KB NA
NA
NA
s
Authent 100
ication MHz
Length
133
MHz
133
MHz
HyperFl NA
ash
NA
NA
NA
NA
256 KB 128 KB 32 KB
in bytes
Time in 100
133
MHz
133
MHz
HyperFl 27.302 3.47
ash
25.347 1.63
0.819 0.211 7.4165 4.15405 1.7064
25 075
ms
MHz
5
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
77
Reset sequence
JUMPTO
APPLICATION
CODE
CLOCK
INITIALIZATION
AND
QSPI INIT
RESET
AFTER SELF
TEST
DCD EXECUTION
TO CONFIGURE
DDR
APPLICATION IMAGE DOWNLOAD
CSE FIRMWARE DOWNLOAD +
APPLICATION IMAGE AUTHENTICATION
(SECURE BOOT)
25.3
7.4
1.6
DDR(FASTBOOT)
0.82
CSEAUTHENTICATIONTIME
4.1
3.47 ms
FROM DDR
1.7
0.2
0
5
10
Time inms
Time inms
256 kB
128 kB
32 kB
4 MB
256 kB
128 kB
32kB
Figure 58. Boot diagram
10.3 Reset sequence description
The figures in this section show the internal states of the device during the five different
reset sequences. The doted lines in the figures indicate the starting point and the end point
for which the duration is specified in Table 65.
The application code execution starts when boot code has finished all the mandatory
tasks and jumps over the downloaded image. The download time and authentication time
will vary as per Application code image size.
"EXT_POR" pin (Active Low) is recommended to be de-asserted after external supplies
became stable. Deassertion of EXT_POR pin triggers the start of reset sequence.
The following figures show the internal states of the device during the execution of the
reset sequence and the possible states of the RESET (Active-low) signal pin.
NOTE
RESET (Active-low) is a bidirectional pin. The voltage level on
this pin can either be driven low by an external reset generator
or by the device internal reset circuitry. A high level on this pin
can only be generated by an external pullup resistor (10-15
kiloohm) which is strong enough to overdrive the weak internal
pulldown resistor. The rising edge on RESET (Active-low) in
the following figures indicates the time when the device stops
S32V234 Data Sheet, Rev. 9, 03/2020
78
NXP Semiconductors
Reset sequence
driving it low. The reset sequence durations given in Table 65
are applicable only if the internal reset sequence is not
prolonged by an external reset generator keeping RESET
(Active-low) asserted low beyond the last Phase3.
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Boot Code Self-test
Execution Setup
Establish
FIRC and
PWR
Fuse
Init
Fuse
Init
MBIST
LBIST
Device
Config
Device
Config
Application
Execution
Boot
Code
Execution
T
< T
< T
RESET DRB, max
DRB, min
Figure 59. Destructive reset sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE0
PHASE1,2
PHASE3
DRUN
Establish
FIRC and
PWR
Fuse
Init
Device
Config
Application
Execution
Boot
Code
Execution
T
< T
< T
RESET DR, max
DR, min
Figure 60. Destructive reset sequence, BIST disabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
BIST
PHASE1,2
PHASE3
DRUN
Fuse
Init
Fuse
Init
Device
config
Boot
Code
execution
Device
Config
Application
Execution
Self-test
Setup
LBIST
MBIST
Boot
code
execution
T
< T
RESET
< T
ERLB, max
ERLB, min
Figure 61. External reset sequence long, BIST enabled
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
79
Power sequencing requirements
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE1,2
PHASE3
DRUN
Fuse
Init
Device
Config
Application
Boot Ex ecut ion
code
execution
T
< T
< T
RESET FRL, max
FRL, min
Figure 62. Functional reset sequence long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
PHASE3
DRUN
Boot
code
Application
Execution
execution
T
< T
< T
RESET FRS, max
FRS, min
Figure 63. Functional reset sequence short
The reset sequences shown in Figure 62 and Figure 63 are triggered by functional reset
events. RESET (Active-low) is driven low during these two reset sequences only if the
corresponding functional reset source (which triggered the reset sequence) was enabled to
drive RESET (Active-low) low for the duration of the internal reset sequence. See the
RGM_FBRE register in the device reference manual for more information.
11 Power sequencing requirements
While designing the system, it is important to take care of following constraints:
• PCIE_VP and PCIE_VPH supplies should be powered up within 50 ms of each other.
• VDD_HV_CSI and VDD_LV_CSI supplies should be powered up within 50 ms of each
other.
• VREFH_ADC should never differ from VDD_HV_ADV by more than 100 mV at any time
including during power-up or power-down.
S32V234 Data Sheet, Rev. 9, 03/2020
80
NXP Semiconductors
Revision history
• DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of VDD_DDR0_IO
and VDD_DDR1_IO supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1 supply
variations as measured at the receiver. Peak-to-Peak noise on DDR0_VREF0 and
DDR1_VREF0 supplies should be between +/- 15 mV.
• The maximum rise time for the POR and RESET signal is 1 ms. Very slow ramps
can induce bounces in the input read state during the transition from logic low to
logic high, which causes the part getting locked in a self-reset loop. Any external
noise on this pin can increase the problem.
NOTE
VDD_HV_ADV must be powered for using LFAST interface.
Each supply group mentioned in the table below can be independently powered up/down
from the other supply groups. Power supplies in the same group must be powered up/
down together. Supply groups belonging to the same supply domain can be ganged
together on board level (with appropriate noise isolation) to allow these groups to power
up/down together. Following supply groups have been tested for power sequencing tests:
Table 67. Supply groups tested for power sequencing
Supply Group No.
Voltage domain
3.3 V
S32V234 power supplies
VDD_GPIO0
1
2
3
4
5
6
7
8
9
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.5 V/1.8 V/2.5 V/3.3 V
1.8 V
VDD_GPIO1
VDD_GPIO2
VDD_HV_IO_VIU0
VDD_HV_IO_VIU1
VDD_HV_DIS
VDD_HV_IO_FLA
VDD_HV_IO_ETH
VDD_HV_PLL, VDD_HV_LFASTPLL, VDD_HV_FXOSC
,
VDD_HV_PMC, VDD_HV_EFUSE, VDD_HV_DDR
PCIE_VPH, VDD_HV_CSI, VDDIO_LFAST
,
10
1.0 V
VDD_LV_CORE_SOC, VDD_LV_CORE_ARM, VDD_LV_GPU
VDD_LV_PLL, PCIE_VP, VDD_LV_CSI
,
11
12
1.8 V
VDD_HV_ADV, VREFH_ADC
VDD_DDR_IO
1.2 V/1.35 V/1.5 V
12 Revision history
Table 68. Revision history
Revision
Date
Description of changes
1
03/2015 Initial release.
Table continues on the next page...
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
81
Revision history
Table 68. Revision history (continued)
Revision
Date
06/2015 Overall:
• Editorial changes.
Description of changes
2
Added topic PCB routing guideliness.
Added topic RESET pin glitch filter specifications.
In Table 15, added the sentence "For internal ADC channels, the minimum sampling time required
is 3 microsecond" in the foot note on "Sample time".
In Power Management Controller (PMC) electrical specifications, changed the introductory
paragraph. Added Low Voltage Detector for IRC (VDD_HV_OSC).
In Table 3, modified minimum value of 3.3 V input/output supply voltage.
In Reset sequence description, updated both "External reset sequence long, BIST enabled" and
"Destructive reset sequence, BIST enabled" images.
In Table 17, updated the condition of Oscillator start-up time from fOSC = 24,40 MHz to fFXOSCHS
24,40 MHz.
=
In Power sequencing requirements, changed VREFL_ADC to VREFH_ADC, VDD_HV_CSI1/2 to
VDD_HV_CSI, and VDD_LV_CSI1/2 to VDD_LV_CSI.
In Table 10, added footnote in ovdd.
In Table 5, changed VS4 to S32V234 and VS2 to S32V232.
Made extensive changes in QuadSPI AC specifications.
In Table 3, added Supply ramp rate specifications.
In Table 5, changed maximum value of vdd_hv_pll from 30 mA to 35 mA and maximum value of
vdd_lv_pll from 55 mA to 80 mA.
In DDR3 and DDR3L timing parameters , added a note.
In Table 29, updated the table title to include DDR3L. Also updated minimum value of DDR4. DDR5,
DDR6, and DDR7 and changed units of DDR1 and DDR2.
In Table 30, updated the table title to include DDR3L. Also updated minimum value of DDR26.
In Table 31, updated the table title to include DDR3L. Updated minimum values of DDR17 and
DDR18, and units of DDR21 and DDR22.
In Table 32, updated LP1 and LP2 symbols and units.
In Figure 15, changed figure title from “LPDDR3 write cycle” to “LPDDR2 write cycle”.
In Table 34, updated minimum value of LP18, and minimum and maximum value of LP21. Also
updated units of LP21, LP22, and LP23.
Updated topic titles DDR SDRAM Specific Parameters (DDR3, DDR3L, and LPDDR2), DDR3 and
DDR3L timing parameters , DDR3 and DDR3L read cycle, and DDR3 and DDR3L write cycle.
Updated figure titles Figure 10, Figure 11, and Figure 12.
In Reset sequence description, added value of external pull up resistor as 10-15 kiloohm.
In Table 18, modified the parameter "IRCOSC frequency variation afterprocess trimming" to
"IRCOSC frequency variation with respect to supply and temperature after process trimming".
Updated Table 16.
In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC), added the sentence
"uSDHC_VEND_SPEC[CMD_OE_PRE_EN] field should be programmed to 1 for proper functioning
of uSDHC external interface".
In Table 59, updated maximum value of TCK Rise and Fall Times.
Table continues on the next page...
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Revision history
Table 68. Revision history (continued)
Revision
Date
Description of changes
In Table 58, updated minimum value of TCK Cycle Time and the footnote. Also, added CJTAG TCK
Cycle Time and updated maximum value of TCK Rise and Fall Times.
Added DDR3L mode and DDR3L mode DC electrical specifications.
Removed LPDDR2 I/O AC specifications.
Deleted the word "Dual" from "Dual QuadSPI supporting Execute-In-Place (XIP)" in "Features"
section as there is only one QuadSPI.
Changed all instances of XOSC to FXOSC throughout the document.
Changed all instances of MIPI-CSI2, MIPI, and CSI2 to MIPICSI2 throughout the document.
2.1
3
06/2015 Overall:
• Editorial changes.
04/2017
• Editorial changes.
• Updated Figure 1.
• Modified Figure 4.
• Modified Figure 6.
• Modified Figure 7.
• Updated Figure 29.
• Updated Figure 38.
• Updated Figure 43.
• Updated Figure 48.
• Removed Figure "DSPI modified transfer format timing – slave, CPHA = 0" and Figure "DSPI
modified transfer format timing — slave, CPHA = 1".
• In Table 1, updated ARM Cortex-A53 Core feature for S32V232 from “Up to 600 MHz Quad
ARM Cortex-A53” to “Up to 800 MHz Dual ARM Cortex-A53 (single cluster)”.
• In Table 3 :
• added the footnote "All the grounds viz. VSS, VSS_XOSC,VSS_PMC and
VSS_HV_ADV are tied together at the package level” in Common ground voltage.
• minimum operating voltage of VDD_HV_IO_ETH has been changed from 1.71 V to 1.5 V,
and maximum value of DDR I/O supply voltage LPDDR2 changed from 1.26 V to 1.30
V.
• parameter “Supply ramp rate” has been changed to “Supply ramp rate for all supplies
on the device”
• added LFAST IO bank supply (VDDIO_LFAST) in the list of symbols for "1.8 V supply
voltage (for analog circuits, PLLs)"
• In Table 4 :
• added Band Gap Reference value of PMC.
• maximum value of trimmed VTH threshold of VDD_LV_CORE_SOC (low voltage
monitoring) has been changed from 939 to 946 mV, and maximum values of trimmed
VTL and VTH threshold of VDD_LV_CORE_SOC (high voltage monitoring) have been
changed from 1081 to 1093, and 1096 to 1093 mV, respectively.
• In Table 5 :
• modified table footnotes to clarify that power numbers are estimated for 1.01 V and 125
°C.
• VDD_HV_LFASTPLL Simulation values (Maximum) and Maximum Values of Use cases
"PLL operating with 320 MHz (LFAST used)” and "PLL not operational (LFAST not
used)” have been modified.
• use case “eFuse reading happening” of VDD_HV_EFUSE and its specifications are
removed.
• max simulation values of MIPICSI2 interface operating as per MIPICSI not used (not
powered?) in VDD_HV_CSI and VDD_LV_CSI have been changed from .1 mA to 1.6
mA and 11 mA to 15 mA.
• for PCIE_VP and PCIE_VPH, Powered down (leakage only) use case has been
changed to Reset/idle. Max simulation values for PCIE_VP and PCIE_VPH (Reset/idle)
Table continues on the next page...
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83
Revision history
Table 68. Revision history
Revision
Date
Description of changes
use cases are removed, and PCIE_VPH (5 GHz operation) use case has been changed
from 30 to 32 mA. Max values of both PCIE_VP and PCIE_VPH (for both cases) have
been included.
• modified the table heading. Removed Front Camera (w power binning) from
VDD_LV_CORE and updated max values for “Adder 4x A53 CPU with Dhrystone MIPS
running on each CPU @1 GHz” from 1.0 A to 1.4 A.
• removed "Simulation values" column.
• PCIE_VPH limits changed for “5 GHz operation (PCIe 2.0)” from 40 mA to 50 mA and
“Reset/Idle” from 11 mA to 20 mA.
• minimum and maximum values of PMC Band Gap Reference value have been changed
from 1185 to 1176 mV, and 1215 to 1224 mV respectively.
• In Table 10 :
• added the note ”After bootup, application software should switch to manual voltage
detect mode using VSEL_x settings of SRC_GPR14 register to ensure optimum
performance of the GPIO pads. Please refer to SRC chapter in the Reference Manual
for the register details.”
• changed the maximum value of Input current (no pull-up/down) from 1 to 8 μA.
• removed “Input Hysteresis”
• maximum value of parameter “Input current (50 kilohm PU)” has been changed from
100 to 150 μA.
• maximum value of parameter “Input current (100 kilohm PU)” has been changed from
50 to 60 μA.
• removed parameter “pad keeeper resistance” and "maximum external resistor value
that is guaranteed to overdrive the pad keeper".
• maximum value of parameter “Input current (50 kilohm PD)” with test condition Vin=0
has been changed from 1 to 8 μA. Also, when Vin = Vdd, maximum value of Input
current (33 kilohm PU), Input current (50 kilohm PU), and Input current (100 kilohm PU)
have been changed from 1 to 6 μA.
• test conditions "Ioh=-1 mA" changed to "Ioh=-100 μA" and "Ioh= 1 mA" changed to
"Ioh=-100 μA".
• In Table 12, Table 13, and Table 14,
• Added Vih (DC) and Vil (DC) specifications .
• All tri-state supply current items are removed and updated test conditions of "High-level
output voltage" and "Low-level output voltage".
• Maximum value of parameter “ Input current (no pullup/pulldown)” has been changed
from 3 to 5 μA, 3 to 5 μA, and 2.5 to 5 μA, respectively.
• In Table 12, removed parameter “Rod_keep”. Updated minimum, typical, and maximum value
of parameter Rkeep.
• In Table 13, removed parameter “Rod_keep”.
• In Table 14, removed parameter “Rod_keep” and deleted footnote “Note that the Jedec
LPDDR2 specification (JESD209-2B) supersedes any specification in this document”.
• In Table 15
• updated ADC Input Clock frequency
• added ADC Conversion clock frequency
• removed conditions of Sample time and Conversion time
• removed all information about parameter “Max positive/negative injection” and modified
“Total unadjusted error” in “TUE”.
• In Table 17, modified the minimum and maximum values of VIH and VIL.
• In Table 19 :
• Changed maximum value of SSCG modulation depth from -6% to -5.4%, and added
condition STEPSIZE x STEPNO < 18432.
• Removed “PLL VCO frequency” and “PLL output clock PHI0”, and deleted footnote "All
PLLs have same specifications. PLL programming should take maximum clock
frequencies as per Reference Manual recommendation”.
• Added Table 19.
Table continues on the next page...
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84
NXP Semiconductors
Revision history
Table 68. Revision history
Revision
Date
Description of changes
• In Table 21 :
• unit for Total Jitter has been changed from ps to ns.
• removed max Deterministic and max Random jitter specifications; added footnote in
max Total Jitter.
• In Table 22 :
• Made modification in DDR mode.
• Updated values of QuadSPI_SOCCR[FDCC_FB] and QuadSPI_SOCCR[FDCC_FA] for
SDR and DDR mode (internal DQS Mode) and added footnote “Device qualification is
not complete.”
• Deleted Table "QuadSPI input timing (DDR mode) specifications with learning"
• In Table 24 changed Minimum value of Chip select output setup time and Chip select output
hold time.
• In Table 25
• changed maximum value of SCK Clock Frequency and updated configuration. Also,
changed table caption
• changed the minimum value of "Setup time for incoming data".
• In Table 26 :
• deleted "Chip select output setup time" and "Chip select output hold time".
• changed the maximum value of "Output Data Valid" and minimum value of "Output Data
Hold".
• In Table 27, updated minimum value of parameters “Setup time for incoming data” and “Hold
time for incoming data”.
• In Table 28, updated maximum value of “Ck to Ck2 skew max” and minimum value of “Ck to
Ck2 skew min”.
• In Table 29 changed symbol and minimum value of DDR4, DDR5, DDR6, and DDR7.
• In Table 30 modified minimum value of DDR26 from 540 to 563 ps.
• In Table 31 changed the symbol and minimum value of DDR17 and DDR18.
• In Table 32 changed the symbol and minimum value of parameters CKE setup time, CKE hold
time, CA setup time, and CA hold time.
• In Table 33 changed the minimum value of LP26.
• In Table 34 changed the symbol and minimum value of LP17 and LP18.
• In Table 35 :
• Updated footnotes to include changes in PCSSCK, CSSCK, PASC, ASC values.
• Updated footnotes in minimum timing of parameter DSPI cycle time, PCS to SCK delay,
and After SCK delay.
• In Table 36 changed the heading of table from "SD/eMMC4.3 interface timing specification" to
"SDR mode timing specification".
• In Table 37 changed the heading of table from "SD3.0/eMMC4.5 interface timing
specification" to "DDR mode timing specification" and updated parameter "Clock Frequency
(eMMC4.5 DDR)" to "Clock Frequency (eMMC4.4 DDR)".
• In Table 38 :
• updated min, typ, and max values of VOS_DRF and |ΔVOD_DRF
• deleted ROUT_DRF and VHYS_DRF
|
• modified RIN_DRF
• added LFAST Clock characteristics
• parameter Rise/Fall time (10% - 90% of swing) is changed to Rise/Fall time (20% - 80%
of swing) and minimum and maximum values of the parameter have been changed from
0.26 to 0.1 ns and 1.5 to 0.73 ns.
• added footnote “Rise/fall time is defined for 20 to 80% signal voltage levels, at 2pF
Cload and 100 Ohm termination resistor load”.
• Updated minimum and maximum value of “Common mode voltage” (Transmitter) from
1.125 to 1.1 V and 1.375 to 1.475 V.
• Updated maximum value of “Common mode voltage” (Receiver) from 1.6 to 1.5 V.
Table continues on the next page...
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NXP Semiconductors
85
Revision history
Table 68. Revision history
Revision
Date
Description of changes
• Updated the footnote in minimum and maximum values of “Common mode voltage”
(Receiver).
• Changed minimum value of “Differential input voltage” (Receiver) from 100 to 150 mV.
• In Table 43 changed minimum and maximum value of RX_CLK duty cycle.
• In Table 44 :
• changed minimum and maximum value of TX_CLK duty cycle and minimum value of
Out delay from TX_CLK.
• included "TX_CLK to Output Valid" and "TX_CLK to Output Invalid".
• In Table 45 removed the foot note from "Characteristic".
• In Table 49 :
• Changed minimum value of “Data hold time0” and “Data setup time” from 0 to 25 ns,
and 0 to 250 (standard mode); 100 (fast mode) respectively
• Added note "ipg_clk frequency should be greater than 5 MHz for standard mode and 20
MHz for fast mode" to minimum value of “Data setup time”
• Updated the column "Number"
• In Table 50, minimum value of “Stop condition setup time” has been changed from 10 to 11
IPS bus cycle.
• In Table 51, changed Display pixel clock period from 6.4 to 6.66 ns.
• In Table 52, changed pixel clock period from 6.36 to 6.66 ns.
• In Table 53, changed description "VIU data setup time" to "VIU Data/Hsync/Vsync setup time"
and "VIU data hold time" to "VIU Data/Hsync/Vsync hold time".
• In Table 54, removed "Contention Line Receiver DC Specifications".
• In Table 57, Data to Clock Setup Time and Clock to Data Hold Time are updated to include
condition where the PHY is used to a maximum data rate of 1.0Gbps and data rates greater
than 1.0Gbps.
• In Table 60, updated Clock frequency.
• In Table 65 :
• changed minimum and maximum values of “Destructive Reset Sequence, BIST
disabled” from 5 ms to 50 µs and 10 ms to 90 µs
• changed minimum and maximum values of “Functional Reset Sequence Long,
Unsecure Boot, BIST disabled” from 5 ms to 50 µs and 10 ms to 90 µs
• changed minimum and maximum values of ”Functional Reset Sequence Short,
Unsecure Boot, BIST disabled” from 5 ms to 2 µs and 6 ms to 7 µs.
• Added Table 67 and a paragraph preceding it “Each supply group mentioned in the table
below can be independently powered up/down from the other supply groups. Supply domains
belonging to the same supply group are supposed to be ganged together on board level (with
appropriate noise isolation) to allow this group to power up/down together”.
• All IRC and IRCOSC in the document changed to FIRC.
• In Features, modified JPEG and H.264 information.
• Removed hysteresis information from Features, Table 1, and from Table 10.
• Modified content in Family comparison.
• Added topic Operation above maximum operating conditions.
• Updated Ordering information
• In Power consumption, modified the statement “These specifications are design targets and
are subject to change per device characterization” to “These specifications are subject to
change per device characterization.”
• In PCB routing guidelines changed the subheading from "DDR3 PCB design" to "DDR3/
DDR3L PCB design".
• Added topic GPIO speed at various voltage levels.
• In DDR pads, deleted table "DDR operating conditions".
• In ADC electrical specifications, Updated the note to “While measuring scaled supply voltages
on ADC Channels, Maximum (+5/-10%) variation can be expected .”
• In Main oscillator electrical characteristics, added crystal information.
• In ADC electrical specifications added the note “While measuring scaled supply voltages on
ADC Channels, Maximum 10% variation can be expected”.
Table continues on the next page...
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NXP Semiconductors
Revision history
Table 68. Revision history (continued)
Revision
Date
Description of changes
• In Thermal Monitoring Unit (TMU), changed all occurrences of “Temperature Sensor” to
“Thermal Monitoring Unit”.
• In 48 MHz FIRC electrical characteristics, min and max value of “IRCOSC frequency variation
with respect to supply and temperature after process trimming” has been changed from -5 to
-10 and +5 to +10 %.
• In QuadSPI AC specifications deleted sentence "DDR configurations are applicable when
used without learning enabled."
• Added a note in DSPI timing.
• In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) changed the introductory
paragraph.
• Renamed topic "SD/eMMC4.3 (Single Data Rate) AC Timing" to "SDR Mode Timing
Specifications". In this topic SDR mode timing specifications deleted the introductory
paragraph and deleted the existing figure. Two new figures Figure 23 and Figure 24 are
added. Modified Table 36.
• Renamed topic "SD/eMMC4.4/5.0 (Dual Data Rate) eSDHCv3 AC Timing" to "DDR Mode
Timing Specifications". In this topic DDR mode timing specifications, deleted the introductory
paragraph and replaced the existing figure with four new figures (Figure 25, Figure 26, Figure
27, Figure 28).
• In DSPI timing changed the note from "DSPI on this chip neither supports interaction with a
Slave in MTFE mode nor acts as one" to "DSPI Timing specs on this chip are valid with Slave
in Classic Mode only."
• In Ethernet Switching Specifications, ” statement "For RGMI, output load is 15 pF and pad
settings are DSE[2:0] = 111 and FSEL[1:0] = 11" is changed to "For RGMII, output load is 5
pF and pad settings are DSE[2:0] = 111 and FSEL[1:0] = 11."
• Added topic MII/RMII Serial Management channel timing (MDC/MDIO).
• In Video input unit (VIU) timing specifications heading "Video input unit (VIU) electrical
specifications" changed to "Video input unit (VIU) timing specifications".
• Added topic Boot performance matrix.
• In Power sequencing requirements :
• added note "VDD_HV_ADV must be powered for using LFAST interface". Changed
“VREFH_ADC should never be more than 100 mV above VDD_HV_ADV” to
“VREFH_ADC should never differ from VDD_HV_ADV by more than 100 mV at any
time including during power-up or power-down”.
• Changed the sentence from "DDR0_VREF0 and DDR1_VREF0 supplies are expected
to be 0.5 of VDD_HV_DDR0 and VDD_HV_DDR1 I/O supplies and are to track
VDD_HV_DDR0 and VDD_HV_DDR1 supply variations as measured at the receiver” to
"DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of VDD_DDR0_IO
and VDD_DDR1_IO supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1
supply variations as measured at the receiver”.
• Updated the statement "VDD_HV_CSI and VDD_LV_CSI should be powered up
together on board to prevent any electrical crossover currents" to "VDD_HV_CSI and
VDD_LV_CSI supplies should be powered up within 50 ms of each other".
3.1
4
07/2017
11/2017
• The only changes between S32V234 Rev 3.1 and Rev 3 is the removal of "Confidential
Proprietary" from the footer.
• In Ordering information, added a table mentioning the production part numbers with
respective feature configurations.
• In Table 19, updated SSCG modulation depth values.
• In Features, updated the statement for "APEX2-CL Image cognition processor" to remove the
mention of OpenCL 1.2 support.
• In Features, updated the first statement under "Memory interfaces" with the correct LPDDR2/
DDR3/DDR3L operating specs.
• Updated LPDDR2 and DDR3 operating clock rate and data rate in Figure 1.
• In Feature Set, updated the "Memory Interfaces" entry for the correct operating data rate and
clock rate of LPDD2 and DDR3.
Table continues on the next page...
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87
Revision history
Table 68. Revision history (continued)
Revision
Date
Description of changes
• In PCB routing guidelines, added a note under the "CLK/Addess/Commands" section. And
updated the third point under the section for clarification.
• In Table 3, row 2 and 3 has been split into sub-sections for different I/O voltages.
• In Table 5, updated max value for VDD_HV_LFASTPLL when "PLL operating with 320 MHz
(LFAST used)". Value is changed from 24 mA to 26 mA.
• In Table 16, updated TADC at TJ = 40 °C to 125 °C, from +/- 5 °C to +/- 6 °C.
• In Table 5, updated descriptions for VDD_HV_CSI and VDD_LV_CSI. The string "not
powered?" is changed to "IP Powered and Disabled".
• In Main oscillator electrical characteristics, updated the section to remove references of 24
MHz FXOSC support.
• In Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC), updated the topic title and
added a paragraph describing voltage restriction with eMMC booting.
• In Table 5, removed the footnotes from the "Max Values" column, and added one to the
VDD_LV_CORE entry.
• In Table 19, updated the frequency values for "PLL input clock".
• In Table 20, updated the "Input Frequency" values.
• Updated the specs in following tables:
• Table 29
• Table 31
• Table 32
• Table 34
• Removed the table "PLL maximum frequencies" from the section PLL electrical specifications.
• In DFS electrical specifications, updated mfn division factor from [0:255] to [1:255], and
updated the footnote from the Table 20.
5
6
03/2018
08/2018
• This device is qualified now, so removed the footnote from Table 22 that said "Device
qualification is not complete.".
• Corrected "Operating Max Supply Voltage" for "3.3 V DGO Voltage Domain" in Table 2 to 3.6
V.
• Corrected Block diagram to add DRAM-ECC to MMDC_1 block, similar to it was with
MMDC_0.
• Updated the specs for VDD_LV_CORE in Table 5.
• Updated max values for TDRB and TERLB in Table 65.
• GPIO speed at various voltage levels - Added a note at the end of the section.
• Power sequencing requirements - Added one new point to the bullet list mentioning the
maximum rise time for POR signal.
• Boot Configuration Pins Specification - Added two notes in this section.
• Table 56 - Updated "Maximum serial data rate" spec from "80 to 1.5 Gbps" to "80 to 1500
Mbps".
• Following changes are made throughout the document for better clarification:
• DSE[2:0] changed to SIUL2_MSCRn[DSE].
• ipp_dse<1:0> changed to SIUL2_MSCRn[DSE].
• FSEL[1:0] changed to SIUL2_MSCRn[SRE].
• ipp_fsel changed to SIUL2_MSCRn[SRE].
• Deleted the test condition about ipp_do.
• Added a note to the following sections to clarify that to match with the measurements given in
the section you must ensure the configuration mentioned. That may not be the default
configuration of the chip after reset.
• QuadSPI AC specifications
• DSPI timing
• Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
• Ethernet Switching Specifications
• MII/RMII Serial Management channel timing (MDC/MDIO)
• Interface to TFT panels
Table continues on the next page...
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Revision history
Table 68. Revision history (continued)
Revision
Date
Description of changes
• JTAG interface timing
• Debug trace timing specifications
• Electrostatic discharge (ESD) specifications - Removed the VESD(CDM) specs for corner
pins.
7
8
08/2018
12/2018
• GPIO speed at various voltage levels - Added the text "The maximum rise time for all GPIO
pins is 1 ms" to the existing note.
• Power sequencing requirements - Updated the last bullet to "The maximum rise time for the
POR and RESET.........this pin can increase the problem.".
• Changed all instances of XOSC to FXOSC throughout the document.
• In Table 1 - For S32V232 changed "Up to 800 MHz Dual ARM Cortex-A53 (single cluster)" to
"Up to 1000 MHz Dual ARM Cortex-A53 (single cluster)" and in communications row removed
all the text and added text "Same as S32V234" for S32V232.
• In Ordering information - Changed text from "The orderable part numbers of this chip are in
the table below" to "An example of orderable part numbers of this chip are in the table below".
• In GPIO speed at various voltage levels - Added the Drive Strength "001" and "010" in the
"GPIO rise/fall times (1.8 V range)", "GPIO rise/fall times (2.5 V range)" and "GPIO rise/fall
times (3.3 V range)" tables.
• In Features - Removed the text "ARM TrustZone (TZ) architecture support" and added text
"Secure vs non-secure applications separation supported via ARM v8 exception level support
in the ARM Cortex A53 clusters and its extension via XRDC on SoC level".
• In Table 5 updated the following:
• Replaced descriptive text with orderable part number.
• Removed @ 125 C from each row.
• Split the row "DD_LV_CORE" into "DD_LV_CORE (static)" and "DD_LV_CORE
(dynamic)" into separate rows.
• Added "Tj" as the temperature in the footnote.
• Added further static power entries. Added values for 125 Tj and 105 Tj for
VDD_LV_CORE (Static).
• Added parameters "VDD_HV_ADV" and "VDD_REFH_ADC".
• In DDR3 and DDR3L timing parameters added Note "DDR3 and DDR3L timing parameters
are compliant with JESD79-3F and JESD79-3-1A.01 specifications respectively".
• In LPDDR2 timing parameter added Note "LPDDR2 timing parameters are compliant with
JESD209-2B specification".
9
01/2020
• In Ordering information :
• Added Figure 1.
• Added a note "For the latest information on orderable parts please check https://
www.nxp.com/s32v234 Buy/Parametrics section".
• In Features changed the text from "Secure vs non-secure applications separation supported
via ARM v8 exception level support in the ARM Cortex A53 clusters and its extension via
XRDC on chip level" to "ARM TrustZone (TZ) architecture support".
• In Table 2 removed the "Operating Max Supply Voltage" rows.
• Removed the Maximum and Minimum values of Vtt and added a footnote in Table 13 and
Table 12.
• Updated the text from "Supply domains belonging to the same supply group are supposed to
be ganged together on board level (with appropriate noise isolation) to allow this group to
power up/down together" to "Power supplies in the same group must be powered up/down
together. Supply groups belonging to the same supply domain can be ganged together on
board level (with appropriate noise isolation) to allow these groups to power up/down
together" in Power sequencing requirements.
• In Table 38 for |ΔVI_DRF|added the conditions "VICOM_DRF>1.4 V" and "VICOM_DRF<= 1.4 V".
S32V234 Data Sheet, Rev. 9, 03/2020
NXP Semiconductors
89
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Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, and UMEMS
are trademarks of NXP B.V. All other product or service names are the property of their respective
owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink,
CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP,
RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS,
ULINKpro, μVision, Versatile are trademarks or registered trademarks of Arm Limited (or its
subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of
patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered
trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word marks and the
Power and Power.org logos and related marks are trademarks and service marks licensed by
Power.org.
© 2020 NXP B.V.
Document Number S32V234
Revision 9, 03/2020
相关型号：
SI9130DB
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SI9135LG-T1
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
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SI9136_11
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SI9130CG-T1-E3
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