FTT1010-M/EG [NXP]
Frame Transfer CCD Image Sensor; 帧转移CCD图像传感器
| 型号： | FTT1010-M/EG |
| 厂家： | 
NXP |
| 描述： | Frame Transfer CCD Image Sensor |
| 文件： | 总17页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IMAGE SENSORS
FTT1010-M
Frame Transfer CCD Image Sensor
Product specification
1999 September 21
File under Image Sensors
Philips
Semiconductors
TRAD
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
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1-inch optical format
1M active pixels (1024H x 1024V)
Progressive scan
Excellent anti-blooming
Variable electronic shuttering
Square pixel structure
H and V binning
100% optical fill factor
High dynamic range (>72dB)
High sensitivity
Description
The FTT 1010-M is a monochrome progressive-scan frame-transfer
image sensor offering 1K x 1K pixels at 30 frames per second through
a single output buffer. The combination of high speed and a high
linear dynamic range (>12 true bits at room temperature without
cooling) makes this device the perfect solution for high-end real time
medical X-ray, scientific and industrial applications. A second output
can either be used for mirrored images, or can be read out
simultaneously with the other output to double the frame rate. The
device structure is shown in figure 1.
Low dark current and fixed pattern noise
Low read-out noise
Data rate up to 2 x 40 MHz
Mirrored and split read-out
Device structure
6 black lines
Z
Y
Optical size:
12.288 mm (H) x 12.288 mm (V)
Chip size:
Pixel size:
Active pixels:
Total no. of pixels:
Optical black pixels:
Timing pixels:
Dummy register cells:
Optical black lines:
14.572 mm (H) x 26.508 mm (V)
12 µm x 12 µm
1024 (H) x 1024 (V)
1072 (H) x 1030 (V)
Image Section
1024
active
lines
4
4
20
20
Left: 20
Left: 4
Left: 7
Right: 20
Right: 4
Right: 7
1024 active pixels
2060
lines
Bottom: 6 Top: 6
Storage Section
W
7
X
6 black lines
1072 cells
Output
7
amplifier
Output register
Figure 1 - Device structure
1999 September
2
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Architecture of the FTT1010-M
The FTT1010-M consists of a shielded storage section and an open
image section. Both sections are electronically the same and have
the same cell structure with the same properties.The only difference
between the two sections is the optical light shield.
The left and the right half of each output register can be controlled
independently. This enables either single or multiple read-out.
During vertical transport the C3 gates separate the pixels in the
register. The letters W, X, Y and Z are used to define the four
quadrants of the sensor. The central C3 gates of both registers are
part of the W and Z quadrants of the sensor.
The optical centres of all pixels in the image section form a square
grid. The charge is generated and integrated in this section. Output
registers are located below the storage section.The output amplifiers
Y and Z are not used in Frame Transfer mode and should be
connected as not-used amplifiers.
Both upper and lower registers can be used for vertical binning.
Both registers also have a summing gate at each end that can be
used for horizontal binning. Figure 2 shows the detailed internal
structure.
After the integration time the charge collected in the image section
is shifted to the storage section. The charge is read out line by line
through the lower output register.
IMAGE SECTION
Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
17.38 mm
1:1
12.288 x 12.288 mm2
12x12 µm2
100%
Geometric fill factor
Image clock pins
Capacity of each clock phase
Number of active lines
A1, A2, A3, A4
2.5nF per pin
1024
Number of black reference lines
Number of dummy black lines
Total number of lines
2
4
1030
Number of active pixels per line
Number of overscan (timing) pixels per line
Number of black reference pixels per line
Total number of pixels per line
1024
8 (2x4)
40 (2x20)
1072
STORAGE SECTION
Storage width x height
Cell width x height
12.864 x 12.360 mm2
12x12 µm2
Storage clock phases
Capacity of each clock phase
Number of cells per line
Number of lines
B1, B2, B3, B4
2.5nF per pin
1072
1030
OUTPUT REGISTERS
Output buffers (three-stage source follower)
Number of registers
4 (one on each corner)
2 (one above, one below)
14 (2x7)
Number of dummy cells per register
Number of register cells per register
Output register horizontal transport clock pins
Capacity of each C-clock phase
Overlap capacity between neighbouring C-clocks
Output register Summing Gates
Capacity of each SG
1072
C1, C2, C3
60pF per pin
20pF
4 pins (SG)
15pF
Reset Gate clock phases
Capacity of each RG
4 pins (RG)
15pF
1999 September
3
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
7 dummy
pixels
20 black & 4
timing columns
1K image
pixels
20 black & 4 timing
columns
7 dummy
pixels
RD
RD
RG
RG
OG SG C2 C1 C3
C2 C1 C3 C2 C1 CC33 C2 C1 C3
C2 C1 C3 C2 C1 C3
C2 C1 C3 C2 C1 C3
C2 C1 C3 C2 C1 C3 C2 C1 C3
C2 C1 SG OG
A1
A2
A3
A4
A1
A2
A3
A4
OUT_Z
OUT_Y
(not used)
(not used)
6 black
lines
A1
A2
A3
A4
A1
A2
A3
A4
A1
A2
A3
A4
A1
A2
A3
A4
IMAGE
One Pixel
1K active
images lines
A1
A2
A3
A4
B1
B2
B3
B4
A1
A2
A3
A4
B1
B2
B3
B4
FT CCD
SG: summing gate
OG: output gate
RG: reset gate
RD: reset drain
1K storage
lines
AB11
B2
B3
B4
B1
B2
B3
B4
AB11
B2
B3
B4
B1
B2
B3
B4
STORAGE
6 black lines
B1
B2
B3
B4
B1
B1
B2
B3
B4
B1
OUT_W
OUT_X
OG SG C2 C1
C2 C1
C2 C1
C2 C1
C2 C1
C2 C1
C2 C1
C2 C1
C2 C1
C2 C1 SG OG
C3
C3
C3
C2 C1 C3 C2 C1
C3
C3
C3
C3
C3
C3
C3
C3
C3
RG
RD
RG
RD
column
1
column
24 + 1
column
24 + 1K
column
24 + 1K + 24
A1, A2, A3, A4: clocks of image section
B1, B2, B3, B4: clocks of storage section
C1, C2, C3: clocks of horizontal registers
Figure 2 - Detailed internal structure
1999 September
4
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Specifications
ABSOLUTE MAXIMUM RATINGS1
MIN.
MAX.
UNIT
GENERAL:
storage temperature
-55
-40
-20
-0.2
0
+80
+60
+20
+2.0
10
°C
°C
V
µA
mA
ambient temperature during operation
voltage between any two gates
DC current through any clock phase (absolute value)
OUT current (no short circuit protection)
VOLTAGES IN RELATION TO VPS:
VNS, SFD, RD
VCS, SFS
-0.5
-8
-5
+30
+5
+25
V
V
V
all other pins
VOLTAGES IN RELATION TO VNS:
SFD, RD
VCS, SFS, VPS
-15
-30
-30
+0.5
+0.5
+0.5
V
V
V
all other pins
DC CONDITIONS2
MIN. [V]
TYPICAL [V]
MAX. [V]
MAX. [mA]
15
15
4.5
1
VNS3
VPS
SFD
SFS
VCS
OG
N substrate
P substrate
18
1
16
-
24
3
20
0
0
6
28
7
24
-
Source Follower Drain
Source Follower Source
Current Source
Output Gate
-5
4
3
8
-
-
RD
Reset Drain
13
15.5
18
-
AC CLOCK LEVEL CONDITIONS2
MIN.
TYPICAL
MAX.
UNIT
IMAGE CLOCKS:
A-clock amplitude during integration and hold
A-clock amplitude during vertical transport (duty cycle=5/8)4
A-clock low level
8
10
10
14
0
V
V
V
V
Charge Reset (CR) level on A-clock 5
-5
-5
STORAGE CLOCKS:
B-clock amplitude during hold
B-clock amplitude during vertical transport (duty cycle=5/8)
8
10
10
14
V
V
OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. transport = 3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level
4.75
2
5
5.25
10
V
V
V
V
3.5
10
3.5
OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub
5
0
10
3
10
10
10
V
V
V
5
1 During Charge Reset it is allowed to exceed maximum rating levels (see note5).
2 All voltages in relation to SFS.
3 To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.
4 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration.
A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed.
5 Charge Reset can be achieved in two ways:
• The typical CR level is applied to all image clocks simultaneously (preferred).
• The typical A-clock low level is applied to all image clocks;for proper CR, an additional Charge Reset pulse on VNS is required.This will also affect
the charge handling capacity in the storage areas.
1999 September
5
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Timing diagrams (for default operation)
AC CHARACTERISTICS
MIN.
TYPICAL
18
MAX.
UNIT
MHz
1
Horizontal frequency (1/Tp)
0
40
Vertical frequency
0
2
10
10
3
450
5
20
20
5
1000
kHz
µs
ns
ns
ns
ns
ns
Charge Reset (CR) time
Rise and fall times: image clocks (A)
storage clocks (B)
register clocks (C)2
summing gate (SG)
reset gate (RG)
1/6 Tp
1/6 Tp
1/6 Tp
3
3
5
5
1 Tp = 1 clock period
2 Duty cycle = 50% and phase shift of the C clocks is 120 degrees.
Line Timing
H
SSC
105Tp
L
H
L
19Tp
14Tp
15Tp
24Tp
34Tp
B1
25Tp
15Tp
H
L
B2
H
L
B3
H
L
B4
15Tp
H
L
2 Tp
CR
101Tp
H
L
*
AHigh
VD
105Tp
H
L
H
L
BLC
30Tp
141Tp
Pixel Timing
1079 pixels
1Tp
H
SSC
L
H
L
C1
H
L
C2
H
L
C3
H
L
SG
RG
Tp / 6
H
L
Tp = 1 clock period = 1 / 18MHz = 55.56ns
Pixel output sequence: 7 dummy, 20 black, 4 timing, 1024 active, 4 timing, 20 black
* During AHigh = H the phiA high level is increased from 10V to 14V
Line Time: 1184 x Tp = 65.7µs
VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
B1 to B4: Vertical storage clocks
C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
RG: Reset gate
Figure 3 - Line and pixel timing diagrams
1999 September
6
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Frame Timing
Black
B
1019 1020 1021 1022 1023 1024
Sensor Output
B
B
B
B
1
2
3
4
H
L
SSC
H
L
A1, A2, A3
A4
H
L
H
L
B1
H
L
B2, B3, B4
CR
H
L
Frame Shift
H
L
*
Ahigh
H
L
VD
H
L
BLC
H
EXT. SHUTTER
L
Integration Time
Frame Shift Timing
1
Tframe shift = 1027 x 8 x N clock periods
H
A1
A2
A3
A4
B1
B2
B3
B4
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
1
8 phases correspond with 2 line shifts
Horizontal freq.
18MHz
450kHz x 8
N =
,
for example:
= 5
Vertical freq. x 8
VD: Frame pulse
CR: Charge Reset
BLC: Black Level Clamp
B1 to B4: Vertical storage clocks
C1 to C3: Horizontal register clocks
SSC: Start-Stop C-clocks
SG: Summing gate
A1 to A4: Vertical image clocks
RG: Reset gate
Figure 4 - Frame timing diagrams
1999 September
7
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Line timing
SSC
B1
B2
B3
B4
—> time
Y / Div.
: 10V (B1, B2, B3, B4); 5V (SSC)
Figure 5 - Vertical readout
Pixel timing
C1
C2
C3
SG
RG
—> time
Y / Div.
: 5V (C1, C2, C3); 10V (SG, RG)
Figure 6 - Start horizontal readout
1999 September
8
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Performance
The test conditions for the performance characteristics are as follows:
• All values are measured using typical operating conditions.
• VNS is adjusted as low as possible while maintaining proper
Vertical Anti-Blooming.
• Vertical transport frequency = 450kHz (unless specified otherwise).
• Integration time = 10ms (unless specified otherwise).
• The light source is a 3200K lamp with neutral density filters and
a 1.7mm thick BG40 infrared cut-off filter. For Linear Operation
measurements, a temperature conversion filter (Melles Griot type
no. 03FCG261, -120 mired, thickness: 2.5mm) is applied.
• Sensor temperature = 60°C (333K).
• Horizontal transport frequency = 18MHz.
LINEAR OPERATION
MIN.
4200:1
TYPICAL
MAX.
UNIT
Linear dynamic range 1
Charge Transfer Efficiency 2 vertical
Charge Transfer Efficiency 2 horizontal
Image lag
0.999995
0.999999
0
0
%
Smear 3
-39
dB
%
Resolution (MTF) @ 42 lp/mm
Responsivity
65
180
25
250
30
kel/lux·s
Quantum efficiency @ 530 nm
White Shading 4
Random Non-Uniformity (RNU) 5
VNS required for good Vertical Anti-Blooming (VAB)
Power dissipation at 15 frames/s
%
2.5
5
%
0.3
24
%
18
28
V
410
mW
1
Linear dynamic range is defined as the ratio of Q lin to read-out noise (the latter reduced by Correlated Double Sampling).
Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer.
Smear is defined as the ratio of 10% of the vertical transport time to the integration time. It indicates how visible a spot of 10% of the image
height would become.
2
3
4
5
White Shading is defined as the ratio of the one-σ value of the pixel output distribution expressed as a percentage of the mean value output
(low pass image).
RNU is defined as the ratio of the one-σ value of the highpass image to the mean signal value at nominal light.
Linear Dynamic Range
20,000
18,000
35ºC
16,000
14,000
45ºC
12,000
55ºC
10,000
8,000
6,000
4,000
2,000
0
0
5
10
15
20
25
30
35
40
Hor. Frequency (MHz)
Figure 7 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature
1999 September
9
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Maximum Read-out Speed
80
70
60
50
40
30
20
10
0
2 outputs
1 output
0
10
20
30
40
50
60
70
80
90
100
Integration time (ms)
Figure 8 - Maximum number of images/second versus integration time
Quantum Efficiency
30
25
20
15
10
5
0
400
450
500
550
600
650
700
750
800
Wavelength (nm)
Figure 9 - Quantum efficiency versus wavelength
1999 September
10
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
LINEAR/SATURATION
MIN.
TYPICAL
MAX.
UNIT
Full-well capacity saturation level (Qmax) 1
Full-well capacity shading (Qmax, shading) 2
Full-well capacity linear operation (Qlin) 3
Charge handling capacity 4
250
200
100
500
600
50
kel.
%
10
350
600
200
kel.
kel.
Overexposure 5 handling
x Qmax level
1 Qmax is determined from the lowpass filtered image.
2 Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax.
3 The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity.
4 Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer.
5 Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB). It is tested by measuring the dark line.
Charge Handling vs. Integration/Transport Voltage
600
10V/14V
500
9V/13V
400
300
8V/12V
200
100
0
1
2
3
4
5
6
Exposure (arbitrary units)
Figure 10 - Charge handling versus integration/transport voltage
1999 September
11
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
OUTPUT BUFFERS
MIN.
TYPICAL
MAX.
UNIT
Conversion factor
Mutual conversion factor matching (∆ACF)1
6
8
0
4
12
2
µV/el.
µV/el.
mA
Supply current
110
400
MHz
Ω
Bandwidth
Output impedance buffer (Rload = 3.3kΩ, Cload = 2pF)
1 Matching of the four outputs is specified as ∆ACF with respect to reference measured at the operating point (Qlin/2).
DARK CONDITION
MIN.
TYPICAL
MAX.
UNIT
Dark current level @ 30° C
Dark current level @ 60° C
Fixed Pattern Noise 1 (FPN) @ 60° C
20
30
0.6
25
30
pA/cm2
nA/cm2
el.
0.3
15
25
el.
RMS readout noise @ 9MHz bandwidth after CDS
1 FPN is the one-σ value of the highpass image.
Dark Current
1000
100
10
1
0
10
20
30
40
50
60
Temp. (oC)
Figure 11 - Dark current versus temperature
1999 September
12
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Application information
Current handling
One of the purposes of VPS is to drain the holes that are generated
during exposure of the sensor to light. Free electrons are either
transported to the VRD connection and, if excessive (from over-
exposure), free electrons are drained to VNS. No current should
flow into anyVPS connection of the sensor.During high overexposure
a total current 10 to 15mA through all VPS connections together
may be expected. The PNP emitter follower in the circuit diagram
(figure 12) serves these current requirements.
The CCD output buffer can easily be destroyed by ESD. By using
this emitter follower, this danger is suppressed; do NOT reintroduce
this danger by measuring directly on the output pin of the sensor
with an oscilloscope probe. Instead, measure on the output of the
emitter follower. Slew rate limitation is avoided by avoiding a too-
small quiescent current in the emitter follower; about 10mA should
do the job.The collector of the emitter follower should be decoupled
properly to suppress the Miller effect from the base-collector
capacitance.
VNS drains superfluous electrons as a result of overexposure. In
other words, it only sinks current. During high overexposure a total
current of 10 to 15mA through all VNS connections together may be
expected. The NPN emitter follower in the circuit diagram meets
these current requirements.The clamp circuit, consisting of the diode
and electrolytic capacitor, enables the addition of a Charge Reset
(CR) pulse on top of an otherwise stable VNS voltage.To protect the
CCD, the current resulting from this pulse should be limited. This
can be accomplished by designing a pulse generator with a rather
high output impedance.
A CCD output load resistor of 3.3kΩ typically results in a bandwidth
of 110MHz. The bandwidth can be enlarged to about 130MHz by
using a resistor of 2.2kΩ instead, which, however, also enlarges the
on-chip power dissipation.
Device protection
The output buffers of the FTT1010-M are likely to be damaged if
VPS rises above SFD or RD at any time.This danger is most realistic
during power-on or power-off of the camera.The RD voltage should
always be lower than the SFD voltage.
Decoupling of DC voltages
All DC voltages (not VNS, which has additional CR pulses as
described above) should be decoupled with a 100nF decoupling
capacitor. This capacitor must be mounted as close as possible to
the sensor pin. Further noise reduction (by bandwidth limiting) is
achieved by the resistors in the connections between the sensor
and its voltage supplies. The electrons that build up the charge
packets that will reach the floating diffusions only add up to a small
current, which will flow throughVRD.Therefore a large series resistor
in the VRD connection may be used.
Never exceed the maximum output current. This may damage the
device permanently. The maximum output current should be limited
to 10mA. Be especially aware that the output buffers of these image
sensors are very sensitive to ESD damage.
Because of the fact that our CCDs are built on an n-type substrate,
we are dealing with some parasitic npn transistors.To avoid activation
of these transistors during switch-on and switch-off of the camera,
we recommend the application diagram of figure 12.
Outputs
Unused sections
To limit the on-chip power dissipation, the output buffers are designed
with open source outputs. Outputs to be used should therefore be
loaded with a current source or more simply with a resistance to
GND. In order to prevent the output (which typically has an output
impedance of about 400Ω) from bandwidth limitation as a result of
capacitive loading, load the output with an emitter follower built from
a high-frequency transistor.Mount the base of this transistor as close
as possible to the sensor and keep the connection between the
emitter and the next stage short.
To reduce power consumption the following steps can be taken.
Connect unused output register pins (C1...C3, SG, OG) and unused
SFS pins to zero Volts.
More information
Detailed application information is provided in the application note
AN01 entitled ‘Camera Electronics for the mK x nK CCD Image
Sensor Family’.
1999 September
13
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Device Handling
An image sensor is a MOS device which can be destroyed by electro-
static discharge (ESD). Therefore, the device should be handled
with care.
When cleaning the glass we recommend using ethanol (or possibly
water). Use of other liquids is strongly discouraged:
• if the cleaning liquid evaporates too quickly, rubbing is likely to
cause ESD damage.
Always store the device with short-circuiting clamps or on conductive
foam.Always switch off all electric signals when inserting or removing
the sensor into or from a camera (the ESD protection in the CCD
image sensor process is less effective than the ESD protection of
standard CMOS circuits).
• the cover glass and its coating can be damaged by other liquids.
Rub the window carefully and slowly.
Being a high quality optical device, it is important that the cover
glass remain undamaged.When handling the sensor, use fingercots.
Dry rubbing of the window may cause electro-static charges or
scratches which can destroy the device.
VSFD
CR pulse
0
keep short
<10mm!
BC
850C
-
keep short!
+
VNS
SFD
BFR
OUT
92A
BAT74
100 Ω
output for
preprocessing
BC
850C
BAT74
27Ω
BAT74
Schottky!
VPS
VRD
VCS
15Ω
BAT74
Schottky!
860C
10kΩ
BC
VOG
10kΩ
10kΩ
Figure 12 - Application diagram to protect the FTT1010-M
1999 September
14
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Pin configuration
The FTT1010-M is mounted in a Pin Grid Array (PGA) package with
76 pins in a 15x13 grid of 40.00 x 40.00 mm2. The position of pin A1
is marked with a gold dot on top of the package.
The clock phases of quadrant W are internally connected to X, and
the clock phases of Y are connected to Z.
Symbol
VNS
Name
Pin # W
A12
D11
E11
E12
-
C11
A13
A10
A11
B13
B12
-
Pin # X
A3
B2
D3
E2
E3
C3
A1
B5
A4
B1
B3
-
Pin # Y
J2
F3
-
Pin # Z
F11
H12
J11
-
N substrate
N substrate
N substrate
N substrate
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
VNS
VNS
VNS
VNS
VPS
SFD
SFS
VCS
OG
RD
A1
A2
A3
A4
B1
B2
B3
B4
C1
-
-
-
G3
J1
J4
J3
H1
H2
F1
G2
F2
G1
-
-
-
-
H5
H6
J6
H4
J5
H3
H7
G11
J13
H9
J10
H13
H11
F13
G12
F12
G13
-
Output Gate
Reset Drain
Image Clock (Phase 1)
Image Clock (Phase 2)
Image Clock (Phase 3)
Image Clock (Phase 4)
Storage Clock (Phase 1)
Storage Clock (Phase 2)
Storage Clock (Phase 3)
Storage Clock (Phase 4)
Register Clock (Phase 1)
Register Clock (Phase 2)
Register Clock (Phase 3)
Summing Gate
-
-
-
-
-
-
D13
C12
D12
C13
B9
B8
A8
B10
A9
B11
B7
D1
C2
D2
C1
A6
A7
B6
A2
A5
B4
-
-
-
J8
C2
C3
SG
RG
OUT
NC
J7
H8
J12
J9
Reset Gate
Output
Not connected
H10
13 12 11 10
9
8
7
6
5
4
3
2
1
SFD
SG
VNS VCS
RG
C1
C3
C2
VCS VNS
SFD
OG
C3
C2
RG
C1
SFS
SG
J
H
G
F
J
H
G
F
OG
VNS
RD
OUT
SFS
NC
OUT
VPS
VNS
RD
A2
A3
VPS
VNS
A4
A1
A2
A3
A4
A1
TOP
IMAGE
Y
Z
X
W
STORAGE
FTT1010-M
VNS VNS
VNS
VNS
E
D
C
B
A
E
D
C
B
A
VNS
VPS
VNS
VPS
B3
B2
B1
B4
B3
B2
B1
B4
NC
C2
OG
RD
OUT
SG
C1
C2
C3
C3
C1
SFS OUT
RD
VNS
SG
OG
SFD VNS
VCS SFS
RG
RG
VCS VNS
SFD
13 12 11 10
9
8
7
6
5
4
3
2
1
Figure 13 - FTT1010-M pin configuration (top view)
1999 September
15
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Package information
Top cover glass to top chip 2.4 ± 0.25
Chip - bottom package 1.7 ± 0.15
Chip - cover glass 1.3 ± 0.20
Cover glass 1.0 ± 0.05
SENSOR CRYSTAL
A ZONE
COVER GLASS
Image sensor chip
1.4 /100
TOP VIEW
INDEX
MARK
PIN 1
26
±
0.15
40
COVER GLASS
±
0.40
(2.54)
0.46 0.05
±
STAND-OFF PIN
A is the center of the image area.
Position of A:
26 ± 0.15 to left edge of package
20 ± 0.10 to bottom of package
Angle of rotation: less than ± 10
Sensor flatness: < 7 µm (P-V)
BOTTOM VIEW
Cover glass: Corning 7059
Thickness of cover glass: 1.00 ± 0.05
Refractive index: nd = 1.53
Single sided AR coating inside (430-660 nm)
All drawing units are in mm
35.56 ± 0.20
Figure 14 - Mechanical drawing of the PGA package of the FTT1010-M
1999 September
16
Order codes
The sensors can be ordered using the following codes:
FTT1010-M sensors
Description
Quality Grade
Order Code
FTT1010-M/TG
FTT1010-M/EG
FTT1010-M/IG
FTT1010-M/HG
Test grade
9922 157 35031
9922 157 35051
9922 157 35021
9922 157 35011
Economy grade
Industrial grade
High grade
You can contact the Image Sensors division of Philips
Semiconductors at the following address:
Philips Semiconductors
Image Sensors
Internal Postbox WAG-05
Prof. Holstlaan 4
5656 AA Eindhoven
The Netherlands
phone
fax
+31 - 40 - 27 44 400
+31 - 40 - 27 44 090
www.semiconductors.philips.com/imagers/
lmtb
Philips
Semiconductors
TRAD
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